Three-dimensional memory structure and circuit

Abstract

A three-dimensional memory structure includes a memory array including first and second sub-arrays each having a first select line, a plurality of word lines, and a second select line; a connection structure including a plurality of connection regions, wherein an extension of at least one of the first select line, the plurality of word lines, and the second select line is coupled to a respective connection region of the plurality of connection regions; a transfer gate set disposed below the connection structure and between the first and second sub-arrays, the transfer gate set including a plurality of transfer gates, the plurality of transfer gates respectively coupled to a respective plurality of connection regions; and a drive circuit coupled to the transfer gate set and disposed below the connection structure.

Description

Technical Field

[0001] This invention relates to a three-dimensional memory structure and circuit, and more particularly to a connection structure between a driving circuit and a memory array in a three-dimensional memory. Background Technology

[0002] In three-dimensional (3D) memory technology, as the density of 3D memory increases and it becomes increasingly multi-layered, the height of the 3D memory array also increases. Therefore, in terms of manufacturing processes, it is necessary to reduce the word line thickness to decrease the memory array height. However, reducing the word line thickness also increases the on-plane resistivity of the word lines. Furthermore, a large word line time constant (i.e., RC value) is not suitable for high-speed designs involving memory operations (read / program / erase).

[0003] In existing technologies, word line drivers for memory arrays can employ side-driven circuitry, which allows for a smaller layout area. However, this architecture provides longer word line lengths and larger word line time constants, resulting in slower word line transition speeds. Alternatively, existing technologies can use a center-driven circuitry configuration. While this architecture has a larger layout area, it offers faster word line transition speeds due to shorter word lines and smaller word line time constants. However, some package types limit the width of the driver circuitry layout, necessitating a higher memory block height. Typically, a memory block requires four sub-blocks for its driver circuitry layout, but a center-driven circuitry architecture increases this to eight sub-blocks, effectively doubling the block density.

[0004] Furthermore, more sub-blocks increase word line switching power, which is supported by the high-voltage pump circuitry. Therefore, a higher word line switching power requires a larger high-voltage pump circuit. However, the die size limits the size of the high-voltage pump circuit. If the high-voltage pump circuit cannot fully support the word line switching power, the word line switching speed is not only limited by the word line time constant but also affected by the output capability of the high-voltage pump circuit. This will result in a slower word line switching speed.

[0005] Therefore, the advantages of a center-mounted driver circuit are lost. This would result in a larger driver circuit, which in turn would increase the die size. Furthermore, a larger block size would increase power consumption during word line transitions. Also, a larger block size and fewer blocks would make the controller more difficult to use. A large block size would also increase the failure rate of bad blocks.

[0006] Figure 1A This diagram illustrates the connection between a traditional center drive circuit and the select and word lines of a memory. Figure 1B This diagram illustrates the vertical connection between a traditional center-drive circuit and the select and word lines of a memory. (Example:) Figure 1A As shown, the memory structure 100 includes at least a first half-memory array 102a and a second half-memory array 102b (each having the same number of word lines), a first connection region 104a and a second connection region 104b, a first transmission gate group 106a and a second transmission gate group 106b, and a centrally located driver 108.

[0007] like Figure 1A , 1B As shown, the first connection region 104a and the second connection region 104b are coupled to the first half-memory array 102a and the second half-memory array 102b, respectively. The first transmission gate group 106a and the second transmission gate group 106b are generally disposed below the first connection region 104a and the second connection region 104b, respectively. Each transmission gate in the first transmission gate group 106a is coupled to the corresponding select line SSL, GSL and word lines WL0 to WLN in the first half-memory array 102a via the corresponding connection region in the first connection region 104a. Each transmission gate in the second transmission gate group 106b is coupled to the corresponding select line SSL, GSL and word lines WL0 to WLN in the second half-memory array 102b via the corresponding connection region in the second connection region 104b. The center-mounted drive circuit 108 is disposed between and below the first half-memory array 102a and the second half-memory array 102b, and is coupled to the first transmission gate group 106a and the second transmission gate group 106b. The first half-memory array 102a and the second half-memory array 102b constitute the entire memory array.

[0008] Figure 2A A top view of a block structure of a 3D memory with side-drive circuitry. Figure 2B A top view of a block structure of a 3D memory with a centrally located driver circuit is shown. Figure 2A As shown in the side drive circuit architecture, the drive circuit 120 is located on the side (one side of the memory array 134). Generally speaking, a block of the memory array 134 includes 4 sub-blocks, and each block corresponds to a transmission gate group 132. The block layout width of the transmission gate group 132 is a.

[0009] As shown in the center-drive circuit architecture of Figure 2b, this architecture divides a memory array into two subarrays 134a and 134b. These two subarrays 134a and 134b are half the size of the entire memory array 134, but they have the same structure and the same number of word lines. This is because, under this architecture, each side of the memory arrays 134a and 134b is essentially similar to... Figure 2A The memory array 134, therefore, if it is to maintain Figure 1AThe architecture of four sub-blocks inevitably means that the layout width of the transmission gate groups 132a and 132b for each of the sub-arrays 134a and 134b will also become 'a'. However, this would double the layout area width of the entire transmission gate group and increase the memory size. Therefore, it is best to reduce the width of the transmission gates 132a and 132b to 'b', for example, by half. However, due to the reduction in width, if the total number of transmission gates is not improved, the height of the transmission gate layout will increase. The increased space due to the increased height will cause the number of sub-blocks on the memory side to change from four to eight. Thus, the word line, which was originally shared by four sub-blocks, will now be shared by eight sub-blocks, increasing the load on the transmission gates.

[0010] Therefore, this technology field needs further development of center drive circuit design to achieve smaller drive circuits, higher word line transition speeds, and fewer sub-blocks per block. Summary of the Invention

[0011] According to an embodiment of the present invention, a three-dimensional memory structure is provided, comprising: a memory array including a first subarray and a second subarray, each having a first select line, a plurality of word lines, and a second select line; a connection structure including a plurality of connection regions, wherein an extension structure of at least one of the first select line, the plurality of word lines, and the second select line is coupled to a corresponding connection region among the plurality of connection regions; a transmission gate group disposed below the connection structure and between the first and second subarrays, the transmission gate group including a plurality of transmission gates, the plurality of transmission gates being respectively coupled to the corresponding plurality of connection regions; and a driving circuit coupled to the transmission gate group and disposed below the connection structure.

[0012] According to an embodiment of the present invention, a three-dimensional memory circuit is provided, comprising: a memory array including a first subarray and a second subarray, each having a first select line, multiple word lines, and a second select line, wherein the memory array comprises multiple blocks, each block having multiple subblocks, and in each subblock, one of the first select line, multiple word lines, and a second select line of the first subarray and the second subarray is coupled to each other; a driving circuit located below the memory array and between the first and second subarrays, for driving the first subarray and the second subarray; and a plurality of transmission gates coupled to the driving circuit for transmitting control signals and data of the driving circuit to the first and second subarrays via the plurality of transmission gates. The plurality of transmission gates are respectively connected to extension structures of the corresponding first select line, multiple word lines, and second select lines via a plurality of connection regions, and are disposed below the plurality of connection regions. Attached Figure Description

[0013] Figure 1A This diagram illustrates the connection between a traditional center-drive circuit and the select and word lines of a 3D memory.

[0014] Figure 1B This diagram illustrates the vertical connection between a traditional center-drive circuit and the select line and word line of a 3D memory.

[0015] Figure 2A A top view of a block structure of a 3D memory with side-drive circuitry.

[0016] Figure 2B A top view of a block structure of a 3D memory with a central drive circuit.

[0017] Figure 3 A conceptual schematic diagram of a 3D memory structure according to an embodiment of the present invention is shown.

[0018] Figure 4 A schematic connection diagram of a 3D memory structure according to an embodiment of the present invention is shown.

[0019] Figure 5 A schematic connection diagram of a 3D memory structure according to an embodiment of the present invention is shown.

[0020] Figure 6 Draw Figure 5 A schematic diagram showing a variation of the 3D memory structure.

[0021] Figure 7 A schematic connection diagram of a 3D memory structure is shown according to another embodiment of the present invention.

[0022] Explanation of reference numerals in the attached figures

[0023] 100, 200, 300, 300', 400: 3D memory structure

[0024] 102a / 102b: First / Second Subarray

[0025] 104a / 104b: First / Second connection structure

[0026] 106a / 106b: First / Second transmission gate group

[0027] 108, 202, 302, 402: Drive circuits

[0028] 204, 304, 404: Memory array

[0029] 204a / 204b, 304a / 304b, 404a / 404b: First / Second Subarray

[0030] 206, 306, 406: Connection structure

[0031] 306a / 306b, 406a / 406b: First / Second connection structure

[0032] 208, 308, 408: Transmission gate groups

[0033] 308a / 308b, 408a / 408b: First / Second transmission gate group

[0034] SSL: Select Line

[0035] GSL: Select Line

[0036] WL0~WLN: Word lines

[0037] Ps, P0, P1, ..., PN-1, PN, PG: Transmission gates Detailed Implementation

[0038] This invention proposes a novel configuration for the center-drive circuit of a 3D memory, which does not increase the number of transmission gates or the number of sub-blocks in a single memory block; the number remains the same as that of a memory using a side-drive circuit. Hereinafter, the memory will be referred to simply as the 3D memory.

[0039] Figure 3 A schematic diagram of a memory structure according to an embodiment of the present invention is shown. Figure 3 As shown, the 3D memory structure 200 includes a memory array 204, a central driving circuit (hereinafter referred to as the driving circuit) 202, a connection structure 206, and a transmission gate group 208. The memory array 204 further includes a first subarray 204a and a second subarray 204b.

[0040] According to one embodiment of the present invention, the first subarray 204a and the second subarray 204b together constitute a complete memory array 204. Each of the first subarray 204a and the second subarray 204b has a select line SSL, word lines WL0 to WLN, and a select line GSL. In one example, the first subarray 204a and the second subarray 204b may be two subarrays that equally divide the memory array 204, that is, the first subarray 204a and the second subarray 204b have the same number of word lines, but the number of memory cells is half that of the memory array 204. In this embodiment, the word lines WL0 to WLN are numbered from high to low and from small to large in the vertical direction of the memory array 204, but they can also be numbered in the opposite way.

[0041] Furthermore, in the first subarray 204a and the second subarray 204b, two corresponding select lines SSL, two corresponding word lines (WL0 to WLN), and two corresponding select lines GSL are short-circuited or coupled to each other through the non-cut-off region 204c. For example, the select line SSL of the first subarray 204a is coupled to the select line SSL of the second subarray 204b through the corresponding portion of SSL in the non-cut-off region 204c, the select line GSL of the first subarray 204a is coupled to the select line GSL of the second subarray 204b through the corresponding portion of GSL in the non-cut-off region 204c, and the word lines WLi (i = 0 to N) of the first subarray 204a are coupled to the word lines WLi of the second subarray 204b through the corresponding portion of WLi in the non-cut-off region 204c.

[0042] Furthermore, for example, in this embodiment, the memory array 204 of the 3D memory structure 200 is a block, and under normal specifications, it typically contains four sub-blocks. Each sub-block's memory array includes a select line SSL, word lines WL0 to WLN, and a select line GSL. Operationally, one sub-block can be selected first using the select lines SSL and GSL, followed by the select word lines. Therefore, a single transmission gate group 206 can be used to share resources among the four sub-blocks.

[0043] The 3D memory structure 200 further includes a connection structure 206, which comprises multiple connection regions. The connection structure 206 is arranged side-by-side with the first subarray 204a and the second subarray 204b. The number of connection regions in the connection structure 206 is the same as the sum of the number of word lines, select lines SSL, and GSL, and they correspond one-to-one. In other words, each of the word lines WL0 to WLN, select lines SSL, and select lines GSL corresponds to a connection region. These connection regions provide downward coupling for each of the word lines WL0 to WLN, select lines SSL, and select lines GSL to the corresponding transmission gates PS, P0 to PN, and PG in the transmission gate group 208. These transmission gates PS, P0 to PN, and PG can be MOS transistors. The multiple connection regions of the connection structure 206 can be connected to each of the word lines WL0 to WLN, select lines SSL, and select lines GSL, respectively. In this way, the drive circuit 202 can transmit control signals to the selected word lines and select lines through the transmission gates to drive the memory cells (not shown) on the selected word lines.

[0044] The driving circuit 202 is disposed below the connection structure 206, and in one embodiment, it may also be disposed between the first subarray 204a and the second subarray 204b. The driving circuit 202 can drive the first subarray 204a and the second subarray to perform related operations, such as reading, programming, and erasing. The transmission gate group 208 is disposed below the aforementioned connection area 206.

[0045] Furthermore, according to this embodiment, only one set of transmission gate groups 206 is provided, the number of which corresponds at least to the select line SSL, word lines WL0~WLN, and select line GSL. According to this embodiment, although a mid-range driver circuit is used, it is not necessary to use two transmission gate groups respectively provided to the first subarray 204a and the second subarray 204b, as in conventional technologies. Furthermore, the transmission gate group 208 is disposed below the connection structure 206. It should be noted that although... Figure 3 The transmission gate group 208 is drawn next to the connection structure 206, but this is only for ease of understanding; this embodiment uses only one set of transmission gate groups 208 as a conceptual diagram. To achieve the technical effects of this invention, a set of transmission gate groups 208 can have different configuration settings, which will be further explained below.

[0046] Figure 4 A schematic diagram of a 3D memory structure is shown according to an embodiment of the present invention. Figure 4 The image shown is a 45° side view (vertical direction) of the 3D memory structure 200, which is... Figure 3 One embodiment of the conceptual diagram. Furthermore, the non-cut-off region (i.e., the extended structure) 204c has the same height as the connection region 206 for each word line WL. The 3D memory 200 has a driving (center-driven) circuit 202 disposed below the connection region 206 and between the first subarray 204a and the second subarray 204b. Each of the first subarray 204a and the second subarray 204b includes a select line SSL (first select line, one select line SSL per subblock), word lines WL0 to WLN, and a select line GSL (second select line, one select line GSL per subblock).

[0047] Furthermore, the select lines SSL, word lines WL0 to WLN, and select line GSL of the first subarray 204a and the second subarray 204b are all coupled using the non-cut-off region 204c. That is, the select lines SSL of the first subarray 204a and the second subarray 204b are short-circuited or coupled to each other, the word lines WLi (i = 0 to N) of the first subarray 204a and the second subarray 204b are short-circuited or coupled to each other, and the select lines GSL of the first subarray 204a and the second subarray 204b are also short-circuited or coupled to each other. Although not shown, the select lines SSL, word lines WL0 to WLN, and select line GSL can be isolated from each other using insulating material.

[0048] The 3D memory structure 200 also includes a connection structure 206, which comprises multiple connection regions. The number of connection regions is the same as the total number of select lines SSL, word lines WL0-WLN, and select lines GSL. Each connection region in the connection structure 206 corresponds one-to-one with a select line SSL, word lines WL0-WLN, and select line GSL. In this embodiment, each connection region extends from the first subarray 204a to the second subarray 204b (or vice versa). Each connection region is coupled to the corresponding select line SSL, word lines WL0-WLN, and select line GSL in the first subarray 204a. In another embodiment, each connection region may not be connected to the corresponding select line SSL, word lines WL0-WLN, and select line GSL in the second subarray 204b. That is, each connection region is only coupled to the select line SSL, word lines WL0-WLN, and select line GSL in either the first subarray 204a or the second subarray 204b.

[0049] The multiple connection regions of the connection structure 206 are stacked in the vertical direction of the memory array 204. As an example, the multiple connection regions can be stacked in a stepped shape to facilitate wiring to the underlying transmission gate group 208.

[0050] The transmission gate group 208 is coupled to the drive circuit 202, and various control signals from the drive circuit 202 can be transmitted to the selected word line through each transmission gate of the transmission gate group 208. In this embodiment, the transmission gate group 208 is located below the connection structure 206. The transmission gate group 208 is composed of multiple transmission gates PS, P0 to PN, PG. The number of transmission gates PS, P0 to PN, PG is at least the same as the number of connection areas in the connection structure 206. The transmission gates PS, P0 to PN, PG can generally be composed of MOS transistors. Each transmission gate PS, P0 to PN, PG is coupled to the corresponding connection area in pairs using wires or other feasible methods.

[0051] In this embodiment, the corresponding select lines SSL, word lines WL0~WLN, and select line GSL of the first subarray 204a and the second subarray 204b are coupled to each other, and only one transmission gate group 208 is used. Therefore, under the above architecture, even with a centrally located driver circuit, the entire memory array 204 only requires one transmission gate group 208 to allow the first subarray 204a and the second subarray 204b to be used simultaneously, instead of requiring two transmission gate groups as in conventional technology. Furthermore, a block can still contain four subblocks. Therefore, the memory array 204 does not increase the block height. Thus, the load on the driver circuit and each transmission gate of the transmission gate group is not too large.

[0052] Figure 5 A schematic diagram of a 3D memory structure according to an embodiment of the present invention is shown. Figure 5 As shown, similarly, the 3D memory 300 has a driving (mid-drive) circuit 302 disposed under the connection structure 306 and between the first subarray 304a and the second subarray 304b. Each of the first subarray 304a and the second subarray 304b includes a select line SSL, word lines WL0 to WLN, and a select line GSL.

[0053] The select lines SSL, word lines WL0 to WLN, and select line GSL of the first subarray 304a and the second subarray 304b are all coupled using non-cut-off regions (i.e., extension structures) 304c. That is, the select lines SSL of the first subarray 304a and the second subarray 304b are short-circuited or coupled to each other, the word lines WLi (i = 0 to N) of the first subarray 304a and the second subarray 304b are short-circuited or coupled to each other, and the select lines GSL of the first subarray 304a and the second subarray 304b are also short-circuited or coupled to each other. Although not shown, the select lines SSL, word lines WL0 to WLN, and select line GSL can be isolated from each other using insulating material.

[0054] In this embodiment, the 3D memory structure 300 further includes a connection structure 306, which further includes a first connection structure 306a and a second connection structure 306b. The first connection structure 306a and the second connection structure 306b each include multiple connection regions. The number of connection regions in each of the first connection structure 306a and the second connection structure 306b is the same as the total number of select lines SSL, word lines WL0-WLN, and select lines GSL; however, this relationship is merely an example and not intended to limit the invention. Each connection region of the first connection structure 306a corresponds one-to-one with and is coupled to each non-cut-off region (extension structure) 304c of the select lines SSL, word lines WL0-WLN, and select lines GSL of the first subarray 304a. Each connection region of the second connection structure 306b corresponds one-to-one with and is coupled to the select lines SSL, word lines WL0-WLN, and select lines GSL of the second subarray 304b. Here, the one-to-one architecture is merely an example and not intended to limit the invention.

[0055] In this embodiment, the multiple connection regions of each of the first and second structures 306a and 306b are stacked in the vertical direction of the memory array 304. As an example, the multiple connection regions can be stacked in a stepped shape to facilitate wiring to the underlying transmission gate group 308.

[0056] In addition, Figure 5The 3D memory structure 300 shown divides a transmission gate group 308 into two subgroups; that is, the transmission gate group 308 in this embodiment includes a first transmission gate subgroup 308a and a second transmission gate subgroup 308b. The first transmission gate group 308a is used, for example, for the select line SSL and odd number line WL of the first subarray 304a and is coupled to the second subarray 304b via a non-cut-off region 304c; the second transmission gate group 308b is used, for example, for the even number line WL and select line GSL of the second subarray 304b and is coupled to the first subarray 304a via a non-cut-off region 304c.

[0057] The first transmission gate group 308a and the second transmission gate group 308b are respectively coupled to the driving circuit 302. Various control signals of the driving circuit 302 can be transmitted to the selected word lines of the first or second subarray 304a, 304b through the transmission gates of the first and second transmission gate groups 308a, 308b. In this embodiment, the first and second transmission gate groups 308a, 308b are respectively disposed below the first and second connection structures 306a, 306b, that is, below the memory array 304, and are disposed on both sides of the driving circuit 302.

[0058] The first and second transmission gate subgroups 308a and 308b are each composed of multiple transmission gates, and the total number of transmission gates PS, P0 to PN, PG is at least the same as the total number of select lines SSL, word lines WL0 to WLN, and select lines GSL of the first subarray 304a (or the second subarray 304b). Similarly, the transmission gates PS, P0 to PN, PG can be composed of MOS transistors. In this embodiment, the first and second transmission gate subgroups 308a and 308b each have the same number of transmission gates. For example, the first transmission gate subgroup 308a is provided with transmission gates PS, P1, ..., PN-2, PN, while the second transmission gate subgroup 308b is provided with transmission gates P0, P2, ..., PN-1, PG. In other words, the transmission gates PS, P1, ..., PN-2, PN of the first transmission gate subgroup 308a are connected upwards to the selection line SSL and odd-numbered word lines WL1, WL3, ..., WL(N-2), WLN of the first subarray 304a via wiring or other means through the corresponding connection areas of the first connection structure 306a. Furthermore, the transmission gates P0, P2, ..., PN-1, PG of the second transmission gate subgroup 308b are connected upwards to the selection line GSL and even-numbered word lines WL0, WL2, ..., WL(N-1) of the second subarray 304b via wiring or other means through the corresponding connection areas of the second connection structure 306b.

[0059] As described above, in this embodiment, because the number of the first transmission gate subgroup 308a is only half that of the original transmission gate subgroup, only half of the connection area in the first connection structure 306a will be used. That is, through the connection areas in the first connection structure 306a corresponding to the selection line SSL and odd-numbered word lines WL1, WL3, ..., WL(N-2), WLN of the first subarray 304a, each transmission gate of the first transmission gate subgroup 308a can be connected upwards to the corresponding selection line SSL and odd-numbered word lines WL1, WL3, ..., WL(N-2), WLN. Similarly, through the connection areas in the second connection structure 306b corresponding to the even-numbered word lines WL0, WL2, ..., WL(N-1) and selection line GSL of the second subarray 304b, each transmission gate of the second transmission gate subgroup 308b can be connected upwards to the corresponding selection line GSL and even-numbered word lines WL0, WL2, ..., WL(N-1).

[0060] Therefore, in this centrally configured driver circuit architecture, each of the two subarrays 304a and 304b of the memory array 304 is provided with a corresponding connection structure 306a and 306b. However, in this embodiment, the select line SSL, word lines WL0~WLN, and select line GSL of the two subarrays 304a and 304b are coupled with a non-cut-off region 304c, and a transmission gate group is divided into two subgroups. Therefore, this embodiment can still use one transmission gate group to drive the first subarray 304a and the second subarray 304b, instead of requiring two transmission gate groups as in conventional technology. Thus, one block can still maintain four subblocks. In this way, the load on the driver circuit and each transmission gate of the transmission gate group will not be too large.

[0061] Figure 6 Draw Figure 5 A schematic diagram of a variation of the 3D memory structure is shown. In this variation, identical components in the 3D memory structure 300' are labeled with the same reference numerals, and their corresponding descriptions are not repeated. In this embodiment of the invention, the select line SSL, word lines WL0~WLN, and select line GSL of the first subarray 304a and the second subarray 304b are all coupled using non-cut-off regions 304c. Figure 4 or Figure 5In the 3D memory structure shown, because the number of word lines is extremely large, it is impractical to connect them with additional wires or metal layers. Therefore, in typical manufacturing processes, the word lines are formed using the same material as the word lines themselves, and the connection is achieved without severing the word lines between the two subarrays. For example, the word lines of the first subarray 304a and the second subarray 304b can be formed simultaneously, and then the word lines between the first subarray 304a and the second subarray 304b are cut off, allowing the corresponding word lines in the first subarray 304a and the second subarray 304b to be coupled to each other. The uncut regions of selected lines SSL and GSL can also be formed in this manner.

[0062] However, for the selection lines SSL and GSL, since a block typically has four sub-blocks, there are four selection lines for SSL and four for GSL. Therefore, in Figure 6 In the variation example, the non-cut-off regions 312, 314 between the select line SSL and select line GSL of the first subarray 304a and the second subarray 304b can be connected using different methods, such as using metal layers, wires or different process materials.

[0063] Figure 7 A schematic diagram of a 3D memory structure is shown according to another embodiment of the present invention. The memory structure 400 is substantially the same as... Figure 5 The structure shown is similar, also including a memory array 404 with a first subarray 404a and a second subarray 404b, a connection structure 406 with a first connection structure 406a and a second connection structure 406b, a transmission gate group 408 with a first transmission gate group 408a and a second transmission gate group 408b, and a driving circuit 402. This part of the structure is similar to... Figure 5 The same applies, so it will not be described again. Each transmission gate of the first transmission gate subgroup 408a is coupled to a connection area in the first connection structure 406a corresponding to the select line SSL, word lines WL0 to WL(N-1), and select line GSL of the first subarray 404a, respectively. Similarly, each transmission gate of the second transmission gate subgroup 408b is coupled to a connection area in the second connection structure 406b corresponding to the select line SSL, word lines WL0 to WL(N-1), and select line GSL of the second subarray 404b. However, since the word lines WL(N-2) of the first subarray 404a and the second subarray 404b are connected via a non-cut-off region 404c, only one transmission gate is needed to connect the word line WL(N-2). That is, only one transmission gate subgroup (in this example, the first transmission gate subgroup 408a) provides a transmission gate to connect to the word line WL(N-2).

[0064] Furthermore, this embodiment is similar to Figure 5 Another difference in the illustrated embodiment lies in the arrangement of the non-cut-off region 404c. In the above... Figures 4-6 In the embodiments described above, the corresponding select lines SSL, word lines WL0-WLN, and select line GSL of the first and second subarrays are all short-circuited or coupled using non-cut-off regions. However, in this embodiment, these lines do not need to be all coupled to each other; at least one of the select lines SSL, word lines WL0-WLN, and select line GSL can be coupled to each other. Even if only a portion of the select lines SSL, word lines WL0-WLN, and select line GSL are coupled to each other, a certain technical effect can still be achieved in reducing transmission gates.

[0065] In the above embodiments, the memory array is divided into two sub-arrays of the same size, but different partitioning methods can be used depending on the requirements. Additionally, in Figure 5 In this memory structure, the connections between the transmission gates of the two transmission gate subgroups and the two subarrays are allocated using the parity numbers of the select lines and word lines, but the order of the select lines and word lines can also be used. For example, if there are 0 to N word lines (N and j are natural numbers, j < N), then each transmission gate of the first transmission gate subgroup can be coupled to the first select line and word lines 0 to j of the first subarray, and each transmission gate of the second transmission gate subgroup can be coupled to the second select line and word lines (j+1) to N of the second subarray.

[0066] In summary, according to embodiments of the present invention, when a centrally located drive circuit is used in the 3D memory structure, the select lines and word lines of the two subarrays are coupled to each other, allowing the use of only one set of transmission gates. One transmission gate set has the same number of transmission gates as the select lines and word lines, thus eliminating the need for two transmission gate sets as in conventional technologies. Furthermore, a single memory array block can still maintain four sub-blocks without increasing to eight sub-blocks as in conventional technologies. Consequently, the load on the drive circuit and each transmission gate of the transmission gate set is not excessive.

Claims

1. A three-dimensional memory structure, characterized in that, include: The memory array includes a first subarray and a second subarray, each having a first select line, multiple word lines, and a second select line; A connection structure includes multiple connection regions, wherein an extension structure of at least one of the first selection line, the plurality of word lines, and the second selection line is coupled to a corresponding connection region in the plurality of connection regions, wherein each of the plurality of connection regions extends from the first subarray to the second subarray, and the first selection line, the plurality of word lines, and the second selection line of the first subarray are respectively connected one-to-one with the first selection line, the plurality of word lines, and the second selection line of the second subarray via each of the extension structures; A transmission gate group is disposed below the connection structure and between the first subarray and the second subarray, wherein the transmission gate group includes a plurality of transmission gates and the plurality of transmission gates are respectively coupled to the respective plurality of connection regions; as well as A driving circuit is coupled to the transmission gate group and is disposed below the connection structure.

2. The three-dimensional memory structure according to claim 1, characterized in that, The number of the plurality of transmission gates is at least the same as the total number of the first selection line, the plurality of word lines, and the second selection line.

3. The three-dimensional memory structure according to claim 1, characterized in that, The memory array is a block containing multiple sub-blocks. In each sub-block, the first select line of the first sub-array and the second sub-array, and one of the multiple word lines and the second select line are coupled to each other.

4. The three-dimensional memory structure according to claim 1, characterized in that, The plurality of connection regions of the connection structure are respectively coupled to the first selection line, the plurality of word lines and the extension structure of the second selection line of the first subarray, and extend into the second subarray.

5. The three-dimensional memory structure according to claim 4, characterized in that, The plurality of connection regions of the connection structure are stacked in the vertical direction of the memory array.

6. The three-dimensional memory structure according to claim 5, characterized in that, The plurality of connection regions of the connection structure are stacked in a stepped shape.

7. The three-dimensional memory structure according to claim 1, characterized in that, The connection structure further includes a first connection structure and a second connection structure, wherein the first connection structure has multiple first connection regions and the second connection structure has multiple second connection regions. The number of the plurality of first connection regions is the same as the total number of the first select lines, the plurality of word lines, and the second select lines of the first subarray; the number of the plurality of second connection regions is the same as the total number of the first select lines, the plurality of word lines, and the second select lines of the second subarray. The transmission gate group further includes a first transmission gate subgroup and a second transmission gate subgroup, wherein the first and second transmission gate subgroups each have half the number of the plurality of transmission gates. The first selection line of the first subarray and the odd-numbered word lines among the plurality of word lines are respectively coupled to each of the transmission gates of the first transmission gate subgroup via the corresponding first connection regions in the first connection structure. The second selection line of the second subarray and the even-numbered word lines among the plurality of word lines are respectively coupled to each of the transmission gates of the second transmission gate subgroup via the corresponding second connection regions in the second connection structure.

8. The three-dimensional memory structure according to claim 7, characterized in that, The plurality of first connection regions of the first connection structure and the plurality of second connection regions of the second connection structure are stacked in the vertical direction of the memory array.

9. The three-dimensional memory structure according to claim 8, characterized in that, The plurality of first and second connection regions of the first and second connection structures are stacked in a stepped shape.

10. The three-dimensional memory structure according to claim 1, characterized in that, The connection structure further includes a first connection structure and a second connection structure. The first connection structure has multiple first connection areas, and the second connection structure has multiple second connection areas. The number of each of the multiple first connection areas is the same as the number of the first selection lines, the multiple word lines, and the second selection lines. The transmission gate group further includes a first transmission gate subgroup and a second transmission gate subgroup, wherein the first and second transmission gate subgroups each have half the number of the plurality of transmission gates. The first selection line of the first subarray and the 0th to jth word lines of the plurality of word lines are respectively coupled to each of the transmission gates of the first transmission gate subgroup via the corresponding first connection regions in the first connection structure. The second selection line of the second subarray and the (j+1)th to Nth word lines of the plurality of word lines are respectively coupled to the respective transmission gates of the second transmission gate subgroup via the corresponding second connection regions in the second connection structure, wherein the plurality of word lines are the 0th to Nth word lines, N, j are natural numbers, and j <N。 11. The three-dimensional memory structure according to claim 1, characterized in that, The connection between the first selection line and the second subarray, and between the multiple word lines and the second selection line, is achieved by connecting each of the extended structure regions. The material of each extended structure is the same as the material used in the first selection line, the multiple word lines, and the second selection line.

12. The three-dimensional memory structure according to claim 1, characterized in that, The multiple word lines between the first subarray and the second subarray are connected by extension structures made of the same process material, and at least one of the first selection line and the second selection line between the first subarray and the second subarray is connected by different process materials.

13. The three-dimensional memory structure according to claim 12, characterized in that, The different process materials include metal layers or wires of process materials that are different from the first and second selection lines.

14. The three-dimensional memory structure according to claim 1, characterized in that, The first subarray may be the same size as or different from the second subarray.

15. The three-dimensional memory structure according to claim 3, characterized in that, The number of sub-blocks is four.

16. A three-dimensional memory circuit, characterized in that, include: A memory array includes a first subarray and a second subarray, each having a first select line, multiple word lines, and a second select line. The memory array comprises multiple blocks, each of which has multiple subblocks. In each subblock, at least one of the first select line of the first subarray and the second subarray, the multiple word lines, and the second select line are connected to each other. A driving circuit, located below the memory array and between the first and second sub-arrays, is used to drive the first sub-array and the second sub-array; as well as Multiple transmission gates are coupled to the driving circuit to transmit the control signals of the driving circuit to the first and second sub-arrays via the multiple transmission gates. The plurality of transmission gates are respectively connected upward to the extension structures of the corresponding first selection line, the plurality of word lines and the second selection line via a plurality of connection regions, and are disposed below the plurality of connection regions. Each of the plurality of connection regions extends from the first subarray to the second subarray, and the first selection line, the plurality of word lines and the second selection line of the first subarray are respectively connected one-to-one with the first selection line, the plurality of word lines and the second selection line of the second subarray via each of the extension structures.

17. The three-dimensional memory circuit according to claim 16, characterized in that, The plurality of transmission gates are disposed on one side of the drive circuit and below the plurality of connection areas.

18. The three-dimensional memory circuit according to claim 16, characterized in that, Half of the plurality of transmission gates are disposed on one side of the driving circuit, and the other half of the plurality of transmission gates are disposed on the other side of the driving circuit. The plurality of connection regions also include a plurality of first connection regions and a plurality of second connection regions. The first selection line of the first subarray and the extension structures of the odd-numbered word lines among the plurality of word lines are respectively coupled to half of the plurality of transmission gates via corresponding first connection regions in the plurality of first connection regions. The extension structures of the second selection line of the second subarray and the even-numbered word lines among the plurality of word lines are respectively coupled to the other half of the plurality of transmission gates via corresponding second connection regions in the plurality of second connection regions.

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