Methods, devices, and computer equipment for fast rereading of solid-state drives after UECC error.
The Plane Read retry solution addresses the read performance issues caused by UECC in SSDs, enabling concurrent read retry in multi-plane UECC scenarios and improving read efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUZHOU UNIONMEMORY INFORMATION SYST LTD
- Filing Date
- 2023-08-03
- Publication Date
- 2026-07-31
AI Technical Summary
In solid-state drives (SSDs), NAND flash memory chips are prone to large-scale data flipping during high-low temperature transitions or long-term data retention scenarios, leading to Unfair Data Entry (UECC). In existing technologies, multi-plane UECC data within a die cannot be read retryed concurrently, affecting read performance.
A Plane Read retry scheme was designed. By obtaining the host read command and judging UECC, the read voltage is set simultaneously for the plane where UECC occurs, and the voltage is restored after the data error correction is completed, thus realizing concurrent read retry operation in multi-plane UECC scenarios.
Improved read performance of SSDs in UECC scenarios, ensuring that read and read retry operations of each plane within the die do not interfere with each other, thus improving read efficiency.
Smart Images
Figure CN116798469B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of solid-state drive technology, and in particular to a method, apparatus, computer device, and storage medium for fast rereading of a solid-state drive after UECC occurs. Background Technology
[0002] Solid-state drives (SSDs), as a new type of storage medium, use NAND flash memory chips as their data storage medium. Compared to traditional HDDs, their biggest advantage lies in their significantly higher read and write performance. However, due to the working principle of NAND, the data stored on NAND is prone to bit flipping under certain high-low temperature transitions and long-term data retention scenarios. In the event of a large number of data flips, the controller needs to adjust the read voltage to attempt to retrieve the correct data from the NAND.
[0003] Early NAND flash memory only supported changing the read voltage at the die level. This meant that read commands and voltage-changing commands could only be executed sequentially within a die. If multiple planes within a die encountered UECC (Uncorrectable Error Correction Code), this error correction strategy would significantly impact SSD read performance. This is mainly reflected in two aspects: UECC data in other planes within the die cannot be read retried concurrently, and non-UECC data in other planes within the die cannot be read normally. Summary of the Invention
[0004] Therefore, it is necessary to provide a method, apparatus, computer device, and storage medium for fast rereading of solid-state drives after UECC occurs, in order to address the above-mentioned technical problems.
[0005] A method for fast rereading of a solid-state drive after UECC occurs, the method comprising:
[0006] Obtain the read command issued by the host, and read data from the specified position on the NAND according to the read command;
[0007] Determine if a UECC error occurs when reading page data;
[0008] If UECC occurs, the voltage reading operation will be performed simultaneously on all planes where UECC data is located;
[0009] After the UECC data correction within the Plane is completed, restore the corresponding Plane's read voltage, and then read the data for the next page within the Plane.
[0010] In one embodiment, the step of obtaining a read command issued by the host and reading data from a specified location on the NAND flash memory according to the read command further includes:
[0011] Obtain the read command issued by the host and convert the read command into multiple read commands on the NAND;
[0012] Determine if the Plane is in a retry state; if so, further determine if a UECC occurs on a page within the Plane.
[0013] In one embodiment, the step of further determining whether a UECC occurs in a page within the Plane includes:
[0014] If a bit flip occurs in the page data, it indicates that the page data within the Plane is UECC data.
[0015] In one embodiment, the step following the step of further determining whether a UECC occurs in a page within the Plane includes:
[0016] If a UECC occurs in a page within the Plane, then change the Plane's read voltage;
[0017] If UECC does not appear in the page within the Plane, check if the Plane's read voltage is the default value. If the Plane's read voltage is not the default value, restore it to the default voltage.
[0018] A device for fast rereading of a solid-state drive after UECC (Unauthorized Access Control) error, the device comprising:
[0019] The acquisition module is used to acquire read commands issued by the host and read data from a specified position on the NAND according to the read commands;
[0020] The first judgment module is used to determine whether UECC occurs when reading page data;
[0021] A voltage setting module is used to simultaneously set and read the voltage of all planes containing UECC data if UECC occurs.
[0022] The voltage recovery module is used to restore the reading voltage of the corresponding Plane after the UECC data error correction in the Plane is completed, and then read the next page data in the Plane.
[0023] In one embodiment, the device further includes:
[0024] The command conversion module is used to obtain the read command issued by the host and convert the read command into multiple read commands on the NAND flash memory.
[0025] The second judgment module is used to determine whether the Plane is in a retry state. If so, it further determines whether a UECC occurs in the page within the Plane.
[0026] In one embodiment, the second determining module is used to:
[0027] If a bit flip occurs in the page data, it indicates that the page data within the Plane is UECC data.
[0028] In one embodiment, the second determining module is further configured to:
[0029] If a UECC occurs in a page within the Plane, then change the Plane's read voltage;
[0030] If UECC does not appear in the page within the Plane, check if the Plane's read voltage is the default value. If the Plane's read voltage is not the default value, restore it to the default voltage.
[0031] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of any of the methods described above.
[0032] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the above methods.
[0033] The aforementioned method, apparatus, computer device, and storage medium for fast rereading after a Solid State Drive (SSD) experiences a UECC (Underlying Memory Error Correction) event involve: obtaining a read command from the host and reading data from a specified location on the NAND flash memory according to the command; determining whether a UECC has occurred while reading page data; if a UECC has occurred, simultaneously setting the read voltage for all planes containing the UECC data; restoring the read voltage of the corresponding plane after the UECC data correction is completed, and then reading the next page data within the plane. This invention designs a plane read retry scheme based on NAND flash memory that supports independent plane reads. In multi-plane UECC scenarios, read retry operations can be executed concurrently, and read and read retry operations within each plane of the die do not affect each other, thereby improving the read performance of the SSD in this scenario. Attached Figure Description
[0034] Figure 1 This is a schematic diagram of the interaction of the existing Read retry scheme;
[0035] Figure 2 This is a timing diagram for rereading under the existing Read retry scheme;
[0036] Figure 3 This is a flowchart illustrating a method for fast rereading of a solid-state drive after UECC occurs in one embodiment.
[0037] Figure 4 This is a flowchart illustrating a fast reread method for a solid-state drive after UECC occurs, as described in another embodiment.
[0038] Figure 5 This is a flowchart illustrating a method for fast rereading of a solid-state drive after UECC occurs, as described in another embodiment.
[0039] Figure 6 This is a timing diagram of the reread scheme provided by the present invention;
[0040] Figure 7 This is a structural block diagram of a fast reread device for a solid-state drive after UECC occurs in one embodiment.
[0041] Figure 8 This is a structural block diagram of a fast reread device for a solid-state drive after UECC occurs, as shown in another embodiment.
[0042] Figure 9 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation
[0043] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0044] refer to Figure 1 The diagram shows the interaction of the existing Read retry scheme and Figure 2 The timing diagram of the existing Read retry scheme shown mainly includes the following steps: 1. The host sends a read command to the SSD; 2. After receiving the read command, the SSD reads the data from the specified location on the NAND; 3. If a bit flip occurs in the data on the page, we consider the data to be UECC data; otherwise, proceed to step 6; 4. Set the read voltage for the UECC data appearing in the die; 5. After the data is corrected, restore the read voltage of the die; otherwise, continue to step 4; 6. Read the next page of the die; 7. The software continues to repeat steps 2 to 6 to process subsequent Read commands.
[0045] This shows that this approach has two drawbacks when dealing with a large number of Write commands:
[0046] 1. UECC data in other planes within this die cannot be read and retried concurrently;
[0047] 2. Non-UECC data in the remaining Planes within this Die cannot be read normally.
[0048] This invention addresses the two shortcomings mentioned above by designing a Plane Read retry solution based on NAND flash memory that supports Plane Independent Read, thereby improving the read performance of SSDs.
[0049] In one embodiment, such as Figure 3 As shown, a method for fast rereading after a solid-state drive (SSD) experiences a UECC (User Unknown Error Correction) event is provided. This method includes:
[0050] Step 302: Obtain the read command issued by the host, and read data from the specified location on the NAND according to the read command;
[0051] Step 304: Determine if UECC occurs when reading page data;
[0052] Step 306: If UECC occurs, then simultaneously perform the voltage setting and reading operation on all planes where UECC data is located;
[0053] Step 308: After the UECC data error correction in the Plane is completed, restore the reading voltage of the corresponding Plane, and then read the data of the next page in the Plane.
[0054] In this embodiment, a method for fast rereading after a solid-state drive (SSD) experiences a UECC (Underwriters' Rights Protection) error is provided. This solution incorporates a Plane Read Retry mechanism to address the concurrent reading voltage issues between multiple planes within a die when a UECC error occurs while reading data from the host.
[0055] Specifically, first, the read command issued by the host is obtained, and data is read from the specified position on the NAND according to the read command. Then, it is determined whether UECC occurs when reading page data.
[0056] If a UECC (Unique Variable Correction) occurs, the read voltage will be set simultaneously for all planes containing the UECC data. When multiple planes within a die experience UECC, read retry operations will be executed concurrently. Meanwhile, if other planes do not experience UECC, read commands can continue to be executed; read and read retry operations within different planes of the die do not affect each other.
[0057] Finally, after the UECC data correction within the Plane is completed, the corresponding Plane's read voltage is restored, and then the next page of data within the Plane is read. Subsequently, the above steps of reading data and determining whether UECC has occurred are repeated.
[0058] In this embodiment, a read command is obtained from the host, and data is read from a specified location on the NAND flash memory according to the read command. It is then determined whether UECC (Uncorrected Continuous Error Correction) occurs while reading the page data. If UECC occurs, the read voltage is simultaneously set for all planes containing the UECC data. After the UECC data correction within a plane is completed, the read voltage of the corresponding plane is restored, and then the next page data within the plane is read. This solution is based on a NAND flash memory chip that supports independent plane reads and incorporates a plane read retry scheme. In multi-plane UECC scenarios, read retry operations can be executed concurrently, and the read and read retry operations within each plane of the die do not affect each other, thereby improving the read performance of the SSD in this scenario.
[0059] In one embodiment, such as Figure 4 As shown, a method for fast rereading after a solid-state drive (SSD) experiences a UECC (User Unknown Error Correction) event is provided. This method also includes:
[0060] Step 402: Obtain the read command issued by the host and convert the read command into multiple read commands on the NAND;
[0061] Step 404: Determine if the Plane is in a retry state. If so, further determine if a UECC occurs on the page within the Plane.
[0062] Step 406: If the page data shows a bit flip, it indicates that the page data in the Plane is UECC data;
[0063] Step 408: If a UECC occurs in a page within the Plane, change the Plane's read voltage;
[0064] Step 410: If UECC does not appear in the page of Plane, determine whether the read voltage of Plane is the default value. If the read voltage of Plane is not the default value, restore it to the default voltage.
[0065] Specifically, refer to Figure 5 The method shown is to quickly reread the solid-state drive after UECC occurs. Figure 6 The timing diagram for the read retry scheme provided by this approach is shown below. The implementation steps of this method are as follows:
[0066] Step 5.1. The host sends a read command to the SSD.
[0067] Step 5.2. After receiving the read command, the SSD reads the data from the specified location on the NAND.
[0068] Step 5.3. If the data on the page shows bit flipping, we consider the data to be UECC data; otherwise, proceed to step 5.6.
[0069] Step 5.4. Set the read voltage for all planes containing the UECC data appearing in the Die.
[0070] Step 5.5. After correcting the data of a certain Plane to the correct data, restore the reading voltage of that Plane; otherwise, continue to step 5.4.
[0071] Step 5.6. Read the next page of the Plane.
[0072] Step 5.7. The software continues to repeat steps 5.2 to 5.6 to process subsequent Read commands.
[0073] As can be seen from the above process, when the software detects UECC in multiple planes within the die, it will simultaneously set the read voltage of the corresponding plane and then read the data. Meanwhile, if no UECC occurs in the other planes, the read command can continue to be executed, thus improving the read performance of the SSD when UECC occurs.
[0074] It should be understood that, although Figures 1-6 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figures 1-6 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.
[0075] In one embodiment, such as Figure 7 As shown, a fast reread device 700 for solid-state drives after UECC occurs is provided. The device includes:
[0076] Acquisition module 701 is used to acquire a read command issued by the host and read data from a specified position on the NAND according to the read command;
[0077] First judgment module 702, the first judgment module is used to determine whether UECC occurs when reading page data;
[0078] Voltage setting module 703, the voltage setting module is used to simultaneously set and read the voltage of all planes where UECC data is located if UECC occurs;
[0079] The voltage recovery module 704 is used to restore the reading voltage of the corresponding Plane after the UECC data error correction in the Plane is completed, and then read the next page data in the Plane.
[0080] In one embodiment, such as Figure 8 As shown, a fast reread device 700 for solid-state drives after UECC occurs is provided. The device further includes:
[0081] Command conversion module 705, the command conversion module is used to obtain the read command issued by the host and convert the read command into multiple read commands on the NAND;
[0082] The second judgment module 706 is used to determine whether the Plane is in a retry state. If so, it further determines whether a UECC occurs in the page within the Plane.
[0083] In one embodiment, the second determining module 706 is used for:
[0084] If a bit flip occurs in the page data, it indicates that the page data within the Plane is UECC data.
[0085] In one embodiment, the second determining module 706 is further configured to:
[0086] If a UECC occurs in a page within the Plane, then change the Plane's read voltage;
[0087] If UECC does not appear in the page within the Plane, check if the Plane's read voltage is the default value. If the Plane's read voltage is not the default value, restore it to the default voltage.
[0088] For specific limitations on the fast reread device after UECC occurs on a solid-state drive, please refer to the limitations on the fast reread method after UECC occurs on a solid-state drive mentioned above, which will not be repeated here.
[0089] In one embodiment, a computer device is provided, the internal structure of which can be shown as follows: Figure 9As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and databases. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The network interface is used for communication with external terminals via a network connection. When executed by the processor, the computer program implements a method for fast rereading of a solid-state drive after UECC (Underwriters' Rights Protection) occurs.
[0090] Those skilled in the art will understand that Figure 8 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0091] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps in the various method embodiments described above.
[0092] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the various method embodiments described above.
[0093] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.
[0094] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0095] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for fast rereading of a solid-state drive after UECC occurs, the method comprising: Obtain the read command issued by the host, and read data from the specified position on the NAND according to the read command; Determine if a UECC error occurs when reading page data; If UECC occurs, the voltage reading operation will be performed simultaneously on all planes where UECC data is located; After the UECC data correction within the Plane is completed, restore the corresponding Plane's read voltage, and then read the data for the next page within the Plane. The step of obtaining the read command issued by the host and reading data from a specified location on the NAND according to the read command further includes: Obtain the read command issued by the host and convert the read command into multiple read commands on the NAND; Determine if the Plane is in a retry state; if so, further determine if the page within the Plane contains UECC data. This includes: if the page data shows a bit flip, it indicates that the page data within the Plane is UECC data. The steps following the step of further determining whether a UECC occurs in a page within the Plane also include: If a UECC occurs in a page within the Plane, then change the Plane's read voltage; If UECC does not appear in the page within the Plane, check if the Plane's read voltage is the default value. If the Plane's read voltage is not the default value, restore it to the default voltage.
2. A device for fast re-reading after UECC of a solid state drive, characterized in that, The device includes: The acquisition module is used to acquire read commands issued by the host and read data from a specified position on the NAND according to the read commands; The first judgment module is used to determine whether UECC occurs when reading page data; A voltage setting module is used to simultaneously set and read the voltage of all planes containing UECC data if UECC occurs. The voltage recovery module is used to restore the reading voltage of the corresponding Plane after the UECC data in the Plane has been corrected, and then read the data of the next page in the Plane. The command conversion module is used to obtain the read command issued by the host and convert the read command into multiple read commands on the NAND flash memory. The second judgment module is used to determine whether the Plane is in a retry state. If so, it further determines whether the page in the Plane contains UECC data. If the page data shows bit flipping, it indicates that the page data in the Plane is UECC data. The second judgment module is also used for: If a UECC occurs in a page within the Plane, then change the Plane's read voltage; If UECC does not appear in the page within the Plane, check if the Plane's read voltage is the default value. If the Plane's read voltage is not the default value, restore it to the default voltage.
3. A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method of claim 1.
4. A computer-readable storage medium having a computer program stored thereon, characterized in that, The computer program, which is executed by a processor, implements the steps of the method as claimed in claim 1.