Electronic device and driving method thereof

Abstract

This disclosure relates to the field of storage technology, providing an electronic device and its driving method. The electronic device includes a sensitive amplifier and a voltage regulation circuit. The sensitive amplifier includes a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, and a control circuit. The control circuit is connected to a third node, a fourth node, a preset voltage terminal, and a first control signal terminal, and is used to connect the preset voltage terminal and the third and fourth nodes in response to a signal from the first control signal terminal. The voltage regulation circuit is connected to the preset voltage terminal and a regulation signal terminal, and is used to input a preset voltage signal to the preset voltage terminal according to the regulation signal from the regulation signal terminal. This electronic device can write a preset voltage signal of appropriate size to the sensitive amplifier through the voltage regulation circuit, so that the sensitive amplifier has an appropriate voltage difference between the bit line and the complementary bit line during the offset cancellation stage.

Description

Technical Field

[0001] This disclosure relates to the field of storage technology, and more particularly to an electronic device and a driving method thereof. Background Technology

[0002] In related technologies, sensitive amplifiers typically include two P-type transistors and two N-type transistors, which are used to amplify the signals of the bit lines and complementary bit lines.

[0003] The semiconductor devices that make up a sensitive amplifier may have different device characteristics (e.g., threshold voltage) due to factors such as process variations and temperature. Different device characteristics can cause offset noise in the sensitive amplifier, which reduces the effective read margin of the sensitive amplifier, resulting in reduced data read accuracy and degrading memory data performance.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] According to one aspect of this disclosure, an electronic device is provided, comprising: a sensitive amplifier and a voltage regulation circuit. The sensitive amplifier includes: a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, and a control circuit. The first P-type transistor has a first terminal connected to a first node, a second terminal connected to a readout bit line, and a gate connected to a third node. The second P-type transistor has a first terminal connected to the first node, a second terminal connected to a complementary readout bit line, and a gate connected to a fourth node. The first N-type transistor has a first terminal connected to a second node, a second terminal connected to the readout bit line, and a gate connected to the bit line. The second N-type transistor has a first terminal connected to the second node, a second terminal connected to the complementary readout bit line, and a gate connected to the complementary bit line. The control circuit is connected to the third node, the fourth node, a preset voltage terminal, and a first control signal terminal, and is used to connect the preset voltage terminal and the third node and the fourth node in response to a signal from the first control signal terminal. The voltage regulation circuit is connected to the preset voltage terminal and a regulation signal terminal, and is used to input a preset voltage signal to the preset voltage terminal according to a regulation signal from the regulation signal terminal.

[0006] In an exemplary embodiment of this disclosure, the adjustment signal terminal includes multiple sub-adjustment signal terminals; the voltage adjustment circuit includes: an operational amplifier and a first adjustment unit, the non-inverting input terminal of the operational amplifier is connected to a reference voltage terminal, the inverting input terminal is connected to a fifth node, the fifth node is connected to a ground terminal, and the output terminal is connected to the preset voltage terminal; the first adjustment unit is connected to the fifth node and the output terminal of the operational amplifier, and the first adjustment unit includes: at least one first resistor and at least one first switch, the at least one first resistor is connected in series between the fifth node and the output terminal of the operational amplifier; the first switch is correspondingly arranged with the first resistor and correspondingly arranged with the sub-adjustment signal terminals, the first end and the second end of the first switch are respectively connected to the two ends of the corresponding first resistor, and the control terminal of the first switch unit is connected to the corresponding sub-adjustment signal terminal.

[0007] In an exemplary embodiment of this disclosure, the adjustment signal terminal includes multiple sub-adjustment signal terminals; the voltage adjustment circuit includes: an operational amplifier and a second adjustment unit, the non-inverting input terminal of the operational amplifier is connected to a reference voltage terminal, the inverting input terminal is connected to a fifth node, the fifth node is connected to the output terminal of the operational amplifier, and the output terminal is connected to the preset voltage terminal; the second adjustment unit is connected between the fifth node and a ground terminal, and the second adjustment unit includes: at least one second resistor and at least one second switch, the at least one second resistor is connected in series between the fifth node and the ground terminal; the second switch is correspondingly arranged with the second resistor and correspondingly arranged with the sub-adjustment signal terminals, the first end and the second end of the second switch are respectively connected to the two ends of the corresponding second resistor, and the control terminal of the second switch unit is connected to the corresponding sub-adjustment signal terminal.

[0008] In one exemplary embodiment of this disclosure, the voltage regulation circuit further includes: a second regulation unit connected between the fifth node and the ground terminal; the second regulation unit includes: at least one second resistor and at least one second switch; the at least one second resistor is connected in series between the fifth node and the ground terminal; the second switch is configured corresponding to the second resistor and corresponding to the sub-regulation signal terminal; the first end and the second end of the second switch are respectively connected to the two ends of the corresponding second resistor; and the control terminal of the second switch unit is connected to the corresponding sub-regulation signal terminal.

[0009] In one exemplary embodiment of this disclosure, each of the first resistors has the same resistance value, or at least some of the first resistors have different resistance values; each of the second resistors has the same resistance value, or at least some of the second resistors have different resistance values.

[0010] In one exemplary embodiment of this disclosure, at least one first resistor includes two first resistors, and at least one second resistor includes two second resistors.

[0011] In one exemplary embodiment of this disclosure, the electronic device further includes: a signal generation circuit connected to the adjustment signal terminal, used to input the adjustment signal to the adjustment signal terminal according to a preset control signal.

[0012] In one exemplary embodiment of this disclosure, the control circuit includes: a first transistor and a second transistor, wherein the first terminal of the first transistor is connected to the third node, the second terminal is connected to the preset voltage terminal, and the gate is connected to the first control signal terminal; the first terminal of the second transistor is connected to the fourth node, the second terminal is connected to the preset voltage terminal, and the gate is connected to the first control signal terminal; wherein the first transistor and the second transistor are both N-type transistors or both P-type transistors.

[0013] In one exemplary embodiment of this disclosure, the sensitive amplifier further includes: a first isolation circuit, which connects the readout bit line, the complementary readout bit line, the third node, the fourth node, and the second control signal terminal. The first isolation circuit is used to connect the readout bit line and the fourth node in response to a signal from the second control signal terminal, and to connect the complementary readout bit line and the third node.

[0014] In one exemplary embodiment of this disclosure, the first isolation circuit includes: a third transistor and a fourth transistor, wherein the first terminal of the third transistor is connected to the readout bit line, the second terminal is connected to the fourth node, and the gate is connected to the second control signal terminal; the first terminal of the fourth transistor is connected to the complementary readout bit line, the second terminal is connected to the third node, and the gate is connected to the second control signal terminal; wherein the third transistor and the fourth transistor are both N-type transistors or both P-type transistors.

[0015] In one exemplary embodiment of this disclosure, the sensitive amplifier further includes: an offset cancellation circuit, a second isolation circuit, and a voltage equalization circuit. The offset cancellation circuit is connected to the bit line, the complementary bit line, the readout bit line, the complementary readout bit line, and a first control signal terminal, and is used to connect the bit line and the readout bit line in response to a signal from the first control signal terminal, and is also used to connect the complementary bit line and the complementary readout bit line in response to a signal from the first control signal terminal. The second isolation circuit is connected to the bit line, the complementary bit line, the readout bit line, the complementary readout bit line, and a third control signal terminal, and is used to connect the bit line and the complementary readout bit line in response to a signal from the third control signal terminal, and is also used to connect the complementary bit line and the readout bit line in response to a signal from the third control signal terminal. The voltage equalization circuit is connected to the readout bit line, the complementary readout bit line, and a fourth control signal terminal, and is used to connect the readout bit line and the complementary readout bit line in response to a signal from the fourth control signal terminal.

[0016] In one exemplary embodiment of this disclosure, the offset cancellation circuit includes: a fifth transistor and a sixth transistor, wherein the first terminal of the fifth transistor is connected to the bit line, the second terminal is connected to the readout bit line, and the gate is connected to the first control signal terminal; the first terminal of the sixth transistor is connected to the complementary bit line, the second terminal is connected to the complementary readout bit line, and the gate is connected to the first control signal terminal; wherein the fifth transistor and the sixth transistor are both N-type transistors or both P-type transistors.

[0017] In one exemplary embodiment of this disclosure, the second isolation circuit includes a seventh transistor and an eighth transistor. The first terminal of the seventh transistor is connected to the bit line, the second terminal is connected to the complementary readout bit line, and the gate is connected to the third control signal terminal. The first terminal of the eighth transistor is connected to the complementary bit line, the second terminal is connected to the readout bit line, and the gate is connected to the third control signal terminal. The seventh transistor and the eighth transistor are both N-type transistors or both P-type transistors.

[0018] In one exemplary embodiment of this disclosure, the voltage equalization circuit includes: a ninth transistor, the first terminal of the ninth transistor being connected to the readout bit line, the second terminal being connected to the complementary readout bit line, and the gate being connected to the fourth control signal terminal.

[0019] In one exemplary embodiment of this disclosure, the electronic device further includes a programmable fuse circuit connected to the signal generation circuit and used to input the preset control signal to the signal generation circuit.

[0020] In one exemplary embodiment of this disclosure, the electronic device further includes: a test signal terminal connected to the signal generation circuit, used to input different test control signals to the signal generation circuit during the test phase.

[0021] In one exemplary embodiment of this disclosure, the electronic device is a memory.

[0022] According to one aspect of this disclosure, an electronic device driving method is provided, the driving method being used to drive the aforementioned electronic device, the driving method comprising:

[0023] During the testing phase, different control signals are input to the signal generation circuit using the test signal terminal to obtain the optimal voltage at the preset voltage terminal;

[0024] During the driving phase, the programmable fuse circuit is used to input the control signal corresponding to the optimal voltage to the signal generation circuit.

[0025] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0026] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0027] Figure 1 This is a schematic diagram of the structure of an exemplary embodiment of the sensitive amplifier disclosed herein;

[0028] Figure 2 for Figure 1 The timing diagram of each node in a driving method for a sensitive amplifier is shown.

[0029] Figure 3 for Figure 1 The equivalent state diagram of the sensitive amplifier during the precharge phase is shown.

[0030] Figure 4 for Figure 1 The equivalent state diagram of the sensitive amplifier during the offset cancellation stage is shown.

[0031] Figure 5 for Figure 1 The equivalent state diagram of the sensitive amplifier during the charge sharing phase is shown.

[0032] Figure 6 for Figure 1 The equivalent state diagram of the sensitive amplifier in the pre-sensing stage is shown.

[0033] Figure 7 for Figure 1 The equivalent state diagram of the sensitive amplifier during the amplification stage is shown below.

[0034] Figure 8 This is a schematic diagram of the structure of an exemplary embodiment of the electronic device disclosed herein;

[0035] Figure 9 This is a schematic diagram of the voltage regulation circuit in an exemplary embodiment of the electronic device disclosed herein;

[0036] Figure 10 This is a schematic diagram of another exemplary embodiment of the electronic device disclosed herein. Detailed Implementation

[0037] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0038] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0039] This exemplary embodiment first provides a sensitive amplifier, such as Figure 1 The diagram shown is a schematic representation of an exemplary embodiment of the sensitive amplifier disclosed herein. The sensitive amplifier may include: a first P-type transistor PM1, a second P-type transistor PM2, a first N-type transistor NM1, a second N-type transistor NM2, and a control circuit 1. The first P-type transistor PM1 has its first terminal connected to a first node PCS, its second terminal connected to a read bit line SABLT, and its gate connected to a third node ISB. The second P-type transistor PM2 has its first terminal connected to the first node PCS, its second terminal connected to a complementary read bit line SABLT, and its gate connected to a fourth node IST. The first N-type transistor NM1 has its first terminal connected to a second node NCS, its second terminal connected to the read bit line SABLT, and its gate connected to bit line BLT. The second N-type transistor NM2 has its first terminal connected to the second node NCS, its second terminal connected to the complementary read bit line SABLT, and its gate connected to the complementary bit line BLB. The control circuit 1 is connected to the third node ISB, the fourth node IST, a preset voltage terminal VB, and a first control signal terminal OC, and is used to connect the preset voltage terminal VB and the third node ISB and the fourth node IST in response to a signal from the first control signal terminal OC.

[0040] During the offset cancellation phase, the sensitive amplifier can connect the preset voltage terminal VB, the third node ISB, and the fourth node IST using control circuit 1. This allows the conduction levels of the first P-type transistor PM1 and the second P-type transistor PM2 to be adjusted by controlling the voltage at the preset voltage terminal VB, thereby canceling the offset of PM1 and PM2. Simultaneously, it stabilizes the voltages of bit line BLT and complementary bit line BLB, ensuring the voltage difference between BLT and BLB remains within a suitable range.

[0041] In this exemplary embodiment, as Figure 1 As shown, the control circuit 1 may include: a first transistor M1 and a second transistor M2. The first transistor M1 has its first terminal connected to the third node ISB, its second terminal connected to the preset voltage terminal VB, and its gate connected to the first control signal terminal OC. The second transistor M2 has its first terminal connected to the fourth node IST, its second terminal connected to the preset voltage terminal VB, and its gate connected to the first control signal terminal OC. The first transistor M1 and the second transistor M2 may both be N-type transistors. It should be understood that in other exemplary embodiments, the first transistor M1 and the second transistor M2 may also both be P-type transistors.

[0042] In this exemplary embodiment, as Figure 1 As shown. The sensitive amplifier may further include: a first isolation circuit 2, which connects the readout bit line SABLT, the complementary readout bit line SABLB, the third node ISB, the fourth node IST, and the second control signal terminal ISOP. The first isolation circuit 2 is used to connect the readout bit line SABLT and the fourth node IST in response to the signal of the second control signal terminal ISOP, and to connect the complementary readout bit line SABLB and the third node ISB.

[0043] In this exemplary embodiment, as Figure 1 As shown, the first isolation circuit 2 may include: a third transistor M3 and a fourth transistor M4. The first terminal of the third transistor M3 is connected to the readout bit line SABLT, the second terminal is connected to the fourth node IST, and the gate is connected to the second control signal terminal ISOP. The first terminal of the fourth transistor M4 is connected to the complementary readout bit line SABLB, the second terminal is connected to the third node ISB, and the gate is connected to the second control signal terminal ISOP. The third transistor M3 and the fourth transistor M4 may both be N-type transistors. It should be understood that in other exemplary embodiments, the third transistor M3 and the fourth transistor M4 may also both be P-type transistors.

[0044] In this exemplary embodiment, as Figure 1As shown, the sensitive amplifier may further include: an offset cancellation circuit 5, a second isolation circuit 3, and a voltage equalization circuit 4. The offset cancellation circuit 5 is connected to the bit line BLT, the complementary bit line BLB, the read bit line SABLT, the complementary read bit line SABLT, and the first control signal terminal OC. It is used to connect the bit line BLT and the read bit line SABLT in response to the signal of the first control signal terminal OC, and is also used to connect the complementary bit line BLB and the complementary read bit line SABLT in response to the signal of the first control signal terminal OC. The second isolation circuit 3 is connected to the bit line BLT, the complementary bit line BLB, the read bit line SABLT, and the first control signal terminal OC. The system includes a bit line SABLT, a complementary read bit line SABLB, and a third control signal terminal ISON, used to connect the bit line BLT and the complementary read bit line SABLB in response to the signal of the third control signal terminal ISON, and also used to connect the complementary bit line BLB and the read bit line SABLT in response to the signal of the third control signal terminal ISON; a voltage equalization circuit 4 connects the read bit line SABLT, the complementary read bit line SABLB, and a fourth control signal terminal EQ, used to connect the read bit line SABLT and the complementary read bit line SABLB in response to the signal of the fourth control signal terminal EQ.

[0045] In this exemplary embodiment, as Figure 1 As shown, the offset cancellation circuit 5 includes a fifth transistor M5 and a sixth transistor M6. The first terminal of the fifth transistor M5 is connected to the bit line BLT, the second terminal is connected to the readout bit line SABLT, and the gate is connected to the first control signal terminal OC. The first terminal of the sixth transistor M6 is connected to the complementary bit line BLB, the second terminal is connected to the complementary readout bit line SABLT, and the gate is connected to the first control signal terminal OC. The fifth transistor M5 and the sixth transistor M6 can both be N-type transistors. It should be understood that in other exemplary embodiments, the fifth transistor M5 and the sixth transistor M6 can also both be P-type transistors.

[0046] In this exemplary embodiment, as Figure 1 As shown, the second isolation circuit 3 may include: a seventh transistor M7 and an eighth transistor M8. The first terminal of the seventh transistor M7 is connected to the bit line BLT, the second terminal is connected to the complementary readout bit line SABLB, and the gate is connected to the third control signal terminal ISON. The first terminal of the eighth transistor M8 is connected to the complementary bit line BLB, the second terminal is connected to the readout bit line SABLT, and the gate is connected to the third control signal terminal ISON. The seventh transistor M7 and the eighth transistor M8 may both be N-type transistors. It should be understood that in other exemplary embodiments, the seventh transistor M7 and the eighth transistor M8 may also both be P-type transistors.

[0047] In this exemplary embodiment, as Figure 1 As shown, the voltage equalization circuit 4 may include: a ninth transistor M9, the first terminal of the ninth transistor M9 being connected to the readout bit line SABLT, the second terminal being connected to the complementary readout bit line SABLB, and the gate being connected to the fourth control signal terminal EQ. The ninth transistor M7 may be an N-type transistor.

[0048] like Figure 1 As shown, the bit line BLT can be connected to one electrode of the first capacitor C1 via the tenth transistor M10, and the gate of the tenth transistor M10 can be connected to the first word line WL-UP. The complementary bit line BLB can be connected to the first electrode of the second capacitor C2 via the eleventh transistor M11, and the gate of the eleventh transistor M11 can be connected to the second word line WL-DN.

[0049] like Figure 2 As shown, Figure 1 The diagram shows the timing diagrams of each node in a driving method for a sensitive amplifier. Here, EQ is the timing diagram for the fourth control signal terminal, ISON is the timing diagram for the third control signal terminal, ISP is the timing diagram for the second control signal terminal, OC is the timing diagram for the first control signal terminal, WL-UP is the timing diagram for the first word line, PCS (dashed line) is the timing diagram for the first node, NCS is the timing diagram for the second node, SABLT (dashed line) is the timing diagram for the readout bit line, SABLB (solid line) is the timing diagram for the complementary readout bit line, BLT (dashed line) is the timing diagram for the bit line, and BLB (solid line) is the timing diagram for the complementary bit line.

[0050] like Figure 2 As shown, the driving method of the sensitive amplifier may include five stages: pre-charge stage t1, offset cancellation stage t2, charge sharing stage t3, pre-sensing stage t4, and amplification stage t5.

[0051] During the pre-charge phase t1, high-level signals are provided to the fourth control signal terminal EQ, the third control signal terminal ISON, the second control signal terminal ISOP, and the first control signal terminal OC. For example... Figure 3 As shown, Figure 1 The diagram shows the equivalent state of the sensitive amplifier during the pre-charge phase. In this diagram, transistors M1, M2, M3, M4, M5, M6, M7, M8, and M9 are all turned on. The preset voltage terminal VB writes a preset voltage signal to bit line BLT, complementary bit line BLB, readout bit line SABLT, and complementary readout bit line SABLB. The first node PCS and the second node NCS can maintain the preset voltage signal through an external voltage.

[0052] During the offset cancellation phase t2, low-level signals can be provided to the fourth control signal terminal EQ, the third control signal terminal ISON, and the second control signal terminal IOP, while a high-level signal can be provided to the first control signal terminal OC. Simultaneously, a first power signal is provided to the first node PCS and a second power signal is provided to the second node NCS via an external power supply. The first power signal has a first voltage, and the second power signal can be a signal from the ground terminal.

[0053] like Figure 4 As shown, Figure 1 The diagram shows the equivalent state of the sensitive amplifier during the offset cancellation phase. Transistors M3, M4, M7, M8, and M9 are off, while M1, M2, M5, and M6 are on. P-type transistors PM1 and PM2 are on under the influence of a preset voltage signal at the preset voltage terminal VB. The first node PCS is connected to the read bit line SABLT and the complementary read bit line SABLB, respectively. Simultaneously, the first N-type transistor NM1 is on under the influence of the signal at bit line BLT, and the second N-type transistor NM2 is on under the influence of the signal at the complementary bit line BLB. The second node NCS is connected to both the read bit line SABLT and the complementary read bit line SABLB, respectively. Ultimately, due to the threshold differences between the first P-type transistor PM1, the second P-type transistor PM2, the first N-type transistor NM1, and the second N-type transistor NM2, a voltage difference exists between the bit line BLT and the complementary bit line BLB. Thus, in the charge sharing stage t3, the pre-sensing stage t4, and the amplification stage t5, the first N-type transistor NM1 and the second N-type transistor NM2, or the first P-type transistor PM1 and the second P-type transistor PM2, can be controlled by the bit line BLT with a certain voltage difference and the complementary bit line BLB, thereby achieving offset elimination of the first N-type transistor NM1 and the second N-type transistor NM2, and the first P-type transistor PM1 and the second P-type transistor PM2.

[0054] The sensitive amplifier in this embodiment can achieve offset cancellation not only for N-type transistors but also for P-type transistors. Specifically, the conduction levels of the first P-type transistor PM1 and the second P-type transistor PM2 can be stably controlled by controlling the preset voltage signal at the preset voltage terminal VB. This avoids the conduction of the first P-type transistor PM1 and the second P-type transistor PM2 being affected by the voltage difference between the bit line BLT and the complementary bit line BLB. Simultaneously, it maintains a stable potential difference between the bit line BLT and the complementary bit line BLB during the offset cancellation phase, ensuring that the voltage difference between the bit line BLT and the complementary bit line BLB is within a suitable voltage range. Within this suitable voltage range, the potential difference between the bit line BLT and the complementary bit line BLB can achieve a good offset cancellation effect, and the bit line BLT and the complementary bit line BLB can be easily sensed and amplified by the sensitive amplifier.

[0055] During the charge sharing phase t3, low-level signals can be provided to the first control signal terminal OC and the third control signal terminal ISON, while high-level signals can be provided to the fourth control signal terminal EQ, the second control signal terminal ISOP, and the first word line WL-UP. For example... Figure 5 As shown, Figure 1 The diagram shows the equivalent state of the sensitive amplifier during the charge-sharing phase. Transistors M3, M4, and M9 are all turned on, while M1, M2, M5, M6, M7, and M8 are all turned off. Based on the fourth control signal terminal EQ, the potentials of the read bit line SABLT and the complementary read bit line SABLB are the same. Since the first node PCS and the second node NCS are set to the voltage of the preset voltage signal, the potentials of the read bit line SABLT and the complementary read bit line SABLB will recover to the voltage of the preset voltage signal.

[0056] Simultaneously, based on the high-level signal of the first word line WL-UP, the data stored in the first capacitor C1 will be transmitted to the bit line BLT. For example, when the data stored in the first capacitor C1 is logic 0, the voltage of the bit line BLT will decrease.

[0057] During the pre-sensing phase t4, low-level signals can be provided to the first control signal terminal OC and the fourth control signal terminal EQ, while high-level signals can be provided to the third control signal terminal ISON, the second control signal terminal ISP, and the first word line WL-UP. For example... Figure 6 As shown, Figure 1 The diagram shows the equivalent state of the sensitive amplifier during the pre-sensing phase. Transistors M3, M4, M7, and M8 are all on, while M1, M2, M5, M6, and M9 are all off. The complementary readout bit line SABLB is connected to the bit line BLT, and the readout bit line SABLT is connected to the complementary bit line BLB. The voltage of the complementary readout bit line SABLB decreases slightly under the influence of bit line BLT.

[0058] During the amplification stage t5, low-level signals can be provided to the first control signal terminal OC and the fourth control signal terminal EQ, while high-level signals can be provided to the third control signal terminal ISON, the second control signal terminal ISOP, and the first word line WL-UP. For example... Figure 7 As shown, Figure 1The diagram shows the equivalent state of the sensitive amplifier during the amplification stage. Simultaneously, a first power supply signal is provided to the first node PCS, and a second power supply signal is provided to the second node NCS. The third transistor M3, fourth transistor M4, seventh transistor M7, and eighth transistor M8 are all turned on, while the first transistor M1, second transistor M2, fifth transistor M5, sixth transistor M6, and ninth transistor M9 are all turned off. The first P-type transistor PM1 is turned on under the low-level voltage of the complementary read bit line SABLB, and the read bit line SABLT is pulled up to a high potential by the first node PCS. The second N-type transistor NM2 is turned on under the voltage of the read bit line SABLT, and the potential of the complementary read bit line SABLB is further pulled down by the second node NCS, thereby amplifying the voltages of the read bit line SABLT and the complementary read bit line SABLB. The amplified signals can be read out to the bit line BLT and the complementary bit line BLB, respectively, and data recovery is performed on the potential of the first capacitor C1 through the bit line BLT.

[0059] This exemplary embodiment also provides an electronic device, such as Figure 8 The diagram shown is a schematic representation of an exemplary embodiment of the electronic device disclosed herein. The electronic device may include the aforementioned sensitive amplifier SA and voltage regulation circuit 6. Voltage regulation circuit 6 may be connected to the preset voltage terminal VB and the adjustment signal terminal TRIM of the sensitive amplifier SA, and is used to input a preset voltage signal to the preset voltage terminal VB according to the adjustment signal of the adjustment signal terminal TRIM.

[0060] In this exemplary embodiment, as Figure 9 The diagram shown is a schematic representation of the voltage regulation circuit in an exemplary embodiment of the electronic device disclosed herein. Figure 9As shown, the adjustment signal terminal TRIM includes multiple sub-adjustment signal terminals TRIM1, TRIM2, TRIM3, and TRIM4. The voltage adjustment circuit 6 may include: an operational amplifier 61 and a first adjustment unit 62. The non-inverting input terminal of the operational amplifier 61 is connected to the reference voltage terminal Vref, and the inverting input terminal is connected to the fifth node N5. The fifth node N5 is connected to the ground terminal GND, and the output terminal is connected to the preset voltage terminal VB. The first adjustment unit 62 is connected between the fifth node N5 and the output terminal of the operational amplifier. The first adjustment unit 62 may include: multiple first resistors R11 and R12, and multiple first switches T11 and T12. The multiple first resistors R11 and R12 are connected in series between the fifth node N5 and the operational amplifier. The first switch is connected to the output terminal of the device; the first switch is configured to correspond to the first resistor and to the sub-adjustment signal terminal. For example, the first switch T11 is configured to correspond to the first resistor R11 and the sub-adjustment signal terminal TRIM1, and the sub-adjustment signal terminal TRIM1 controls the conduction of the first switch T11. The first switch T12 is configured to correspond to the first resistor R12 and the sub-adjustment signal terminal TRIM2, and the sub-adjustment signal terminal TRIM2 controls the conduction of the first switch T12. The first end and the second end of the first switch are respectively connected to the two ends of the corresponding first resistor. The control terminal of the first switch unit is connected to the corresponding sub-adjustment signal terminal.

[0061] In this exemplary embodiment, as Figure 9 As shown, the voltage regulation circuit may further include a second regulation unit 63, which is connected between the fifth node N5 and the ground terminal GND. The second regulation unit 63 may include multiple second resistors R21 and R22, and multiple second switches T21 and T22. The multiple second resistors R21 and R22 are connected in series between the fifth node N5 and the ground terminal GND. The second switches are configured corresponding to the second resistors and to the sub-regulation signal terminals. For example, the second switch T21 is configured corresponding to the second resistor R21 and the sub-regulation signal terminal TRIM3, and the sub-regulation signal terminal TRIM3 controls the conduction of the second switch T21. The second switch T22 is configured corresponding to the second resistor R22 and the sub-regulation signal terminal TRIM4, and the sub-regulation signal terminal TRIM4 controls the conduction of the second switch T22. The first and second ends of the second switches are respectively connected to the two ends of their corresponding second resistors, and the control terminal of the second switch unit is connected to its corresponding sub-regulation signal terminal.

[0062] In this exemplary embodiment, the voltage at the operational amplifier output terminal is V = Vref(1 + R1 / R2). Here, Vref is the voltage at the reference voltage terminal, R1 is the total resistance of the first resistor connected in series between the fifth node and the operational amplifier output terminal, and R2 is the total resistance of the second resistor connected in series between the fifth node and the ground terminal GND. This exemplary embodiment can control the opening and closing of the first switches T11 and T12 and the second switches T21 and T22 via the sub-adjustment signal terminal, thereby controlling the total resistance value R1 of the first resistor connected in series between the fifth node and the operational amplifier output terminal, and controlling the total resistance value R2 of the second resistor connected in series between the fifth node and the ground terminal, thereby controlling the voltage at the operational amplifier output terminal. For example, when the first switches T11 and T12 and the second switches T21 and T22 are both off, the voltage V at the output of the operational amplifier is V = Vref × [1 + (R11 + R12) / (R21 + R22)]. As another example, when the first switch T11 is on, the first switch T12 is off, and the second switches T21 and T22 are both off, the voltage V at the output of the operational amplifier is V = Vref × [1 + R12 / (R21 + R22)]. Where R11 is the resistance of the first resistor R11, R12 is the resistance of the first resistor R12, R21 is the resistance of the second resistor R21, and R22 is the resistance of the second resistor R22.

[0063] In this exemplary embodiment, the first adjustment unit 62 may include two first resistors and two first switches, and the second adjustment unit 63 may include two second resistors and two second switches. It should be understood that in other exemplary embodiments, the number of first resistors and second resistors may be other quantities; for example, the number of both first resistors and second resistors may be one or more. Furthermore, in other exemplary embodiments, the first adjustment unit 62 may not include a first switch unit; that is, in the first adjustment unit 62, the total resistance value of the first resistors connected in series between the fifth node N5 and the operational amplifier output terminal is a constant value. This setting allows the voltage at the operational amplifier output terminal to be adjusted solely by adjusting the total resistance value of the second resistors connected in series between the fifth node N5 and the ground terminal GND. Similarly, the second adjustment unit 63 may not include a second switch unit; that is, in the second adjustment unit 63, the total resistance value of the second resistors connected in series between the fifth node N5 and the ground terminal GND is a constant value. This setting allows the voltage at the operational amplifier output terminal to be adjusted solely by adjusting the total resistance value of the first resistors connected in series between the fifth node and the operational amplifier output terminal.

[0064] In this exemplary embodiment, each of the first resistors has the same resistance value, or at least some of the first resistors have different resistance values; each of the second resistors has the same resistance value, or at least some of the second resistors have different resistance values.

[0065] In this exemplary embodiment, as Figure 10 The diagram shown is a structural schematic of another exemplary embodiment of the electronic device disclosed herein. The electronic device may further include: a signal generation circuit 7, connected to the adjustment signal terminal TRIM, for inputting the adjustment signal to the adjustment signal terminal TRIM according to a preset control signal.

[0066] In this exemplary embodiment, as Figure 10 As shown, the electronic device further includes a test signal terminal Test, which is connected to the signal generation circuit 7. The test signal terminal Test can be used to input different test control signals to the signal generation circuit during the test phase to obtain the optimal voltage of the preset voltage terminal VB. This optimal voltage can ensure that the voltage difference between the bit line BLT and the complementary bit line BLB of the sensitive amplifier SA is within a stable range during the offset cancellation phase, thereby improving the offset cancellation effect of each device in the sensitive amplifier SA. At the same time, the bit line BLT and the complementary bit line BLB can be easily amplified by the sensitive amplifier.

[0067] In this exemplary embodiment, as Figure 10 As shown, the electronic device may further include: a programmable fuse circuit 8, which can be connected to the signal generation circuit 7, and can be used to input the control signal corresponding to the optimal voltage to the signal generation circuit 7 during the driving phase.

[0068] The programmable fuse circuit 8 includes multiple programmable fuses. Each programmable fuse outputs a different signal depending on whether it is in a blown state. For example, when the programmable fuse is not blown, it cannot conduct the input voltage and outputs a logic signal "0"; when the programmable fuse is blown, it can conduct the input voltage and outputs a logic signal "1". Thus, multiple control signals can be output through multiple programmable fuses. In this exemplary embodiment, the number of programmable fuses is the same as the number of the first and second switches. During the testing phase, by continuously inputting different test signals, the signal generation circuit outputs different control signals to control the number of closed switches in the voltage regulation circuit, continuously adjusting the output voltage of the voltage regulation circuit 6. Under the optimal test signal, the optimal voltage required by the sensitive amplifier SA, i.e., the voltage of the preset voltage signal, is obtained. Then, some programmable fuses are controlled to burn out to form the optimal test signal. The optimal test signal is a fixed signal. When the memory is working, the signal generation circuit 7 obtains the state of each device in the programmable fuse circuit 8 to generate the optimal control signal, and the voltage regulation circuit 6 generates the preset voltage according to the optimal control signal.

[0069] In this exemplary embodiment, as Figure 10As shown, the electronic device is a memory. This electronic device may further include a memory cell array 9, a row decoder 10, a column decoder 11, and a control unit 12. The memory cell array 9 includes multiple memory cells arranged in rows and columns. The control unit 12 can be used to send the address of the memory cell, which may include both row and column addresses. Simultaneously, the control unit 12 can control the sensitive amplifier SA to enter... Figure 2 The process includes a pre-charge phase t1 and an offset elimination phase t2. The control unit 12 can also open the corresponding row storage cell through the row decoder 10, so that the row sensitive amplifier SA can start entering the charge sharing phase t3, the pre-sensing phase t4, and the amplification phase t5. After the sensitive amplifier SA senses the data from the storage cell, the control unit 12 can open the desired sensitive amplifier SA through the column decoder 11, thereby transmitting the data sensed by the sensitive amplifier SA.

[0070] This exemplary embodiment also provides an electronic device driving method for driving the aforementioned electronic device, the driving method comprising:

[0071] During the testing phase, different control signals are input to the signal generation circuit using the test signal terminal to obtain the optimal voltage of the preset voltage terminal VB.

[0072] During the driving phase, the programmable fuse circuit is used to input the control signal corresponding to the optimal voltage to the signal generation circuit.

[0073] The driving phase is the formal operating phase of the memory, which includes the sensitive amplifier SA. Before the memory officially starts operating, it needs to undergo a lot of testing to ensure that the memory parameters are stable.

[0074] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0075] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. An electronic device, comprising: include: Sensitive amplifier, the sensitive amplifier comprising: The first P-type transistor has its first terminal connected to the first node, its second terminal connected to the read bit line, and its gate connected to the third node. The second P-type transistor has its first terminal connected to the first node, its second terminal connected to the complementary readout bit line, and its gate connected to the fourth node. The first N-type transistor has its first terminal connected to the second node, its second terminal connected to the readout bit line, and its gate connected to the bit line. The second N-type transistor has its first terminal connected to the second node, its second terminal connected to the complementary readout bit line, and its gate connected to the complementary bit line. A control circuit, connected to the third node, the fourth node, a preset voltage terminal, and a first control signal terminal, is used to connect the preset voltage terminal and the third node and the fourth node in response to a signal from the first control signal terminal; wherein the preset voltage terminal and the first node are independent and different nodes. A voltage regulation circuit, connected to the preset voltage terminal and the regulation signal terminal, is used to adjust the voltage value of the preset voltage signal input to the preset voltage terminal according to the regulation signal of the regulation signal terminal; The control circuit includes: The first transistor has a first terminal connected to the third node, a second terminal connected to the preset voltage terminal, and a gate connected to the first control signal terminal. The second transistor has its first terminal connected to the fourth node, its second terminal connected to the preset voltage terminal, and its gate connected to the first control signal terminal. The first transistor and the second transistor are either both N-type transistors or both P-type transistors.

2. The electronic device of claim 1, wherein, The adjustment signal terminal includes multiple sub-adjustment signal terminals; The voltage regulation circuit includes: An operational amplifier has its non-inverting input connected to a reference voltage terminal, its inverting input connected to a fifth node, the fifth node connected to a ground terminal, and its output connected to the preset voltage terminal. A first adjustment unit is connected between the fifth node and the output terminal of the operational amplifier. The first adjustment unit includes: At least one first resistor is connected in series between the fifth node and the output of the operational amplifier; At least one first switch is provided, which is configured to correspond to the first resistor and the sub-adjustment signal terminal. The first and second ends of the first switch are respectively connected to the two ends of the corresponding first resistor, and the control terminal of the first switch unit is connected to the corresponding sub-adjustment signal terminal.

3. The electronic device according to claim 1, characterized in that, The adjustment signal terminal includes multiple sub-adjustment signal terminals; The voltage regulation circuit includes: An operational amplifier has its non-inverting input connected to a reference voltage terminal and its inverting input connected to a fifth node. The fifth node is connected to the output terminal of the operational amplifier, and the output terminal is connected to the preset voltage terminal. A second adjustment unit is connected between the fifth node and the grounding terminal, and the second adjustment unit includes: At least one second resistor is connected in series between the fifth node and the ground terminal; At least one second switch is provided, which is configured to correspond to the second resistor and to the sub-adjustment signal terminal. The first and second ends of the second switch are respectively connected to the two ends of the corresponding second resistor, and the control terminal of the second switch unit is connected to the corresponding sub-adjustment signal terminal.

4. The electronic device according to claim 2, characterized in that, The voltage regulation circuit further includes: a second regulation unit, the second regulation unit being connected between the fifth node and the ground terminal, the second regulation unit comprising: At least one second resistor is connected in series between the fifth node and the ground terminal; At least one second switch is provided, which is configured to correspond to the second resistor and to the sub-adjustment signal terminal. The first and second ends of the second switch are respectively connected to the two ends of the corresponding second resistor, and the control terminal of the second switch unit is connected to the corresponding sub-adjustment signal terminal. Each of the first resistors has the same resistance value, or at least some of the first resistors have different resistance values; Each of the second resistors has the same resistance value, or at least some of the second resistors have different resistance values.

5. The electronic device according to claim 4, characterized in that, At least one of the first resistors comprises two of the first resistors, and at least one of the second resistors comprises two of the second resistors.

6. The electronic device according to claim 1, characterized in that, The electronic device also includes: A signal generation circuit, connected to the adjustment signal terminal, is used to input the adjustment signal to the adjustment signal terminal according to a preset control signal.

7. The electronic device according to claim 1, characterized in that, The sensitive amplifier also includes: A first isolation circuit connects the readout bit line, the complementary readout bit line, the third node, the fourth node, and the second control signal terminal. The first isolation circuit is used to connect the readout bit line and the fourth node in response to the signal from the second control signal terminal, and to connect the complementary readout bit line and the third node.

8. The electronic device according to claim 7, characterized in that, The first isolation circuit includes: The third transistor has its first terminal connected to the read bit line, its second terminal connected to the fourth node, and its gate connected to the second control signal terminal. The fourth transistor has its first terminal connected to the complementary readout bit line, its second terminal connected to the third node, and its gate connected to the second control signal terminal. The third transistor and the fourth transistor are either both N-type transistors or both P-type transistors.

9. The electronic device according to claim 1, characterized in that, The sensitive amplifier also includes: An offset cancellation circuit is connected to the bit line, the complementary bit line, the readout bit line, the complementary readout bit line, and a first control signal terminal. It is used to connect the bit line and the readout bit line in response to a signal from the first control signal terminal, and is also used to connect the complementary bit line and the complementary readout bit line in response to a signal from the first control signal terminal. The second isolation circuit connects the bit line, the complementary bit line, the readout bit line, the complementary readout bit line, and the third control signal terminal. It is used to connect the bit line and the complementary readout bit line in response to the signal of the third control signal terminal, and is also used to connect the complementary bit line and the readout bit line in response to the signal of the third control signal terminal. A voltage equalization circuit is connected to the readout bit line, the complementary readout bit line, and the fourth control signal terminal, and is used to respond to the signal of the fourth control signal terminal to connect the readout bit line and the complementary readout bit line.

10. The electronic device according to claim 9, characterized in that, The offset cancellation circuit includes: The fifth transistor has its first terminal connected to the bit line, its second terminal connected to the read bit line, and its gate connected to the first control signal terminal. The sixth transistor has its first terminal connected to the complementary bit line, its second terminal connected to the complementary readout bit line, and its gate connected to the first control signal terminal. The fifth transistor and the sixth transistor are either both N-type transistors or both P-type transistors.

11. The electronic device according to claim 9, characterized in that, The second isolation circuit includes: The seventh transistor has its first terminal connected to the bit line, its second terminal connected to the complementary readout bit line, and its gate connected to the third control signal terminal. The eighth transistor has its first terminal connected to the complementary bit line, its second terminal connected to the readout bit line, and its gate connected to the third control signal terminal. The seventh transistor and the eighth transistor are either both N-type transistors or both P-type transistors.

12. The electronic device according to claim 9, characterized in that, The voltage equalization circuit includes: The ninth transistor has its first terminal connected to the readout bit line, its second terminal connected to the complementary readout bit line, and its gate connected to the fourth control signal terminal.

13. The electronic device according to claim 6, characterized in that, The electronic device also includes: A programmable fuse circuit, connected to the signal generation circuit, is used to input the preset control signal to the signal generation circuit.

14. The electronic device according to claim 13, characterized in that, The electronic device also includes: The test signal terminal is connected to the signal generation circuit and is used to input different test control signals to the signal generation circuit during the test phase.

15. The electronic device according to any one of claims 1-14, characterized in that, The electronic device is a memory.

16. An electronic device, characterized in that, include: Sensitive amplifier, the sensitive amplifier comprising: The first P-type transistor has its first terminal connected to the first node, its second terminal connected to the read bit line, and its gate connected to the third node. The second P-type transistor has its first terminal connected to the first node, its second terminal connected to the complementary readout bit line, and its gate connected to the fourth node. The first N-type transistor has its first terminal connected to the second node, its second terminal connected to the readout bit line, and its gate connected to the bit line. The second N-type transistor has its first terminal connected to the second node, its second terminal connected to the complementary readout bit line, and its gate connected to the complementary bit line. A control circuit, connected to the third node, the fourth node, a preset voltage terminal, and a first control signal terminal, is used to connect the preset voltage terminal and the third node and the fourth node in response to a signal from the first control signal terminal; wherein the preset voltage terminal and the first node are independent and different nodes. A voltage regulation circuit, connected to the preset voltage terminal and the regulation signal terminal, is used to adjust the voltage value of the preset voltage signal input to the preset voltage terminal according to the regulation signal of the regulation signal terminal; The sensitive amplifier also includes: An offset cancellation circuit is connected to the bit line, the complementary bit line, the readout bit line, the complementary readout bit line, and a first control signal terminal. It is used to connect the bit line and the readout bit line in response to a signal from the first control signal terminal, and is also used to connect the complementary bit line and the complementary readout bit line in response to a signal from the first control signal terminal. The second isolation circuit connects the bit line, the complementary bit line, the readout bit line, the complementary readout bit line, and the third control signal terminal. It is used to connect the bit line and the complementary readout bit line in response to the signal of the third control signal terminal, and is also used to connect the complementary bit line and the readout bit line in response to the signal of the third control signal terminal. A voltage equalization circuit is connected to the readout bit line, the complementary readout bit line, and the fourth control signal terminal, and is used to respond to the signal of the fourth control signal terminal to connect the readout bit line and the complementary readout bit line.

17. The electronic device according to claim 16, characterized in that, The offset cancellation circuit includes: The fifth transistor has its first terminal connected to the bit line, its second terminal connected to the read bit line, and its gate connected to the first control signal terminal. The sixth transistor has its first terminal connected to the complementary bit line, its second terminal connected to the complementary readout bit line, and its gate connected to the first control signal terminal. The fifth transistor and the sixth transistor are either both N-type transistors or both P-type transistors.

18. The electronic device according to claim 16, characterized in that, The second isolation circuit includes: The seventh transistor has its first terminal connected to the bit line, its second terminal connected to the complementary readout bit line, and its gate connected to the third control signal terminal. The eighth transistor has its first terminal connected to the complementary bit line, its second terminal connected to the readout bit line, and its gate connected to the third control signal terminal. The seventh transistor and the eighth transistor are either both N-type transistors or both P-type transistors.

19. The electronic device according to claim 16, characterized in that, The voltage equalization circuit includes: The ninth transistor has its first terminal connected to the readout bit line, its second terminal connected to the complementary readout bit line, and its gate connected to the fourth control signal terminal.

20. The electronic device according to claim 16, characterized in that, The adjustment signal terminal includes multiple sub-adjustment signal terminals; The voltage regulation circuit includes: An operational amplifier has its non-inverting input connected to a reference voltage terminal, its inverting input connected to a fifth node, the fifth node connected to a ground terminal, and its output connected to the preset voltage terminal. A first adjustment unit is connected between the fifth node and the output terminal of the operational amplifier. The first adjustment unit includes: At least one first resistor is connected in series between the fifth node and the output of the operational amplifier; At least one first switch is provided, which is configured to correspond to the first resistor and the sub-adjustment signal terminal. The first and second ends of the first switch are respectively connected to the two ends of the corresponding first resistor, and the control terminal of the first switch unit is connected to the corresponding sub-adjustment signal terminal.

21. The electronic device according to claim 16, characterized in that, The adjustment signal terminal includes multiple sub-adjustment signal terminals; The voltage regulation circuit includes: An operational amplifier has its non-inverting input connected to a reference voltage terminal and its inverting input connected to a fifth node. The fifth node is connected to the output terminal of the operational amplifier, and the output terminal is connected to the preset voltage terminal. A second adjustment unit is connected between the fifth node and the grounding terminal, and the second adjustment unit includes: At least one second resistor is connected in series between the fifth node and the ground terminal; At least one second switch is provided, which is configured to correspond to the second resistor and to the sub-adjustment signal terminal. The first and second ends of the second switch are respectively connected to the two ends of the corresponding second resistor, and the control terminal of the second switch unit is connected to the corresponding sub-adjustment signal terminal.

22. The electronic device according to claim 20, characterized in that, The voltage regulation circuit further includes: a second regulation unit, the second regulation unit being connected between the fifth node and the ground terminal, the second regulation unit comprising: At least one second resistor is connected in series between the fifth node and the ground terminal; At least one second switch is provided, which is configured to correspond to the second resistor and to the sub-adjustment signal terminal. The first and second ends of the second switch are respectively connected to the two ends of the corresponding second resistor, and the control terminal of the second switch unit is connected to the corresponding sub-adjustment signal terminal. Each of the first resistors has the same resistance value, or at least some of the first resistors have different resistance values; Each of the second resistors has the same resistance value, or at least some of the second resistors have different resistance values.

23. The electronic device according to claim 22, characterized in that, At least one of the first resistors comprises two of the first resistors, and at least one of the second resistors comprises two of the second resistors.

24. A method for driving an electronic device, characterized in that, The driving method for driving the electronic device of claim 14 includes: During the testing phase, different control signals are input to the signal generation circuit using the test signal terminal to obtain the optimal voltage at the preset voltage terminal; During the driving phase, the programmable fuse circuit is used to input the control signal corresponding to the optimal voltage to the signal generation circuit.

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