Rram-based tcam search array and kernel cell manufacturing method thereof
Patent Information
- Application Number
- CN202310757943.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-25
- Publication Date
- 2026-09-25
- Estimated Expiration
- 2043-06-25
AI Technical Summary
虽然目前基于忆阻器的存储单元已经实现，但是其能耗与延时较大、集成度与兼容性不够以及结构复杂等问题仍难以解决
[0040]首先，该发明的基于RRAM的TCAM搜索阵列以阻变随机存储器(RRAM)为存储单元的三态寻址寄存器(TCAM)，极大地简化了以往的TCAM结构。不同于一般的2T2R使用来控制晶体管开断，该发明中的TCAM搜索阵列中的内核单元采取NMOS晶体管与PMOS晶体管并联的2T2R结构，只需要一条选择线SL就可以同时对两种晶体管状态进行控制，这样仅仅只多了一条字线WL，却减少了一半选择线SL的数量；
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Figure CN116798479B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a TCAM search array based on RRAM and a method for manufacturing its core cells. Background Technology
[0002] With the massive growth of data volume and mobile devices, and the increasing demand for extracting information from large datasets using machine learning and deep learning technologies, computing hardware and architectures with high-performance designs have emerged. As the amount of data generated and analyzed continues to grow exponentially, data transmission efficiency significantly impacts the overhead and latency of traditional computing.
[0003] To quickly retrieve data within existing data sets, Content-Addressable Memory (CAM) was proposed. This CAM compares the data to be searched with its existing database. Once a match is found, the CAM returns the address of the corresponding data, making it ideal for data storage and parallel data searching. However, this approach increases power consumption to improve performance, making it less suitable for commercial applications. Therefore, Ternary Content-Addressable Memory (TCAM) is used in network nodes for addressing and searching.
[0004] In tri-state content-addressable memory, the kernel MOS transistor stores three logical states: [0], [1], and [X (arbitrary)]. Data is input via the search line SL (Search Line) and compared in parallel with the data stored in the TCAM to perform the search function. When a matching data is detected, the data address is returned via the match line ML (Match Line). Thanks to the third logical state [X (arbitrary)] of the TCAM, its operational flexibility is increased, enabling both precise matching and fuzzy matching searches, achieving parallel searching of large datasets. However, for larger memory arrays, the problems of large exposed area of the kernel MOS transistor and low energy efficiency cannot be avoided.
[0005] Unlike traditional complementary metal-oxide-semiconductor (CMOS) solutions, memory computing accelerators based on novel resistive random access memory (ReRAM), ferroelectric memory (FeRAM), and phase-change memory (PRAM) have been proposed to reduce power consumption and increase computational density. Although memristor-based memory cells have been realized, problems such as high power consumption and latency, insufficient integration and compatibility, and complex structures remain unresolved. Summary of the Invention
[0006] The first technical problem to be solved by the present invention is to provide a TCAM search array based on RRAM that has low power consumption, simple structure, and higher integration and compatibility compared to the above-mentioned prior art.
[0007] The second technical problem to be solved by the present invention is to improve the manufacturing method of the kernel unit of the above-mentioned TCAM search array.
[0008] The technical solution adopted by this invention to solve the first technical problem is: a TCAM search array based on RRAM, characterized in that it includes:
[0009] The core cell array has multiple core cells, each with a WL line connected to its upper and lower edges respectively. Each core cell includes an NMOS transistor, a first memristor, a PMOS transistor, and a second memristor. The NMOS transistor is connected in series with the first memristor, and the PMOS transistor is connected in series with the second memristor. The source of the NMOS transistor is connected to the drain of the PMOS transistor through the first memristor. The first memristor is programmed as a high-resistance state, and the second memristor is programmed as a low-resistance state. The first memristor and the NMOS transistor's on / off states cooperate to store three logic states: logic state 0, logic state 1, and logic state X. Similarly, the second memristor and the PMOS transistor's on / off states cooperate to store three logic states: logic state 0, logic state 1, and logic state X.
[0010] Multiple function lines SL, each function line SL is shared by kernel cells in the same column in the kernel cell array. The function line SL is used to search or select the array when writing data; wherein, in the kernel cells in the same column, adjacent transistors between two kernel cells share one function line SL.
[0011] Multiple word lines WL are shared by kernel cells in the same row of the kernel cell array. The word line WL is used to search or select the array when writing data. In the kernel cells in the same row, adjacent transistors between two kernel cells share a word line WL, and each word line WL is kept at a high level.
[0012] Multiple matching lines ML are shared by the kernel units in the same row of the kernel unit array. Each matching line ML is grounded through an external resistor to generate a search signal and to determine whether a match is made based on the high or low output level of the matching line ML.
[0013] Improvedly, in the RRAM-based TCAM search array, in the same core cell, the gate of the NMOS transistor and the gate of the PMOS transistor are connected to the same function line SL; wherein, when the function line SL is high or low, one transistor in the same core cell is turned on, and the other transistor is connected to the word line WL and remains at a high level.
[0014] In a further improvement, in the RRAM-based TCAM search array, the top electrode of the first memristor is connected to the source of the NMOS transistor, the bottom electrode of the second memristor is connected to the source of the PMOS transistor, and the top electrode of the second memristor is connected to the corresponding word line WL.
[0015] Further improvements are made to the RRAM-based TCAM search array, within the same core unit:
[0016] When the first memristor is in a high-resistance state and the second memristor is in a low-resistance state, the logic state stored in this kernel unit is logic state 1.
[0017] When the first memristor is in a low-resistance state and the second memristor is in a high-resistance state, the logic state stored in this kernel unit is logic state 0.
[0018] When the first memristor is in a high-resistance state and the second memristor is in a high-resistance state, the logic state stored in this kernel unit is logic state X.
[0019] Furthermore, in the RRAM-based TCAM search array, voltages are applied to the gates of the NMOS transistors and the PMOS transistors to control the transistor's on / off state; wherein:
[0020] When the NMOS transistor is in the on state 1 and the PMOS transistor is in the off state 0, it means that state 1 is being searched.
[0021] When the NMOS transistor is in the on state (0) and the PMOS transistor is in the off state (1), it means that state 0 is being searched.
[0022] Further improvements are made to the RRAM-based TCAM search array, where the kernel unit stores data bits that match the search signal, indicating a matching state; and where the kernel unit stores data bits that do not match the search signal, indicating a mismatch state.
[0023] The technical solution adopted by this invention to solve the second technical problem is: a method for manufacturing kernel cells of a TCAM search array based on RRAM, characterized by comprising the following steps 1 to 3:
[0024] Step 1, execute the FEOL process for the front end of a CMOS transistor; it includes the following steps a1 to a6:
[0025] Step a1: Epitaxial growth of silicon substrate;
[0026] Step a2: Perform shallow trench STI region isolation on the silicon substrate;
[0027] Step a3, forming the n-well region of the PMOS transistor and the p-well region of the NMOS transistor by ion implantation;
[0028] Step a4: thermally oxidize to grow a gate oxide layer, and then fabricate a polysilicon gate on top of the gate oxide layer;
[0029] Step a5 involves performing lightly doped drain ion implantation and sidewall implantation.
[0030] Step a6: Ion implantation is performed to form an active region and SiON is deposited in preparation for subsequent processes.
[0031] Step 2 involves performing RRAM integration on the source region of the CMOS transistor; this includes the following steps b1 to b5:
[0032] Step b1: Using a CVD process, USG and BPSG are deposited on the transistor to form a dielectric layer.
[0033] Step b2: Deposit silica for protection and planarize using CMP;
[0034] Step b3: The required dielectric layer pattern is photolithographically patterned using CT photolithography. After dry etching to create vias, the photoresist is removed, leaving the source contact holes of the NMOS transistor and the source-drain contact holes of the PMOS transistor. The drain contact hole of the PMOS transistor is used to connect to the source memristor of the NMOS transistor.
[0035] Step b4: A layer of oxide is deposited in the source and drain contact holes of each transistor by magnetron sputtering.
[0036] Step b5: Use CVD to fill all source / drain contact holes with deposits;
[0037] Step 3: Perform the conventional BEOL process for CMOS transistors to obtain the processed product; wherein, the processed product is a core unit of the TCAM search array.
[0038] Furthermore, in the RRAM-based TCAM search array core cell manufacturing method, the oxide in step b4 is tungsten oxide, iron oxide, or titanium oxide.
[0039] Compared with the prior art, the advantages of the present invention are as follows:
[0040] First, the RRAM-based TCAM search array of this invention uses a tri-state addressing register (TCAM) with resistive random access memory (RRAM) as the storage unit, which greatly simplifies the previous TCAM structure. Unlike the general 2T2R structure... To control the switching on and off of transistors, the core cell in the TCAM search array of this invention adopts a 2T2R structure with NMOS transistors and PMOS transistors connected in parallel. Only one select line SL is needed to control the state of the two transistors at the same time. This only adds one word line WL, but reduces the number of select lines SL by half.
[0041] Secondly, the TCAM search array based on RRAM of this invention adopts a cascode structure composed of PMOS transistors and memristors, which alleviates the problem of slow migration rate caused by PMOS transistors using holes as carriers, increases the output impedance, and makes the current change very small when there is a large voltage change, thereby maintaining the stability of the circuit output signal and reducing power consumption.
[0042] Furthermore, the RRAM-based TCAM search array of this invention uses the matching line in the general TCAM structure to be connected to a high level and the BL line or WL line to be connected to a low level as a new matching line ML. It does not require pre-charging of the matching line ML for each search, as the charge can leak to the ground through the matching line ML itself, eliminating the timing control of pre-charging and greatly reducing power consumption. At the same time, the degree of mismatch in the search can be easily determined by the level change at the output of the matching line ML. Attached Figure Description
[0043] Figure 1 This is a schematic diagram of a TCAM search array based on RRAM in an embodiment of the present invention. Detailed Implementation
[0044] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.
[0045] This embodiment provides a TCAM search array based on RRAM. Specifically, see [link to documentation]. Figure 1 As shown, the RRAM-based TCAM search array in this embodiment includes:
[0046] The core unit array has multiple core units. For example, the core unit array in this embodiment includes core unit 1, core unit 2, core unit 3, and core unit 4. Each core unit is connected to a WL line above and below it, respectively. That is, a WL1 line is connected above core unit 1, and a WL2 line is connected below core unit 1; a WL1 line is connected above core unit 2, and a WL2 line is connected below core unit 2; a WL2 line is connected above core unit 3, and a WL3 line is connected below core unit 3; a WL2 line is connected above core unit 4, and a WL3 line is connected below core unit 4. Each core unit includes an NMOS transistor 5, a first memristor 6, a PMOS transistor 7, and a second memristor 8. The NMOS transistor 5 is connected to the first memristor 6. Memristor 6 is connected in series, PMOS transistor 7 is connected in series with second memristor 8, and the source of NMOS transistor 5 is connected to the drain of PMOS transistor 7 through first memristor 6; first memristor 6 is programmed as a high-resistance state, second memristor 8 is programmed as a low-resistance state, and the on / off states of first memristor 6 and NMOS transistor 5 cooperate to store three logic states: logic state 0, logic state 1, and logic state X, where X is an arbitrary state; and the on / off states of second memristor 8 and PMOS transistor 7 cooperate to store three logic states: logic state 0, logic state 1, and logic state X; the top electrode of first memristor 6 is connected to the source of NMOS transistor 5, the bottom electrode of second memristor 8 is connected to the source of PMOS transistor 7, and the top electrode of second memristor 8 is connected to the corresponding word line WL;
[0047] Multiple function lines SL are shared by core cells in the same column of the core cell array. These function lines SL are used to search or select the array during data writing. Specifically, in this embodiment, core cells 1 and 3 in the same column share the same function line SL1, and core cells 2 and 4 in the same column share the same function line SL2. Function lines SL are used to input search signals, signals for erasing and writing data stored in the memristor, and transistor switching signals. Within the same core cell, the gates of NMOS transistors and PMOS transistors are connected to the same function line SL. When function line SL is high or low, one transistor in the same core cell is turned on, and the other transistor is connected to word line WL and remains high.
[0048] Multiple word lines WL are provided, each shared by kernel cells in the same row of the kernel cell array. These word lines WL are used to search or select the array during data writing. Specifically, in the same row, adjacent transistors between two kernel cells share one word line WL; and in the same column, adjacent transistors between two kernel cells share one word line WL. Each word line WL is held at a high level. In this embodiment, kernel cells 1 and 2 in the same row share the same word line WL1, and kernel cells 3 and 4 in the same row share the same word line WL2.
[0049] Multiple matching lines ML are shared by the kernel units in the same row of the kernel unit array. Each matching line ML is grounded through an external resistor R. It is used to generate a search signal and determine whether a match is made based on the high or low output level of the matching line ML.
[0050] Specifically, in this embodiment, within the same kernel unit:
[0051] When the first memristor 6 is in a high-resistance state and the second memristor 8 is in a low-resistance state, the logic state stored in the core unit 1 is logic state 1.
[0052] When the first memristor 6 is in a low-resistance state and the second memristor 8 is in a high-resistance state, the logic state stored in the core unit 1 is logic state 0.
[0053] When the first memristor 6 is in a high-resistance state and the second memristor 8 is in a high-resistance state, the logic state stored in the core unit 1 is logic state X.
[0054] In addition, in this embodiment, voltages are applied to the gates of the NMOS transistor and the PMOS transistor to control the transistor's on / off state:
[0055] When the NMOS transistor is in the on state "1" and the PMOS transistor is in the off state "0", it means that the state being searched is [1];
[0056] When the NMOS transistor is in the on state "0" and the PMOS transistor is in the off state "1", it means that the search is for state [0].
[0057] In the RRAM-based TCAM search array of this embodiment, when the data bits stored in the kernel unit are consistent with the search signal, it is a matching state; when the data bits stored in the kernel unit are inconsistent with the search signal, it is a mismatch state.
[0058] The following combination Figure 1 The operation of the RRAM-based TCAM search array in this embodiment is explained below:
[0059] (I) Implementing TCAM search function
[0060] In kernel unit 1:
[0061] When the first memristor 6 is in a high-resistance state (HRS) and the second memristor 8 is in a low-resistance state (LRS), the logical state stored in kernel unit 1 is defined as state 1.
[0062] When the first memristor 6 is in a low resistance state (LRS) and the second memristor 8 is in a high resistance state (HRS), the logical state stored in kernel unit 1 is defined as state 0.
[0063] When both the first memristor 6 and the second memristor 8 in kernel unit 1 are in a high-resistance state (HRS), the logical state stored in kernel unit 1 is defined as state X.
[0064] The switching state of the transistor is controlled by whether a voltage is applied to the transistor gate: when the NMOS transistor 5 is in the on state "1", the PMOS transistor 7 must be in the off state "0", which means that state 1 is being searched; when the NMOS transistor 5 is in the on state "0" and the PMOS transistor 7 is in the off state "1", it means that state 0 is being searched.
[0065] In the working state, the drain of NMOS transistor 5 in core unit 1 is connected to line WL1, and the source of PMOS transistor 7 is connected to line WL2, with each WL line maintaining a high level.
[0066] The matching line ML is used to generate a search signal, which is compared with the stored data and then the kernel unit level is pulled down by an external resistor to generate a judgment signal.
[0067] The function line SL is used to input search signals, signals for erasing and writing data stored in the memristor, and transistor switching signals.
[0068] When the data bit stored in the kernel unit matches the search signal, it is in a matched state. When all kernel units on the same matching line are in a matched state, the resistance of the kernel unit is extremely high, occupying most of the voltage, and the matching line remains at a low level.
[0069] When the data bits stored in the kernel unit are inconsistent with the search signal, it is a mismatch state, i.e., a non-matched state. When one or more kernel units on the same matching line are in a mismatch state, the matching line level is significantly pulled high. The number of mismatched bits can be further determined by the change in the output level.
[0070] When the logic state stored in core unit 1 is state [1], when searching [1] with the function line SL=1 signal, NMOS transistor 5 is turned on and PMOS transistor 7 is turned off, the lower half of core unit 1 is cut off, and since the first memristor 6 is in a high resistance state, the level of the matching line ML hardly changes; when searching [0] with the function line SL=1 signal, NMOS transistor 5 is still turned on and PMOS transistor 7 is turned off, but the second memristor 8 is in a low resistance state, which will cause the matching line ML to have a significant voltage rise;
[0071] When the logic state stored in kernel unit 1 is state [X], regardless of whether the function line SL signal is used to search [1] or SL signal is used to search [0], the overall resistance of kernel unit 1 is high resistance, and the voltage of the matching line ML hardly changes.
[0072] Kernel unit 1 is in a matched state, kernel unit 1 stores bit [1], and the search signal is [1]. At this time, the overall resistance of kernel storage unit 1 is high, which does not affect the matching voltage of matching line ML1. Kernel unit 2 is in a mismatched state, kernel unit 2 stores bit [0], and the search signal is [1], which pulls the level of the output terminal of matching line ML1 high. Kernel unit 3 is in a matched state, kernel unit 3 stores bit [X], and the search signal [0] / [1] does not affect the level of matching line ML2. Kernel unit 4 is in a matched state, kernel unit 4 stores bit [1], and the search signal [1] does not affect the level of matching line ML2, so the output terminal of matching line ML2 continues to remain at a low level.
[0073] (II) Implementing TCAM data writing function
[0074] When performing the data write function, the function line SL1 can be kept high to select NMOS transistor 5. At this point, adjusting the voltages of WL1 and ML1 will adjust the voltage difference across the first memristor 6, thus changing its resistance state. For example, by keeping WL1 high and ML1 low, making the voltage difference greater than the set voltage, the first memristor 6 of the bipolar resistive random access memory will become low-resistance. Although NMOS transistor 5 in the same column is also selected, its state will not be affected as long as WL2 and ML2 are not changed, thus avoiding programming confusion. For writing the state of the second memristor 8, simply keeping the function line SL1 low to select PMOS transistor 8, with the rest of the operation similar. During the data search phase, the voltage of the word line WL needs to be controlled to prevent the voltage across the second memristor 8 from exceeding the set voltage and changing its state; generally, it needs to be lower than the voltage during data write.
[0075] In this embodiment of the RRAM-based TCAM search array, the tri-state addressing register (TCAM) using resistive random access memory (RRAM) as the storage unit greatly simplifies the conventional TCAM structure. Unlike the typical 2T2R configuration... To control the switching on and off of transistors, the core cell in the TCAM search array of this embodiment adopts a 2T2R structure with NMOS transistors and PMOS transistors connected in parallel. Only one select line SL is needed to control the state of the two transistors at the same time, which not only reduces the number of select lines SL by half, but also adds only one word line WL.
[0076] The RRAM-based TCAM search array in this embodiment uses a cascode structure composed of PMOS transistors and memristors, which alleviates the problem of slow migration rate caused by PMOS transistors using holes as carriers, increases output impedance, and makes the current change very small when there is a large voltage change, thereby maintaining the stability of the circuit output signal and reducing power consumption.
[0077] The RRAM-based TCAM search array in this embodiment uses the matching line in the general TCAM structure to be connected to a high level and the BL line or WL line to be connected to a low level as a new matching line ML. It does not require pre-charging of the matching line ML during each search, as the charge itself leaks to ground through the matching line ML, eliminating the timing control of pre-charging and greatly reducing power consumption. At the same time, the degree of mismatch in the search can be easily determined by the level change at the output of the matching line ML.
[0078] Furthermore, this embodiment also provides a method for manufacturing the kernel cell of the aforementioned RRAM-based TCAM search array. Specifically, the kernel cell manufacturing method includes the following steps:
[0079] The method for manufacturing core cells of a TCAM search array based on RRAM is characterized by comprising the following steps 1 to 3:
[0080] Step 1, execute the FEOL process for the front end of a CMOS transistor; it includes the following steps a1 to a6:
[0081] Step a1: Epitaxial growth of silicon substrate;
[0082] Step a2: Perform shallow trench STI region isolation on the silicon substrate;
[0083] Step a3, forming the n-well region of the PMOS transistor and the p-well region of the NMOS transistor by ion implantation;
[0084] Step a4: thermally oxidize to grow a gate oxide layer, and then fabricate a polysilicon gate on top of the gate oxide layer;
[0085] Step a5 involves performing lightly doped drain ion implantation and sidewall implantation.
[0086] Step a6: Ion implantation is performed to form an active region and SiON is deposited in preparation for subsequent processes.
[0087] Step 2 involves performing RRAM integration on the source region of the CMOS transistor; this includes the following steps b1 to b5:
[0088] Step b1: Using a CVD process, USG and BPSG are deposited on the transistor to form a dielectric layer.
[0089] Step b2: Deposit silica for protection and planarize using CMP;
[0090] Step b3: The required dielectric layer pattern is photolithographically patterned using CT photolithography. After dry etching to create vias, the photoresist is removed, leaving the source contact holes of the NMOS transistor and the source-drain contact holes of the PMOS transistor. The drain contact hole of the PMOS transistor is used to connect to the source memristor of the NMOS transistor.
[0091] Step b4: A layer of oxide is deposited in the source and drain contact holes of each transistor by magnetron sputtering; wherein the oxide may be tungsten oxide, iron oxide, or titanium oxide, etc.
[0092] Step b5: Use CVD to fill all source / drain contact holes with deposits;
[0093] Step 3: Perform the conventional BEOL process for CMOS transistors to obtain the processed product; wherein, the processed product is a core unit of the TCAM search array.
[0094] It should be noted that the core cell manufacturing method of the RRAM-based TCAM search array proposed in this embodiment is simple and can be implemented in conventional CMOS processes.
[0095] Although preferred embodiments of the present invention have been described in detail above, it should be clearly understood that various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A TCAM search array based on RRAM, characterized in that, include: The core cell array has multiple core cells, each with a WL line connected to its upper and lower edges respectively. Each core cell includes an NMOS transistor, a first memristor, a PMOS transistor, and a second memristor. The NMOS transistor is connected in series with the first memristor, and the PMOS transistor is connected in series with the second memristor. The source of the NMOS transistor is connected to the drain of the PMOS transistor through the first memristor. The first memristor is programmed as a high-resistance state, and the second memristor is programmed as a low-resistance state. The first memristor and the NMOS transistor's on / off states cooperate to store three logic states: logic state 0, logic state 1, and logic state X. Similarly, the second memristor and the PMOS transistor's on / off states cooperate to store three logic states: logic state 0, logic state 1, and logic state X. Multiple function lines SL, each function line SL is shared by kernel cells in the same column in the kernel cell array. The function line SL is used to search or select the array when writing data; wherein, in the kernel cells in the same column, adjacent transistors between two kernel cells share one function line SL. Multiple word lines WL are shared by kernel cells in the same row of the kernel cell array. The word line WL is used to search or select the array when writing data. In the kernel cells in the same row, adjacent transistors between two kernel cells share a word line WL, and each word line WL is kept at a high level. Multiple matching lines ML are shared by the kernel units in the same row of the kernel unit array. Each matching line ML is grounded through an external resistor to generate a search signal and to determine whether a match is made based on the high or low output level of the matching line ML.
2. The RRAM-based TCAM search array according to claim 1, characterized in that, Within the same core cell, the gates of the NMOS transistor and the PMOS transistor are connected to the same function line SL. When the function line SL is high or low, one transistor in the same core cell is turned on, while the other transistor is connected to the word line WL and remains at a high level.
3. The RRAM-based TCAM search array according to claim 1, characterized in that, The top electrode of the first memristor is connected to the source of the NMOS transistor, the bottom electrode of the second memristor is connected to the source of the PMOS transistor, and the top electrode of the second memristor is connected to the corresponding word line WL.
4. The RRAM-based TCAM search array according to any one of claims 1 to 3, characterized in that, Within the same kernel unit: When the first memristor is in a high-resistance state and the second memristor is in a low-resistance state, the logic state stored in this kernel unit is logic state 1. When the first memristor is in a low-resistance state and the second memristor is in a high-resistance state, the logic state stored in this kernel unit is logic state 0. When the first memristor is in a high-resistance state and the second memristor is in a high-resistance state, the logic state stored in this kernel unit is logic state X.
5. The RRAM-based TCAM search array according to claim 4, characterized in that, Voltages are applied to the gates of the NMOS transistor and the PMOS transistor to control the transistor's on / off state; wherein: When the NMOS transistor is in the on state 1 and the PMOS transistor is in the off state 0, it means that state 1 is being searched. When the NMOS transistor is in the on state (0) and the PMOS transistor is in the off state (1), it means that state 0 is being searched.
6. The RRAM-based TCAM search array according to claim 1, characterized in that, When the data bits stored in the kernel unit match the search signal, it is in a matching state; when the data bits stored in the kernel unit do not match the search signal, it is in a mismatch state.
7. A method for manufacturing the core cell of a TCAM search array based on RRAM, characterized in that, Includes the following steps 1 to 3: Step 1, execute the FEOL process for the front end of a CMOS transistor; it includes the following steps a1 to a6: Step a1: Epitaxial growth of silicon substrate; Step a2: Perform shallow trench STI region isolation on the silicon substrate; Step a3, forming the n-well region of the PMOS transistor and the p-well region of the NMOS transistor by ion implantation; Step a4: thermally oxidize to grow a gate oxide layer, and then fabricate a polysilicon gate on top of the gate oxide layer; Step a5 involves performing lightly doped drain ion implantation and sidewall implantation. Step a6: Ion implantation is performed to form an active region and SiON is deposited in preparation for subsequent processes. Step 2: Perform RRAM integration on the source region of the CMOS transistor; It includes the following steps b1 to b5: Step b1: Using a CVD process, USG and BPSG are deposited on the transistor to form a dielectric layer. Step b2: Deposit silica for protection and planarize using CMP; Step b3: The required dielectric layer pattern is photolithographically patterned using CT photolithography. After dry etching to create vias, the photoresist is removed, leaving the source contact holes of the NMOS transistor and the source-drain contact holes of the PMOS transistor. The drain contact hole of the PMOS transistor is used to connect to the source memristor of the NMOS transistor. Step b4: A layer of oxide is deposited in the source and drain contact holes of each transistor by magnetron sputtering. Step b5: Use CVD to fill all source / drain contact holes with deposits; Step 3: Perform the conventional BEOL process for CMOS transistors to obtain the processed product; wherein, the processed product is a core unit of the TCAM search array.
8. The method for manufacturing the core unit of a TCAM search array based on RRAM according to claim 7, characterized in that, The oxide in step b4 is tungsten oxide, iron oxide, or titanium oxide.