Semiconductor memory device

Abstract

The present application provides a semiconductor storage device capable of improving the performance of an erase operation. The semiconductor storage device of an embodiment includes a plurality of memory cells and a control circuit that controls an erase operation on the plurality of memory cells, the erase operation including an erase process that applies an erase voltage to the plurality of memory cells and an erase verification process that determines threshold voltages of the plurality of memory cells after the erase process. The control circuit sequentially performs a first erase process, a first erase verification process, a second erase process, and a second erase verification process on the plurality of memory cells in the erase operation. In the first erase verification process, a first memory cell having a threshold voltage of less than or equal to a first verification voltage is obtained from among the plurality of memory cells. In the second erase verification process, a number of second memory cells having a threshold voltage higher than the first verification voltage is obtained from among the first memory cell, and it is determined whether the number of second memory cells is greater than a first value.

Description

[0001] [Related Applications]

[0002] This application claims priority to Japanese Patent Application No. 2022-044009 (filed on March 18, 2022). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device. Background Technology

[0004] A type of NAND (Not AND) flash memory that can non-volatilely store data is known. Summary of the Invention

[0005] A semiconductor memory device is provided that can improve the performance of the erase operation.

[0006] The semiconductor memory device of the embodiment includes a plurality of memory cells and a control circuit for controlling the erasure operation performed on the plurality of memory cells. The erasure operation includes an erasure process of applying an erasure voltage to the plurality of memory cells and an erasure verification process of determining the threshold voltage of the plurality of memory cells after the erasure process. In the erasure operation, the control circuit sequentially performs a first erasure process, a first erasure verification process, a second erasure process, and a second erasure verification process on the plurality of memory cells. In the first erasure verification process, a first memory cell with a threshold voltage below a first verification voltage is obtained among the plurality of memory cells. In the second erasure verification process, the number of second memory cells with a threshold voltage above the first verification voltage is obtained, and it is determined whether the number of second memory cells is greater than a first value. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating the configuration of the semiconductor memory device according to the first embodiment.

[0008] Figure 2 This is a circuit diagram of a block within the memory cell array in the first embodiment.

[0009] Figure 3 This is a diagram showing the circuit configuration of the sensing amplifier in the first embodiment.

[0010] Figure 4 This is a cross-sectional view of a portion of a block within the storage cell array in the first embodiment.

[0011] Figure 5 This is a diagram showing the cross-sectional structure of the memory pillars within the memory cell array in the first embodiment.

[0012] Figure 6 This is a graph showing the relationship between the threshold voltage distribution achievable by the memory cell transistor in the first embodiment and the data.

[0013] Figure 7 This is a diagram showing an outline of the erase operation in the semiconductor memory device of the first embodiment.

[0014] Figure 8 This is a graph showing the shift in the threshold voltage distribution of the memory cell transistors caused by the erase operation in the first embodiment.

[0015] Figure 9 This is a flowchart illustrating the erase operation in the semiconductor memory device of the first embodiment.

[0016] Figure 10 This is a diagram showing the voltage waveform of the signal during the erasure operation in the first embodiment.

[0017] Figure 11 This is a diagram illustrating an outline of another erase operation in the semiconductor memory device of the first embodiment.

[0018] Figure 12 This is a diagram showing an outline of the erase operation in the semiconductor memory device of the second embodiment.

[0019] Figure 13 This is a flowchart illustrating the erase operation in the semiconductor memory device of the second embodiment.

[0020] Figure 14 This is a graph showing the shift in the threshold voltage distribution of the memory cell transistors caused by the erase operation in the second embodiment.

[0021] Figure 15 This is a diagram showing the voltage waveform of the signal during the erasure operation in the second embodiment.

[0022] Figure 16 This is a diagram illustrating an outline of another erase operation in the semiconductor memory device of the second embodiment.

[0023] Figure 17 This is a flowchart illustrating the erase operation in the semiconductor memory device of the third embodiment.

[0024] Figure 18 This is a flowchart illustrating the erase operation in the semiconductor memory device of the fourth embodiment. Detailed Implementation

[0025] The embodiments will now be described with reference to the accompanying drawings. In the following description, common reference numerals are used to denote constituent elements having the same function and configuration. Furthermore, the embodiments shown below are illustrative of apparatus and methods for implementing the technical concept of these embodiments, and are not intended to specifically describe the materials, shapes, structures, and arrangements of the constituent parts as described below.

[0026] 1. First Implementation Method

[0027] The semiconductor memory device according to the first embodiment will be described below. Hereinafter, regarding semiconductor memory devices, a three-dimensional stacked NAND flash memory in which memory cell transistors are stacked in three dimensions on a semiconductor substrate will be described as an example. NAND flash memory is a semiconductor memory capable of non-volatile data storage.

[0028] 1.1 Configuration of the first embodiment

[0029] 1.1.1 Composition of Semiconductor Memory Devices

[0030] First, the configuration of the semiconductor memory device of the first embodiment will be described. Figure 1 This is a block diagram illustrating the configuration of the semiconductor memory device according to the first embodiment.

[0031] The semiconductor memory device 10 includes a memory cell array 11, input / output circuitry 12, logic control circuitry 13, ready / busy circuitry 14, a register group 15, a sequencer (or control circuitry) 16, a voltage generation circuit 17, a row decoder 18, a column decoder 19, a data register 20, and a sense amplifier 21. The register group 15 includes a status register 15A, an address register 15B, and an instruction register 15C.

[0032] The memory cell array 11 includes one or more blocks BLK0, BLK1, BLK2, ..., BLKm (where m is a natural number greater than or equal to 0). Each of the blocks BLK0 to BLKm contains multiple memory cell transistors (hereinafter also referred to as memory cells) paired with rows and columns. Memory cell transistors are non-volatile memory cells that can be electrically erased and written to (or programmed). The memory cell array 11 includes multiple word lines, multiple bit lines, and source lines for applying voltage to the memory cell transistors. The specific structure of block BLKm will be described below.

[0033] Input / output circuit 12 and logic control circuit 13 are connected to memory controller 1 via input / output terminals (or NAND bus). Input / output circuit 12 and memory controller 1 exchange I / O (Input / Output) signals DQ (e.g., DQ0, DQ1, DQ2, ..., DQ7) via input / output terminals. I / O signals DQ transmit information such as instructions, addresses, and data.

[0034] The logic control circuit 13 receives external control signals from the memory controller 1 via input / output terminals (or the NAND bus). These external control signals include, for example, the chip enable signal CEn, the instruction latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, the read enable signal REen, and the write protect signal WPn. The "n" in the signal name indicates that the signal is active-low.

[0035] The chip enable signal CEn enables the selection of semiconductor memory devices 10 when multiple semiconductor memory devices 10 are installed, and takes effect when the corresponding semiconductor memory device 10 is selected. The instruction latch enable signal CLE latches the instruction sent as signal DQ into the instruction register 15C. The address latch enable signal ALE latches the address sent as signal DQ into the address register 15B. The write enable signal WEn enables the data sent as signal DQ to be stored in the input / output circuit 12. The read enable signal REn enables the data read from the memory cell array 11 to be output as signal DQ. The write protect signal WPn takes effect when write and erase operations on the semiconductor memory device 10 are prohibited.

[0036] The ready / busy circuit 14 generates a ready / busy signal R / Bn based on control from the sequencer 16. The ready / busy signal R / Bn indicates whether the semiconductor memory device 10 is in a ready or busy state. A ready state indicates that the semiconductor memory device 10 is capable of accepting commands from the memory controller 1. A busy state indicates that the semiconductor memory device 10 is unable to accept commands from the memory controller 1. The memory controller 1 can determine whether the semiconductor memory device 10 is in a ready or busy state by receiving the ready / busy signal R / Bn from the semiconductor memory device 10.

[0037] Status register 15A stores status information STS required for the operation of semiconductor memory device 10. Status register 15A transmits the status information STS to input / output circuit 12 according to the instructions of sequencer 16.

[0038] Address register 15B stores the address ADD transferred from input / output circuit 12. Address ADD includes row address and column address. The row address includes, for example, block address and page address, where the block address specifies the block BLKm to be acted upon, and the page address specifies the word line WL to be acted upon within the specified block.

[0039] Instruction register 15C stores instructions CMD transmitted from input / output circuit 12. Instructions CMD may include, for example, write instructions that command sequencer 16 to perform write operations, read instructions that command sequencer 16 to perform read operations, and erase instructions that command sequencer 16 to perform erase operations.

[0040] For example, SRAM (static random access memory) can be used for status register 15A, address register 15B, and instruction register 15C.

[0041] The sequencer 16 receives instructions from the instruction register 15C and controls the semiconductor memory device 10 in a sequence based on those instructions.

[0042] The sequencer 16 controls the voltage generation circuit 17, row decoder 18, column decoder 19, data register 20, and sense amplifier 21 to perform write, read, and erase operations. Specifically, based on write commands received from the instruction register 15C, the sequencer 16 controls the voltage generation circuit 17, row decoder 18, data register 20, and sense amplifier 21 to write data to multiple memory cell transistors specified by address ADD. The sequencer 16 also controls the voltage generation circuit 17, row decoder 18, column decoder 19, data register 20, and sense amplifier 21 to read data from multiple memory cell transistors specified by address ADD, based on read commands received from the instruction register 15C. Furthermore, based on erase commands received from the instruction register 15C, the sequencer 16 controls the voltage generation circuit 17, row decoder 18, column decoder 19, data register 20, and sense amplifier 21 to erase the data stored in the block specified by address ADD.

[0043] The voltage generation circuit 17 receives a power supply voltage VDD and a ground voltage VSS from outside the semiconductor memory device 10 via a power supply terminal. The power supply voltage VDD is an external voltage supplied from outside the semiconductor memory device 10, for example, 3.3V. The ground voltage VSS is an external voltage supplied from outside the semiconductor memory device 10, for example, 0V.

[0044] The voltage generation circuit 17 uses the power supply voltage VDD to generate multiple voltages required for write, read, and erase operations. The voltage generation circuit 17 supplies the generated voltages to the memory cell array 11, the line decoder 18, and the sense amplifier 21, etc.

[0045] The line decoder 18 receives the line address from the address register 15B and decodes it. Based on the decoding result of the line address, the line decoder 18 selects any one of multiple blocks, and then selects the word line WL within the selected block BLKm. Next, the line decoder 18 transmits multiple voltages supplied from the voltage generation circuit 17 to the selected block BLKm.

[0046] The column decoder 19 receives the column address from the address register 15B and decodes the column address. Based on the decoding result of the column address, the column decoder 19 selects the latch circuit in the data register 20.

[0047] Data register 20 has multiple latching circuits. The latching circuits temporarily store data to be written or read.

[0048] When performing a data readout operation, the sense amplifier 21 senses and amplifies the data read from the memory cell transistor to the bit lines. Then, the sense amplifier 21 temporarily stores the readout data DAT from the memory cell transistor and transfers the stored readout data DAT to the data register 20. Conversely, when performing a data write operation, the sense amplifier 21 temporarily stores the write data DAT transferred from the input / output circuit 12 via the data register 20. Then, the sense amplifier 21 transfers the write data DAT to the bit lines.

[0049] 1.1.2 Composition of Storage Cell Array

[0050] Next, the circuit configuration of the memory cell array 11 within the semiconductor memory device 10 will be described. As described above, the memory cell array 11 has multiple blocks BLK0 to BLKm. The circuit configuration of block BLKm will be described below.

[0051] Figure 2 This is a circuit diagram of a block BLKm within the memory cell array 11. A block BLKm may have multiple string sets SU0, SU1, SU2, and SU3. Hereafter, when written as string set SU, it refers to each of string sets SU0 to SU3. Each string set SU has multiple NAND strings (or memory strings) NS.

[0052] Here, to simplify the explanation, an example is shown where a NAND string NS has, for instance, eight memory cell transistors MT0, MT1, MT2, ..., MT7, and two select transistors ST1 and ST2. From now on, when writing memory cell transistor MT, it refers to each of the memory cell transistors MT0 through MT7.

[0053] The memory cell transistor MT has a control gate and a charge storage layer, and stores data non-volatilely. Memory cell transistors MT0 to MT7 are connected in series between the source of select transistor ST1 and the drain of select transistor ST2. The memory cell transistor MT can store 1 bit of data or more than 2 bits of data.

[0054] The gates of the multiple selection transistors ST1 contained in the serial group SU0 are connected to the selection gate line SGD0. Similarly, the gates of the selection transistors ST1 in each of the serial groups SU1 to SU3 are connected to the selection gate lines SGD1 to SGD3 respectively. Each selection gate line SGD0 to SGD3 is independently controlled by the serial decoder 18.

[0055] The gates of the multiple selection transistors ST2 included in the string group SU0 are connected to the selection gate line SGS. Similarly, the gates of the selection transistors ST2 in each string group SU1 to SU3 are connected to the selection gate line SGS. Alternatively, there are cases where individual selection gate lines SGS are connected to the gates of the selection transistors ST2 in each string group SU0 to SU3. Selection transistors ST1 and ST2 are used for selecting the string group SU in various operations.

[0056] The control gates of the memory cell transistors MT0 to MT7 contained in block BLKm are respectively connected to word lines WL0 to WL7. Each word line WL0 to WL7 is independently controlled by the linear decoder 18.

[0057] Bit lines BL0 to BLr (where r is a natural number greater than 0) are each connected to multiple blocks BLK0 to BLKm, and are connected to one NAND string NS within the string group set SU contained in block BLKm. In other words, bit lines BL0 to BLr are each connected to the drain of the selection transistor ST1 of multiple NAND strings NS located in the same column within the NAND strings NS arranged in a matrix within block BLKm. Additionally, the source line SL is connected to multiple blocks BLK0 to BLKm. That is, the source line SL is connected to the source of multiple selection transistors ST2 contained in block BLKm.

[0058] In brief, a string set SU contains multiple NAND strings NS, which are connected to different bit lines BL and the same select gate line SGD. Additionally, a block BLKm contains multiple string sets SU that share a word line WL. Furthermore, the memory cell array 11 contains multiple blocks BLK0 to BLKm that share a bit line BL.

[0059] A block BLKm is, for example, a unit for data erasure. That is, the data stored in the memory cell transistor MT contained within a block BLKm is erased all at once. Furthermore, data can also be erased in units of string sets SU, or in units smaller than string sets SU.

[0060] A set of multiple memory transistors MTs sharing a word line WL within a single string set SU is called a cell set CU. The collection of 1-bit data stored by each of the multiple memory transistors MTs within a cell set CU is called a page. The storage capacity of a cell set CU varies depending on the number of bits of data stored by each memory transistor MT. For example, if each memory transistor MT stores 1 bit of data, the cell set CU stores 1 page of data; if each memory transistor MT stores 2 bits of data, the cell set CU stores 2 pages of data; and if each memory transistor MT stores 3 bits of data, the cell set CU stores 3 pages of data.

[0061] Write and read operations for a cell set (CU) are performed on a page-by-page basis. In other words, read and write operations are performed simultaneously on multiple memory cell transistors (MT) connected to a single word line (WL) of a cell set (SU).

[0062] Furthermore, the number of string groups in the block BLKm is not limited to SU0 to SU3, but can be arbitrarily set. Additionally, the number of NAND strings NS included in the string group SU, and the number of memory cell transistors and select transistors in each NAND string NS, can also be arbitrarily set. Furthermore, the memory cell transistor MT can be a MONOS (metal-oxide-nitride-oxide-silicon) type using an insulating film as the charge storage layer, or an FG (floating gate) type using a conductive layer as the charge storage layer.

[0063] 1.1.3 Composition of the sensing amplifier

[0064] Next, the circuit configuration of the sense amplifier 21 within the semiconductor memory device 10 will be described. Figure 3This is a diagram showing the circuit configuration of the sense amplifier 21 within the semiconductor memory device 10 of the first embodiment. The sense amplifier 21 includes a plurality of sense amplifier sets SAU0, SAU1, ..., SAUr (r is a natural number greater than or equal to 0).

[0065] The sense amplifier groups SAU0 to SAUr are associated with bit lines BL0 to BLr, respectively. That is, the sense amplifier groups SAU0 to SAUr are electrically connected to bit lines BL0 to BLr, respectively. The sense amplifier group SAUr includes, for example, a sense amplifier section SAr, latch circuits SDL, ADL and BDL, and a bus LBUS.

[0066] For example, during a read operation, the sensing amplifier section SAr determines whether the read data is "0" or "1" based on the voltage of the bit line BLr. In other words, the sensing amplifier section SAr senses and amplifies the voltage read from the bit line BLr and determines the data stored in the selected memory cell transistor MT. The latch circuits SDL, ADL, and BDL temporarily store the read data and the write data, respectively.

[0067] The sensing amplifier section SAr, as well as the latching circuits SDL, ADL, and BDL, are connected to the LBUS bus, and can send and receive data with each other via the LBUS bus.

[0068] Additionally, the latch circuit XDL included in the data register 20 is connected to the input / output circuit 12 of the semiconductor memory device 10, and is used to input and output data between the sense amplifier assembly SAUr and the input / output circuit 12. Furthermore, the latch circuit XDL can also be used as a cache memory for the semiconductor memory device 10. For example, even when the latch circuits SDL, ADL, and BDL are in use, the semiconductor memory device 10 can be set to a ready state as long as the latch circuit XDL is idle.

[0069] 1.1.4 Cross-sectional structure of the memory cell array

[0070] Next, an example of the cross-sectional structure of block BLKm within the memory cell array 11 will be described. Figure 4 This is a cross-sectional view of a portion of block BLKm within storage cell array 11. Figure 4 In this design, two directions parallel to and orthogonal to the surface of the semiconductor substrate 30 are designated as the X direction and the Y direction, and a direction orthogonal to the surface (XY plane) containing the X and Y directions is designated as the Z direction. The X direction corresponds to the extension direction of the word line WL, the Y direction corresponds to the extension direction of the bit line BL, and the Z direction corresponds to the stacking direction of the word line WL. Furthermore, Figure 4 The interlayer insulating layer between conductive layers is omitted.

[0071] like Figure 4As shown, the memory cell array 11 includes conductive layers 31-35 disposed above the semiconductor substrate 30, memory pillars MP, contact plugs CV1, and slits SLT.

[0072] A conductive layer 31 is disposed above the semiconductor substrate 30. The conductive layer 31 is formed as a flat plate parallel to the main surface (or XY plane) of the semiconductor substrate 30. This conductive layer 31 functions as a source line SL. The conductive layer 31 may contain, for example, polycrystalline silicon doped with impurities, or tungsten (W).

[0073] Multiple slits SLTs are arranged along the XZ plane in the Y direction on the conductive layer 31. The structures (or stacks) located between adjacent slits SLTs on the conductive layer 31 correspond to, for example, multiple string sets SU.

[0074] Between adjacent slits (SLTs) on conductive layer 31, conductive layer 32, multiple conductive layers 33, and conductive layer 34 are sequentially disposed from the bottom layer. Adjacent conductive layers in the Z-direction are stacked with an interlayer insulating film in between. Conductive layers 32-34 are each formed as a flat plate parallel to the XY plane. Conductive layer 32 functions as the select gate line (SGS). The multiple conductive layers 33, sequentially from the bottom layer, function as word lines WL0-WL7. Conductive layer 34 functions as the select gate line (SGD). Conductive layers 32-34 may contain, for example, tungsten (W) or polysilicon.

[0075] Multiple memory pillars (MPs) are arranged in a staggered manner, for example, in the X and Y directions. Each of the multiple memory pillars (MPs) extends (or penetrates) along the Z direction within the stacked body between the slots (SLTs). Each memory pillar (MP) is disposed by passing through conductive layers 34, 33, and 32, reaching the upper surface of conductive layer 31 from above conductive layer 34. Each memory pillar (MP) has, for example, a block insulating layer 40, a charge storage layer 41, a tunnel insulating layer (also called a tunnel insulating film) 42, and a semiconductor layer 43. Each memory pillar (MP) functions as a NAND string (NS).

[0076] A plurality of conductive layers 35 are disposed above the memory cylinder MP, separated by an interlayer insulating film. The conductive layers 35 are arranged along the X direction. Each conductive layer 35 is a linear wiring layer extending along the Y direction, functioning as a bit line BL. Each conductive layer 35 is electrically connected to a corresponding memory cylinder MP in each string group SU. Specifically, in each string group SU, a contact plug CV1 is disposed on the semiconductor layer 43 of each memory cylinder MP, and a conductive layer 35 is disposed on the contact plug CV1. The conductive layer 35 comprises, for example, aluminum (Al) or tungsten (W). The contact plug CV1 comprises a conductive layer, for example, tungsten (W).

[0077] The above structure follows the record Figure 4There are multiple orthogonal directions (depth direction) on the paper, and the set of multiple storage columns MP (that is, NAND strings NS) arranged along the depth direction constitutes the string set SU.

[0078] In addition, the number of word lines WL, and the number of select gate lines SGD and SGS are varied according to the number of memory cell transistors MT, and the number of select transistors ST1 and ST2.

[0079] Figure 5 It is along Figure 4 The cross-sectional view along the VV line shows the cross-sectional structure of the memory column MP within the memory cell array 11. Figure 5 The cross-section of the storage pillar MP in the layer containing the conductive layer 33, which is parallel to the surface of the semiconductor substrate 30, is extracted and shown.

[0080] The storage column MP, as described above, includes, for example, a block insulating layer 40, a charge storage layer 41, a tunnel insulating layer (also called a tunnel insulating film) 42, and a semiconductor layer 43. Specifically, a block insulating layer 40 is provided on the inner wall of the storage cavity used to form the storage column MP. A charge storage layer 41 is provided on the inner wall of the block insulating layer 40. A tunnel insulating layer 42 is provided on the inner wall of the charge storage layer 41. Furthermore, a semiconductor layer 43 is provided inside the tunnel insulating layer 42. In other words, the semiconductor layer 43 is provided, for example, in the central portion of the storage column MP. The tunnel insulating layer 42 surrounds the side surface of the semiconductor layer 43. The charge storage layer 41 surrounds the side surface of the tunnel insulating layer 42. The block insulating layer 40 surrounds the side surface of the charge storage layer 41. A conductive layer 33 surrounds the side surface of the block insulating layer 40. Alternatively, the storage column MP may also have a structure in which a core insulating layer is provided inside the semiconductor layer 43.

[0081] In the structure of the memory pillar MP, the portion where the memory pillar MP intersects with the conductive layer 32 functions as the selection transistor ST2. The portion where the memory pillar MP intersects with the conductive layer 33 functions as the memory cell transistors MT0 to MT7, respectively. Furthermore, the portion where the memory pillar MP intersects with the conductive layer 34 functions as the selection transistor ST1.

[0082] Semiconductor layer 43 functions as a channel layer for memory cell transistors MT0 to MT7 and selection transistors ST1 and ST2. Current paths for the NAND string NS are formed within semiconductor layer 43.

[0083] The tunnel insulating layer 42 functions as a potential barrier when charge is injected from the semiconductor layer 43 into the charge storage layer 41, or when charge stored in the charge storage layer 41 diffuses into the semiconductor layer 43. The tunnel insulating layer 42 may include, for example, a silicon oxide film.

[0084] The charge storage layer 41 has the function of storing the charge injected from the semiconductor layer 43 in the memory cell transistors MT0 to MT7. The charge storage layer 41 is, for example, an insulating layer containing a silicon nitride film.

[0085] The insulating layer 40 prevents the charge stored in the charge storage layer 41 from diffusing to the conductive layer 33 (word line WL). The insulating layer 40 may include, for example, an aluminum oxide layer, a silicon oxide layer, and a silicon nitride layer.

[0086] 1.1.5 Threshold voltage distribution of memory cell transistors

[0087] Next, we will explain the relationship between the threshold voltage distribution achievable by the memory cell transistor MT and the data.

[0088] Figure 6 This is a graph showing the relationship between the threshold voltage distribution achievable by the memory cell transistor MT and the data. Here, regarding the storage method of the memory cell transistor MT, an example of a TLC (Triple-Level Cell) method that can store 3 bits of data in one memory cell transistor MT is shown. In addition, this embodiment can also be applied to other storage methods such as an SLC (Single-Level Cell) method that can store 1 bit of data in one memory cell transistor MT, an MLC (Multi-Level Cell) method that can store 2 bits of data in one memory cell transistor MT, and a QLC (Quad-Level Cell) method that can store 4 bits of data in one memory cell transistor MT.

[0089] The 3 bits of data that a memory cell transistor MT can store are defined by the lower bit, middle bit, and upper bit. When the memory cell transistor MT stores 3 bits, it can realize any of eight states corresponding to multiple threshold voltages. These eight states are named "Er", "A", "B", "C", "D", "E", "F", and "G" in ascending order. Multiple memory cell transistors MT belonging to each of the states "Er", "A", "B", "C", "D", "E", "F", and "G" form a structure as follows: Figure 6 The distribution of threshold voltages is shown.

[0090] For example, the states "Er", "A", "B", "C", "D", "E", "F", and "G" can be assigned data such as "111", "110", "100", "000", "010", "011", "001", and "101" respectively. If the lower bit is set to "X", the middle bit to "Y", and the upper bit to "Z", then the bit arrangement is "Z, Y, X". Furthermore, the threshold voltage distribution and data allocation can be arbitrarily set.

[0091] To read the data stored in the memory cell transistor MT, which is the target of the readout, the state of the threshold voltage of the memory cell transistor MT must be determined. To determine the state, readout voltages AR, BR, CR, DR, ER, FR, and GR are used. The voltage applied to the memory cell transistor MT, including readout voltages AR, BR, CR, DR, ER, FR, and GR, to determine the level is sometimes referred to as the readout voltage VCGRV.

[0092] The state "Er" is equivalent to the state where the data has been erased (erasure state). The threshold voltage of the memory cell transistor MT belonging to the state "Er" is lower than the voltage AR, for example, it has a negative value.

[0093] States "A" through "G" represent states where charge has been injected into the charge storage layer and data has been written into the memory cell transistor MT. The threshold voltage of the memory cell transistor MT in states "A" through "G" is, for example, positive. The threshold voltage of the memory cell transistor MT in state "A" is higher than the read voltage AR but lower than the read voltage BR. The threshold voltage of the memory cell transistor MT in state "B" is higher than the read voltage BR but lower than the read voltage CR. The threshold voltage of the memory cell transistor MT in state "C" is higher than the read voltage CR but lower than the read voltage DR. The threshold voltage of the memory cell transistor MT in state "D" is higher than the read voltage DR but lower than the read voltage ER. The threshold voltage of the memory cell transistor MT in state "E" is higher than the read voltage ER but lower than the read voltage FR. The threshold voltage of the memory cell transistor MT in state "F" is higher than the read voltage FR but lower than the read voltage GR. The threshold voltage of the memory cell transistor MT in state "G" is higher than the read voltage GR and lower than the voltage VREAD.

[0094] The voltage VREAD is the word line WL applied to the memory cell transistor MT connected to the non-read-out cell group CU, and is higher than the threshold voltage of the memory cell transistor MT in any state. Therefore, the memory cell transistor MT with the control gate to which the voltage VREAD is applied is in the ON state regardless of the data stored.

[0095] Additionally, verification voltages to be used during write operations are set between adjacent threshold distributions. Specifically, verification voltages AV, BV, CV, DV, EV, FV, and GV are set for states "A", "B", "C", "D", "E", "F", and "G", respectively. For example, verification voltages AV, BV, CV, DV, EV, FV, and GV are set slightly higher than read voltages AR, BR, CR, DR, ER, FR, and GR, respectively.

[0096] As described above, each memory cell transistor MT can be set to any of eight states and stores 3 bits of data. Furthermore, writes and reads are performed on a page-by-page basis within a single cell set CU. When the memory cell transistor MT stores 3 bits of data, the three pages within a single cell set CU are allocated lower, middle, and upper bits respectively. The page whose lower, middle, and upper bits are written to in a single write operation, or the page whose lower, middle, and upper bits are read out in a single read operation, that is, the set of lower bits, middle bits, and upper bits stored in the cell set CU, are respectively called the lower page, middle page, and upper page.

[0097] When the data allocation described above is applied, the lower page is determined by read operations using read voltages AR and ER. The middle page is determined by read operations using read voltages BR, DR, and FR. The upper page is determined by read operations using read voltages CR and GR.

[0098] 1.2 Operation of the first embodiment

[0099] The erasure operation in the semiconductor memory device 10 of the first embodiment will be described. The erasure operation is the operation of setting the memory cell to an erasure state. In other words, the erasure operation is the operation of removing or annihilating electrons stored in the charge storage layer of the memory cell transistor MT, thereby changing the threshold voltage of the memory cell transistor MT to within the threshold voltage distribution of state Er.

[0100] 1.2.1 Overview of the erasure action

[0101] The erase operation in the semiconductor memory device 10 of the first embodiment will now be described in summary. Figure 7 This is a diagram showing an outline of the erase operation in the semiconductor memory device 10. Furthermore, as described above, the erase operation in the semiconductor memory device 10 can be performed in blocks (BLK) or in units smaller than blocks (e.g., in string sets (SU)). Here, the case of performing the erase operation in blocks is illustrated.

[0102] like Figure 7 As shown, the erasure operation in the first embodiment includes erasure processing, erasure verification processing, and "calculation and determination of the number of storage units OF1".

[0103] Erasure is the process of erasing data stored in the memory transistor MT within the target block. In other words, erasure involves applying an erase voltage VERA to the memory transistor MT within the target block to erase the data stored there. More specifically, erasure involves applying an erase voltage VERA to the source line CELSRC to remove electrons from the charge storage layer of the memory transistor MT within the target block. Alternatively, it can involve applying an erase voltage VERA to the source line CELSRC to inject holes into the charge storage layer of the memory transistor MT within the target block, causing electron annihilation.

[0104] The erase verification process verifies the data erasure operation performed on the memory cell transistor MT through the erase process. In other words, the erase verification process confirms whether the threshold voltage of the memory cell transistor MT has transitioned to the threshold voltage distribution within the erase state during a read operation. Specifically, the erase verification process supplies a verification voltage to the word line WL and determines whether the threshold voltage of the memory cell transistor MT is lower than the verification voltage.

[0105] In an erase operation, the erase process and the subsequent erase verification process constitute one erase cycle. Figure 7 The example shown illustrates the first erase cycle R1, the second erase cycle R2, and the third erase cycle R3. Erasure cycle R1 includes erase process E1 and erase verification process V1. Erasure cycle R2 includes erase process E2 and erase verification process V2. Furthermore, erase cycle R3 includes erase process E3 and erase verification process V3.

[0106] In the first embodiment, after executing erase cycle R2, the number of memory cells OF1 is calculated and determined. The calculation and determination of the number of memory cells OF1 is an operation to confirm the erasure characteristics of the memory cell transistors MT generated through the erasure process. Specifically, it involves checking the number of memory cell transistors that passed verification in erase verification process V1 but reverted to failing verification in erase verification process V2. Based on the determination result of the number of memory cells OF1, it is determined that the erasure verification has failed, or erase cycle R3 is executed.

[0107] In the erase verification processes V1 to V3, if the number of memory cell transistors MT with a threshold voltage higher than a certain voltage level (hereinafter referred to as the verification level or verification voltage) VL1 is less than a specified number, the sequencer 16 determines that the erase verification has passed. On the other hand, if the number of memory cell transistors MT with a threshold voltage higher than the verification level VL1 is greater than or equal to the specified number, the sequencer 16 determines that the erase verification has failed. If the erase verification fails, the sequencer 16 repeats the erase cycle; if the erase verification passes, the sequencer 16 ends the erase operation. Details of the erase operation, including the calculation and determination of the erase cycles R1 to R3 and the number of memory cells OF1, will be described below.

[0108] Figure 8 It is a graph showing the threshold voltage distribution of the memory cell transistor MT when an erase operation is performed on the memory cell transistor MT in the block containing data.

[0109] The number of memory cell transistors MT with a threshold voltage higher than the verification level VL1 will not immediately fall below the specified number in the first erase cycle R1, but will only fall below the specified number through multiple erase cycles, including erase cycles R2 and R3. For example, if the erase verification fails in the first erase cycle R1, then the second erase cycle R2 is implemented. If the erase verification fails in the second erase cycle R2, then the third erase cycle R3 is implemented. During the erase process of these repeated erase cycles, the erase voltage VERA is as follows: Figure 7 As shown, the value is set to the value obtained by increasing the voltage ΔV each time.

[0110] Here, we focus on the memory cell transistor MT that passed the erase verification in the first erase cycle R1. After performing the second erase cycle R2 on the memory cell transistor MT that passed the erase verification, sometimes a memory cell transistor MT that failed the erase verification may appear. That is, sometimes a memory cell transistor MT that passed the verification in the first erase verification process V1 may revert to a memory cell transistor MT that failed the verification in the second erase verification process V2.

[0111] In this scenario, during the third erase cycle R3, even if the number of memory cell transistors MT that previously passed erase verification but subsequently failed increases, the block will pass erase verification as long as the number of memory cell transistors MT with a threshold voltage higher than the verification level VL1 is less than a specified number. However, if writing and erasing are performed on blocks with more than a certain number of memory cell transistors MT that previously passed erase verification but subsequently failed, the characteristics of the memory cell transistors MT will deteriorate.

[0112] Therefore, in the first embodiment, the number of memory cell transistors MT that previously passed the erase verification but subsequently failed the erase verification is required. This number of memory cell transistors MT that previously passed the erase verification but subsequently failed the erase verification is the memory cell count OF1. Furthermore, if the memory cell count OF1 exceeds a reference value, the block is considered a bad block and is disabled.

[0113] 1.2.2 Details of the erasure action

[0114] The erasure operation in the semiconductor memory device 10 of the first embodiment will now be described in detail. Figure 9 This is a flowchart illustrating the erase operation in the semiconductor memory device 10. This operation is controlled by the sequencer 16.

[0115] After the erasure operation begins, the sequencer 16 performs erasure processing E1 (S1) on the block BLK to be erased using the erasure voltage VERA. Specifically, the erasure voltage VERA is applied (or supplied) to the source line CELSRC to erase the data stored in the memory cell transistor MT within the block BLK. In other words, applying (or supplying) the erasure voltage VERA to the source line CELSRC causes the threshold voltage of the memory cell transistor MT within the block BLK to transition to the state Er side. The voltage waveforms of the source line CELSRC, word line WL, select gate lines SGD and SGS, and bit line BL in the erasure processing E1 will be described below.

[0116] Next, the sequencer 16 performs an erasure verification process V1 (S2) on the erase target block BLK using a verification level VL1. That is, using the verification level VL1 as the readout voltage, a readout operation is performed to determine the erasure state of the memory cell transistor MT after the erasure process E1. Specifically, the verification level VL1 is applied to the word line WL within the erase target block, which is the target for determination, and a readout operation is performed on the memory cell transistor MT. In this readout operation, memory cell transistors MT with a threshold voltage below the verification level VL1 are turned on, and memory cell transistors MT with a threshold voltage above the verification level VL1 are turned off. Furthermore, in the use of… Figure 7 and Figure 8 In the explanation, the state in which the memory cell transistor MT is in the ON state is referred to as "passed verification", and the state in which it is in the OFF state is referred to as "failed verification".

[0117] Sequencer 16 obtains the number of memory cell transistors MT in the off state by performing a readout operation using the verification level VL1 in the erase verification process V1. Hereinafter, the number of memory cell transistors MT in the off state during the erase verification process V1 will be referred to as the off bit count F1. Through this readout operation, sequencer 16 further obtains information about memory cell transistors MT in the on state. For example, by storing the data read from the memory cell transistors MT in the first latch circuit of the sense amplifier group SAUr, information about the on-state memory cell transistors MT can be obtained.

[0118] The sequencer 16 determines whether the number of disconnected bits F1 obtained during the read operation exceeds a specified value (S2). If the number of disconnected bits F1 exceeds the specified value (verification failed), the sequencer 16 determines that the erase target block after the erase process E1 has failed the erase verification and proceeds to step S3. On the other hand, if the number of disconnected bits F1 does not exceed the specified value (verification passed), the sequencer 16 determines that the erase target block has passed the erase verification and proceeds to step S12. Then, the erase target block is managed as a usable block that has been erased (S12). The voltage waveforms of the source line CELSRC, word line WL, select gate lines SGD and SGS, and bit line BL in the erase verification process V1 will be described below.

[0119] Next, if the erase verification process V1 fails, the sequencer 16 performs an erase process E2 (S3) on the block BLK to be erased using the erase voltage "VERA+ΔV". Specifically, the erase voltage "VERA+ΔV" is applied to the source line CELSRC, causing the threshold voltage of the memory cell transistor MT in the block BLK to further transition to the state Er side.

[0120] Subsequently, the sequencer 16 performs an erasure verification process V2 (S4) on the erase target block BLK using the verification level VL1. That is, using the verification level VL1 as the readout voltage, a readout operation is performed to determine the erasure state of the memory cell transistor MT after the erasure process E2. Specifically, the verification level VL1 is applied to the word line WL within the erase target block, which is the target for determination, and a readout operation is performed on the memory cell transistor MT. In this readout operation, memory cell transistors MT with a threshold voltage below the verification level VL1 are turned on, and memory cell transistors MT with a threshold voltage above the verification level VL1 are turned off.

[0121] Sequencer 16 obtains the number of memory cell transistors MT in the off state by performing a readout operation using the verification level VL1 in the erase verification process V2. Hereinafter, the number of memory cell transistors MT in the off state during the erase verification process V2 will be referred to as the off bit number F2. Through this readout operation, sequencer 16 further obtains information about memory cell transistors MT in the on state. For example, by storing the data read from the memory cell transistors MT in the second latch circuit of the sense amplifier group SAUr, information about the on-state memory cell transistors MT can be obtained.

[0122] The sequencer 16 determines whether the number of disconnected bits F2 obtained during the read operation exceeds a specified value. If the number of disconnected bits F2 exceeds the specified value (verification failed), the sequencer 16 determines that the erased block after the erase process E2 failed the erase verification and proceeds to step S5. On the other hand, if the number of disconnected bits F2 does not exceed the specified value (verification passed), the sequencer 16 determines that the erased block passed the erase verification and proceeds to step S12. Then, the erased block is managed as a usable block that has been erased (S12).

[0123] Next, if the erasure verification process V2 fails, the sequencer 16 determines whether the number OF1 of memory cell transistors MT that changed from the on state in erasure verification process V1 to the off state in erasure verification process V2 exceeds the reference value X1 (S5). In other words, it determines whether the number OF1 of memory cell transistors MT that were on in erasure verification process V1 but became off in the subsequent erasure verification process V2 exceeds the reference value X1. Specifically, the sequencer 16 compares the information of the on-state memory cell transistors MT obtained in erasure verification process V1 with the information of the off-state memory cell transistors MT obtained in erasure verification process V2 to calculate the number OF1 of memory cell transistors MT that changed from the on state to the off state. Then, the sequencer 16 determines whether the number OF1 of memory cell transistors exceeds the reference value X1.

[0124] Subsequently, if the number of memory cells OF1 exceeds the reference value X1 in step S5 (yes), then the sequencer 16 determines that the erase target block after the erase process E2 has failed the erase verification and proceeds to step S11. Then, the erase target block is managed as an unusable bad block (S11). Through the determination in step S5, the sequencer 16 can quickly determine the degradation of the erase characteristics of the memory cell transistor MT within the erase target block, thereby stopping the subsequent erase cycle for the erase target block.

[0125] On the other hand, if the number of memory cells OF1 does not exceed the reference value X1 in step S5 (No), then the sequencer 16 performs an erasure process E3 (S6) on the block BLK to be erased by applying an erasure voltage “VERA+2ΔV”. Specifically, an erasure voltage “VERA+2ΔV” is applied to the source line CELSRC, causing the threshold voltage of the memory cell transistor MT in the block BLK to further transition to the state Er side.

[0126] Next, the sequencer 16 performs an erase verification process V3 (S7) on the erase target block BLK using the verification level VL1. That is, using the verification level VL1 as the read voltage, a read operation is performed to determine the erase state of the memory cell transistor MT after the erase process E3. Specifically, the verification level VL1 is applied to the word line WL within the erase target block, which is the target of determination, and a read operation is performed on the memory cell transistor MT. In this read operation, memory cell transistors MT with a threshold voltage below the verification level VL1 are turned on, and memory cell transistors MT with a threshold voltage above the verification level VL1 are turned off.

[0127] Sequencer 16 obtains the number of memory cell transistors MT in the off state by performing a readout operation using the verification level VL1 in the erase verification process V3. Hereinafter, the number of memory cell transistors MT in the off state during the erase verification process V3 will be referred to as the off bit number F3. Through this readout operation, sequencer 16 further obtains information about memory cell transistors MT in the on state. For example, by storing the data read from the memory cell transistors MT in the third latch circuit of the sense amplifier group SAUr, information about the on-state memory cell transistors MT can be obtained.

[0128] The sequencer 16 determines whether the number of disconnected bits F3 obtained during the read operation exceeds a specified value. If the number of disconnected bits F3 exceeds the specified value (verification failed), the sequencer 16 determines that the erase target block after the erase process E3 failed the erase verification and proceeds to step S8. On the other hand, if the number of disconnected bits F3 does not exceed the specified value (verification passed), the sequencer 16 determines that the erase target block passed the erase verification and proceeds to step S12. Then, the erase target block is managed as a usable block that has been erased (S12).

[0129] Next, if the erasure verification process V3 fails verification, the sequencer 16 determines whether the number OF2 of memory cell transistors MT that changed from the on state in erasure verification process V2 to the off state in erasure verification process V3 exceeds the reference value X1 (S8). In other words, it determines whether the number OF2 of memory cell transistors MT that were on in erasure verification process V2 but became off in the subsequent erasure verification process V3 exceeds the reference value X1. Specifically, the sequencer 16 compares the information of the on-state memory cell transistors MT obtained in erasure verification process V2 with the information of the off-state memory cell transistors MT obtained in erasure verification process V3 to calculate the number OF2 of memory cell transistors MT that changed from the on state to the off state. Then, the sequencer 16 determines whether the number OF2 of memory cell transistors exceeds the reference value X1.

[0130] Subsequently, if the number of memory cells OF2 exceeds the reference value X1 in step S8 (yes), then the sequencer 16 determines that the erase target block after the erase process E3 has failed the erase verification and proceeds to step S11. Then, the erase target block is managed as an unusable bad block (S11). Through the determination in step S8, the sequencer 16 can quickly determine the degradation of the erase characteristics of the memory cell transistor MT within the erase target block, thereby stopping the subsequent erase cycle for the erase target block.

[0131] On the other hand, if the number of memory cells OF2 does not exceed the reference value X1 (No) in step S8, then the sequencer 16 performs an erasure process E4 (S9) on the block BLK to be erased by applying an erasure voltage "VERA+3ΔV". Specifically, an erasure voltage "VERA+3ΔV" is applied to the source line CELSRC, causing the threshold voltage of the memory cell transistor MT in the block BLK to further transition to the state Er side.

[0132] Next, the sequencer 16 performs an erasure verification process V4 (S10) on the erase target block BLK using the verification level VL1. That is, using the verification level VL1 as the read voltage, a read operation is performed to determine the erasure state of the memory cell transistor MT after the erasure process E4. Specifically, the verification level VL1 is applied to the word line WL within the erase target block, which is the target for determination, and a read operation is performed on the memory cell transistor MT. In this read operation, memory cell transistors MT with a threshold voltage below the verification level VL1 are turned on, and memory cell transistors MT with a threshold voltage above the verification level VL1 are turned off.

[0133] The sequencer 16 obtains the number of memory cell transistors MT that are in the off state by performing a read operation using the verification level VL1 in the erase verification process V4. Hereinafter, the number of memory cell transistors MT that are in the off state in the erase verification process V4 will be referred to as the number of off bits F4.

[0134] The sequencer 16 determines whether the number of disconnected bits F4 obtained during the read operation exceeds a specified value. If the number of disconnected bits F4 exceeds the specified value (verification failed), the sequencer 16 determines that the erase target block after the erase process E4 failed the erase verification and proceeds to step S11. Then, the erase target block is managed as an unusable bad block (S11). On the other hand, if the number of disconnected bits F4 does not exceed the specified value (verification passed), the sequencer 16 determines that the erase target block passed the erase verification and proceeds to step S12. Then, the erase target block is managed as a usable block that has been erased (S12). Through the above steps, the erase operation ends.

[0135] The erasure action is performed when the maximum number of erasure cycles is set to 4. If the maximum number of erasure cycles is set to more than 4, the erasure cycle is repeated until the erasure verification is passed, or until the maximum number of erasure cycles is reached.

[0136] In addition, during the read operation of the erase verification process, the on or off state of the memory cell transistor MT can be determined for each block BLK or each string group set SU.

[0137] Alternatively, the on / off state of the memory cell transistor MT can be determined for each word line or multiple word lines of a block (or string set). Furthermore, the resistance value can be measured for each NAND string NS (or memory cell MP) to determine the on / off state of the memory cell transistor MT contained in the NAND string NS. For example, the word lines of a block (or string set) can be divided, and the on / off state of the memory cell transistor MT can be determined for each divided word line. More specifically, the word lines of a block (or string set) can be divided into even-numbered word lines and odd-numbered word lines along the word line stacking direction, and the on / off state of the memory cell transistor MT connected to the even-numbered word line and the memory cell transistor MT connected to the odd-numbered word line can be alternately determined.

[0138] 1.2.3 Voltage waveform of the erasure action

[0139] The voltage waveforms of the source line CELSRC, word line WL, select gate lines SGD and SGS, and bit line BL in the erase operation, which includes erase processing and erase verification processing, are described below. Figure 10This is a diagram showing the voltage waveforms of each signal in the erase process and the erase verification process. Here, the erase process E1 and the erase verification process V1 are used as examples for explanation.

[0140] First, erase process E1 is performed between times t0 and t5. Then, erase verification process V1 is performed between times t5 and t10. The series of processes up to t0 to t10 corresponds to one erase cycle.

[0141] The erase process E1 is described below. At time t0, the bit line BL, select gate lines SGD and SGS, word line WL, and source line CELSRC are set to voltage VSS (e.g., 0V).

[0142] Next, at times t1 to t3, for example, an erase voltage VERA is applied to the source line CELSRC. As a result, at times t1 to t3, the channel region of the memory cell transistor MT will rise to the erase voltage VERA. Furthermore, through capacitive coupling caused by the voltage VERA applied to the source line CELSRC, the bit line BL, the select gate lines SGD and SGS, and the word line WL of the block not to be erased (or the non-selected block) will rise to the voltage VERA. Additionally, the select gate line SGS will rise to a voltage Δ lower than the voltage VERA.

[0143] Furthermore, between times t1 and t3, the line decoder 18 applies a voltage Vwl lower than the erase voltage VERA to the word line WL of the block (or selection block) to be erased. This creates a potential difference between the erase voltage VERA in the channel region of the memory cell transistor MT and the voltage Vwl of the word line WL of the block to be erased, causing electrons to be drawn from the charge storage layer of the memory cell transistor MT within the block to the channel layer, or holes to be injected into the charge storage layer of the memory cell transistor MT, resulting in electron annihilation. In other words, the data in the memory cell transistor MT within the block to be erased is erased.

[0144] Then, between times t3 and t5, the bit line BL, select gate lines SGD and SGS, word line WL, and source line CELSRC are set to voltage VSS. Through these steps, the erase process E1 ends.

[0145] Next, the erasure verification process V1 from time t5 to t10 will be described.

[0146] At time t6, the line decoder 18 applies voltage VSG to the select gate lines SGD and SGS of the select block. Voltage VSG is the voltage that turns on the select transistors ST1 and ST2.

[0147] Next, between times t7 and t9, the line decoder 18 applies a verification level VL1 to the word line WL of the erase target block that is being determined. Then, the line decoder 18 applies a voltage VREAD to the word lines WL that are not being determined. The verification level VL1 is a read voltage used to determine the erase state of the memory cell transistor MT within the erase target block. The voltage VREAD is a voltage that turns the memory cell transistor MT on regardless of its erase state.

[0148] Therefore, the sensing amplifier 21 senses and amplifies the data read out to bit line BL. Based on the readout result, the sequencer 16, as described above, determines whether the erasure verification has passed or failed.

[0149] The voltage waveforms in the other erase processes E2 to E4 are the same as in erase process E1, except that the erase voltage VERA is set to gradually increase by ΔV each time. That is, in erase process E2, the erase voltage is set to "VERA + ΔV", in erase process E3, the erase voltage is set to "VERA + 2ΔV", and further, in erase process E4, the erase voltage is set to "VERA + 3ΔV". Additionally, the voltage waveforms in erase verification processes V2 to V4 are the same as in erase verification process V1.

[0150] Furthermore, in the described embodiment, the case where the erasure voltage VERA increases by ΔV each time in the erasure processes E1 to E4 is explained, but it is not limited to this. Figure 11 As shown, the erase voltage VERA in the erase processes E1 to E4 is sometimes set to a fixed value.

[0151] 1.3 Effects of the first embodiment

[0152] According to the first embodiment, a semiconductor memory device that can improve the performance of the erase operation can be provided.

[0153] The effects of the first embodiment will now be explained.

[0154] In the first embodiment, the number of memory cells OF1 (or OF2) of the memory cell transistors MT within the erase target block that were turned on in the first erase verification and then turned off in the second erase verification performed after the first erase verification is calculated. In other words, the number of memory cells OF1 of the memory cell transistors MT within the erase target block that passed the first erase verification and then failed the second erase verification is calculated. Then, it is determined whether the number of memory cells OF1 exceeds a reference value X1. If the number of memory cells OF1 exceeds the reference value X1, it can be determined that the degradation of the erase target block has progressed, and the erase target block is treated as a bad block.

[0155] This reduces the number of erase cycles after the erased block is executed, thereby reducing the inefficient use of resources. Furthermore, by performing write and erase operations on the block after erase verification, the degradation of the characteristics of the memory cell transistors (MT) within the block can be prevented.

[0156] As described above, the semiconductor memory device according to the first embodiment can improve the performance of the erase operation.

[0157] 2. Second Implementation Method

[0158] The semiconductor memory device according to the second embodiment will be described. In the first embodiment, if the number of memory cells that change from an on state to an off state during the erase verification process exceeds a reference value, the block to be erased is treated as a bad block. However, in the second embodiment, the block to be erased is not treated as a bad block, but is verified through a gentle erase verification process, and if the verification is passed, it becomes usable. In the second embodiment, the differences from the first embodiment will be mainly described.

[0159] 2.1 Configuration of the Second Embodiment

[0160] The block configuration of the semiconductor memory device 10, the structure of the memory cell array 11, and the configuration of the sensing amplifier 21 in the second embodiment are the same as those in the first embodiment.

[0161] 2.2 Operation of the second embodiment

[0162] The erasure operation in the semiconductor memory device of the second embodiment will be described.

[0163] 2.2.1 Overview of the erasure action

[0164] The erase operation in the semiconductor memory device 10 of the second embodiment will now be described in summary. Figure 12This is a diagram showing an outline of the erase operation in the semiconductor memory device 10.

[0165] The erasure action in the second embodiment includes erasure processing, erasure verification processing, calculation and determination of the number of storage units OF1, and "mild erasure verification processing".

[0166] The erase process, erase verification process, and the calculation and determination of the number of memory cells OF1 are the same as in the first embodiment. The mild erase verification process uses a higher verification level than the erase verification process to verify the data erasure operation performed on the memory cell transistor MT by the erase process.

[0167] exist Figure 12 The example shown illustrates the first erase cycle R1, the second erase cycle R2, and the third erase cycle R3. Erasure cycle R1 includes erase process E1 and erase verification process V1. Erasure cycle R2 includes erase process E2 and erase verification process V2. Furthermore, erase cycle R3 includes erase process E3 and erase verification process V3.

[0168] In the second embodiment, after executing the erase cycle R2, the number of storage cells OF1 is calculated and determined. Based on the result of the calculation and determination of the number of storage cells OF1, a mild erase verification process RV1 or an erase cycle R3 is performed. That is, in the second embodiment, if the number of storage cells OF1 that changed from the on state to the off state exceeds a reference value, a mild erase verification process RV1 is performed to check whether the block to be erased can be used in any way other than as a block that has been erased. On the other hand, if the number of storage cells OF1 does not exceed the reference value, an erase cycle R3 is performed.

[0169] 2.2.2 Details of the erasure action

[0170] The erasure operation in the semiconductor memory device 10 of the second embodiment will now be described in detail. Figure 13 This is a flowchart illustrating the erase operation in the semiconductor memory device 10. This operation is controlled by the sequencer 16.

[0171] After the erasure operation begins, the sequencer 16 performs the erasure process E1 (S1) on the block BLK to be erased using the erasure voltage VERA. Specifically, the erasure voltage VERA is applied to the source line CELSRC, causing the threshold voltage of the memory cell transistor MT in the block BLK to switch to the state Er side.

[0172] Next, the sequencer 16 performs an erase verification process V1 (S2) on the erase target block BLK using the verification level VL1. That is, using the verification level VL1 as the read voltage, a read operation is performed to determine the erase state of the memory cell transistor MT after the erase process E1. Specifically, the verification level VL1 is applied to the word line WL within the erase target block, which is the target of determination, and a read operation is performed on the memory cell transistor MT. In this read operation, memory cell transistors MT with a threshold voltage below the verification level VL1 are turned on, and memory cell transistors MT with a threshold voltage above the verification level VL1 are turned off.

[0173] Sequencer 16 obtains the number of disconnected bits F1 of the memory cell transistor MT in the disconnected state by performing a readout operation using the verification level VL1 in the erase verification process V1. Through this readout operation, sequencer 16 further obtains information about the memory cell transistor MT in the connected state. For example, by storing the data read from the memory cell transistor MT in the first latch circuit of the sense amplifier group SAUr, information about the memory cell transistor MT in the connected state can be obtained.

[0174] The sequencer 16 determines whether the number of disconnected bits F1 obtained during the read operation exceeds a specified value (S2). If the number of disconnected bits F1 exceeds the specified value (verification failed), the sequencer 16 determines that the erase target block after the erase process E1 failed the erase verification and proceeds to step S3. On the other hand, if the number of disconnected bits F1 does not exceed the specified value (verification passed), the sequencer 16 determines that the erase target block passed the erase verification and proceeds to step S12. Then, the erase target block is managed as a usable block that has been erased (S12).

[0175] Next, if the erase verification process V1 fails, the sequencer 16 performs an erase process E2 (S3) on the block BLK to be erased using the erase voltage "VERA+ΔV". Specifically, the erase voltage "VERA+ΔV" is applied to the source line CELSRC, causing the threshold voltage of the memory cell transistor MT in the block BLK to further transition to the state Er side.

[0176] Subsequently, the sequencer 16 performs an erasure verification process V2 (S4) on the erase target block BLK using the verification level VL1. That is, using the verification level VL1 as the readout voltage, a readout operation is performed to determine the erasure state of the memory cell transistor MT after the erasure process E2. Specifically, the verification level VL1 is applied to the word line WL within the erase target block, which is the target for determination, and a readout operation is performed on the memory cell transistor MT. In this readout operation, memory cell transistors MT with a threshold voltage below the verification level VL1 are turned on, and memory cell transistors MT with a threshold voltage above the verification level VL1 are turned off.

[0177] Sequencer 16 obtains the number of disconnected bits F2 of the memory cell transistor MT in the disconnected state by performing a readout operation using the verification level VL1 in the erase verification process V2. Through this readout operation, sequencer 16 further obtains information about the memory cell transistor MT in the on state. For example, by storing the data read from the memory cell transistor MT in the second latch circuit of the sense amplifier group SAUr, information about the memory cell transistor MT in the on state can be obtained.

[0178] The sequencer 16 determines whether the number of disconnected bits F2 obtained during the read operation exceeds a specified value. If the number of disconnected bits F2 exceeds the specified value (verification failed), the sequencer 16 determines that the erased block after the erase process E2 failed the erase verification and proceeds to step S5. On the other hand, if the number of disconnected bits F2 does not exceed the specified value (verification passed), the sequencer 16 determines that the erased block passed the erase verification and proceeds to step S12. Then, the erased block is managed as a usable block that has been erased (S12).

[0179] Next, if the erase verification process V2 fails the verification, the sequencer 16 determines whether the number OF1 of the memory cell transistor MT that changed from the on state in the erase verification process V1 to the off state in the erase verification process V2 exceeds the reference value X1 (S5). In other words, it determines whether the number OF1 of the memory cell transistor MT that was on in the erase verification process V1 and then became off in the subsequent erase verification process V2 exceeds the reference value X1.

[0180] Then, if in step S5 the number of storage units OF1 exceeds the reference value X1 (yes), then proceed to step S21. Then, sequencer 16... Figure 14As shown, a mild erase verification process RV1 (S21) is performed on the erase target block BLK using a verification level VL2. That is, a readout operation is performed using a verification level VL2, which is higher than the verification level VL1, to determine the erase state of the memory cell transistor MT after the erase process E2. Specifically, the verification level VL2 is applied to the word line WL within the erase target block, and a readout operation is performed on the memory cell transistor MT. In this readout operation, memory cell transistors MT with a threshold voltage below the verification level VL2 are turned on, and memory cell transistors MT with a threshold voltage above the verification level VL2 are turned off.

[0181] The sequencer 16 obtains the number of memory cell transistors MT in the off state through a readout operation using the verification level VL2 in the gentle erase verification process RV1. Hereinafter, the number of memory cell transistors MT in the off state in the gentle erase verification process RV1 will be referred to as the number of off bits RF1.

[0182] The sequencer 16 determines whether the number of disconnected bits RF1 obtained during the read operation exceeds a specified value. If the number of disconnected bits RF1 exceeds the specified value (failed verification), the sequencer 16 determines that the erase target block after the erase process E2 has failed the mild erase verification and proceeds to step S11. Then, the erase target block is managed as an unusable bad block (S11). Through the determinations in steps S5 and S21, the sequencer 16 can quickly determine the degradation of the erase characteristics of the memory cell transistor MT in the erase target block, thereby stopping the subsequent erase cycle for the erase target block.

[0183] On the other hand, if the number of disconnected bits RF1 does not exceed the specified value (verified), the sequencer 16 determines that the erase target block has passed the mitigated erase verification and proceeds to step S22. Then, the erase target block is managed as a block that has completed mitigated erasure (S22). The method of using this block that has completed mitigated erasure will be described below.

[0184] Additionally, if the number of memory cells OF1 does not exceed the reference value X1 (No) in step S5, then the sequencer 16 performs an erasure process E3 (S6) on the block BLK to be erased using an erasure voltage “VERA+2ΔV”. Specifically, an erasure voltage “VERA+2ΔV” is applied to the source line CELSRC, causing the threshold voltage of the memory cell transistor MT in the block BLK to further transition towards the state Er side.

[0185] Next, the sequencer 16 performs an erase verification process V3 (S7) on the erase target block BLK using the verification level VL1. That is, using the verification level VL1 as the read voltage, a read operation is performed to determine the erase state of the memory cell transistor MT after the erase process E3. Specifically, the verification level VL1 is applied to the word line WL within the erase target block, which is the target of determination, and a read operation is performed on the memory cell transistor MT. In this read operation, memory cell transistors MT with a threshold voltage below the verification level VL1 are turned on, and memory cell transistors MT with a threshold voltage above the verification level VL1 are turned off.

[0186] Sequencer 16 obtains the number of disconnected bits F3 of the memory cell transistor MT in the disconnected state by performing a readout operation using the verification level VL1 in the erase verification process V3. Through this readout operation, sequencer 16 further obtains information about the memory cell transistor MT in the on state. For example, by storing the data read from the memory cell transistor MT in the third latch circuit of the sense amplifier group SAUr, information about the memory cell transistor MT in the on state can be obtained.

[0187] The sequencer 16 determines whether the number of disconnected bits F3 obtained during the read operation exceeds a specified value. If the number of disconnected bits F3 exceeds the specified value (verification failed), the sequencer 16 determines that the erase target block after the erase process E3 failed the erase verification and proceeds to step S8. On the other hand, if the number of disconnected bits F3 does not exceed the specified value (verification passed), the sequencer 16 determines that the erase target block passed the erase verification and proceeds to step S12. Then, the erase target block is managed as a usable block that has been erased (S12).

[0188] Next, if the erase verification process V3 fails the verification, the sequencer 16 determines whether the number OF2 of the memory cell transistor MT that changed from the on state in the erase verification process V2 to the off state in the erase verification process V3 exceeds the reference value X1 (S8). In other words, it determines whether the number OF2 of the memory cell transistor MT that was on in the erase verification process V2 and then changed to the off state in the subsequent erase verification process V3 exceeds the reference value X1.

[0189] Subsequently, if the number of memory cells OF2 exceeds the reference value X1 (yes) in step S8, then the sequencer 16 proceeds to step S21. Then, a mild erase verification process RV1 (S21) is performed on the erase target block BLK using the verification level VL2. That is, a read operation is performed using the verification level VL2, which is higher than the verification level VL1, to determine the erase state of the memory cell transistor MT after the erase process E3. Specifically, the verification level VL2 is applied to the word line WL within the erase target block, which is the target of determination, and a read operation is performed on the memory cell transistor MT. In this read operation, memory cell transistors MT with a threshold voltage below the verification level VL2 are turned on, and memory cell transistors MT with a threshold voltage above the verification level VL2 are turned off.

[0190] The sequencer 16 obtains the number of memory cell transistors MT in the off state through a readout operation using the verification level VL2 in the gentle erase verification process RV1. Hereinafter, the number of memory cell transistors MT in the off state in the gentle erase verification process RV1 will be referred to as the number of off bits RF2.

[0191] The sequencer 16 determines whether the number of disconnected bits RF2 obtained during the read operation exceeds a specified value. If the number of disconnected bits RF2 exceeds the specified value (failed verification), the sequencer 16 determines that the erase target block after the erase process E3 has failed the mild erase verification and proceeds to step S11. Then, the erase target block is managed as an unusable bad block (S11). Through the determinations in steps S8 and S21, the sequencer 16 can quickly determine the degradation of the erase characteristics of the memory cell transistor MT in the erase target block, thereby stopping the subsequent erase cycle for the erase target block.

[0192] On the other hand, if the number of disconnected bits RF2 does not exceed the specified value (verified), the sequencer 16 determines that the erase target block has passed the mitigated erase verification and proceeds to step S22. Then, the erase target block is managed as a block that has completed mitigated erasure (S22). The method of using this block that has completed mitigated erasure will be described below.

[0193] Additionally, if the number of memory cells OF2 does not exceed the reference value X1 (No) in step S8, then the sequencer 16 performs an erasure process E4 (S9) on the block BLK to be erased using an erasure voltage “VERA+3ΔV”. Specifically, an erasure voltage “VERA+3ΔV” is applied to the source line CELSRC, causing the threshold voltage of the memory cell transistor MT in the block BLK to further transition towards the state Er side.

[0194] Next, the sequencer 16 performs an erasure verification process V4 (S10) on the erase target block BLK using the verification level VL1. That is, using the verification level VL1 as the read voltage, a read operation is performed to determine the erasure state of the memory cell transistor MT after the erasure process E4. Specifically, the verification level VL1 is applied to the word line WL within the erase target block, which is the target for determination, and a read operation is performed on the memory cell transistor MT. In this read operation, memory cell transistors MT with a threshold voltage below the verification level VL1 are turned on, and memory cell transistors MT with a threshold voltage above the verification level VL1 are turned off.

[0195] The sequencer 16 obtains the number of disconnected bits F4 of the memory cell transistor MT that is in the disconnected state by erasing the read operation using the verification level VL1 in the verification process V4.

[0196] The sequencer 16 determines whether the number of disconnected bits F4 obtained during the read operation exceeds a specified value. If the number of disconnected bits F4 exceeds the specified value (verification failed), the sequencer 16 determines that the erase target block after the erase process E4 failed the erase verification and proceeds to step S11. Then, the erase target block is managed as an unusable bad block (S11). On the other hand, if the number of disconnected bits F4 does not exceed the specified value (verification passed), the sequencer 16 determines that the erase target block passed the erase verification and proceeds to step S12. Then, the erase target block is managed as a usable block that has been erased (S12). Through the above steps, the erase operation ends.

[0197] The erasure action is the same as in the first embodiment, where the maximum number of erasure cycles is set to 4. When the maximum number of erasure cycles is set to more than 4, the erasure cycle is repeated until the erasure verification is passed, or until the maximum number of erasure cycles is reached.

[0198] The following describes how to use the blocks that have undergone mitigated erasure. If the erasure verification is passed in the mitigated erasure verification process RV1 in step S21, then the sequencer 16 will manage the block to be erased as a block that has undergone mitigated erasure.

[0199] For example, the method of using blocks that have been mitigated and erased has the following points (1) to (4).

[0200] (1) Compared with blocks that have passed the erase verification process V1 to V4 normally (hereinafter referred to as erased blocks), blocks that have completed the mitigation erase have a higher upper edge of the threshold distribution of state Er, which may lead to a decrease in reliability. Therefore, they should be used under this premise.

[0201] (2) During the write operation, the write cycle, which includes write processing and write verification processing, is repeated until the threshold voltage of the memory cell transistor MT exceeds the write verification level. The write processing is the operation of injecting charge into the charge storage layer of the memory cell transistor MT by applying (or supplying) a write voltage VPGM to the gate electrode (i.e., the word line WL), thereby raising the threshold voltage of the memory cell transistor MT. The write verification processing is the operation of checking whether the threshold voltage of the memory cell transistor MT has reached the write verification level.

[0202] When writing to the memory cell transistor MT within a block that has undergone gentle erasure, the write verification level set to each state must be set higher than the write verification level set to each state of the memory cell transistor MT within the erased block. This raises the lower edge of the threshold voltage distribution of the memory cell transistor MT being written to, improving the reliability of the data stored in the memory cell transistor MT.

[0203] (3) During the write operation, a write loop consisting of write processing and write verification processing is repeated until the threshold voltage of the memory cell transistor MT exceeds the verification level. The write voltage VPGM used in the write processing is set to the voltage obtained by increasing the write voltage ΔV each time the write loop is repeated. When performing a write operation on the memory cell transistor MT in a block that has already been gently erased, the voltage ΔV set when performing the write processing on a block that has already been gently erased is set to a voltage smaller than the voltage ΔV set when performing the write processing on a block that has already been erased. This improves the reliability of the write operation.

[0204] (4) When using TLC or QLC for the memory cell transistor MT in a block that has been erased, MLC should be used for the memory cell transistor MT in a block that has been gently erased. In this way, by reducing the storage capacity of one memory cell transistor MT, the interval of the threshold voltage distribution of each state of the memory cell transistor MT can be expanded. As a result, the reliability of the data stored in the memory cell transistor MT can be improved.

[0205] 2.2.3 Voltage waveform of the erasure action

[0206] The voltage waveforms of the source line CELSRC, word line WL, select gate lines SGD and SGS, and bit line BL during the erase operation, which includes erase processing, erase verification processing, and mild erase verification processing, will be explained below. Figure 15This is a diagram showing the voltage waveforms of each signal in the erase process, erase verification process, and gentle erase verification process. Here, we will use the erase process E1, the erase verification process V1, and the gentle erase verification process RV1 as examples for explanation.

[0207] Figure 15 In the process, the erasure process E1 is executed from time t0 to t5, the erasure verification process V1 is executed from time t5 to t10, and the mild erasure verification process RV1 is executed from time t11 to t16.

[0208] The erasure process E1 from time t0 to t5 and the erasure verification process V1 from time t5 to t10 are the same as in the first embodiment.

[0209] The following section explains the gradual erasure verification process RV1 from time t11 to t16.

[0210] At time t12, the line decoder 18 applies voltage VSG to the select gate lines SGD and SGS of the select block. Voltage VSG is the voltage that turns on the select transistors ST1 and ST2.

[0211] Next, between times t13 and t15, the line decoder 18 applies a verification level VL2 to the word line WL of the erase target block, which is the target for determination. Verification level VL2 is a read voltage used to determine the erase state of the memory cell transistor MT within the erase target block. Verification level VL2 is a voltage higher than verification level VL1. Then, the line decoder 18 applies a voltage VREAD to the word line WL that is not the target for determination.

[0212] Therefore, the sensing amplifier 21 senses and amplifies the data read out to bit line BL. Based on the readout result, the sequencer 16, as described above, determines whether the erasure verification has passed or failed.

[0213] Furthermore, in the described embodiment, the case where the erasure voltage VERA increases by ΔV each time in the erasure processes E1 to E4 is explained, but it is not limited to this. Figure 16 As shown, the erase voltage VERA in the erase processes E1 to E4 is sometimes set to a fixed value.

[0214] 2.3 Effects of the second embodiment

[0215] According to the second embodiment, a semiconductor memory device that can improve the performance of the erase operation can be provided.

[0216] The effects of the second embodiment will now be explained.

[0217] In the second embodiment, the number of memory cells OF1 (or OF2) of the memory cell transistors MT within the erase target block that were turned on in the first erase verification and then turned off in the second erase verification performed after the first erase verification is calculated. In other words, the number of memory cells OF1 of the memory cell transistors MT within the erase target block that passed the first erase verification and then failed the second erase verification is calculated. Then, it is determined whether the number of memory cells OF1 exceeds a reference value X1. If the number of memory cells OF1 exceeds the reference value X1, the second embodiment does not treat the erase target block as a bad block, but instead performs a third erase verification using a second verification level with a voltage higher than the first verification level used in the first and second erase verifications. Then, if the erase target block passes the third erase verification, it is managed as a block that has undergone a mitigated erase. On the other hand, if the erased object block fails the third erase verification, then the erased object block is treated as a bad block.

[0218] By managing the erase target block as a block that has been mitigated after passing the third erase verification, the blocks can be used more effectively, thereby improving the memory performance of the semiconductor memory device.

[0219] On the other hand, by managing the block to be erased as a bad block if it fails the third erase verification, the number of erase cycles after the erase block is executed can be reduced, thereby reducing the ineffective use of resources. Furthermore, by performing write and erase operations on the block after the erase block passes the erase verification, the characteristic degradation of the memory cell transistors MT within the block can be prevented.

[0220] As described above, the semiconductor memory device according to the second embodiment can improve the performance of the erase operation.

[0221] 3. Third Implementation Method

[0222] The semiconductor memory device according to the third embodiment will be described. In the third embodiment, an example of performing the erase verification process as described in the first embodiment on a NAND string basis will be described. The configuration, operation, and effects of the semiconductor memory device not described are the same as those in the first embodiment.

[0223] 3.1 Operation of the third embodiment

[0224] In the third embodiment, an erase verification process is performed for each NAND string NS. Specifically, for only one NAND string NS among multiple NAND strings NS connected to one bit line, it is determined whether that NAND string NS changed from passing verification to failing verification during the erase verification process. For example, ... Figure 4 When the NAND string on the left is set to NS0 and the right is set to NS1, only the NAND string NS0 is checked to see if it has changed from passing the previous erase verification process to failing the current erase verification process. Multiple bit lines are connected to NAND strings NS0, and each NAND string NS0 is checked to see if it has changed from passing to failing the erase verification process.

[0225] Figure 17 This is a flowchart illustrating the erase operation in the semiconductor memory device 10 according to the third embodiment. This operation is controlled by the sequencer 16. Here, the focus is mainly on... Figure 9 The different points in the flowchart shown are explained.

[0226] In each erasure verification process V1a to V4a in steps S2, S4, S7, and S10, for Figure 4 The word lines WL0 to WL7 are supplied with a verification level VL1 to determine whether the threshold voltages of the memory cell transistors MT0 to MT7 of each of the multiple NAND strings NS are lower than the verification level VL1. When the threshold voltages of the memory cell transistors MT0 to MT7 are lower than the verification level VL1, the NAND string NS is considered to have passed the erase verification. Thus, in this third embodiment, the sequencer 16 determines whether the erase verification has passed on a per-NAND-string basis. Whether each of the multiple NAND strings NS contained in a block has passed the erase verification is stored in latch circuits connected to each bit line.

[0227] In step S5, after executing the erase verification process V1a, when performing the erase verification process V2a in the next erase cycle, the number of NAND strings NS0 that passed verification in erase verification process V1a but failed verification in erase verification process V2a (hereinafter referred to as string number PF1) is calculated. Then, it is determined whether the string number PF1 exceeds the reference value X2. That is, the sequencer 16 determines whether the string number PF1 of the NAND strings NS0 that changed from passing verification in erase verification process V1a to failing verification in erase verification process V2a exceeds the reference value X2. This determination is made by comparing the data stored in the latch circuit in erase verification process V1a with the data obtained in erase verification process V2a, and then comparing the comparison result with the reference value X2. In addition, the string number PF1 is not calculated and determined for other NAND strings containing NAND string NS1.

[0228] If, in step S5, the string number PF1 exceeds the reference value X2 (yes), then the sequencer 16 causes the process to proceed to step S11. On the other hand, if the string number PF1 does not exceed the reference value X2 (no), then the sequencer 16 causes the process to proceed to step S6.

[0229] In step S8, after performing the erase verification process V2a, when performing the subsequent erase verification process V3a, the number of NAND strings NS0 that passed verification in erase verification process V2a but failed verification in erase verification process V3a (hereinafter referred to as string number PF2) is calculated. Then, it is determined whether the string number PF2 exceeds the reference value X2. That is, the sequencer 16 determines whether the string number PF2 of the NAND strings NS0 that changed from passing verification in erase verification process V2a to failing verification in erase verification process V3a exceeds the reference value X2. This determination is made by comparing the data stored in the latch circuit in erase verification process V2a with the data obtained in erase verification process V3a, and then comparing the comparison result with the reference value X2. In addition, the string number PF1 is not calculated and determined for other NAND strings containing NAND string NS1.

[0230] If, in step S8, the string number PF2 exceeds the reference value X2 (yes), then the sequencer 16 causes the process to proceed to step S11. On the other hand, if the string number PF2 does not exceed the reference value X2 (no), then the sequencer 16 causes the process to proceed to step S9.

[0231] In this way, in the third embodiment, an erasure verification process is performed for each NAND string NS. Furthermore, the string number PF1 or PF2 is calculated and determined only for one of the multiple NAND strings NS connected to one bit line.

[0232] 3.2 Examples of variations in the third embodiment

[0233] In the third embodiment, the erasure verification process is performed on... Figure 4 The word lines WL0 to WL7 shown are all supplied with the verification level VL1. However, in this variation, it is... Figure 4 The even-numbered lines (e.g., WL0, WL2, WL4, WL6) and odd-numbered lines (e.g., WL1, WL3, WL5, WL7) are alternately supplied with a verification level VL1. For example, while the even-numbered lines are supplied with verification level VL1, the odd-numbered lines are supplied with a voltage higher than verification level VL1, known as the path voltage. First, only the even-numbered lines are checked for pass or fail of the erase verification, and then the odd-numbered lines are checked for pass or fail. If both pass, then the erase verification is considered to have passed.

[0234] In this variation, for example, data that passed the erasure verification process (only the even-numbered bits) in the previous erasure verification process is stored in a latch circuit connected to the bit lines. When performing the erasure verification process in the next erasure cycle, it is also necessary to determine whether the erasure verification passed for both the even-numbered bits and the odd-numbered bits. For NAND string NS0 that passed verification in the previous erasure verification process but failed verification in this one, the result is determined by comparing the data from the previous latch circuit with the data from this one, provided that the verification level VL1 is supplied only to the even-numbered bits.

[0235] In this variation, the string number PF1 or PF2 is calculated and determined only for one of the multiple NAND strings NS connected to the bit lines, and only for either the even-numbered or odd-numbered bit lines. Furthermore, the string number PF1 or PF2 is not calculated or determined for other NAND strings containing NAND string NS1.

[0236] 3.3 Effects of the third embodiment

[0237] According to the third embodiment and its variations, a semiconductor memory device that can improve the performance of the erase operation can be provided.

[0238] The effects of the third embodiment and its variations will now be explained.

[0239] In the third embodiment and its variations, the string number PF1 (or PF2) is calculated and determined only for NAND string NS0 among the multiple NAND strings NS connected to the bit lines. That is, among the multiple NAND strings NS0 within the erase target block, the string number PF1 is calculated for NAND string NS0 that passed verification in the first erase verification but failed verification in the subsequent second erase verification. Then, it is determined whether the string number PF1 exceeds a reference value X2. If the string number PF1 exceeds the reference value X2, it can be determined that the degradation of the erase target block has progressed, and the erase target block is treated as a bad block.

[0240] This reduces the number of erase cycles after the erased block is executed, thereby reducing the inefficient use of resources. Furthermore, by performing write and erase operations on the block after erase verification, the degradation of the characteristics of the memory cell transistors (MT) within the block can be prevented.

[0241] As described above, the semiconductor memory device according to the third embodiment and its variations can improve the performance of the erase operation.

[0242] 4. Fourth Implementation Method

[0243] The semiconductor memory device according to the fourth embodiment will be described. In the fourth embodiment, an example of performing the erase verification process as described in the second embodiment on a NAND string basis will be described. The configuration, operation, and effects of the semiconductor memory device not described are the same as those in the second embodiment.

[0244] 4.1 Operation of the fourth embodiment

[0245] Similar to the third embodiment, the erasure verification process described in the second embodiment can be performed on a per-NAND-string basis. In this case, the erasure verification process is also performed for each NAND-string NS. Furthermore, for example, it is determined whether each NAND-string NS0, which is connected to multiple bit lines, has changed from passing verification to failing verification during the erasure verification.

[0246] Figure 18 This is a flowchart illustrating the erase operation in the semiconductor memory device 10 according to the fourth embodiment. This operation is controlled by the sequencer 16.

[0247] The erasure verification processes V1a to V4a in steps S2, S4, S7, and S10, and the calculation and determination of string numbers PF1 and PF2 in steps S5 and S8 are the same as in the third embodiment.

[0248] 4.2 Examples of variations in the fourth embodiment

[0249] In this variation, similar to the variation of the third embodiment, the string number PF1 or PF2 is calculated and determined only for one of the multiple NAND strings NS connected to the bit lines, and only for either the even-numbered or odd-numbered bit lines. Furthermore, the string number PF1 or PF2 is not calculated or determined for the other NAND strings containing NAND string NS1.

[0250] 4.3 Effects of the fourth embodiment

[0251] According to the fourth embodiment and its variations, a semiconductor memory device that can improve the performance of the erase operation can be provided.

[0252] The effects of the fourth embodiment and its variations will now be explained.

[0253] In the fourth embodiment and its variations, the string number PF1 (or PF2) is calculated and determined only for NAND string NS0 among the multiple NAND strings NS connected to the bit lines. That is, among the multiple NAND strings NS0 within the erase target block, the string number PF1 of the NAND string NS0 that passed verification in the first erase verification but failed verification in the subsequent second erase verification is calculated. Then, it is determined whether the string number PF1 exceeds a reference value X2. If the string number PF1 exceeds the reference value X2, it can be determined that the degradation of the erase target block has progressed, and the erase target block is treated as a bad block.

[0254] This reduces the number of erase cycles after the erased block is executed, thereby reducing the inefficient use of resources. Furthermore, by performing write and erase operations on the block after erase verification, the degradation of the characteristics of the memory cell transistors (MT) within the block can be prevented.

[0255] As described above, the semiconductor memory device according to the fourth embodiment and its variations can improve the performance of the erase operation.

[0256] 5. Other variations, etc.

[0257] The functional modules described in the embodiments can be implemented in the form of hardware, computer software, or a combination of both. Functional modules, as shown in the following examples, do not necessarily need to be distinguished. For example, some functions may also be performed by functional modules different from the illustrated functional modules. Furthermore, the illustrated functional modules may be divided into more detailed functional sub-modules. Additionally, the flowcharts described in the embodiments may have their processing order rearranged within permissible limits.

[0258] Several embodiments of the present invention have been described, but these embodiments are merely examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the scope of the invention as described in the claims and its equivalents.

[0259] [Explanation of Symbols]

[0260] 1. Memory controller

[0261] 10 Semiconductor memory devices

[0262] 11-cell array

[0263] 12 Input / Output Circuits

[0264] 13 Logic Control Circuit

[0265] 14 Ready / Busy Circuits

[0266] 15 Register Group

[0267] 15A Status Register

[0268] 15B Address Register

[0269] 15C Instruction Register

[0270] 16 Sequencers

[0271] 17 Voltage Generation Circuit

[0272] 18-line decoder

[0273] 19-column decoder

[0274] 20 Data Registers

[0275] 21 Sensing Amplifier

[0276] 30 Semiconductor substrate

[0277] 31-35 Conductive layers

[0278] 40 insulating layers

[0279] 41 Charge Storage Layer

[0280] 42 Tunnel insulation layer

[0281] 43 Semiconductor layer

[0282] E1~E4 Erasure Treatment

[0283] R1~R3 erase cycle

[0284] RV1 Mild Erasure Verification Process

[0285] V1~V4 Erasure verification process.

Claims

1. A semiconductor memory device comprising: Multiple storage units; and A control circuit controls the erasure operation performed on the plurality of memory cells; The erasure action includes an erasure process that applies an erasure voltage to the plurality of memory cells, and an erasure verification process that determines the threshold voltage of the plurality of memory cells after the erasure process. During the erasure operation, the control circuit sequentially performs a first erasure process, a first erasure verification process, a second erasure process, and a second erasure verification process on the plurality of storage cells. In the first erase verification process, the number of first memory cells with a threshold voltage below the first verification voltage among the plurality of memory cells is obtained. In the second erase verification process, the number of second memory cells in the first memory cell that have a threshold voltage higher than the first verification voltage is obtained. If it is determined that the number of the second storage unit is greater than a first specified value related to the number of storage units, the erasure operation is stopped.

2. The semiconductor memory device according to claim 1, wherein In the second erasure verification process, The control circuit renders the plurality of storage units unusable.

3. The semiconductor memory device according to claim 1, wherein... The semiconductor memory device comprises a NAND flash memory in which the plurality of memory cells are arranged in three dimensions.

4. A semiconductor memory device comprising: Multiple storage units; and A control circuit controls the erasure operation performed on the plurality of memory cells; The erasure action includes an erasure process that applies an erasure voltage to the plurality of memory cells, and an erasure verification process that determines the threshold voltage of the plurality of memory cells after the erasure process. During the erasure operation, the control circuit sequentially performs a first erasure process, a first erasure verification process, a second erasure process, and a second erasure verification process on the plurality of storage cells. In the first erase verification process, the number of first memory cells with a threshold voltage below the first verification voltage among the plurality of memory cells is obtained. In the second erase verification process, the number of second memory cells in the first memory cell that have a threshold voltage higher than the first verification voltage is obtained, wherein... In the second erase verification process, if it is determined that the number of the second storage cells is below a first specified value related to the number of storage cells, The control circuit sequentially performs the third erase process and the third erase verification process on the plurality of memory cells, and In the second erase verification process, the number of third memory cells among the plurality of memory cells that have a threshold voltage below the first verification voltage is obtained. In the third erase verification process, the number of fourth storage cells in the third storage cell that have a threshold voltage higher than the first verification voltage is obtained.

5. A semiconductor memory device comprising: Multiple storage units; and A control circuit controls the erasure operation performed on the plurality of memory cells; The erasure action includes an erasure process that applies an erasure voltage to the plurality of memory cells, and an erasure verification process that determines the threshold voltage of the plurality of memory cells after the erasure process. During the erasure operation, the control circuit sequentially performs a first erasure process, a first erasure verification process, a second erasure process, and a second erasure verification process on the plurality of storage cells. In the first erase verification process, the number of first memory cells with a threshold voltage below the first verification voltage among the plurality of memory cells is obtained. In the second erase verification process, the number of second memory cells in the first memory cell that have a threshold voltage higher than the first verification voltage is obtained, wherein... In the second erase verification process, if it is determined that the number of the second storage units is greater than a first specified value related to the number of storage units, The control circuit uses a second verification voltage, which is higher than the first verification voltage, to perform a third erase verification process that determines the threshold voltage of the plurality of memory cells, and In the third erase verification process, the number of fifth memory cells among the plurality of memory cells that have a threshold voltage higher than the second verification voltage is obtained.

6. The semiconductor memory device according to claim 5, wherein In the third erase verification process, if it is determined that the number of the fifth storage unit is below a second specified value related to the number of storage units, The control circuit controls the first write operation performed on the plurality of memory cells and the second write operation performed on a sixth memory cell that is different from the plurality of memory cells. The first write operation includes a write process of applying a write voltage to the plurality of memory cells, and a write verification process of determining whether the threshold voltage of the plurality of memory cells after the write process exceeds the first write verification voltage. The second write operation includes a write process of applying the write voltage to the sixth memory cell, and a write verification process of determining whether the threshold voltage of the sixth memory cell after the write process exceeds the second write verification voltage. The first write verification voltage is higher than the second write verification voltage.

7. The semiconductor memory device according to claim 5, wherein In the third erase verification process, if it is determined that the number of the fifth storage unit is below a second specified value related to the number of storage units, The control circuit controls the first write operation performed on the plurality of memory cells and the second write operation performed on a sixth memory cell that is different from the plurality of memory cells. The first write operation includes a first write process of applying a first write voltage to the plurality of memory cells, and a first write verification process of determining whether the threshold voltage of the plurality of memory cells after the first write process exceeds the write verification voltage. The second write operation includes a second write process of applying a second write voltage to the sixth memory cell, and a second write verification process of determining whether the threshold voltage of the sixth memory cell after the second write process exceeds the write verification voltage. In the first write operation, the control circuit repeatedly executes the first write process and the first write verification process until the threshold voltage of the plurality of memory cells exceeds the write verification voltage. In the second write operation, the second write process and the second write verification process are repeatedly executed until the threshold voltage of the sixth memory cell exceeds the write verification voltage. Each time the first write process is repeated, the first write voltage of the first write process increases by the amount of the first voltage. Each time the second write process is repeated, the second write voltage of the second write process increases by a second voltage amount. The first voltage is a voltage that is less than the second voltage.

8. The semiconductor memory device according to claim 5, wherein In the third erase verification process, if it is determined that the number of the fifth storage unit is below a second specified value related to the number of storage units, The control circuit reduces the storage capacity of at least one of the plurality of storage units.

9. The semiconductor memory device according to any one of claims 1, 4, and 5, It also includes a wiring layer connecting the plurality of storage units, and In the first erasure process, a first erasure voltage is supplied to the wiring layer, and in the second erasure process, a second erasure voltage is supplied to the wiring layer. The second erasure voltage is different from the first erasure voltage.

10. The semiconductor memory device according to any one of claims 1, 4, and 5, It also includes a wiring layer connecting the plurality of storage units, and In the first erase verification process and the second erase verification process, the first verification voltage is supplied to the wiring layer.

11. The semiconductor memory device according to any one of claims 1, 4, and 5, further comprising: The first digit line is set along the first direction; and Multiple columns extend along a second direction intersecting the first direction, passing through the first letter line; and The plurality of storage units are disposed at the intersection of the first word line and the plurality of pillars.

12. The semiconductor memory device according to any one of claims 1, 4, and 5, further comprising: Multiple conductive layers, extending along a first direction, are deposited on a substrate; and Multiple pillars extend along a second direction intersecting the first direction, passing through the multiple conductive layers; and The plurality of storage cells are disposed at the intersection of the plurality of conductive layers and the plurality of pillars.

Images