Page buffer circuit and method of operation thereof

Abstract

Embodiments of the present disclosure relate to a page buffer circuit and a method of operating the same. The page buffer circuit can include a data transfer circuit configured to transfer data transferred to a first sensing node through a bit line to a second sensing node during a data sensing operation, a first latch circuit configured to sense the data transferred to the first sensing node and store the sensed data, and a second latch circuit configured to sense the data transferred to the second sensing node and store the sensed data.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2022-0034787, filed on March 21, 2022, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Various embodiments generally relate to a page buffer circuit and a method of operating the same, and more specifically, to a page buffer circuit and a method of operating the same capable of performing data sensing operations on data programmed into a memory cell. Background Technology

[0004] Semiconductor memory devices can be classified as volatile memory devices or non-volatile memory devices. Memory devices can receive power and perform data processing operations to store or output data. Volatile memory devices have high data processing speeds but require continuous power to retain the stored data. Non-volatile memory devices do not require continuous power to retain the stored data; however, they have low data processing speeds.

[0005] Recent advancements in semiconductor memory device manufacturing processes and design have reduced the speed difference in data processing between volatile and non-volatile memory devices. Consequently, significant attention has recently been paid to non-volatile memory devices that do not require power to retain stored data.

[0006] A representative example of a non-volatile memory device is a NAND flash memory device with a string structure, in which multiple memory cells are coupled in series. Each memory cell in a NAND flash memory device includes a floating gate. Therefore, the memory cell can store logic "high" data or logic "low" data by injecting electrons into or emitting electrons from the floating gate using the Fowler-Nordheim tunneling method.

[0007] Non-volatile memory devices, including NAND flash memory devices, perform programming operations to store data in memory cells and read operations to output the data stored in the memory cells. Furthermore, the non-volatile memory device performs an erase operation to erase the data stored in the memory cells before performing programming operations. The non-volatile memory device also performs a verification operation to verify whether expected data has been programmed into the memory cells. The read and verification operations include data sensing operations for sensing the data programmed into the memory cells. Summary of the Invention

[0008] In one embodiment according to this disclosure, the page buffer circuit may include: a data transfer circuit configured to transfer data received via bit lines to a first sensing node and a second sensing node during a data sensing operation. The page buffer circuit may further include a first latch circuit configured to sense data transferred to the first sensing node and store the sensed data transferred to the first sensing node. The page buffer circuit may further include a second latch circuit configured to sense data transferred to the second sensing node and store the sensed data transferred to the second sensing node.

[0009] The operation method of the page buffer circuit according to this disclosure may include: evaluating multiple sensing nodes based on data transmitted during data sensing operations. The method may further include sensing the multiple sensing nodes and storing the sensing results. The method may also include reading the result of sensing the multiple sensing nodes and storing the sensing results. Attached Figure Description

[0010] Figure 1 This is a block diagram illustrating the configuration of a semiconductor memory device according to one embodiment.

[0011] Figure 2 It's a diagram. Figure 1 A block diagram showing the internal configuration of multiple page buffer circuits in the circuit.

[0012] Figure 3 It is a schematic diagram. Figure 2 The first page contains a circuit diagram of some components of the buffer circuit.

[0013] Figure 4 It's a diagram. Figure 3 A graph showing the voltage levels of the shared sensing node and the data sensing node.

[0014] Figure 5 It is used to describe Figure 3 The first page contains the timing diagram of the buffer circuit operation.

[0015] Figure 6 It is a schematic diagram illustrating the following: Figure 2 The first page shows a circuit diagram of some components of one embodiment of the buffer circuit.

[0016] Figure 7 It is illustrated according to Figure 2 The first page shows a circuit diagram of some components of one embodiment of the buffer circuit.

[0017] Figure 8 It is used to describe Figure 3 The first page shows a diagram illustrating the operation of the buffer circuit. Detailed Implementation

[0018] This disclosure describes embodiments of the structure and / or function. The scope of this disclosure should not be construed as limited to the embodiments described in the specification. That is, since embodiments can be modified in various ways and can have various forms, the scope of this disclosure should be understood to include equivalents that can achieve the spirit of the technology. Furthermore, the purposes or effects set forth in this disclosure do not imply that a particular embodiment should include all purposes or effects or only those effects. Therefore, the scope of this disclosure should not be construed as being limited thereto.

[0019] The terms described in this application should be understood as follows.

[0020] Terms such as “first” and “second” are used to distinguish one element from another, and the scope of this disclosure should not be limited by these terms. For example, a first element may be named a second element. Similarly, a second element may be named a first element.

[0021] Unless otherwise expressly stated in the context, a singular expression shall be understood to include a plural expression. Terms such as “comprising” or “having” shall be understood to indicate the presence of a defined characteristic, number, step, operation, element, part or combination thereof, but do not preclude the possibility of the presence or addition of one or more other characteristics, numbers, steps, operations, elements, parts or combinations thereof.

[0022] In each of the steps, symbols (e.g., a, b, and c) are used for ease of explanation, and these symbols do not describe the order of the steps. Unless a specific order is clearly described in the context, these steps may be performed in a different order than that described in the context. That is, these steps may be performed in the stated order, substantially simultaneously with the stated order, or in the reverse order.

[0023] Unless otherwise defined, all terms used herein (including technical or scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. Unless expressly defined in the application, terms defined in commonly used dictionaries shall be interpreted as having the same meaning as in the context of the relevant art, and not as having an idealized or overly formal meaning.

[0024] Various embodiments relate to a page buffer circuit and a method of operating thereof capable of minimizing or reducing data sensing operations on data programmed into a memory cell.

[0025] According to this embodiment, data sensing operations on data programmed in memory cells can be minimized or reduced, thereby minimizing or reducing read and verification operation time.

[0026] Figure 1 This is a block diagram illustrating the configuration of a semiconductor memory device according to one embodiment.

[0027] refer to Figure 1 The semiconductor memory device may include a memory cell array circuit 1000, an operation driving circuit 2000, and an operation control circuit 3000.

[0028] The memory cell array circuit 1000 can be configured to store data. The memory cell array circuit 1000 may include multiple memory block circuits BK1 to Bkn, where n is a natural number. Each of the multiple memory block circuits BK1 to BKn may include multiple memory cells for storing data. The multiple memory cells may have a string structure, wherein the memory cells are arranged in a series. Figure 1 The memory cells are connected in series in the vertical direction. Multiple memory cells can be coupled to multiple word lines WL1 to WLn and multiple bit lines BL1 to BLn respectively, and thus have a matrix structure, where m is a natural number. Although described below, the multiple word lines WL1 to WLn can be driven to a preset voltage according to programming, reading, erasing, or verification operations of the word line drive circuit 2200. The multiple bit lines BL1 to BLm can be driven to a preset voltage according to the data stored in the memory cell or the data to be stored in the memory cell.

[0029] The operation drive circuit 2000 can be driven to perform programming, reading, erasing, or verification operations on the memory cell array circuit 1000. The operation drive circuit 2000 may include a voltage generation circuit 2100, a word line drive circuit 2200, a multiple page buffer circuit 2300, a column decoding circuit 2400, and a data input / output circuit 2500. The components included in the operation drive circuit 2000 will be described in detail below.

[0030] The voltage generation circuit 2100 can be configured to generate the required internal voltage V_INN for each of the programming, reading, erasing, and verification operations. The voltage generation circuit 2100 can generate internal voltages V_INN with various voltage levels corresponding to each operation based on the voltage control signal CTR_V generated by the operation control circuit 3000.

[0031] The word line driving circuit 2200 can be configured to selectively drive multiple word lines WL1 to WLn to the internal voltage V_INN generated by the voltage generation circuit 2100. The word line driving circuit 2200 can receive the internal voltage V_INN from the voltage generation circuit 2100 and a drive address signal ADD_D from the operation control circuit 3000. The drive address signal ADD_D can be a signal used to selectively enable a corresponding word line among the multiple word lines WL1 to WLn. Therefore, the word line driving circuit 2200 can selectively enable multiple word lines WL1 to WLn based on the drive address signal ADD_D and the internal voltage V_INN, and drive the enabled word lines to the corresponding internal voltage V_INN.

[0032] Although not shown in the accompanying drawings, the word line driver circuit 2200 can also be coupled to the drain select line, source select line, and common source line included in the memory cell array circuit 1000. Therefore, the word line driver circuit 2200 can drive the drain select line, source select line, and common source line to a preset internal voltage V_INN according to programming operations, read operations, erase operations, or verification operations.

[0033] As described above, multiple memory cells can be coupled to multiple word lines WL1 to WLn, respectively. The word lines coupled to the memory cells selected during programming, reading, erasing, or verifying operations can be driven by the corresponding internal voltage V_INN. Hereinafter, for ease of explanation, the memory cells selected during programming, reading, erasing, or verifying operations will be defined as "selected memory cells," and the word lines coupled to the selected memory cells will be defined as "selected word lines." Furthermore, memory cells other than the selected memory cells will be defined as "unselected memory cells," and the word lines coupled to the unselected memory cells will be defined as "unselected word lines." In other words, the selected word lines coupled to the selected memory cells during programming, reading, erasing, or verifying operations can be driven by the corresponding internal voltage V_INN.

[0034] For example, during a programming operation, the word line driver circuit 2200 can apply a programming voltage, which is one of the internal voltages V_INN, to a selected word line among multiple word lines WL1 to WLn, and apply a programming pass voltage to the other unselected word lines. The programming pass voltage has a lower voltage level than the programming voltage. Furthermore, during a read operation, the word line driver circuit 2200 can apply a read voltage to the selected word line and apply a read pass voltage to the unselected word lines. The read pass voltage has a higher voltage level than the read voltage. Furthermore, during an erase operation, the word line driver circuit 2200 can apply a ground voltage to the selected word line. Furthermore, during a verification operation, the word line driver circuit 2200 can apply a verification voltage, which is one of the internal voltages V_INN, to the selected word line and apply a verification pass voltage to the unselected word lines. The verification pass voltage has a higher voltage level than the verification voltage.

[0035] Multiple page buffer circuits 2300 can be coupled to the memory cell array circuit 1000 via multiple bit lines BL1 to BLm. The multiple page buffer circuits 2300 can be configured to transfer data to the multiple bit lines BL1 to BLm during programming operations. Furthermore, the multiple page buffer circuits 2300 can be configured to receive data from the multiple bit lines BL1 to BLm during read and verification operations. The multiple page buffer circuits 2300 can each be configured as multiple latch circuits. Each of the multiple latch circuits can perform circuit operations based on programming, read, or verification operations on the input / output data based on the operation control signal CTR_OP generated by the operation control circuit 3000.

[0036] The number of latch circuits can vary depending on the design. Specifically, the number of latch circuits can vary depending on the number of data distributions stored in the memory cell. In this regard, the memory cell of a non-volatile memory device is defined as a single-level cell, a multi-level cell, a three-level cell, or a four-level cell, depending on the number of data distributions stored in a memory cell during programming operations. A single-level cell can store one of two logic data states corresponding to a single bit. The logic "high" and logic "low" data states described above can represent two logic data states. A multi-level cell can store four logic data states corresponding to two bits, a three-level cell can store eight logic data states corresponding to three bits, and a four-level cell can store 16 logic data states corresponding to four bits. Therefore, the number of latch circuits can correspond to the number of data distributions stored in the memory cell.

[0037] The column decoding circuit 2400 can be configured to control the transmission path of input / output data. The column decoding circuit 2400 can receive data to be output to the outside of the semiconductor memory device from multiple page buffer circuits 2300, and can receive data to be input to the inside of the semiconductor memory device from the data input / output circuit 2500. Furthermore, the column decoding circuit 2400 can receive a selection address signal ADD_S from the operation control circuit 3000 and control the transmission path of the input / output data. The selection address signal ADD_S can be a signal used to select a corresponding bit line among multiple bit lines BL1 to BLm.

[0038] The data input / output circuit 2500 can be configured to control the input / output of an internal data signal DAT_INN and an external data signal DAT_EXT. The internal data signal DAT_INN can include data input to / output from the semiconductor memory device. The external data signal DAT_EXT can include data input to / output from the semiconductor memory device. The data input / output circuit 2500 can perform data input / output operations based on the input / output control signal CTR_IO generated by the operation control circuit 3000. The data input / output circuit 2500 can output external data DAT_EXT, for example, input via a host device or control device during programming operations, as internal data DAT_INN based on the input / output control signal CTR_IO. Furthermore, the data input / output circuit 2500 can output internal data DAT_INN input from the column decoding circuit 2400 during read operations as external data DAT_EXT based on the input / output control signal CTR_IO.

[0039] The operation control circuit 3000 can be configured to control the voltage generation circuit 2100, word line driving circuit 2200, multiple page buffer circuit 2300, column decoding circuit 2400, and data input / output circuit 2500 included in the operation drive circuit 2000. For example, the operation control circuit 3000 can generate a voltage control signal CTR_V for controlling the voltage generation circuit 2100 based on a command signal CMD and an address signal ADD input via a host device or control device. Furthermore, the operation control circuit 3000 can generate a drive address signal ADD_D for controlling the word line driving circuit 2200, an operation control signal CTR_OP for controlling the multiple page buffer circuit 2300, a selection address signal ADD_S for controlling the column decoding circuit 2400, and an input / output control signal CTR_IO for controlling the data input / output circuit 2500. Therefore, the operation control circuit 3000 can generate various signals to control the overall operation of the semiconductor memory device.

[0040] Figure 2 It's a diagram. Figure 1 A block diagram of the internal configuration of the multiple page buffer circuits 2300.

[0041] refer to Figure 1 and Figure 2 Multiple page buffer circuits 2300 can be configured to store data input / output based on programming operations, read operations, and verification operations, based on the operation control signal CTR_OP. The multiple page buffer circuits 2300 may include first page buffer circuits 210_1 to m-th page buffer circuits 210_m, respectively coupled to multiple bit lines BL1 to BLm. In the following description, for ease of illustration, the first page buffer circuit 210_1, coupled to the first bit line BL1, will be representatively described.

[0042] The first page buffer circuit 210_1 can be coupled to the first bit line BL1 and is configured to store data input to / output from the first bit line BL1 during programming, reading, and verification operations. The first page buffer circuit 210_1 may include a sense latch circuit 211, multiple data latch circuits 212, and a cache latch circuit 213.

[0043] The sensing latch circuit 211 can be configured to receive data stored in a memory cell during a read operation and sense the received data. During a read operation, depending on the data transmitted via the first bit line BL1, the sensing latch circuit 211 can retain the data stored therein or invert the data and store the inverted data.

[0044] Multiple data latch circuits 212 can be configured to store data during programming and reading operations. The number of data latch circuits 212 can correspond to the number of data distributions stored in memory cells. Furthermore, the multiple data latch circuits 212 can be used for various purposes. For example, the multiple data latch circuits 212 may include a verification data latch circuit for storing verification data based on a verification operation.

[0045] For reference only. Figure 2 The sense latch circuit 211 and the plurality of data latch circuits 212 are illustrated separately. However, the sense latch circuit 211 and the plurality of data latch circuits 212 are distinguished from each other only for representative applications, and their general circuit configurations are the same. Although described in more detail below, the first page buffer circuit 210_1 according to this embodiment may include at least two of the sense latch circuit 211 and the plurality of data latch circuits 212. These two latch circuits may have different circuit configurations.

[0046] The cache latch circuit 213 can be configured to receive data stored in multiple data latch circuits 212 during a read operation and output the received data as the final data. The cache latch circuit 213 can then transmit the stored final data to the column decoding circuit 2400 (see reference). Figure 1 The cache latch circuit 213 can be configured to store data input to the first page buffer circuit 210_1 during programming operations.

[0047] Figure 3 It is a schematic diagram. Figure 2 The first page contains a circuit diagram of some components of buffer circuit 210_1. For ease of explanation, Figure 3 Representative map Figure 2 Two latch circuits are included in the sensing latch circuit 211 and the plurality of data latch circuits 212. For reference, one of the two latch circuits may be configured as a cache latch circuit 213. In the following description, the two latch circuits will be defined as a first latch circuit 320 and a second latch circuit 330.

[0048] Before proceeding with the explanation, it can be based on the following: Figure 1 The operation control circuit 3000 generates an operation control signal CTR_OP to control the first page buffer circuit 210_1. In other words, various control signals used to control the first page buffer circuit 210_1 can be included in the operation control signal CTR_OP. The various control signals will be described below. Read and verification operations may include data sensing operations. Data sensing operations may include a series of operations for sensing data transmitted via the first bit line BL1 and storing the sensed data.

[0049] refer to Figure 3 The first page buffer circuit 210_1 may include a data transmission circuit 310, a first latch circuit 320, and a second latch circuit 330.

[0050] The data transfer circuit 310 can be configured to transfer data transmitted via the first bit line BL1 to the common sensing node CSO to the data sensing node DSO during data sensing operation. The common sensing node CSO can have a voltage level corresponding to the state of data programmed into the selected memory cell during data sensing operation. Similarly, the data sensing node DSO can have a voltage level corresponding to the state of data programmed into the selected memory cell during data sensing operation. In other words, the data transfer circuit 310 can transfer data programmed into the selected memory cell to both the common sensing node CSO and the data sensing node DSO. The data transfer circuit 310 may include first NMOS transistors to third NMOS transistors NM1, NM2, and NM3, and a first PMOS transistor PM1 and a second PMOS transistor PM2.

[0051] A first NMOS transistor NM1 can be coupled between the first bit line BL1 and the common sensing node CSO. The first NMOS transistor NM1 can have a gate terminal configured to receive the buffer sensing control signal PB_SENSE. A second NMOS transistor NM2 can be coupled between the first PMOS transistor PM1 and the common sensing node CSO. The second NMOS transistor NM2 can have a gate terminal configured to receive the current control signal SA_CSOC. A third NMOS transistor NM3 can be coupled between the common sensing node CSO and the data sensing node DSO. The third NMOS transistor NM3 can have a gate terminal configured to receive the transmit control signal SA_SENSE. The first PMOS transistor PM1 and the second PMOS transistor PM2 can be connected in series between the power supply voltage terminal VCORE and the data sensing node DSO. The first PMOS transistor PM1 can have a gate terminal configured to receive the first precharge signal SA_PRE_N, and the second PMOS transistor PM2 can have a gate terminal configured to receive the second precharge signal SA_PRECH_N.

[0052] The following describes a simplified circuit operation for the data sensing operation of the data transmission circuit 310. For reference, the data sensing operation may include a pre-charge operation, an evaluation operation, and a data latching operation.

[0053] During the precharge operation, the first PMOS transistor PM1 and the second PMOS transistor PM2 can be turned on. Therefore, the data sensing node DSO can be precharged at the voltage level applied to the power supply voltage terminal VCORE. The third NMOS transistor NM3 can also be turned on. At this time, the common sensing node CSO can be precharged at a voltage level lower than that of the data sensing node DSO. When the voltage level of the transmission control signal SA_SENSE is equal to the voltage level applied to the power supply voltage terminal VCORE, the common sensing node CSO can be precharged at a voltage level lower than the threshold voltage of the third NMOS transistor NM3 than the voltage level applied to the power supply voltage terminal VCORE.

[0054] During the evaluation operation, the second PMOS transistor PM2 can be turned off. Therefore, the voltage levels of the common sensing node CSO and the data sensing node DSO can be controlled according to the state of the data programmed into the selected memory cell. The selected memory cell can have a threshold voltage corresponding to the state of the data programmed into it. Therefore, when the threshold voltage of the selected memory cell is higher than the read voltage applied to the selected word line during the data sensing operation, no current flows through the first line BL1. Therefore, the voltage levels of the common sensing node CSO and the data sensing node DSO can be maintained at the precharge voltage level. Conversely, when the threshold voltage of the selected memory cell is lower than the read voltage applied to the selected word line during the data sensing operation, current can flow through the first line BL1. Therefore, the voltage levels of the common sensing node CSO and the data sensing node DSO can be reduced by the same amount. In other words, the common sensing node CSO and the data sensing node DSO can have voltage levels corresponding to the state of the data programmed into the selected memory cell during the data sensing operation.

[0055] As a result, the data transmission circuit 310 can transmit data transmitted via the first bit line BL1 to the data sensing node DSO via the shared sensing node CSO during data sensing operations. Data transmitted in this manner can be transmitted and stored in the first latch circuit 320 and the second latch circuit 330, which will be described below, through data latching operations.

[0056] Before describing the first latch circuit 320 and the second latch circuit 330, reference will be made to... Figure 4 Describe the voltage levels of the shared sensing node (CSO) and the data sensing node (DSO).

[0057] Figure 4 It's a diagram. Figure 3 A graph showing the voltage levels of the shared sensing node (CSO) and the data sensing node (DSO). Figure 4In the diagram, the horizontal axis corresponds to time t, and the vertical axis corresponds to voltage V. As described above, current can flow through the first line BL1 depending on the state of the data programmed into the selected memory cell. Hereinafter, for ease of explanation, the current flowing through the first line BL1 will be defined as the trip current itrip. In other words, depending on the state of the data programmed into the selected memory cell, a trip current itrip corresponding to, for example, 20nA, 30nA, 40nA, 50nA, or 100nA can flow through the first line BL1.

[0058] First, the shared sensing node CSO and the data sensing node DSO can be precharged during the precharge operation period T1. During this time, the data sensing node DSO can be precharged at a voltage level corresponding to the power supply voltage terminal VCORE. Furthermore, as the threshold voltage and gate voltage of the third NMOS transistor NM3 are reflected in the shared sensing node CSO, the shared sensing node CSO can be precharged at a lower voltage level than the data sensing node DSO.

[0059] During the evaluation operation period T2, the voltage level of the data sensing node DSO can decrease depending on the switching current itrip. At this time, when the switching current itrip flowing through the first line BL1 is 50nA or 100nA, the voltage level of the data sensing node DSO may become lower than the voltage level of the shared sensing node CSO when it is pre-charged. In other words, when the switching current itrip is 50nA or 100nA, the voltage level of the data sensing node DSO may become lower than the voltage level of the shared sensing node CSO that was pre-charged during the pre-charge operation period T1.

[0060] Therefore, data transmitted to the common sensing node CSO during the data latching operation period T3 can be sensed based on a first trip voltage V_TRIP1 that is lower than the voltage associated with a 40nA trip current itrip and higher than the voltage associated with a 50nA trip current itrip. For example, the first trip voltage V_TRIP1 can be associated with a 45nA trip current itrip. Furthermore, for example, data transmitted to the data sensing node DSO during the data latching operation period T3 can be sensed based on a second trip voltage V_TRIP2 corresponding to a 30nA trip current itrip. The second trip voltage V_TRIP2 can have a higher voltage level than the first trip voltage V_TRIP1. The first trip voltage V_TRIP1 and the second trip voltage V_TRIP2 will be described again below.

[0061] According to this embodiment, the first page buffer circuit 210_1 can sense data transmitted to the common sensing node CSO based on a first switching voltage V_TRIP1, and sense data transmitted to the data sensing node DSO based on a second switching voltage V_TRIP2. In other words, the first page buffer circuit 210_1 can simultaneously perform data sensing operations on the common sensing node CSO and the data sensing node DSO, which are different sensing nodes. Therefore, the first page buffer circuit 210_1 can minimize or reduce data sensing operations. Furthermore, the first page buffer circuit 210_1 can minimize or reduce read and verification operation time through such data sensing operations.

[0062] For reference, currently at least two data sensing operations are performed to more accurately sense the data programmed in the selected memory cell. In other words, in the prior art, at least two precharge operations, at least two evaluation operations, and at least two data latch operations are performed. However, the first page buffer circuit 210_1 according to this embodiment can sense the first transition voltage V_TRIP1 and the second transition voltage V_TRIP2, which are different transition voltages, through a single data sensing operation. Therefore, the first page buffer circuit 210_1 can minimize or reduce the number of data sensing operations.

[0063] Refer again Figure 3 The first latch circuit 320 and the second latch circuit 330 will be described.

[0064] The first latch circuit 320 can be configured to sense and store the sensed data transmitted to the common sensing node CSO during a data sensing operation. The first latch circuit 320 can sense the data transmitted to the common sensing node CSO based on the aforementioned first switching voltage V_TRIP1.

[0065] However, this embodiment is not limited thereto. The first switching voltage V_TRIP1 can be set by designing the first latch circuit 320 to distinguish the voltage level of the common sensing node CSO. The first latch circuit 320 may include a latch drive circuit 321 and a current control circuit 322.

[0066] The latch drive circuit 321 can be configured to store data transmitted to the common sensing node CSO. The latch drive circuit 321 may include a first drive buffer BF1; a second drive buffer BF2; and a fourth to an eighth NMOS transistor NM4, NM5, NM6, NM7 and NM8.

[0067] The first drive buffer BF1 and the second drive buffer BF2 can be coupled in a latched configuration. In other words, the output terminal of the first drive buffer BF1 can be coupled to the input terminal of the second drive buffer BF2, and the output terminal of the second drive buffer BF2 can be coupled to the input terminal of the first drive buffer BF1. The input terminal of the first drive buffer BF1 is defined as the first primary data node QN1, and the output terminal of the first drive buffer BF1 is defined as the first secondary data node QN1_N.

[0068] With this configuration, the latch drive circuit 321 can store the data transmitted to the common sensing node CSO in the first auxiliary data node QN1_N / first main data node QN1, which serves as the corresponding output terminals of the first drive buffer BF1 and the second drive buffer BF2. The configuration and operation for transmitting the data to the common sensing node CSO to the latch drive circuit 321 will be described again below in the description of the current control circuit 322.

[0069] The fourth NMOS transistor NM4 may have a drain and a source terminal coupled between the first main data node QN1 and the sixth NMOS transistor NM6. The fourth NMOS transistor NM4 may have a gate terminal configured to receive a first reset control signal RST1. The fifth NMOS transistor NM5 may have a drain and a source terminal coupled between the first auxiliary data node QN1_N and the sixth NMOS transistor NM6. The fifth NMOS transistor NM5 may have a gate terminal configured to receive a first set control signal SET1. The sixth NMOS transistor NM6 may have a drain and a source terminal coupled between the ground voltage terminal VSS and a common node located between the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5. The sixth NMOS transistor NM6 may have a gate terminal coupled to the data sensing node DSO. The seventh NMOS transistor NM7 and the eighth NMOS transistor NM8 may be connected in series between the data sensing node DSO and the ground voltage terminal VSS. The seventh NMOS transistor NM7 may have a gate terminal configured to receive the first data transmission signal TRAN_1. The eighth NMOS transistor NM8 may have a gate terminal coupled to the first master data node QN1.

[0070] With this configuration, the latch drive circuit 321 can perform a setting operation based on the first setting control signal SET1, and a reset operation based on the first reset control signal RST1. Furthermore, for example, during data migration operations other than data sensing operations, the latch drive circuit 321 can drive the data sensing node DSO based on the first data transfer signal TRAN_1 and the data stored in the first primary data node QN1 / first auxiliary data node QN1_N.

[0071] The current control circuit 322 can be configured to control the drive current of the latch drive circuit 321 based on data transmitted to the common sensing node CSO. The current control circuit 322 can also control the drive current of the latch drive circuit 321 based on an enable control signal CTR_EN activated during data sensing operations. The current control circuit 322 may include a thirty-first NMOS transistor NM31 and a thirty-second NMOS transistor NM32.

[0072] The 31st NMOS transistor NM31 may have a drain terminal and a source terminal coupled between the first main data node QN1 and the 32nd NMOS transistor NM32. The 31st NMOS transistor NM31 may also have a gate terminal coupled to the common sensing node CSO. In other words, the 31st NMOS transistor NM31 may have a gate terminal coupled to the common sensing node CSO and a side coupled to the first main data node QN1. The 32nd NMOS transistor NM32 may have a drain terminal and a source terminal coupled between the 31st NMOS transistor NM31 and the ground voltage terminal VSS. The 32nd NMOS transistor NM32 may have a gate terminal configured to receive an enable control signal CTR_EN. In other words, the 32nd NMOS transistor NM32 can receive the enable control signal CTR_EN through its gate terminal and may be coupled between the other side of the 31st NMOS transistor NM31 and the ground voltage terminal VSS.

[0073] Although will refer to Figure 5 To reiterate, the enable control signal CTR_EN can be a signal activated during data sensing operations. Therefore, when the enable control signal CTR_EN is activated after data is transmitted to the common sensing node CSO, the first master data node QN1 and the ground voltage terminal VSS can be electrically coupled to each other based on the voltage level of the common sensing node CSO. In other words, the drive current of the first master data node QN1 can be controlled based on the data applied to the common sensing node CSO. When the drive current is controlled, the voltage level of the first master data node QN1 can also be controlled.

[0074] With this configuration, the current control circuit 322 can control the drive current of the latch drive circuit 321 based on the data transmitted to the common sensing node CSO. Therefore, the latch drive circuit 321 can store the data transmitted to the common sensing node CSO based on the drive current controlled by the current control circuit 322.

[0075] In short, the first latch circuit 320, including latch drive circuit 321 and current control circuit 322, can sense and store data transmitted to the common sensing node CSO during data sensing operations. More specifically, the first latch circuit 320 can sense the data transmitted to the common sensing node CSO based on a first transition voltage V_TRIP1 and store the sensing result. The voltage level of the first transition voltage V_TRIP1 can be set according to the process design of the thirty-first NMOS transistor NM31 and thirty-second NMOS transistor NM32 included in the current control circuit 322. Although not shown in the figures, the voltage level V_TRIP1 of the first transition voltage can be set differently and selectively through various additional circuit configurations.

[0076] The second latch circuit 330 can be configured to sense and store the sensed data transmitted to the data sensing node DSO during data sensing operations. The second latch circuit 330 can sense the data transmitted to the data sensing node DSO based on the aforementioned second switching voltage V_TRIP2. (See also...) Figure 4 The second switching voltage V_TRIP2 is described as having a voltage level corresponding to a switching current itrip of 30 nA. However, this embodiment is not limited to this. The second switching voltage V_TRIP2 can be set by designing the second latch circuit 330 to distinguish the voltage level of the data sensing node DSO. The second latch circuit 330 may include a latch drive circuit 331 and a current control circuit 332.

[0077] The latch drive circuit 331 can be configured to store data transmitted to the data sensing node DSO. The latch drive circuit 331 may include a third drive buffer BF3, a fourth drive buffer BF4, and a tenth NMOS transistor NM10 and an eleventh NMOS transistor NM11.

[0078] The third drive buffer BF3 and the fourth drive buffer BF4 can be coupled in a latched configuration. In other words, the output terminal of the third drive buffer BF3 can be coupled to the input terminal of the fourth drive buffer BF4, and the output terminal of the fourth drive buffer BF4 can be coupled to the input terminal of the third drive buffer BF3. The input terminal of the third drive buffer BF3 is defined as the second primary data node QN2, and the output terminal of the third drive buffer BF3 is defined as the second auxiliary data node QN2_N.

[0079] With this configuration, the latch drive circuit 331 can store the data transmitted to the data sensing node DSO in the second auxiliary data node QN2_N / second main data node QN2, which serves as the corresponding output terminals of the third drive buffer BF3 and the fourth drive buffer BF4. The configuration and operation for transmitting the data to the data sensing node DSO to the latch drive circuit 331 will be described again below in the description of the current control circuit 332.

[0080] The tenth NMOS transistor NM10 and the eleventh NMOS transistor NM11 can be connected in series between the data sensing node DSO and the ground voltage terminal VSS. The tenth NMOS transistor NM10 can have a gate terminal configured to receive the second data transmission signal TRAN_2. The eleventh NMOS transistor NM11 can have a gate terminal coupled to the second main data node QN2.

[0081] Therefore, with such a configuration, for example, during data migration operations other than data sensing operations, the latch drive circuit 331 can drive the data sensing node DSO based on the second data transmission signal TRAN_2 and the data stored in the second primary data node QN2 / second auxiliary data node QN2_N.

[0082] The current control circuit 332 can be configured to control the drive current of the latch drive circuit 331 based on the data transmitted to the data sensing node DSO. The current control circuit 332 may include twelfth to fourteenth NMOS transistors NM12, NM13 and NM14.

[0083] The twelfth NMOS transistor NM12 may have a drain and a source terminal coupled between the second main data node QN2 and the fourteenth NMOS transistor NM14. The twelfth NMOS transistor NM12 may have a gate terminal configured to receive a second reset control signal RST2. The thirteenth NMOS transistor NM13 may have a drain and a source terminal coupled between the second auxiliary data node QN2_N and the fourteenth NMOS transistor NM14. The thirteenth NMOS transistor NM13 may have a gate terminal configured to receive a second set control signal SET2. The fourteenth NMOS transistor NM14 may have a drain and a source terminal coupled between the ground voltage terminal VSS and the common node located between the twelfth NMOS transistor NM12 and the thirteenth NMOS transistor NM13. The fourteenth NMOS transistor NM14 may have a gate terminal coupled to the data sensing node DSO.

[0084] With this configuration, the current control circuit 332 can perform a setting operation on the latch drive circuit 331 based on the second setting control signal SET2, and a reset operation on the latch drive circuit 331 based on the second reset control signal RST2. The second reset control signal RST2 can be activated during data sensing operations. Therefore, the current control circuit 332 can control the drive current of the latch drive circuit 331 based on the data transmitted to the data sensing node DSO. Therefore, the latch drive circuit 331 can store the data transmitted to the data sensing node DSO based on the drive current controlled by the current control circuit 332.

[0085] In short, during data sensing operations, a second latch circuit 330, including latch drive circuit 331 and current control circuit 332, can sense and store the data transmitted to the data sensing node DSO. More specifically, the second latch circuit 330 can sense the data transmitted to the data sensing node DSO based on a second switching voltage V_TRIP2 and store the sensing result. The voltage level of the second switching voltage V_TRIP2 can be set according to the process design of the twelfth NMOS transistor NM12 and the fourteenth NMOS transistor NM14 included in the current control circuit 332. Although not shown in the figures, the voltage level V_TRIP2 of the second switching voltage can be set differently and selectively through various additional circuit configurations.

[0086] In this respect, the latch drive circuits 321 and 331 of the first latch circuit 320 and the second latch circuit 330 can be implemented using the same process design. When the circuits are implemented using the same process design, the components of the corresponding circuits can be indicated to have the same circuit operating characteristics. As described above, the first switching voltage V_TRIP1 can be set by the current control circuit 322 of the first latch circuit 320, and the second switching voltage V_TRIP2 can be set by the current control circuit 332 of the second latch circuit 330. Therefore, although the latch drive circuits 321 and 331 of the first latch circuit 320 and the second latch circuit 330 have the same circuit operating characteristics, the first latch circuit 320 can apply the first switching voltage V_TRIP1, while the second latch circuit 330 can apply the second switching voltage V_TRIP2.

[0087] As a result, during the data sensing operation, the first latch circuit 320 can sense the data transmitted to the shared sensing node CSO based on the first switching voltage V_TRIP1. Then, during the data sensing operation, the second latch circuit 330 can sense the data transmitted to the data sensing node DSO based on the second switching voltage V_TRIP2.

[0088] According to this embodiment, the first page buffer circuit 210_1 can simultaneously perform corresponding data sensing operations on the shared sensing node CSO and the data sensing node DSO. Therefore, the first page buffer circuit 210_1 can minimize or reduce data sensing operations, thereby minimizing the read and verification operation time.

[0089] Figure 5 It is used to describe Figure 3 The first page shows the timing diagram of the operation of the buffer circuit 210_1. Figure 5 The diagram illustrates the selected word line WL, the buffer sensing control signal PB_SENSE, the first precharge signal SA_PRE_N, the current control signal SA_CSOC, the second precharge signal SA_PRECH_N, the transfer control signal SA_SENSE, the data sensing node DSO, the second reset control signal RST2, and the enable control signal CTR_EN.

[0090] refer to Figures 3 to 5The selected word line WL can receive the read pass voltage VPASS during the precharge operation period T1. The first NMOS transistor NM1 can be turned on based on the buffer sense control signal PB_SENSE. The first PMOS transistor PM1 can be turned on based on the first precharge signal SA_PRE_N. The second NMOS transistor NM2 can be turned on based on the current control signal SA_CSOC. The second PMOS transistor PM2 can be turned on based on the second precharge signal SA_PRECH_N. The third NMOS transistor NM3 can be turned on based on the transmit control signal SA_SENSE.

[0091] In other words, during the pre-charge operation period T1, the power supply voltage terminal VCORE can be electrically coupled to the data sensing node DSO and pre-charged at a voltage level corresponding to the power supply voltage terminal VCORE. (See reference...) Figure 4 As described, the shared sensing node CSO can also be precharged during the precharge operation period T1, just like the data sensing node DSO.

[0092] Then, during the evaluation operation period T2, the second PMOS transistor PM2 can be turned off based on the second precharge signal SA_PRECH_N. Therefore, the voltage level of the data sensing node DSO can be reduced according to the state of the data programmed into the memory cell. (See reference...) Figure 4 As described, the voltage level of the shared sensing node CSO can also be reduced based on the state of the data programmed into the memory cell during the evaluation operation period T2, just like the data sensing node DSO. When the evaluation operation is complete, the third NMOS transistor NM3 can be turned off based on the transfer control signal SA_SENSE.

[0093] Then, during the data latching operation period T3, the second reset control signal RST2 and the enable control signal CTR_EN can be activated. When the second reset control signal RST2 is activated, the data transmitted to the data sensing node DSO can be stored in the second latch circuit 330. Furthermore, when the enable control signal CTR_EN is activated, the data transmitted to the common sensing node CSO can be stored in the first latch circuit 320. The activation periods of the second reset control signal RST2 and the enable control signal CTR_EN can overlap. In other words, the data latching operation of the first latch circuit 320 and the data latching operation of the second latch circuit 330 can be performed simultaneously.

[0094] As described above, the first latch circuit 320 can sense data based on the first transition voltage V_TRIP1, and the second latch circuit 330 can sense data based on the second transition voltage V_TRIP2. Therefore, the first page buffer circuit 210_1 according to this embodiment can obtain a more accurate data sensing operation result through a single data latching operation.

[0095] exist Figure 5 In this example, the enable control signal CTR_EN is activated during the data latching operation period T3. The activation time of the enable control signal CTR_EN is not limited to this. In other words, the enable control signal CTR_EN can be activated during other periods, including the evaluation operation period T2. Furthermore, the deactivation time of the enable control signal CTR_EN can be earlier than the activation time of the second reset control signal RST2. Therefore, before the second latch circuit 330 senses and stores the data transmitted to the data sensing node DSO, the first latch circuit 320 can sense and store the data transmitted to the common sensing node CSO. Furthermore, the deactivation time of the enable control signal CTR_EN can be later than the deactivation time of the second reset control signal RST2.

[0096] During a data sensing operation, the first page buffer circuit 210_1 according to this embodiment can sense the data transmitted to the shared sensing node CSO and the data sensing node DSO based on different first switching voltages V_TRIP1 and second switching voltages V_TRIP2. Therefore, the first page buffer circuit 210_1 can minimize or reduce the data sensing operation.

[0097] Figure 6 It is a schematic diagram illustrating the following: Figure 2 The first page buffer circuit 210_1 is a circuit diagram of some components of one embodiment.

[0098] refer to Figure 6 The first page buffer circuit 210_1 may include a data transmission circuit 610, a first latch circuit 620, and a second latch circuit 630. Figure 6 The configuration of the first latch circuit 620 is similar to the configuration of the first latch circuit 620. Figure 3 The configurations are different. More specifically, Figure 6 The first latch circuit 620 may include a latch drive circuit 621 and a current control circuit 622. Figure 6 The latch drive circuit 621 can correspond to Figure 3 The latch drive circuit 321. Hereinafter, for ease of explanation, the current control circuit 622 will be described.

[0099] The current control circuit 622 can be configured to control the drive current of the latch drive circuit 621 based on data transmitted to the common sensing node CSO. The current control circuit 622 may include a fifteenth NMOS transistor NM15 and a sixteenth NMOS transistor NM16.

[0100] The fifteenth NMOS transistor NM15 may have source and drain terminals coupled between the common sensing node CSO and the sixteenth NMOS transistor NM16. The fifteenth NMOS transistor NM15 may have a gate terminal configured to receive an enable control signal CTR_EN. In other words, the fifteenth NMOS transistor NM15 can receive the enable control signal CTR_EN through its gate terminal and has one side coupled to the common sensing node CSO. The sixteenth NMOS transistor NM16 may have drain and source terminals coupled between the first main data node QN1 and the ground voltage terminal VSS. The sixteenth NMOS transistor NM16 may have a gate terminal coupled to the fifteenth NMOS transistor NM15. In other words, the sixteenth NMOS transistor NM16 can couple its gate terminal to the other side of the fifteenth NMOS transistor NM15 and can also be coupled between the first main data node QN1 and the ground voltage terminal VSS.

[0101] With this configuration, the current control circuit 622 can control the drive current of the latch drive circuit 621 based on the data transmitted to the common sensing node CSO. In other words, when the enable control signal CTR_EN is activated after the data is transmitted to the common sensing node CSO, the first master data node QN1 and the ground voltage terminal VSS can be electrically coupled to each other according to the voltage level of the common sensing node CSO. Therefore, the current control circuit 622 can control the drive current of the first master data node QN1 based on the data applied to the common sensing node CSO. Therefore, the latch drive circuit 621 can store the data transmitted to the common sensing node CSO based on the drive current controlled by the current control circuit 622.

[0102] In short, during data sensing operations, the first latch circuit 620 can sense the data transmitted to the common sensing node CSO based on a first switching voltage V_TRIP1 and store the sensing results. The voltage level of the first switching voltage V_TRIP1 can be set according to the process design of the fifteenth NMOS transistor NM15 and the sixteenth NMOS transistor NM16 included in the current control circuit 622. Although not shown in the figures, the voltage level of the first switching voltage V_TRIP1 can be set differently and selectively through various additional circuit configurations.

[0103] As a result, during the data sensing operation, the first latch circuit 620 can sense the data transmitted to the shared sensing node CSO based on the first switching voltage V_TRIP1. Then, during the data sensing operation, the second latch circuit 630 can sense the data transmitted to the data sensing node DSO based on the second switching voltage V_TRIP2.

[0104] Figure 7 It is illustrated according to Figure 2 The first page buffer circuit 210_1 is a circuit diagram of some components of one embodiment.

[0105] refer to Figure 7 The first page buffer circuit 210_1 may include a data transmission circuit 710, a first latch circuit 720, and a second latch circuit 730. Figure 7 The configuration of the first latch circuit 720 is similar to the configuration of the first latch circuit 720. Figure 3 The configurations are different. More specifically, Figure 7 The first latch circuit 720 may include a latch drive circuit 721 and a current control circuit 722. Figure 7 The latch drive circuit 321 can correspond to Figure 3 The latch drive circuit 321. Hereinafter, for ease of explanation, the current control circuit 722 will be described.

[0106] The current control circuit 722 can be configured to control the drive capability of the latch drive circuit 721 based on data transmitted to the common sensing node CSO. The current control circuit 722 may include a seventeenth NMOS transistor NM17 and an eighteenth NMOS transistor NM18.

[0107] The seventeenth NMOS transistor NM17 may have a drain and a source terminal coupled between the first main data node QN1 and the eighteenth NMOS transistor NM18. The seventeenth NMOS transistor NM17 may have a gate terminal configured to receive an enable control signal CTR_EN. In other words, the seventeenth NMOS transistor NM17 can receive the enable control signal CTR_EN through its gate terminal and has one side coupled to the first main data node QN1. The eighteenth NMOS transistor NM18 may have a drain and a source terminal coupled between the seventeenth NMOS transistor NM17 and the ground voltage terminal VSS. The eighteenth NMOS transistor NM18 may have a gate terminal coupled to the common sensing node CSO. In other words, the eighteenth NMOS transistor NM18 can have its gate terminal coupled to the common sensing node CSO and can also be coupled between the seventeenth NMOS transistor NM17 and the ground voltage terminal VSS.

[0108] With this configuration, the current control circuit 722 can control the drive current of the latch drive circuit 721 based on the data transmitted to the common sensing node CSO. Furthermore, the latch drive circuit 721 can store the data transmitted to the common sensing node CSO based on the drive current controlled by the current control circuit 722. As a result, during data sensing operations, the first latch circuit 720 can sense the data transmitted to the common sensing node CSO and store the sensing result based on the first transition voltage V_TRIP1. The voltage level of the first transition voltage V_TRIP1 can be set according to the process design of the seventeenth NMOS transistor NM17 and the eighteenth NMOS transistor NM18 included in the current control circuit 722. Furthermore, the voltage level of the first transition voltage V_TRIP1 can be set according to the process design of the fifth drive buffer BF5 and the sixth drive buffer BF6.

[0109] exist Figure 7 In this architecture, the seventeenth NMOS transistor NM17 can perform the reset operation of the latch drive circuit 721. Therefore, the enable control signal CTR_EN used to control the seventeenth NMOS transistor NM17 can be activated during the reset operation.

[0110] As a result, during data sensing operations, the first latch circuit 720 can sense the data transmitted to the common sensing node CSO based on the first switching voltage V_TRIP1. Furthermore, during data sensing operations, the second latch circuit 730 can sense the data transmitted to the data sensing node DSO based on the second switching voltage V_TRIP2.

[0111] Figure 8 It is used to describe Figure 3 The first page contains a flowchart of the operation method of the buffer circuit 210_1.

[0112] refer to Figure 3 and Figure 8 The operation method of the first page buffer circuit 210_1 may include an evaluation step 810, a sensing and storage step 820, and a reading step 830.

[0113] Evaluation step 810 may include evaluating multiple sensing nodes based on data transmitted during the data sensing operation. In other words, evaluation step 810 may include evaluating the shared sensing node CSO and the data sensing node DSO based on data transmitted via the first line BL1. Evaluation step 810 may be performed by… Figure 3 The data transmission circuit 310 performs this operation. As described above, the data transmission circuit 310 can be used during the evaluation operation period T2 (reference period). Figure 4 and Figure 5The data is transmitted to the shared sensing node (CSO) and the data sensing node (DSO). Therefore, the shared sensing node (CSO) and the data sensing node (DSO) can each have a voltage level corresponding to the data.

[0114] The sensing and storage step 820 may include sensing multiple sensing nodes and storing the sensing results. In other words, the sensing and storage step 820 may include sensing a shared sensing node CSO and a data sensing node DSO based on data sensing and storing the sensing results. The sensing and storage step 820 may be performed by... Figure 3 The first latch circuit 320 and the second latch circuit 330 are executed. As described above, the first latch circuit 320 and the second latch circuit 330 can be executed during the data latching operation period T3 (refer to...). Figure 5 The system senses the shared sensing node (CSO) and the data sensing node (DSO) and stores the sensing results. More specifically, the first latch circuit 320 can sense the data transmitted to the shared sensing node (CSO) based on a first switching voltage V_TRIP1 and store the sensing results. Furthermore, the second latch circuit 330 can sense the data transmitted to the data sensing node (DSO) based on a second switching voltage V_TRIP2 and store the sensing results.

[0115] The reading step 830 may include reading the result of the sensing and storing step 820. The reading step 830 may include performing a reading operation based on data stored in the first latch circuit 320 and the second latch circuit 330. Step 830 may include a verification operation. In other words, during the verification operation, data stored in the selected memory cell can be sensed and latched by the first page buffer circuit 210_1. Therefore, according to this embodiment, the first page buffer circuit 210_1 can sense and store the sensed data transmitted to the common sensing node CSO based on a first switching voltage V_TRIP1 during the verification operation. Furthermore, during the verification operation, the first page buffer circuit 210_1 can sense and store the sensed data transmitted to the data sensing node DSO based on a second switching voltage V_TRIP2.

[0116] The operation of the buffer circuit 210_1 on the first page may include a pre-charging step 840.

[0117] Pre-charging step 840 can be performed before evaluation step 810. Pre-charging step 840 may include pre-charging multiple sensing nodes to which data is transmitted during the data sensing operation. In other words, pre-charging step 840 may include pre-charging the shared sensing node CSO and the data sensing node DSO to which data is transmitted from the first bit line BL1. Pre-charging step 840 may be performed by… Figure 3The data transmission circuit 310 performs this operation. As described above, the data transmission circuit 310 can be used during the pre-charge operation period T1 (reference period). Figure 4 and Figure 5 The shared sensing node (CSO) and data sensing node (DSO) are pre-charged in the process.

[0118] During data sensing operations, the first page buffer circuit 210_1 according to this embodiment can sense the shared sensing node CSO and the data sensing node DSO, which are multiple sensing nodes, based on different first switching voltages V_TRIP1 and second switching voltages V_TRIP2, and store the sensing results. Therefore, the first page buffer circuit 210_1 can minimize or reduce data sensing operations, thereby minimizing the read and verification operation time.

[0119] Although various embodiments have been described above, those skilled in the art will understand that the described embodiments are merely examples. Therefore, the page buffer circuits and operating methods described herein should not be limited to the described embodiments.

Claims

1. A page buffer circuit, comprising: A data transmission circuit is configured to transmit data received via a bit line to a first sensing node and a second sensing node during a data sensing operation. A first latch circuit is configured to sense data transmitted to the first sensing node and store the sensed data transmitted to the first sensing node. as well as The second latch circuit is configured to sense the data transmitted to the second sensing node and store the sensed data transmitted to the second sensing node. The first latch circuit includes: A latch drive circuit is coupled to the second sensing node, the latch drive circuit being configured to store the data to be transmitted to the first sensing node in a data node and to discharge the second sensing node based on the data node; as well as A current control circuit, coupled to the data node and the first sensing node, is configured to control the drive current of the data node based on the data transmitted to the first sensing node.

2. The page buffer circuit according to claim 1, wherein: The first latch circuit senses the data transmitted to the first sensing node based on the first switching voltage, and The second latch circuit senses the data transmitted to the second sensing node based on the second switching voltage.

3. The page buffer circuit according to claim 2, wherein the second switching voltage is higher than the first switching voltage.

4. The page buffer circuit according to claim 1, wherein the latch drive circuit and the second latch circuit have the same structure.

5. The page buffer circuit of claim 1, wherein the current control circuit controls the drive current based on an enable control signal activated during the data sensing operation.

6. The page buffer circuit according to claim 5, wherein the current control circuit comprises: A first transistor has a gate terminal coupled to the first sensing node and a side of the data node coupled to the latch drive circuit. as well as The second transistor is configured to receive the enable control signal through its gate terminal, and the second transistor is coupled between the other side of the first transistor and the power supply voltage terminal.

7. The page buffer circuit according to claim 5, wherein the current control circuit comprises: A first transistor is configured to receive the enable control signal through its gate terminal, the first transistor having one side coupled to the first sensing node; as well as A second transistor is coupled between the data node and the power supply voltage terminal of the latch drive circuit, and the second transistor has a gate terminal coupled to the other side of the first transistor.

8. The page buffer circuit according to claim 5, wherein the current control circuit comprises: The first transistor has a gate terminal configured to receive the enable control signal activated during a reset operation, and has a side coupled to the data node of the latch drive circuit. as well as The second transistor is coupled between the first transistor and the power supply voltage terminal, and has a gate terminal coupled to the first sensing node.

9. The page buffer circuit of claim 5, wherein the enable control signal is activated during a period including an evaluation operation period.

10. The page buffer circuit of claim 1, wherein the second latch circuit comprises: A latch drive circuit is configured to store data transmitted to the second sensing node; as well as The current control circuit is configured to control the drive current of the latch drive circuit based on the data transmitted to the second sensing node.

11. A method of operating a page buffer circuit, the method comprising: Evaluate multiple sensing nodes based on the data transmitted during the data sensing operation; The system senses the multiple sensing nodes and stores the sensing results. as well as Read the sensing results. in Sensing the plurality of sensing nodes and storing the sensing results includes: A first storage operation that senses a first sensing node among the plurality of sensing nodes and stores the sensing result of the first sensing node; as well as A second storage operation is performed to sense the second sensing node among the plurality of sensing nodes and store the sensing result of the second sensing node. The first storage operation and the second storage operation have overlapping activation periods.

12. The operating method according to claim 11, wherein sensing the plurality of sensing nodes and storing the sensing results comprises: During the data sensing operation, the plurality of sensing nodes are sensed with different switching voltages.

13. The operating method according to claim 11, The sensing of the first sensing node is performed based on the first switching voltage, and The sensing of the second sensing node is performed based on a second switching voltage that is different from the first switching voltage.

14. The operating method of claim 11, wherein reading the sensing result includes a verification operation.

15. The method of operation according to claim 11, further comprising pre-charging the plurality of sensing nodes before evaluating the plurality of sensing nodes.

16. The operating method of claim 15, wherein the plurality of sensing nodes includes a shared sensing node and a data sensing node, and The pre-charging of the plurality of sensing nodes includes: The shared sensing node is pre-charged; as well as The data sensing node is pre-charged at a higher voltage level than that of the shared sensing node. in Sensing the plurality of sensing nodes and storing the sensing results includes: The first storage operation involves sensing the shared sensing node based on the first switching voltage and storing the result of sensing the shared sensing node. as well as The second storage operation involves sensing the data sensing node based on a second switching voltage that is higher than the first switching voltage, and storing the result of sensing the data sensing node.

17. The method of operation according to claim 16, wherein the first storage operation is activated while the plurality of sensing nodes are being evaluated.

18. The method of operation according to claim 16, wherein the first storage operation is deactivated before the second storage operation is activated.

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