Memory system and method of performing error correction on data read from a plurality of memory cells

Abstract

The present disclosure relates to a memory system and a method of performing error correction on data read from a plurality of memory cells. Embodiments provide a memory system having enhanced error correction capability and a method of performing error correction on data read from a plurality of memory cells. A memory system includes a semiconductor memory device including a plurality of memory cells each configured to store data in a non-volatile manner according to a threshold voltage thereof and connected to a word line, and a controller configured to: perform error correction based on hard bit data and soft bit data read from the plurality of memory cells; generate a first table based on the corrected data; determine a voltage difference between a first voltage and a second voltage, the first voltage being a voltage applied to the word line when the data is read; and correct the first table based on the voltage difference.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Japanese Patent Application No. 2022-043995, filed on March 18, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments described herein generally relate to memory systems and methods for performing error correction on data read from multiple memory cells. Background Technology

[0004] Memory systems, including semiconductor memory devices and memory controllers that control the semiconductor memory devices, are known. Soft-decision decoding is a known error correction method when reading data from a semiconductor memory device. Summary of the Invention

[0005] The embodiments provide a memory system with enhanced error correction capabilities and a method for performing error correction on data read from multiple memory primitives.

[0006] Generally, according to one embodiment, the memory system includes: a semiconductor memory device comprising a plurality of memory cells, each memory cell being configured to store data in a non-volatile manner according to its threshold voltage and being connected to a word line; and a controller configured to: perform error correction based on hard-bit data and soft-bit data read from the plurality of memory cells; generate a first table based on the data corrected by the error correction; determine a voltage difference between a first voltage and a second voltage, the first voltage being a voltage applied to the word line when the corrected data is read; and correct the first table based on the voltage difference. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating an example of an information processing system including a memory system according to a first embodiment.

[0008] Figure 2 This is a block diagram illustrating an example configuration of an error checking and correction (ECC) circuit in a memory controller provided in a memory system according to the first embodiment.

[0009] Figure 3 This is a block diagram illustrating an example configuration of a semiconductor memory device arranged in a memory system according to the first embodiment.

[0010] Figure 4This is a circuit diagram showing an array of memory cells in a semiconductor memory device disposed in a memory system according to the first embodiment.

[0011] Figure 5 This is a diagram illustrating an example of the relationship between the threshold voltage distribution of memory primitive transistors arranged in a memory system according to the first embodiment and the data stored by the memory primitive transistors.

[0012] Figure 6 This is a diagram illustrating an example of the relationship between the threshold voltage distribution of memory element transistors arranged in a memory system according to the first embodiment, the voltage used for data reading, and the data read.

[0013] Figure 7 This is a diagram illustrating the process for soft-decision decoding according to the first embodiment.

[0014] Figure 8 This is a conceptual diagram of the log-likelihood ratio (LLR) table based on the first embodiment.

[0015] Figure 9 This is a table showing the channel matrix according to the first embodiment.

[0016] Figures 10A to 10E This is a diagram illustrating the process of generating shift values ​​according to the first embodiment.

[0017] Figure 11A This is a diagram illustrating a first example of the correction process for the dynamic LLR estimation (DLE) table according to the first embodiment.

[0018] Figure 11B This is a diagram illustrating a second example of the correction process for the DLE table according to the first embodiment.

[0019] Figure 11C This is a diagram illustrating a third example of the correction process for the DLE table according to the first embodiment.

[0020] Figure 12 This is a flowchart illustrating a read operation performed by a memory controller provided in a memory system according to the first embodiment.

[0021] Figure 13A and Figure 13B This is a diagram illustrating the effects of the memory system according to the first embodiment.

[0022] Figure 14 This is a block diagram illustrating an example of an information processing system including a memory system according to a second embodiment.

[0023] Figure 15This is a block diagram illustrating an example configuration of the ECC circuit in a memory controller provided in a memory system according to the second embodiment.

[0024] Figure 16 This is a diagram illustrating the process for soft-decision decoding according to the second embodiment.

[0025] Figure 17 This is a diagram illustrating the first and second correction processes of the DLE table according to the second embodiment.

[0026] Figure 18 This is a flowchart illustrating a read operation performed by a memory controller provided in a memory system according to the second embodiment.

[0027] Figure 19 This is a flowchart illustrating a read operation performed by a memory controller provided in a memory system according to the second embodiment.

[0028] Figure 20 This is a conceptual diagram of the LLR schema table according to the third embodiment.

[0029] Figure 21 This is a diagram illustrating the correction process of the DLE table according to the third embodiment.

[0030] Figure 22 This is a diagram illustrating the correction process of the DLE table according to the fourth embodiment.

[0031] Figure 23 This is a flowchart illustrating a read operation performed by a memory controller provided in a memory system according to the fifth embodiment.

[0032] Figure 24 This is a diagram illustrating the symmetry of the LLR in the DLE table according to the fifth embodiment. Detailed Implementation

[0033] In the following description, embodiments will be described with reference to the accompanying drawings. In the description, common components in all the drawings are given common reference numerals.

[0034] In the following examples, the function blocks may not be distinguishable from each other. For example, some functions may be performed by function blocks different from the function block shown. Furthermore, the function block shown may be divided into further subdivided function sub-blocks. The embodiments are not limited to the specific function block that implements the function.

[0035] Furthermore, each functional block can be implemented by either or a combination of hardware and computer software.

[0036] [1] First embodiment

[0037] A memory system according to the first embodiment will be described. Hereinafter, a memory system including NAND flash memory will be described as an example of a semiconductor memory device.

[0038] [1-1] Configuration

[0039] [1-1-1] Memory System Configuration

[0040] Reference Figure 1 A configuration example of a memory system according to an embodiment is described. Figure 1 This is a block diagram illustrating an example of an information processing system including a memory system according to an embodiment.

[0041] The information processing system includes a memory system 1 and a host device 2.

[0042] Memory system 1 is, for example, a solid-state drive (SSD), a universal flash memory (UFS) device, a universal serial bus (USB) memory, a multimedia card (MMC), or Card. The memory system 1 can be connected to the host device 2. The memory system 1 performs processing based on request signals received from the host device 2 or on spontaneous (or internal) processing requests.

[0043] Host device 2 is, for example, a personal computer, server system, mobile device, vehicle-mounted device, or digital camera.

[0044] Next, the internal configuration of memory system 1 will be described.

[0045] The memory system 1 includes a memory controller 10 and a semiconductor memory device 30. The semiconductor memory device 30 is a non-volatile memory such as NAND flash memory. Hereinafter, the semiconductor memory device 30 is also referred to as NAND flash memory 30.

[0046] The memory controller 10 is, for example, a system-on-a-chip (SoC). The memory controller 10 is connected to the host device 2 via a host bus. The memory controller 10 receives request signals from the host device 2 via the host bus. The type of host bus depends on the type of memory system 1. When the memory system 1 is an SSD, it may be a serial SCSI (SAS), serial ATA (SATA), or peripheral component rapid interconnect (PCI) bus. The interface of the PCIe standard is used as the host bus. When the memory system 1 is a UFS device, the M-PHY standard interface is used as the host bus. When the memory system 1 is a USB memory, the USB standard interface is used as the host bus. When the memory system 1 is MMC, the embedded multimedia card (eMMC) standard interface is used as the host bus. Card time, The standard interface is used as the host bus.

[0047] The memory controller 10 controls the NAND flash memory 30 via the NAND bus based on request signals received from the host device 2 or spontaneous processing requests. The NAND bus performs signal transmission and reception according to the NAND interface standard.

[0048] The NAND flash memory 30 includes a plurality of memory primitive transistors. Each of the plurality of memory primitive transistors stores data in a non-volatile manner according to its threshold voltage. The NAND flash memory 30 stores data received from the memory controller 10 in a non-volatile manner in the plurality of memory primitive transistors. The NAND flash memory 30 outputs data read from the plurality of memory primitive transistors to the memory controller 10.

[0049] Next, the internal configuration of the memory controller 10 will be described.

[0050] The memory controller 10 includes a host interface (I / F) circuit 11, a processor (central processing unit (CPU)) 12, a buffer memory 13, an error checking and correction (ECC) circuit 14, a read-only memory (ROM) 15, a random access memory (RAM) 16, a read information generation circuit 17, and a NAND interface (I / F) circuit 18.

[0051] The host interface circuit 11 is responsible for communication between the memory controller 10 and the host device 2. The host interface circuit 11 is connected to the host device 2 via the host bus.

[0052] Processor 12 is the control circuitry for memory controller 10. Processor 12 controls the overall operation of memory controller 10 by executing programs stored in ROM 15. For example, when processor 12 receives a write request from host device 2, processor 12 controls a write operation based on the write request. The same applies to read and erase operations.

[0053] Buffer memory 13 is, for example, static random access memory (SRAM). Buffer memory 13 temporarily stores data to be written and data to be read. Data to be written is data to be written to NAND flash memory 30. Data to be read is data to be read from NAND flash memory 30.

[0054] ECC circuit 14 is a circuit that performs ECC processing. ECC processing includes data encoding and decoding. Encoding is the operation of generating error correction codes (hereinafter also referred to as "parity") based on the data received from host device 2 during a write operation (referred to herein as user data). The error correction codes are added to the user data. Error correction codes (ECC) are added to the user data after encoding is complete. In the following, in ECC circuit 14, the set of data to be decoded is referred to as an "ECC frame". An ECC frame includes user data and error correction codes (ECC). Decoding is the operation of performing error correction on the user data based on the ECC frames received from NAND flash memory 30 during a read operation. Error correction codes (ECC) are used to detect and correct errors.

[0055] Furthermore, write and read operations are performed on a page-by-page basis, as described below. In this disclosure, write and read data having a length of one page are also referred to as "page data." Page data may include multiple ECC frames. Moreover, the data length of the page data and the data length of the ECC frame may be equal to each other.

[0056] In this embodiment, the read operation includes hard bit (HB) read and soft bit (SB) read.

[0057] HB read is a process that uses a read voltage (hereinafter referred to as "HB read voltage") corresponding to the boundary of the threshold voltage distribution of the memory's fundamental transistors to read data and determine whether the data stored in the memory's fundamental transistors is "0" or "1". The page data obtained through HB read is also called "HB data". Each bit of HB data is called a "hard bit".

[0058] SB reading is a process that uses multiple voltages (hereinafter also referred to as "SB reading voltages") set based on the HB reading voltage to read data and obtain the calculation results of logical calculations on multiple read data. SB reading is performed when error correction performed by the hard-decision decoding circuit 20 (described later) fails. The page data obtained through SB reading is also called "SB data". Each bit of SB data is called a "soft bit".

[0059] ROM 15 is, for example, an electrically erasable programmable read-only memory. ROM 15 stores programs such as firmware.

[0060] RAM 16 is, for example, SRAM. RAM 16 serves as the working area for processor 12. RAM 16 stores firmware and various management information for managing NAND flash memory 30. RAM 16 stores, for example, a log-likelihood ratio (LLR) table and the value Vst of the read voltage offset from the default HB read voltage (the initial value of the HB read voltage) (hereinafter also referred to as "shift value Vst"). In the following text, the default HB read voltage will also be referred to as "default voltage Vdt".

[0061] The LLR table is a table in which read data and LLR are correlated. The LLR represents the probability of data stored in the memory transistors being "0" and the probability of data stored in the memory transistors being "1" in a logarithmic ratio. Details of the LLR table and the shift value Vst will be described later. For example, the LLR table is loaded from the NAND flash memory 30 into RAM 16 immediately after power-on. For example, when a shift value Vst is generated, the shift value Vst is written to RAM 16. Note that the initial value of the shift value Vst is equal to the default voltage Vdt.

[0062] The read information generation circuit 17 is a circuit that performs the generation process of a dynamic LLR estimation (DLE) table (referred to herein as the DLE1 table to distinguish it from another DLE table, the DLE2 table, which will be described later) and a shift value Vst, which serve as information regarding HB reads and SB reads. The DLE1 table is a table representing the relationship between the voltage range of the threshold voltages of multiple memory element transistors and the LLR, and is generated based on data successfully corrected in the soft-decision decoding circuit 21 (described later). Details of the processing of the read information generation circuit 17 and the DLE1 table will be described later.

[0063] NAND interface circuit 18 is responsible for communication between memory controller 10 and NAND flash memory 30. NAND interface circuit 18 is connected to NAND flash memory 30 via NAND bus. For example, NAND interface circuit 18 controls the transfer of data, commands, and addresses between memory controller 10 and NAND flash memory 30.

[0064] [1-1-2] Configuration of ECC circuit

[0065] Reference Figure 2 Describe the internal configuration of ECC circuit 14. Figure 2 This is a block diagram illustrating an example configuration of an ECC circuit.

[0066] ECC circuit 14 includes encoding circuit 19, hard decision decoding circuit 20, soft decision decoding circuit 21, LLR conversion circuit 22, and channel matrix generation circuit 23.

[0067] Encoding circuit 19 is the circuit that performs the encoding process. Encoding circuit 19 generates parity checks, including, for example, hard-decision parity checks and soft-decision parity checks. An example of a hard-decision parity check is the Bose-Chaudhuri-Hocquenghem (BCH) code and the Reed-Solomon (RS) code. An example of a soft-decision parity check is a low-density parity check (LDPC) code. Encoding circuit 19 adds the parity check to the user data.

[0068] The hard-decision decoding circuit 20 is a circuit that performs hard-decision decoding. The hard-decision decoding circuit 20 is a circuit that performs error correction using hard-decision parity. Specifically, for HB data, the hard-decision decoding circuit 20 uses hard-decision parity per ECC frame to detect errors in the user data. When an error is detected, the hard-decision decoding circuit 20 corrects the error in the user data. In the following text, the error correction performed by the hard-decision decoding circuit 20 will also be referred to as "HB correction".

[0069] The soft-decision decoding circuit 21 is the circuit that performs soft-decision decoding. The soft-decision decoding circuit 21 is the circuit that performs error correction using LLR and soft-decision parity. Specifically, for HB data and SB data, the soft-decision decoding circuit 21 performs probability-based repetition calculations using LLR and soft-decision parity per ECC frame. The soft-decision decoding circuit 21 corrects errors in the user data based on the results of the repetition calculations. In the following text, the error correction performed by the soft-decision decoding circuit 21 will also be referred to as "SB correction". The LLR is generated by the LLR conversion circuit 22.

[0070] LLR conversion circuit 22 is a circuit that performs LLR conversion processing. LLR conversion circuit 22 uses an LLR table to convert the combination of hard bits and soft bits into LLR for each ECC frame.

[0071] The channel matrix generation circuit 23 is the circuit that performs the channel matrix generation process. The channel matrix generation circuit 23 uses a combination of hard bits and soft bits, along with data successfully corrected in the soft decision decoding circuit 21, to generate the channel matrix for each ECC frame. Hereinafter, the data successfully corrected in the soft decision decoding circuit 21 is also referred to as "corrected data." The channel matrix is ​​generated by counting the number of data "0s" and data "1s" in the corrected data for each combination of hard and soft bits. Details of the channel matrix will be described later.

[0072] The soft-decision decoding circuit 21 includes a memory 24. The memory 24 is, for example, an SRAM. The memory 24 stores HB and SB data obtained from the buffer memory 13, LLR obtained through conversion in the LLR conversion circuit 22, data corrected in the soft-decision decoding circuit 21, and the DLE1 table generated by the read information generation circuit 17.

[0073] The details of the processing of ECC circuit 14 will be described later.

[0074] [1-1-3] Configuration of NAND flash memory

[0075] Reference Figure 3 Describe the configuration of NAND flash memory 30. Figure 3 This is a block diagram illustrating a configuration example of a NAND flash memory 30. The NAND flash memory 30 includes a memory cell array 31, input / output circuitry 32, logic control circuitry 33, ready / busy control circuitry 34, registers 35, a sequencer 36, a driver module 37, a line decoder module 38, and a sense amplifier module 39.

[0076] The memory primitive array 31 includes multiple blocks BLK0 to BLKn (n is an integer of 1 or greater). A block BLK is, for example, a group of multiple memory primitive transistors in which data is collectively erased. For example, a block BLK serves as a unit for data erase operations. A block BLK includes multiple word lines. The memory primitive transistors are capable of storing data in a non-volatile manner. Multiple bit lines and multiple word lines are provided in the memory primitive array 31. Each memory primitive transistor is associated with, for example, one bit line and one word line. Details of the memory primitive array 31 will be described below.

[0077] Input / output circuitry 32 sends input / output signals DQ (e.g., 8-bit signals DQ0 to DQ7) and data strobe signals DQS and DQSn (inverted signals of signal DQS) to and receives these signals from memory controller 10. Signal DQ contains various data transmitted and received between NAND flash memory 30 and memory controller 10. Signal DQ may contain, for example, command CMD, address ADD, status information STS, and data DAT. Signals DQS and DQSn are signals used to control the timing of sending and receiving signals DQ. For example, signals DQS and DQSn are sent from memory controller 10 to NAND flash memory 30 along with signal DQ containing write data during data writing. NAND flash memory 30 receives signal DQ containing write data synchronized with signals DQS and DQSn. Furthermore, signals DQS and DQSn, along with signal DQ containing read data during data reading, are sent from the NAND flash memory 30 to the memory controller 10. The memory controller 10 receives signal DQ containing read data, synchronized with signals DQS and DQSn. Additionally, input / output circuitry 32 can receive signals DQS and DQSn from the memory controller 10 via logic control circuitry 33.

[0078] Furthermore, input / output circuit 32 sends the command CMD from signal DQ to command register 35A. Input / output circuit 32 sends the address ADD from signal DQ to address register 35B. Input / output circuit 32 receives status information STS from status register 35C. Input / output circuit 32 sends data DAT from signal DQ to sense amplifier module 39 and receives data DAT from sense amplifier module 39.

[0079] The logic control circuit 33 receives a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn from the memory controller 10. Signal CEn is used to enable the NAND flash memory 30. Signal CLE indicates that the signal DQ received by the NAND flash memory 30 is the command CMD. Signal ALE indicates that the signal DQ received by the NAND flash memory 30 is the address ADD. Signal WEn commands the input of signal DQ to the NAND flash memory 30. Signal REn commands the output of signal DQ to the NAND flash memory 30. The NAND flash memory 30 generates signals DQS and DQSn based on signal REn. The NAND flash memory 30 outputs signal DQ to the memory controller 10 based on the generated signals DQS and DQSn. The logic control circuit 33 controls the input / output circuit 32 and the sequencer 36 based on the received signals.

[0080] The ready / busy control circuit 34 sends a ready / busy signal RBn to the memory controller 10 based on the operation of the sequencer 36. The signal RBn indicates whether the NAND flash memory 30 is in a ready or busy state. When the NAND flash memory 30 is, for example, in a busy state, the signal RBn goes low. The ready state is when the NAND flash memory 30 is able to receive commands from the memory controller 10. The busy state is when the NAND flash memory 30 is unable to receive commands from the memory controller 10.

[0081] Register 35 includes command register 35A, address register 35B, and status register 35C.

[0082] Command register 35A stores commands (CMD). Commands (CMD) include, for example, instructions (instructions) (sequencer 36) that execute read, write, and erase operations.

[0083] Address register 35B stores address ADD. Address ADD includes, for example, block address BAD, page address PAd, and column address CAd. Block address BAD, page address PAd, and column address CAd are used to select, for example, block BLK, word line, and bit line.

[0084] Status register 35C temporarily stores status information STS during operations such as read, write, and erase. The status information STS is used to notify the memory controller 10 whether the operation has been completed normally.

[0085] The sequencer 36 controls the overall operation of the NAND flash memory 30. For example, the sequencer 36 controls the ready / busy control circuit 34, driver module 37, line decoder module 38, and sense amplifier module 39 based on the command CMD stored in the command register 35A. For example, the sequencer 36 performs read operations, write operations, and erase operations.

[0086] Driver module 37 generates voltages for read, write, and erase operations. Driver module 37 applies the generated voltages to the signal lines corresponding to the selected word lines based on the page address PAd stored in address register 35B.

[0087] The row decoder module 38 selects a block BLK in the memory primitive array 31 based on the block address BAd stored in the address register 35B. The row decoder module 38 sends a voltage to the signal line corresponding to the selected word line in the selected block BLK.

[0088] The sense amplifier module 39 applies a voltage to the bit line based on the write data DAT received from the input / output circuit 32 during the write operation. Furthermore, the sense amplifier module 39 determines the data stored in the memory cell transistors based on the bit line voltage during the read operation. The sense amplifier module 39 sends the determination result as read data DAT to the input / output circuit 32.

[0089] [1-1-4] Circuit configuration of memory cell array

[0090] Reference Figure 4 Describe the circuit configuration of the memory primitive array 31. Figure 4 This is the circuit diagram of memory cell array 31. Figure 4 The circuit configuration of one of the multiple block BLKs arranged in the memory primitive array 31 is shown as an example of the circuit configuration of the memory primitive array 31. Another block BLK also has... Figure 4 The configuration shown.

[0091] Block BLk includes, for example, four string units SU0 to SU3. Each string unit SU is, for example, a group of multiple NAND strings NS that are commonly selected in write or read operations. Each string unit SU includes multiple NAND strings NS associated with bit lines BL0 to BLm (where m is an integer of 1 or greater). The NAND strings NS are a group of multiple memory primitive transistors connected in series. Each NAND string NS includes, for example, memory primitive transistors MC0 to MC7 and select transistors ST1 and ST2. The memory primitive transistors MC store data in a non-volatile manner. The memory primitive transistors MC include a control gate and a charge accumulation layer. The select transistors ST1 and ST2 are switching elements. Each of the select transistors ST1 and ST2 is used to select the string unit SU in various operations.

[0092] In each NAND string NS, memory transistors MC0 through MC7 are connected in series. The drain of selector transistor ST1 is connected to the corresponding bit line BL. The source of selector transistor ST1 is connected to one end of each of the series-connected memory transistors MC0 through MC7. The drain of selector transistor ST2 is connected to the other end of each of the series-connected memory transistors MC0 through MC7. The source of selector transistor ST2 is connected to the source line SL.

[0093] The control gates of memory cell transistors MC0 to MC7 in the same BLK are all connected to word lines WL0 to WL7. The gates of select transistors ST1 in serial cells SU0 to SU3 are all connected to select gate lines SGD0 to SGD3. The gate of select transistor ST2 in the same BLK is all connected to select gate line SGS.

[0094] In the circuit configuration of the memory primitive array 31 described above, the bit line BL is shared by the NAND string NS in each string cell SU, for example, which is assigned the same column address CAd. The source line SL is shared by, for example, multiple blocks BLK.

[0095] A set of multiple memory primitive transistors MC connected to a common word line WL in a serial cell SU is, for example, called a primitive cell CU. A primitive cell CU is also called a page. Data stored in a primitive cell CU, which includes multiple memory primitive transistors MC (each storing 1 bit of data according to a threshold voltage), is equivalent to one page of data. A primitive cell CU can store two or more pages of data based on the number of bits of data stored by each memory primitive transistor MC in the primitive cell CU.

[0096] Please note that the circuit configuration of the memory primitive array 31 is not limited to the configuration described above. For example, the number of string cells SU set in each block BLK, the number of memory primitive transistors MC set in each NAND string NS, and the number of selection transistors ST1 and ST2 can each be any number. In the following text, the memory primitive transistor MC is also referred to as the memory primitive MC.

[0097] [1-1-5] Threshold voltage distribution of memory cells

[0098] Reference Figure 5 Describe the threshold voltage distribution of the memory cell MC. Figure 5 This is a diagram illustrating an example of the relationship between the threshold voltage distribution of a memory cell MC and the data stored by the memory cell MC. Figure 5 The horizontal axis indicates the threshold voltage of the memory cell MC. Figure 5 The vertical axis indicates the number of memory primitives (MCs).

[0099] Each memory cell MC can store, for example, 1 bit of data based on a threshold voltage. In this case, the threshold voltage of the memory cell MC is a value included in one of two threshold voltage distributions. For example, data "1" is assigned to a threshold voltage distribution with a lower threshold voltage. Data "0" is assigned to the other threshold voltage distribution. Data "1" corresponds to the threshold voltage of the state in which charge is removed from the charge accumulation layer of the memory cell MC. The threshold voltage distribution of multiple memory cell MCs corresponding to data "1" is called the "Er" state. The threshold voltage of the memory cell MC corresponding to the "Er" state has a positive or negative value. Data "0" corresponds to the threshold voltage of the state in which charge is accumulated in the charge accumulation layer of the memory cell MC. The threshold voltage distribution of multiple memory cell MCs corresponding to data "0" is called the "A" state. The threshold voltage of the memory cell MC corresponding to the "A" state is higher than the threshold voltage of the memory cell MC corresponding to the "Er" state. The read voltage used to determine whether the threshold voltage of the memory cell MC is in the "A" state is set to voltage AR(0). For example, the threshold voltage of a memory cell MC in the "Er" state is lower than voltage AR(0). For example, the threshold voltage of a memory cell MC in the "A" state is equal to or higher than voltage AR(0).

[0100] For example, sequencer 36 performs HB reading by setting the voltage AR(0) to the HB reading voltage. Figure 5 As shown, when the threshold voltage distribution of the “Er” state and the threshold voltage distribution of the “A” state do not overlap with each other, the memory controller 10 can determine that the threshold voltage of a certain memory cell MC belongs to the same threshold voltage distribution as the threshold voltage distribution during writing. As a result, the memory controller 10 successfully performs hard decision decoding.

[0101] However, as Figure 6 As shown, due to various effects on the memory primitive MC, the threshold voltage distribution of the "Er" state and the threshold voltage distribution of the "A" state may overlap. In this case, even when the sequencer 36 performs an HB read by setting the voltage AR(0) to the HB read voltage, a failure bit may be detected during an HB read when the memory controller 10 cannot determine that the threshold voltage of a memory primitive MC belongs to the same threshold voltage distribution as that at the time of writing. When the number of failure bits exceeds the number of errors that can be corrected, the memory controller 10 fails in hard decision decoding. When hard decision decoding fails, an SB read is performed.

[0102] like Figure 6 As shown, sequencer 36 performs SB readings using multiple SB read voltages (here, voltages AR(-3), AR(-2), AR(-1), AR(+1), AR(+2), and AR(+3)). Figure 6 As shown, voltage dR represents the voltage offset. Voltage AR(-1) is lower than voltage AR(0) by voltage dR. Voltage AR(-2) is lower than voltage AR(-1) by voltage dR. Voltage AR(-3) is lower than voltage AR(-2) by voltage dR. Voltage AR(+1) is higher than voltage AR(0) by voltage dR. Voltage AR(+2) is higher than voltage AR(+1) by voltage dR. Voltage AR(+3) is higher than voltage AR(+2) by voltage dR.

[0103] The initial values ​​of the HB read voltage and SB read voltage can be preset based on design and manufacturing conditions. These initial values ​​are stored, for example, in the NAND flash memory 30. For instance, the initial values ​​of the HB read voltage and SB read voltage are loaded from the NAND flash memory 30 into RAM 16 immediately after power-on. Note that the number of SB read voltages is not limited to three at each of the low-voltage and high-voltage sides of the HB read voltage.

[0104] exist Figure 6In the example, the threshold voltage of the memory cell MC is divided and classified into eight divisions by the HB read voltage (AR(0)) and six SB read voltages (AR(-3) to AR(-1) and AR(+1) to AR(+3)). Specifically, the threshold voltage of division D1 is lower than voltage AR(-3). The threshold voltage of division D2 is equal to or higher than voltage AR(-3) and lower than voltage AR(-2). The threshold voltage of division D3 is equal to or higher than voltage AR(-2) and lower than voltage AR(-1). The threshold voltage of division D4 is equal to or higher than voltage AR(-1) and lower than voltage AR(0). The threshold voltage of division D5 is equal to or higher than voltage AR(0) and lower than voltage AR(+1). The threshold voltage of division D6 is equal to or higher than voltage AR(+1) and lower than voltage AR(+2). The threshold voltage of division D7 is equal to or higher than voltage AR(+2) and lower than voltage AR(+3). The threshold voltage of division D8 is equal to or higher than voltage AR(+3).

[0105] exist Figure 6 In this context, "HB" represents the value of the hard bit based on the threshold voltage of the memory cell MC. The hard bit is obtained by, for example, using voltage AR(0) to determine the data read from the memory cell MC during an HB read. When the threshold voltage of the memory cell MC is in partitions D1 to D4, the value of the hard bit is "1". When the threshold voltage of the memory cell MC is in partitions D5 to D8, the value of the hard bit is "0".

[0106] exist Figure 6 In this context, "SB1" represents the first soft bit. For example, the first soft bit is generated by performing an ENOR (exclusive NOR) operation on multiple data entries read from the memory primitive MC using voltages AR(-2) and AR(+2) respectively. When the threshold voltage of the memory primitive MC is in partitions D1 and D2, the value of the first soft bit is "1". When the threshold voltage of the memory primitive MC is in partitions D3 to D6, the value of the first soft bit is "0". When the threshold voltage of the memory primitive MC is in partitions D7 and D8, the value of the first soft bit is "1".

[0107] exist Figure 6In this context, "SB2" represents the second soft bit. The second soft bit is generated, for example, by performing an ENOR operation on multiple data entries read from memory cell MC using voltages AR(-3), AR(-1), AR(+1), and AR(+3), respectively. When the threshold voltage of memory cell MC is in partition D1, the value of the second soft bit is "1". When the threshold voltage of memory cell MC is in partitions D2 and D3, the value of the second soft bit is "0". When the threshold voltage of memory cell MC is in partitions D4 and D5, the value of the second soft bit is "1". When the threshold voltage of memory cell MC is in partitions D6 and D7, the value of the second soft bit is "0". When the threshold voltage of memory cell MC is in partition D8, the value of the second soft bit is "1".

[0108] Please note that the combination of multiple voltages used to generate the first soft bit and the second soft bit in the SB read is not limited to the combination described above.

[0109] Each of partitions D1 to D8 includes 1 bit corresponding to the hard bit, 1 bit corresponding to the first soft bit, and 1 bit corresponding to the second soft bit. Figure 6 In the example, the indices corresponding to partitions D1 to D8 are set to 0 to 7, respectively. The threshold voltages within the voltage ranges corresponding to indices 0 to 7 are arranged in ascending order of indices 0, 1, 2, 3, 4, 5, 6, and 7.

[0110] [1-1-6] Processing of soft decision decoding

[0111] Reference Figure 7 Describes the processing used for soft-decision decoding. Figure 7 This is a diagram illustrating the process of soft-decision decoding.

[0112] [1-1-6-1] Processing of ECC Circuit

[0113] First, the processing of ECC circuit 14 will be described.

[0114] Buffer memory 13 stores HB data, SB1 data, and SB2 data. SB1 data includes a first soft bit for one page. SB2 data includes a second soft bit for one page. RAM 16 stores multiple LLR tables (e.g., TBL1, TBL2, and TBL3). LLR tables TBL1, TBL2, and TBL3 are LLR tables configured to account for variations in the threshold voltage of the memory primitive MC due to various influences. In LLR tables TBL1, TBL2, and TBL3, the LLRs corresponding to the combinations of hard bits, first soft bits, and second soft bits are different from each other. LLR conversion circuit 22 receives each of the HB data, SB1 data, and SB2 data from buffer memory 13 per ECC frame. LLR conversion circuit 22 selects any one of the multiple LLR tables stored in RAM 16. Using the selected LLR table, LLR conversion circuit 22 converts the combination of hard bits, first soft bits, and second soft bits into an LLR per ECC frame. LLR conversion circuit 22 sends the LLR to soft decision decoding circuit 21.

[0115] Reference Figure 8 Describe the LLR table. Figure 8 This is a conceptual diagram of an LLR table.

[0116] The LLR table stores the LLR for each index, indicating the combination of hard bits, first soft bits, and second soft bits. The LLR takes a larger (positive) value as the probability of the data stored in the memory primitive MC being "0" increases. The LLR takes a smaller (negative) value as the probability of the data stored in the memory primitive MC being "1" increases.

[0117] As referenced above Figure 6 As described, for example, when the threshold voltage of a memory cell MC is in partition D1, the values ​​of the hard bit, the first soft bit, and the second soft bit read from the memory cell MC are "1", "1", and "1", respectively. As described above, the index of the memory cell MC with the threshold voltage in partition D1 is 0, and the LLR value of the memory cell MC is -9. Furthermore, when the threshold voltage of a memory cell MC is in partition D5, the values ​​of the hard bit, the first soft bit, and the second soft bit read from the memory cell MC are "0", "0", and "1", respectively. As described above, the index of the memory cell MC with the threshold voltage in partition D5 is 4, and the LLR value of the memory cell MC is +1. Figure 8 The value of LLR is just an example.

[0118] Return to reference Figure 7The following describes the process: Soft-decision decoding circuit 21 receives the LLR from LLR conversion circuit 22. Soft-decision decoding circuit 21 stores the LLR in memory 24. Soft-decision decoding circuit 21 receives HB data, SB1 data, and SB2 data from buffer memory 13 in ECC frames. Soft-decision decoding circuit 21 stores the HB data, SB1 data, and SB2 data in memory 24. Soft-decision decoding circuit 21 uses soft-decision parity among the LLR, HB data, SB1 data, and SB2 data to perform error correction on the user data. Soft-decision decoding circuit 21 stores the corrected data in memory 24. Soft-decision decoding circuit 21 sends the corrected data to channel matrix generation circuit 23.

[0119] The channel matrix generation circuit 23 receives HB data, SB1 data, and SB2 data from the buffer memory 13 in ECC frames. The channel matrix generation circuit 23 receives corrected data from the memory 24. The channel matrix generation circuit 23 obtains an index based on the HB data, SB1 data, and SB2 data. The channel matrix generation circuit 23 counts the number of data "0"s and data "1"s in the corrected data at each index using DLECNT to generate the channel matrix. The channel matrix generation circuit 23 sends the generated channel matrix to the read information generation circuit 17.

[0120] Reference Figure 9 Describe the channel matrix. Figure 9 This is a table showing an example of a channel matrix.

[0121] exist Figure 9 In the example, the channel matrix is ​​two rows and eight columns in size. The rows indicate the number of data “0” and data “1” in the corrected data. Here, num1[0] to num1[7] represent the number of data “1”. Similarly, num0[0] to num0[7] represent the number of data “0”. The columns represent indices.

[0122] For example, when any bit in the corrected data is "1" and the index corresponding to that bit is 0, the element num1[0] in the first row and first column is incremented by 1. That is, num1[0] represents the number of memory cells MC that have the threshold voltage in partition D1 and store the data "1". For example, when any bit in the corrected data is "0" and the index corresponding to that bit is 0, the element num0[0] in the second row and first column is incremented by 1. That is, num0[0] represents the number of memory cells MC that have the threshold voltage in partition D1 and store the data "0".

[0123] Similarly, when any bit in the corrected data is "1" and the index corresponding to that bit is 4, the element num1[4] in the fifth column of the first row is incremented by 1. That is, num1[4] represents the number of memory cells MC with the threshold voltage in partition D5 and storing data "1". Furthermore, when any bit in the corrected data is "0" and the index corresponding to that bit is 4, the element num0[4] in the fifth column of the second row is incremented by 1. That is, num0[4] represents the number of memory cells MC with the threshold voltage in partition D5 and storing data "0".

[0124] [1-1-6-2] Processing of the information generation circuit

[0125] Next, the processing of the information generation circuit 17 will be described.

[0126] Return to reference Figure 7 The description is as follows: The information generation circuit 17 receives the channel matrix from the channel matrix generation circuit 23.

[0127] (DLE1 table generation process)

[0128] The information generation circuit 17 generates the DLE1 table by statistically calculating the likelihood ratio (specifically, LLR) of the bits for each index using the channel matrix. Specifically, LLR[idx] is calculated for each index in the following equation (1).

[0129]

[0130] Transform equation (1) into equation (2) below.

[0131]

[0132] In the equation above, "idx" represents the index value; "s" represents an integer greater than or equal to 0 and less than or equal to t; and "t" represents the value obtained by subtracting 1 from the index number. The calculated LLR saturates, for example, at integers whose absolute value is less than or equal to 9. That is, when the calculated LLR is less than -9, the LLR becomes -9. When the calculated LLR is greater than 9, the LLR becomes +9.

[0133] (Shift value generation process)

[0134] Reference Figures 10A to 10E Describe the process of generating the shift value Vst. Figure 10A This is a diagram illustrating the process of generating the shift value Vst. Figures 10B to 10E This is a graph showing the relationship between the threshold voltage distribution of the memory cell MC and the channel matrix.

[0135] The read information generation circuit 17 uses the channel matrix to generate the shift value Vst. Specifically, the read information generation circuit 17 uses the number of data "1"s DLECNT (num1[0] to num1[7]) and the number of data "0"s DLECNT (num0[0] to num0[7]) for each index of the channel matrix. For example, by Figure 10B The shaded area indicates the quantity DLECNT(num1[2]), which indicates the number of memory cell MCs among the multiple memory cell MCs that are included in the voltage range corresponding to index 2 and store "1"s in corrected data (i.e., data that has been successfully corrected for errors). Figure 10C The shaded area indicates the quantity DLECNT(num0[2]), which indicates the number of memory cells MCs included in the voltage range corresponding to index 2 and storing "0"s in corrected data among the multiple memory cells MCs. Figure 10D The area enclosed by the diagonal shading corresponds to the quantity DLECNT(num1[3]), which indicates the number of memory cells MCs among the multiple memory cells MCs that are included in the voltage range corresponding to index 3 and store "1"s in the corrected data. Figure 10E The shaded area indicates the quantity DLECNT(num0[3]), which indicates the number of memory cells MCs that are included in the voltage range corresponding to index 3 and store “0” in the corrected data among the multiple memory cells MCs.

[0136] The information generation circuit 17 reads the data and compares the number of data "1"s (DLECNT) and the number of data "0"s (DLECNT) sequentially, starting from the first column of the channel matrix. The information generation circuit 17 also detects the flipped columns of the data "1"s (DLECNT) and data "0"s (DLECNT). Figure 10B and Figure 10C As shown, in the third column of the channel matrix corresponding to index 2 (partition D3), the number of data "1"s (num1[2]) is greater than the number of data "0"s (num0[2]). Figure 10D and Figure 10EAs shown, in the fourth column of the channel matrix corresponding to index 3 (partition D4), the number of data “0” (num0[3]) is greater than the number of data “1” (num1[3]). The magnitudes of the number of data “1” and the number of data “0” are flipped at the voltage boundary of the intersection where the two threshold voltage distributions of the memory primitive MC overlap. In other words, the intersection where the two threshold voltage distributions of the memory primitive MC overlap are estimated to correspond to the point where the magnitudes of the number of data “1” and the number of data “0” are flipped. Accordingly, in the channel matrix, the column where the magnitudes of the number of data “1” and the number of data “0” are flipped is detected to obtain the position with relatively few error bits, i.e., the intersection where the two threshold voltage distributions of the memory primitive MC overlap.

[0137] Therefore, finding the intersection where two threshold voltage distributions overlap is called "tracking". The read information generation circuit 17 obtains the voltage (the voltage obtained by tracking) set between the column whose size is flipped and the column corresponding to a partition (in which the threshold voltage is lower than the column by voltage dR). As a result of adding or subtracting the differential voltage between the voltage obtained by tracking (hereinafter also referred to as "tracking voltage Vtr") and the default voltage Vdt, the read information generation circuit 17 generates a shift value Vst.

[0138] exist Figure 10A In the example shown, as described above, the number of memory cells MC with a threshold voltage corresponding to index 2 (partition D3) and storing data "1" (num1[2]) is greater than the number of memory cells MC with a threshold voltage corresponding to index 2 and storing data "0" (num0[2]). Furthermore, the number of memory cells MC with a threshold voltage corresponding to index 3 (partition D4) and storing data "1" (num1[3]) is less than the number of memory cells MC with a threshold voltage corresponding to index 3 and storing data "0" (num0[3]). That is, in Figure 10AIn the example shown, the size of DLECNT is flipped between the third and fourth columns of the channel matrix (i.e., the left and right of the SB read voltage AR(-1)). The intersection of the two threshold voltage distributions of the estimated memory primitive MC is offset from the HB read voltage AR(0) to the 1×dR low voltage side. In this case, the read information generation circuit 17 calculates the tracking voltage Vtr (the voltage at the intersection of the two threshold voltage distributions) based at least on the number of data “1” (num1[2]) and the number of data “0” (num0[2]) of index 2. Furthermore, the read information generation circuit 17 further calculates the tracking voltage Vtr based on the number of data “1” (num1[3]) and the number of data “0” (num0[3]) of index 3. For example, when any voltage in the voltage range corresponding to index 2 is lower than any voltage in the voltage range corresponding to index 3, the read information generation circuit 17 calculates the tracking voltage Vtr (e.g., voltage AR(-1)) from the voltage range between the voltage range corresponding to index 2 and the voltage range corresponding to index 3, based on the condition that num1[2] is greater than num0[2] and num1[3] is less than num0[3]. Furthermore, the read information generation circuit 17 generates a differential voltage between the tracking voltage Vtr (voltage AR(-1)) and the default voltage Vdt, added to or subtracted from the default voltage Vdt. Figure 10A In the example, the result of Vdif1) is used as the shift value Vst.

[0139] Furthermore, for example, when the magnitude of DLECNT flips between the left and right columns of the HB read voltage AR(0), the read information generation circuit 17 generates a differential voltage between the voltage AR(0) and the default voltage Vdt, added to or subtracted from the default voltage Vdt. Figure 10A In the example, the result of Vdif2) is used as the shift value Vst. When the magnitude of DLECNT flips between the left and right columns of the SB read voltage AR(+2), the read information generation circuit 17 generates a differential voltage between the default voltage Vdt and the voltage AR(+2). Figure 10A In the example, the result of Vdif3) is used as the shift value Vst.

[0140] Please note that, as understood from equations (1) or (2), when the number of memory cells MCs storing data "1" in memory cells MCs with a threshold voltage corresponding to any index idx is greater than the number of memory cells MCs storing data "0" (i.e., when num1[idx] > num0[idx]), the sign of LLR[idx] corresponding to that index idx becomes negative. Simultaneously, when the number of memory cells MCs storing data "1" in memory cells MCs with a threshold voltage corresponding to any index idx is less than the number of memory cells MCs storing data "0" (i.e., when num1[idx] < num0[idx]), the sign of LLR[idx] corresponding to that index idx becomes positive. That is, the index in which the magnitude of DLECNT is flipped in the channel matrix and the index in which the sign of LLR is flipped in the DLE1 table are the same.

[0141] (DLE1 table correction processing)

[0142] Reference Figures 11A to 11C Describe the correction process for table DLE1. Figures 11A to 11C This is a diagram illustrating the correction process for the DLE1 table. Figure 11A An example is shown where the intersection of the two threshold voltage distributions of the memory primitive MC (i.e., the tracking voltage Vtr) is the voltage AR(-1).

[0143] like Figure 11A As shown, the DLE1 table includes LLRs corresponding to the voltage ranges corresponding to indices 0 through 7, respectively. In the following text, the LLRs corresponding to the voltage ranges corresponding to indices 0 through 7 are also referred to as "LLR of index 0," "LLR of index 1," ..., "LLR of index 7," respectively. For example, after generating the DLE1 table, the LLR of index 2 is -1, and the LLR of index 3 is +1.

[0144] The read information generation circuit 17 acquires the HB read voltage (i.e., the voltage applied to the word line when the SB correction is successful, assuming it is voltage AR(0)) and the tracking voltage Vtr (assuming it is voltage AR(-1)). The read information generation circuit 17 corrects the DLE1 meter based on the acquired voltage difference.

[0145] Specifically, the read information generation circuit 17 shifts each LLR of the DLE1 table based on the acquired voltage difference. Figure 11AIn this process, the read information generation circuit 17 shifts the corresponding LLRs of indices 0 to 5 of the DLE1 table one bit to the right. The LLR of index 0 (=-5) is shifted to index 1. The LLR of index 1 (=-3) is shifted to index 2. The LLR of index 2 (=-1) is shifted to index 3. That is, when the HB read voltage after successful SB correction is greater than the tracking voltage Vtr, the read information generation circuit 17 stores the LLR (=-1) stored in index 2 of the DLE1 table before correction as the LLR of index 3 of the corrected DLE1 table. The LLR of index 3 (=+1) is shifted to index 4. The LLR of index 4 (=+3) is shifted to index 5. The LLR of index 5 (=+5) is shifted to index 6. Since the LLR of index 7 (=+9) will be replaced with the integral value described below, the LLR of index 7 is deleted once. At this time, due to the shifting of the LLRs, the LLRs are not included in indices 0 and 7.

[0146] The information generation circuit 17 uses equation (1) to calculate the LLR (also referred to hereinafter as the "integral value") of index 7 based on the DLECNT of multiple indices of the channel matrix. Figure 11A In the example shown, the read information generation circuit 17 substitutes the sum of the number of "0"s (num0[6]) and the number of "0"s (num0[7]) in index 6 of the channel matrix into num0[idx] of equation (1). The read information generation circuit 17 substitutes the sum of the number of "1"s (num1[6]) and the number of "1"s (num1[7]) in index 6 of the channel matrix into num1[idx] of equation (1). That is, the read information generation circuit 17 calculates the integral value based on num0[6] and num0[7] and num1[6] and num1[7]. When the value calculated using equation (1) is greater than +9, the read information generation circuit 17 sets +9 as the integral value. Here, it is assumed that the read information generation circuit 17 calculates +9 as the integral value. The read information generation circuit 17 sets the calculated +9 as LLR of index 7 of the DLE1 table.

[0147] The information generation circuit 17 reads the value (=-9) obtained by reversing the sign of the integral value (LLR of index 7) and sets it as the LLR of index 0 of the DLE1 table. As a result, the correction process of the DLE1 table is completed.

[0148] Figure 11B An example is shown where the voltage applied to the word line is voltage AR(0) when acquiring data of its SB correction success and the intersection of the two threshold voltage distributions of the memory primitive MC is voltage AR(-2).

[0149] exist Figure 11BIn the process, the information generation circuit 17 shifts the corresponding LLRs of indices 0 to 4 of the DLE1 table two bits to the right. The LLR of index 0 (=-3) is shifted to index 2. The LLR of index 1 (=-1) is shifted to index 3. The LLR of index 2 (=+1) is shifted to index 4. The LLR of index 3 (=+3) is shifted to index 5. The LLR of index 4 (=+5) is shifted to index 6. Since the LLR of index 7 (=+9) will be replaced with the integral value, the LLR of index 7 is deleted once. At this point, due to the shifting of the LLRs, the LLRs are not included in indices 0, 1, and 7.

[0150] The information generation circuit 17 uses equation (1) to calculate the integral value based on the three DLECNTs at indices 5 to 7 of the channel matrix. Figure 11B In the example shown, the read information generation circuit 17 substitutes the sum of the number of "0"s at index 5 (num0[5]), the number of "0"s at index 6 (num0[6]), and the number of "0"s at index 7 (num0[7]) into num0[idx] of equation (1). The read information generation circuit 17 substitutes the sum of the number of "1"s at index 5 (num1[5]), the number of "1"s at index 6 (num1[6]), and the number of "1"s at index 7 (num1[7]) into num1[idx] of equation (1). Here, it is assumed that the read information generation circuit 17 calculates +9 as the integral value. The read information generation circuit 17 sets the calculated +9 as the LLR of index 7 of the DLE1 table. The read information generation circuit 17 sets the value (=-9) obtained by reversing the sign of the integral value (LLR of index 7) as the LLR of index 0 of the DLE1 table. The read information generation circuit 17 sets the value (=-5) obtained by reversing the sign of LLR (=+5) of index 6 of the DLE1 table to LLR of index 1 of the DLE1 table.

[0151] The number of SB read voltages is represented by (k×2) (where k is an integer greater than or equal to 1), and the indices of the channel matrix and the DLE1 table are represented by integers greater than or equal to 0 and less than or equal to ((k×2)+1). When the intersection of the two threshold voltage distributions of the memory primitive MC is a voltage AR(-j) instead of its SB-corrected HB read voltage (j is an integer greater than or equal to 1 and less than or equal to k), the read information generation circuit 17 shifts the LLR of the DLE1 table from index 0 to ((k×2)-j) to the right by j bits. The read information generation circuit 17 calculates the integral value based on the (j+1) DLECNTs included in the indices ((k×2)-j+1) to ((k×2)+1) of the channel matrix. The read information generation circuit 17 sets the calculated integral value as the LLR of the DLE1 table index ((k×2)+1). The read information generation circuit 17 sets the value obtained by reversing the sign of the LLRs of the DLE1 table from index ((k×2)+1) to ((k×2)+1-(j-1)) to the LLRs of the DLE1 table from index 0 to (j-1).

[0152] Figure 11C An example is shown where the voltage applied to the word line is voltage AR(0) when acquiring data that has been successfully corrected by the SB, and the intersection of the two threshold voltage distributions of the memory primitive MC is voltage AR(+1).

[0153] like Figure 11C As shown, after generating the DLE1 table, for example, the LLR of index 2 is -5, and the LLR of index 3 is -3.

[0154] exist Figure 11C In this process, the read information generation circuit 17 shifts the corresponding LLRs of indices 2 to 7 of the DLE1 table one bit to the left. It shifts the LLR of index 7 (=+5) to index 6. It shifts the LLR of index 6 (=+3) to index 5. It shifts the LLR of index 5 (=+1) to index 4. It shifts the LLR of index 4 (=-1) to index 3. It shifts the LLR of index 3 (=-3) to index 2. That is, when the HB read voltage after successful SB correction is less than the tracking voltage Vtr, the read information generation circuit 17 stores the LLR (=-3) stored in index 3 of the DLE1 table before correction as the LLR of index 2 of the corrected DLE1 table. It shifts the LLR of index 2 (=-5) to index 1. Since the LLR of index 0 (=-9) will be replaced with the integral value, the LLR of index 7 is deleted once. At this time, due to the LLR shift, LLRs are not included in indices 0 and 7.

[0155] The information generation circuit 17 uses equation (1) to calculate the integral value based on the two DLECNTs with indices 0 to 1 of the channel matrix. Figure 11CIn the example shown, the read information generation circuit 17 substitutes the sum of the number of "0"s at index 0 of the channel matrix (num0[0]) and the number of "0"s at index 1 (num0[1]) into num0[idx] of equation (1). The read information generation circuit 17 substitutes the sum of the number of "1"s at index 0 of the channel matrix (num1[0]) and the number of "1"s at index 1 (num1[1]) into num1[idx] of equation (1). When the value calculated using equation (1) is less than -9, the read information generation circuit 17 sets -9 as the integral value. Here, it is assumed that the read information generation circuit 17 calculates -9 as the integral value. The read information generation circuit 17 sets the calculated -9 as the LLR of index 0 of the DLE1 table. The read information generation circuit 17 sets the value (=+9) obtained by reversing the sign of the integral value (LLR of index 0) as the LLR of index 7 of the DLE1 table.

[0156] Thus, when the intersection of the two threshold voltage distributions of the memory primitive MC is voltage AR(+j) instead of the HB read voltage where its SB correction is successful, the read information generation circuit 17 shifts the LLR of the DLE1 table from index (j+1) to ((k×2)+1) left by j bits. The read information generation circuit 17 calculates the integral value based on the (j+1) DLECNTs included in the channel matrix from index 0 to j. The read information generation circuit 17 sets the calculated integral value as the LLR of index 0 of the DLE1 table. The read information generation circuit 17 sets the value obtained by reversing the sign of the LLRs of the DLE1 table from index 0 to (j-1) as the LLR of the DLE1 table from index ((k×2)+1) to ((k×2)+1-(j-1)).

[0157] Return to reference Figure 7 The information generation circuit 17 sends the shift value Vst generated by the shift value generation process to the RAM 16. When a read operation of the next page in the same BLK is performed, the shift value Vst is applied to the HB read voltage. In the read operation of the next page in the same BLK, the memory controller 10 performs an HB read using the HB read voltage with the shift value Vst applied. Based on the HB read voltage with the shift value Vst applied, the memory controller 10 performs SB reads using multiple SB read voltages.

[0158] The read information generation circuit 17 sends the DLE1 table generated by the DLE1 table generation process to the memory 24. For example, the generated DLE1 table is used as the LLR table when the soft decision decoding circuit 21 performs SB correction for the next ECC frame in the same page, until the DLE1 table correction process is performed. The read information generation circuit 17 sends the corrected DLE1 table, generated by the DLE1 table correction process, to the memory 24. When the DLE1 table is already stored in the memory 24, the corrected DLE1 table is overwritten. For example, when the soft decision decoding circuit 21 performs SB correction for the next ECC frame in the same page, the corrected DLE1 table is used as the LLR table. Furthermore, when the soft decision decoding circuit 21 performs multiple SB corrections for any ECC frame, the soft decision decoding circuit 21 can select the LLR table in the following order: for example, LLR table TBL1, the DLE1 table stored in the memory 24, LLR table TBL2, and LLR table TBL3.

[0159] [1-2] Read operation

[0160] Reference Figure 12 Describe the read operation. Figure 12 This is a flowchart illustrating a read operation performed by a memory controller 10 provided in a memory system 1 according to an embodiment. Hereinafter, a case in which the primitive unit CU stores one page of data will be described as an example.

[0161] When a read operation begins, the memory controller 10 first applies an HB read voltage to a selected word line to perform a read of the HB data corresponding to a page in any block BLK (HB read) (S10). Here, a word line included in the block BLK (hereinafter also referred to as the "first word line") is selected. The HB read voltage is set based on a default voltage value Vdt or a shift value Vst stored in RAM 16. The read HB data (i.e., obtained from the plurality of memory primitives MC connected to the first word line) is stored in the buffer memory 13.

[0162] After performing an HB read, the memory controller 10 receives HB data from the buffer memory 13 in ECC frames. The hard-decision decoding circuit 20 corrects errors in the user data of the ECC frame (HB correction).

[0163] When the HB correction of all ECC frames corresponding to a page of HB data is successful (S11_Yes), and when the current page is not the last page to be read in the same BLK (hereinafter referred to as "last page") (S12_No), the memory controller 10 executes the processing of step S10 for the next page in the same BLK. When the current page is the last page (S12_Yes), the memory controller 10 ends the read operation.

[0164] Simultaneously, when HB correction of at least one ECC frame corresponding to a page of HB data fails (S11_No), the memory controller 10 applies multiple SB read voltages to a selected word line to perform the reading (SB read) of multiple SB data (e.g., SB1 data and SB2 data) (S13). The multiple SB read voltages are set based on the HB read voltage. The read SB1 data and SB2 data (i.e., obtained from multiple memory primitives MC connected to the first word line) are stored in the buffer memory 13.

[0165] After performing the SB read, the memory controller 10 receives HB data, SB1 data and SB2 data from the buffer memory 13 in ECC frames (S14).

[0166] LLR conversion circuit 22 selects any one of multiple LLR tables. Using the selected LLR table, LLR conversion circuit 22 converts the combination of hard bits, first soft bits, and second soft bits into LLR according to the ECC frame. Soft decision decoding circuit 21 uses soft decision parity checking between LLR, HB data, SB1 data, and SB2 data to correct errors in the user data of the ECC frame (SB correction) (S15).

[0167] When the SB correction of the ECC frame is successful (S16_Yes), the read information generation circuit 17 generates a DLE1 table based on the data corrected by the SB correction obtained from multiple memory primitives MC connected to the first word line (S18). The generated DLE1 table is stored in the memory 24.

[0168] Simultaneously, when the SB correction of the ECC frame fails (S16_No) and when there is no unselected LLR table for the same ECC frame (S17_No), the memory controller 10 executes the process of step S19, which will be described later. Although detailed description is omitted, the memory controller 10 may perform additional error correction on the ECC frame using another stronger error correction method, such as product codes, before executing the process of step S19. Alternatively, the memory controller 10 may notify the host device 2 of uncorrectable errors before executing the process of step S19. When there is an unselected LLR table for the same ECC frame (S17_Yes), the memory controller 10 executes the process of step S15 using the next LLR table. Furthermore, "unselected LLR table" refers to, for example, an LLR table that is not selected among LLR tables TBL1, TBL2, and TBL3, and table DLE1.

[0169] Please note that when performing SB correction for any ECC frame, the soft-decision decoding circuit 21 first uses, for example, the LLR table TBL1 stored in RAM 16 to perform SB correction. If SB correction is unsuccessful and the DLE1 table is stored in memory 24, the soft-decision decoding circuit 21 uses the DLE1 table to perform SB correction. If SB correction is unsuccessful or if the DLE1 table is not stored in memory 24, the soft-decision decoding circuit 21 uses the LLR table TBL2 stored in RAM 16 to perform SB correction. If SB correction is unsuccessful, the soft-decision decoding circuit 21 uses the LLR table TBL3 stored in RAM 16 to perform SB correction.

[0170] After the DLE1 table generation process in step S18, or when no unselected LLR table exists (S17_No), the memory controller 10 determines whether the current ECC frame is the last ECC frame in the same page (hereinafter referred to as the "last ECC frame"). When the current ECC frame is not the last ECC frame (S19_No), the memory controller 10 performs the processing of step S14 for the next ECC frame in the same page. Simultaneously, when the current ECC frame is the last ECC frame (S19_Yes) and the current page is the last page (S20_Yes), the memory controller 10 ends the read operation. When the current page is not the last page (S20_No), the read information generation circuit 17 generates a shift value Vst (S21). After the processing step S22 described later, the generated shift value Vst is stored in RAM 16.

[0171] When the generated shift value Vst is the same as the shift value stored in RAM 16 (S22_Yes), the memory controller 10 executes the processing of step S10 for the next page in the same BLK. Simultaneously, when the generated shift value Vst is different from the shift value stored in RAM 16 (S22_No), the read information generation circuit 17 corrects the DLE1 table based on the voltage difference between the voltage applied to the first word line and the tracking voltage Vtr when data with successful SB correction is acquired (S23). The corrected DLE1 table is stored in memory 24. Thereafter, the memory controller 10 executes the processing of step S10 for the next page in the same BLK.

[0172] The processing of the next page within the same BLK is as follows. In step S10, a word line different from the first word line included in the same BLK (hereinafter also referred to as the "second word line") is selected, and the memory controller 10 applies an HB read voltage (shift value Vst, i.e., tracking voltage Vtr) to the second word line to perform an HB read. In step S13, the memory controller 10 applies multiple SB read voltages to the second word line to perform SB reads. In step S16, the memory controller 10 performs error correction on the data obtained from the multiple memory primitives MCs connected to the second word line using a DLE1 table corrected based on data obtained from the multiple memory primitives MCs connected to the first word line included in the same BLK.

[0173] [1-3] Effects

[0174] According to the first embodiment, the data error correction capability of the memory system 1 can be enhanced. Reference will be made below. Figure 13A and 13B Describe the effect. Figure 13A and 13B This is a diagram illustrating the effects of the memory system 1 according to an embodiment.

[0175] In memory system 1, the two threshold voltage distributions (hereinafter referred to as "threshold voltage distributions of the first page") of the memory cell MC in the next page (hereinafter referred to as "the second page") in the same block as the two threshold voltage distributions (hereinafter referred to as "threshold voltage distributions of the first page") of any page (hereinafter also referred to as "the first page") tend to have similar distributions. This is, for example, the case where the first page and the second page are connected to the same word line and are respectively arranged in consecutive string cells SU. Figure 13A and 13B The example shows the threshold voltage distribution on the first page and the threshold voltage distribution on the second page.

[0176] Figure 13A An example of the threshold voltage distribution for the first page is shown, where the intersections of the distributions are located around voltage AR(0). Assume that for the first page with the threshold voltage distribution, voltage AR(+1) is used as the HB read voltage to perform the read operation. For example, when SB correction is successful in the read operation of the first page, the data from its successful SB correction is used to generate... Figure 13A The channel matrix shown. For example. Figure 13A The DLE1 table shown (hereinafter also referred to as "table D1A") is generated using the generated channel matrix.

[0177] exist Figure 13A In the example shown, the size of DLECNT is flipped between indices 2 and 3 of the channel matrix. Therefore, as referenced above... Figure 10A As described, the sign of the LLR is reversed between indices 2 and 3 of table D1A. (See the reference above.) Figures 10B to 10E As described, the intersection (voltage) of the estimated threshold voltage distribution on the first page is located where the size of the channel matrix DLECNT is flipped, that is, where the sign of the LLR in table D1A is flipped.

[0178] In this embodiment, the intersection of the threshold voltage distribution of the first page (voltage AR(0)) is obtained by tracking. However, the HB read voltage AR(+1) used for the first page read operation and successfully corrected in SB does not match the intersection of the threshold voltage distribution of the first page (voltage AR(0)).

[0179] As mentioned above, it is assumed that the threshold voltage distributions of the first page and the second page tend to have similar distributions. Therefore, the estimated intersection position of the threshold voltage distributions of the second page is similar to that of the first page. As mentioned above, the intersection position where the two threshold voltage distributions overlap refers to the position where the number of error bits is relatively small. As a result, by setting the voltage at the intersection of the threshold voltage distributions of the first page (i.e., voltage AR(0)) as the HB read voltage of the second page to perform the read operation, the probability of unsuccessful SB correction of the second page is reduced.

[0180] Therefore, in this embodiment, the result of adding or subtracting the differential voltage between the voltage AR(0) obtained through tracking and the default voltage Vdt is generated as a shift value Vst. The second page read operation is performed by setting the shift value Vst (voltage AR(0)) to the HB read voltage.

[0181] However, as Figure 13A As shown, there is a difference between the location of the intersection of the threshold voltage distribution on the second page and the location where the sign of the LLR in table D1A is reversed. In this case, the probability of unsuccessful SB correction on the second page increases when the LLR of table D1A is applied to the data read from the second page using the HB read voltage AR(0). However, if the location where the sign of the LLR is reversed is between indices 3 and 4, the difference between the location of the intersection of the threshold voltage distribution on the second page and the location where the sign of the LLR in table D1A is reversed is resolved. In this case, the probability of unsuccessful SB correction on the second page decreases.

[0182] Therefore, in this embodiment, as Figure 13B As shown, table D1A is corrected based on the voltage difference between the HB read voltage (AR(+1)) where SB correction was successful during the first page read operation and the voltage at the intersection of the threshold voltage distribution of the first page (voltage AR(0)). Based on this voltage difference, the LLR of table D1A is shifted, and as a result, table D1A is corrected to... Figure 13B The DLE1 table (hereinafter also referred to as "table D1B") is shown. As a result, the position where the sign of the LLR in table D1B is reversed is between indices 3 and 4. That is, the difference between the position of the intersection of the threshold voltage distributions of the second page and the position where the sign of the LLR in table D1B is reversed is resolved. Therefore, when the LLR of table D1B is applied to the data read from the second page using the HB read voltage AR(0), the probability of successful SB correction on the second page increases. Thus, the error correction capability of the data can be enhanced.

[0183] [2] Second embodiment

[0184] The second embodiment will be described. The memory system 1 according to the second embodiment differs from the memory system 1 according to the first embodiment in the configuration of the memory controller 10, the configuration of the ECC circuit 14, and the DLE1 table correction processing performed by the read information generation circuit 17. Hereinafter, the differences from the first embodiment will be primarily described.

[0185] [2-1] Configuration of memory controller 10

[0186] Reference Figure 14 Describe the internal configuration of memory controller 10. Figure 14 This is a block diagram illustrating an example of an information processing system including a memory system 1 according to a second embodiment.

[0187] The memory controller 10 also includes a dynamic LLR estimation 2 (DLE2) table generation circuit 25.

[0188] The DLE2 table generation circuit 25 is a circuit that performs the generation process of the DLE2 table. The DLE2 table is a table representing the relationship between the threshold voltage ranges of multiple memory primitives (MCs) and the LLR (Lower Limit Ratio), and is generated based on data from which corrections were unsuccessful in the soft-decision decoding circuit 21. Details of the processing by the DLE2 table generation circuit 25 will be described later.

[0189] Other configurations and references in memory controller 10 Figure 1 The configuration is the same as that of the first embodiment described. Other configurations in memory system 1 are the same as those in the reference. Figure 1 The configuration is the same as that of the first embodiment described.

[0190] [2-2] Configuration of ECC circuit 14

[0191] Reference Figure 15 Describe the internal configuration of ECC circuit 14. Figure 15 This is a block diagram illustrating an example configuration of an ECC circuit.

[0192] ECC circuit 14 also includes channel matrix estimation circuit 26.

[0193] The channel matrix estimation circuit 26 is the circuit that performs the channel matrix estimation process. The channel matrix estimation circuit 26 estimates the channel matrix per ECC frame using a combination of hard and soft bits, as well as data that was not successfully corrected in the soft decision decoding circuit 21. In the following text, the data that was not successfully corrected in the soft decision decoding circuit 21 is also referred to as "unsuccessful data".

[0194] The memory 24 stores the DLE2 table generated by the DLE2 table generation circuit 25.

[0195] Other configurations and references in ECC circuit 14 Figure 2 The configuration is the same as that of the first embodiment described.

[0196] [2-3] Processing of ECC circuit 14

[0197] Reference Figure 16 Describe the processing of ECC circuit 14. Figure 16 This is a diagram illustrating the processing used for soft-decision decoding.

[0198] When SB correction fails, the soft-decision decoding circuit 21 stores the unsuccessful data in memory 24. The soft-decision decoding circuit 21 then sends the unsuccessful data to the channel matrix estimation circuit 26.

[0199] The channel matrix estimation circuit 26 receives data (HB data, SB1 data, and SB2 data) read from the NAND flash memory 30 in ECC frames from the buffer memory 13. The channel matrix estimation circuit 26 also receives unsuccessful data from the memory 24. The number of error bits included in the unsuccessful data may differ from the number of error bits included in the data received from the buffer memory 13. The channel matrix estimation circuit 26 aggregates the groups of HB data, SB1 data, and SB2 data received from the buffer memory 13 and the unsuccessful data received from the memory 24, and estimates the channel matrix based on the aggregation result. The channel matrix estimation circuit 26 then sends the estimated channel matrix to the DLE2 table generation circuit 25.

[0200] Other processing and references for ECC circuit 14 Figure 7 The processing is the same as in the first embodiment described.

[0201] [2-4] Processing of DLE2 table generation circuit 25

[0202] Reference Figure 16 Describe the processing of the DLE2 table generation circuit 25.

[0203] The DLE2 table generation circuit 25 generates the DLE2 table by statistically calculating the likelihood ratio (specifically, LLR) of the bits of each index using the estimated channel matrix. The DLE2 table generation circuit 25 calculates the DLE2 table based on the estimated channel matrix. The calculation of the DLE2 table is disclosed, for example, in Japanese Patent Application No. 2020-899, filed on January 7, 2020. The entire contents of that patent application are incorporated herein by reference.

[0204] The DLE2 table generation circuit 25 sends the DLE2 table to the memory 24. When the DLE2 table is stored in the memory 24, the DLE2 table stored in the memory 24 is overwritten by the DLE2 table received by the memory 24. The DLE2 table is used for the second correction process of the DLE1 table, which will be described later.

[0205] [2-5] Processing of the information generation circuit 17

[0206] The DLE1 table correction process performed by the read information generation circuit 17 includes a first correction process and a second correction process.

[0207] Reference Figure 17 Describe the first corrective action and the second corrective action. Figure 17 This is a diagram showing the first and second corrective processes for the DLE1 table. Figure 17 An example is shown where the HB read voltage is voltage AR(0) and the intersection of the two threshold voltage distributions of the memory cell MC is voltage AR(-1).

[0208] like Figure 17 As shown, the DLE2 table includes LLRs corresponding to the voltage ranges respectively associated with indices 0 to 7. Figure 17 In the table, indexes 0 to 7 of table DLE2 correspond to indexes 0 to 7 of table DLE1, respectively.

[0209] (First corrective action)

[0210] Similar to the first embodiment, the read information generation circuit 17 shifts the LLR of each of indices 0 to 5 one bit to the right relative to the DLE1 table and calculates the integral value, setting this integral value as the LLR of index 7. As a result, the first correction process is completed. In this step, index 0 does not include the LLR.

[0211] Please note that, for example, when the intersection of the two threshold voltage distributions of the memory primitive MC is voltage AR(-2), similar to the first embodiment, the read information generation circuit 17 shifts the LLR of each of the indices 0 to 4 to the right by 2 bits relative to the DLE1 table and calculates the integral value, and sets the integral value as the LLR of index 7.

[0212] (Second corrective action)

[0213] After the first correction process, the LLR of index 0 of table DLE2 is set to the LLR of index 0 of table DLE1 as corrected by the first correction process. As a result, the second correction process is completed.

[0214] Please note that, for example, when the intersection of the two threshold voltage distributions of the memory cell MC is voltage AR(-2), the read information generation circuit 17 sets the LLR of index 0 of the DLE2 table to the LLR of index 0 of the DLE1 table corrected by the first correction process. The read information generation circuit 17 further sets the LLR of index 1 of the DLE2 table to the LLR of index 1 of the DLE1 table corrected by the first correction process.

[0215] [2-6] Read operation

[0216] Reference Figure 18 and Figure 19 Describe the read operation. Figure 18 and Figure 19 This is a flowchart illustrating a read operation performed by a memory controller 10 provided in a memory system 1 according to the second embodiment. In the second embodiment, operations S30 to S34 are added to those of the first embodiment. Figure 12 The operations of S10 to S23 are shown. Furthermore, in the second embodiment, the operation of S23 is replaced by a first correction process. The operations of S10 to S22 are the same as in the first embodiment. The operations of S23 and S30 to S34 will be mainly described below.

[0217] exist Figure 18 In the process, when the SB correction of the ECC frame fails (S16_No) and there is no unselected LLR table for the same ECC frame (S17_No), the memory controller 10 executes the processing of step S19. When there is an unselected LLR table (S17_Yes), the memory controller 10 determines whether the DLE1 table has been selected as the LLR table for the same ECC frame.

[0218] When the DLE1 table has been selected for the same ECC frame (S30_Yes), the memory controller 10 performs the processing of step S15 using the next LLR table. Meanwhile, when the DLE1 table has not been selected for the same ECC frame (S30_No), the memory controller 10 determines whether the DLE1 table is located in memory 24.

[0219] When the DLE1 table does not exist (S31_No), the memory controller 10 performs the processing of step S15 using the next LLR table. Meanwhile, when the DLE1 table exists (S31_Yes), the memory controller 10 determines whether there is an index in the DLE1 table that does not include an LLR. Note that the state in which an index in the DLE1 table exists that does not include an LLR is, for example, a state in which the LLR is shifted by the first correction process and an empty index exists (where no LLR is set in the DLE1 table).

[0220] When no index excluding LLR exists in the DLE1 table (S32_No), the memory controller 10 performs the processing of step S15 using the next LLR table (e.g., the DLE1 table). Simultaneously, when an index excluding LLR exists in the DLE1 table (S32_Yes), the memory controller 10 (more specifically, the DLE2 table generation circuit 25) generates the DLE2 table (S33). The generated DLE2 table is stored in the memory 24. The read information generation circuit 17 performs a second correction process for the DLE1 table using the generated DLE2 table (S34). The DLE1 table corrected by the second correction process is stored in the memory 24. Thereafter, the memory controller 10 performs the processing of step S15 using the next LLR table (e.g., the DLE1 table corrected by the second correction process).

[0221] exist Figure 19 In the process, when the generated shift value Vst differs from the shift value stored in RAM 16 (S22_No), the read information generation circuit 17 performs the first correction process of the DLE1 table (S23). The DLE1 table corrected by the first correction process is stored in memory 24. Thereafter, the memory controller 10 performs the processing of step S10 for the next page in the same BLK block.

[0222] [2-7] Effects

[0223] The same effect as the first embodiment is shown by the configuration according to the second embodiment.

[0224] Furthermore, according to the second embodiment, a second correction process is performed to create a DLE1 table that is closer to the LLR of the threshold voltage distribution of the ECC frame to be SB corrected.

[0225] [3] Third embodiment

[0226] The third embodiment will be described. The memory system 1 according to this embodiment differs from the memory system 1 according to the first embodiment in that the DLE1 table correction processing is performed by the read information generation circuit 17. The flowchart showing the read operation of the memory controller 10 is the same as that of the first embodiment. Hereinafter, the differences from the first embodiment will be mainly described.

[0227] [3-1] Processing of the information generation circuit 17

[0228] (DLE1 table correction processing)

[0229] The information generation circuit 17 reads the LLR pattern table to correct the DLE1 table. The LLR pattern table is a table that indicates the relationship between the voltage range of the threshold voltages of multiple memory primitives MC and the LLR. For example, the LLR pattern table is loaded from the NAND flash memory 30 into the RAM 16 immediately after power-on. The LLR pattern table is managed by the memory controller 10.

[0230] Reference Figure 20 Describe the LLR schema table. Figure 20 This is a conceptual diagram of the LLR schema table.

[0231] The LLR schema table stores the LLR for each of the indices 0 to 7. For example... Figure 20 As shown, the LLR mode table includes LLRs corresponding to the voltage ranges respectively associated with indices 0 to 7. Figure 20 In the example, the LLR pattern tables are created as indices 0 to 3 corresponding to the low-voltage side partitions D1 to D4 for the HB read voltage, and indices 4 to 7 corresponding to the high-voltage side partitions D5 to D8. The LLR pattern table for the low-voltage side of the HB read voltage includes two LLR patterns, Pat1 and Pat2. LLR pattern Pat1 has LLRs corresponding to each of indices 0 to 3. The same applies to LLR pattern Pat2. The LLR pattern table for the high-voltage side of the HB read voltage includes two LLR patterns, Pat3 and Pat4. LLR pattern Pat3 has LLRs corresponding to each of indices 4 to 7. The same applies to LLR pattern Pat4. Note that... Figure 20 The LLR value is an example. The LLR pattern table for the low-voltage side of the HB read voltage and the LLR pattern table for the high-voltage side of the HB read voltage can be integrated into a single table. For example, for each stress condition, each LLR pattern can be obtained experimentally. Stress conditions include the temperature of the NAND flash memory 30 or the number of data erase operations performed on the NAND flash memory 30. For example, when the NAND flash memory 30 is at a high temperature, LLR pattern Pat1 has an LLR corresponding to each of indices 0 to 3. For example, when the NAND flash memory 30 is at a low temperature, LLR pattern Pat2 has an LLR corresponding to each of indices 0 to 3.

[0232] Reference Figure 21 Describe the correction process for table DLE1. Figure 21 This is a diagram illustrating the correction process for the DLE1 table. Figure 21An example is shown where the HB read voltage is voltage AR(0) and the intersection of the two threshold voltage distributions of the memory primitive MC is voltage AR(-1).

[0233] exist Figure 21 In the table, indexes 0 to 3 of the LLR schema table correspond to indexes 0 to 3 of the DLE1 table, respectively.

[0234] Similar to the first embodiment, the read information generation circuit 17 shifts the LLR of each of indices 0 to 5 in the DLE1 table one bit to the right and calculates the integral value, setting this integral value as the LLR of index 7. Subsequently, the read information generation circuit 17 sets the LLR of a group of three indices 1 to 3 of the DLE1 table (in...) Figure 21 In the example shown, -5, -3, and -1) are compared with a set of three LLRs at indices 1 to 3 of the LLR pattern table. As a result of the comparison, the read information generation circuit 17 selects an LLR pattern whose at least a portion of the LLRs matches an LLR in the DLE1 table. Figure 20 and Figure 21 In the example shown, the read information generation circuit 17 selects the LLR mode Pat1. The read information generation circuit 17 can also select an LLR mode, for example, with a larger number of matching indices. Figure 21 The example shows a case where the number of matching indices is 3 (indices 1 to 3). The read information generation circuit 17 sets the LLR (=-9) of index 0 of the selected LLR pattern Pat1 to the LLR of index 0 of the DLE1 table. As a result, the correction process for the DLE1 table is completed.

[0235] Please note that, for example, if the intersection of the two threshold voltage distributions of the memory primitive MC is voltage AR(-2), then similarly to the first embodiment, the read information generation circuit 17 shifts the LLR of each of indices 0 to 4 two bits to the right relative to the DLE1 table and calculates the integral value, and sets this integral value as the LLR of index 7. Thereafter, the read information generation circuit 17 compares a set of two LLRs of indices 2 and 3 of the DLE1 table with a set of two LLRs of indices 2 and 3 of the LLR pattern table. As a result of the comparison, the read information generation circuit 17 selects an LLR pattern in which at least a portion of the LLRs matches the LLRs of the DLE1 table. The read information generation circuit 17 can select, for example, an LLR pattern with a larger number of matching indices. The read information generation circuit 17 sets the LLR of index 0 of the selected LLR pattern as the LLR of index 0 of the DLE1 table. The read information generation circuit 17 further sets the LLR of index 1 of the selected LLR pattern as the LLR of index 1 of the DLE1 table.

[0236] [3-2] Effect

[0237] By configuring according to the third embodiment, the same effect as the first embodiment was obtained.

[0238] Furthermore, according to the third embodiment, a DLE1 table can be created that is closer to the LLR of the threshold voltage distribution of the ECC frame to be SB corrected.

[0239] [4] Fourth embodiment

[0240] The fourth embodiment will be described. The memory system 1 according to the fourth embodiment differs from the memory system 1 according to the first embodiment in that the DLE1 table correction processing is performed by the read information generation circuit 17. The flowchart showing the read operation of the memory controller 10 is the same as that of the first embodiment. Hereinafter, the differences from the first embodiment will be mainly described.

[0241] [4-1] Processing of the information generation circuit 17

[0242] (DLE1 table correction processing)

[0243] The information generation circuit 17 uses the LLR calculated based on the ratio of the sum of the high-voltage side LLRs of the HB read voltage to the sum of the low-voltage side LLRs of the HB read voltage to correct the DLE1 table.

[0244] Reference Figure 22 Describe the corrective action taken on the DLE1 table. Figure 22 This is a diagram illustrating the correction process for the DLE1 table. Figure 22 An example is shown where the HB read voltage of the successfully corrected SB is voltage AR(0) and the intersection of the two threshold voltage distributions of the memory primitive MC is voltage AR(-1).

[0245] Similar to the first embodiment, the read information generation circuit 17 shifts the LLR of each of indices 0 to 5 one bit to the right relative to the DLE1 table and calculates the integral value, setting this integral value as the LLR of index 7. Thereafter, the read information generation circuit 17 calculates the LLR of empty indices where no LLR is configured, based on the ratio of the sum of the high-voltage side LLRs of the HB read voltage to the sum of the low-voltage side LLRs of the HB read voltage. Specifically, the LLR is calculated using the following equation (3).

[0246] LLR1=LLR8×{-1×(LLR2+LLR3+LLR4) / (LLR5+LLR6+LLR7)} (3)

[0247] In the above formula, LLR1 is the LLR corresponding to index 0. Additionally, LLR2 through LLR8 are the absolute values ​​of the LLRs corresponding to indices 1 through 7, respectively. The calculated LLR saturates, for example, at integers whose absolute values ​​are less than or equal to 9.

[0248] The information generation circuit 17 will set the value (=-9) calculated in equation (3) above as the LLR of index 0 of the DLE1 table. As a result, the correction process of the DLE1 table is completed.

[0249] Please note that, for example, if the intersection of the two threshold voltage distributions of the memory primitive MC is voltage AR(-2), then similar to the first embodiment, the read information generation circuit 17 shifts the LLR of each of indices 0 to 4 two bits to the right relative to the DLE1 table and calculates the integral value, and sets this integral value as the LLR of index 7. Thereafter, the read information generation circuit 17 calculates the LLR of empty indices where no LLR is set based on the ratio of the sum of the high-voltage side LLRs of the HB read voltage to the sum of the low-voltage side LLRs of the HB read voltage. Specifically, the LLR is calculated using the following equation (4).

[0250] LLR2=LLR7×{-1×(LLR3+LLR4) / (LLR5+LLR6)} (4)

[0251] In the above formula, LLR2 is the LLR corresponding to index 1. Additionally, LLR3 through LLR7 are the absolute values ​​of the LLRs corresponding to indices 2 through 6, respectively. The calculated LLR saturates, for example, at integers whose absolute values ​​are less than or equal to 9.

[0252] The read information generation circuit 17 sets the value calculated in equation (4) above as the LLR of index 1 of the DLE1 table. The read information generation circuit 17 sets the value calculated in equation (3) above as the LLR of index 0 of the DLE1 table.

[0253] [4-2] Effects

[0254] By configuring according to the fourth embodiment, the same effect as the first embodiment was obtained.

[0255] Furthermore, according to the fourth embodiment, a DLE1 table can be created that is closer to the LLR of the threshold voltage distribution of the ECC frame to be SB corrected.

[0256] [5] Fifth embodiment

[0257] The fifth embodiment will be described. In the memory system 1 according to the fifth embodiment, the read operation performed by the memory controller 10 differs from that of the second embodiment. Hereinafter, the differences from the second embodiment will be mainly described.

[0258] [5-1] Read operation

[0259] Reference Figure 23 Describe the read operation. Figure 23This is a flowchart illustrating a read operation performed by a memory controller 10 provided in a memory system 1 according to a fifth embodiment. In the fifth embodiment, according to the second embodiment... Figure 19 The processing of step S23 is by Figure 23 The processing of steps S40 to S46 is replaced. The processing of steps S10 to S22 and steps S30 to S34 is the same as in the second embodiment. In the following, the operation of S40 to S46 will be mainly described.

[0260] exist Figure 23 In the process, when the generated shift value Vst is different from the shift value stored in RAM 16 (S22_No), and when the LLR is symmetrical in at least a portion of the DLE1 table based on the position of the sign reversal of the LLR in the DLE1 table (S40_Yes), the read information generation circuit 17 performs the correction process of the DLE1 table according to the first embodiment (S43). Figure 24 This is a diagram illustrating the symmetry of LLRs in the DLE1 table. Figure 24 In the examples, at indices 2 and 3, the absolute values ​​of the LLRs are the same, and the signs of the LLRs are reversed. That is, the LLRs at index 2 and index 3 are symmetrical. At indices 1 and 4, the absolute values ​​of the LLRs are the same, and the signs of the LLRs are reversed. That is, the LLRs at index 1 and index 4 are symmetrical.

[0261] Return to reference Figure 23 The description is as follows. When the LLR is asymmetrical throughout the DLE1 table (S40_No), and at least a portion of the LLR matches in the DLE1 table and the LLR pattern (S41_Yes), the read information generation circuit 17 performs the DLE1 table correction process of the third embodiment (S44).

[0262] When no LLR matches in the DLE1 table and the LLR pattern (S41_No), and at least a portion of the LLR matches in the DLE2 table and the DLE1 table (S42_Yes), the read information generation circuit 17 performs the first correction process of the second embodiment (S45).

[0263] When no LLR matches in either the DLE2 or DLE1 table (S42_No), the read information generation circuit 17 performs the DLE1 table correction process of the fourth embodiment (S46).

[0264] [5-2] Effect

[0265] By configuring according to the fifth embodiment, the same effect as the first embodiment was obtained.

[0266] Furthermore, according to the fifth embodiment, an optimal DLE1 table based on the shape of the threshold voltage distribution can be used.

[0267] [6] Variations

[0268] As described above, the memory system according to the embodiment includes: a semiconductor memory device (30) including a plurality of memory cells (CUs) each memory cell configured to store data in a non-volatile manner and connected to a word line according to its threshold voltage; and a controller (10) configured to: perform error correction (21) based on soft bit data and hard bit data read from the plurality of memory cells; generate a first table (DLE1 table) based on the data corrected by error correction (21); determine a voltage difference between a first voltage (HB read voltage) and a second voltage (Vtr), the first voltage being the voltage applied to the word line when the corrected data is read; and correct the first table based on the voltage difference.

[0269] Furthermore, the embodiments are not limited to the above embodiments, but can be modified in various ways.

[0270] Furthermore, the order of processes can be changed in the flowcharts described in the embodiments. For example, the order of determining the processes in steps S40, S41, and S42 is not limited to... Figure 23 The order shown in the flowchart. Furthermore, in Figure 23 In the flowchart, steps S40 and S43 can be omitted. Steps S41 and S44 can be omitted. Steps S42 and S45 can be omitted. Step S46 can be omitted.

[0271] Although specific embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of this disclosure. In fact, the novel embodiments described herein may be embodied in many other forms; furthermore, various omissions, substitutions, and changes may be made to the form of the embodiments described herein without departing from the spirit of this disclosure. The appended claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of this disclosure.

[0272] 1. Memory System

[0273] 2. Main unit

[0274] 10. Memory Controller

[0275] 11 Host Interface (I / F) Circuit

[0276] 12. Processor (Central Processing Unit (CPU))

[0277] 13 Buffer memory

[0278] 14. Error checking and correction (ECC) circuit

[0279] 15. Read-Only Memory (ROM)

[0280] 16. Random Access Memory (RAM)

[0281] 17 Information generation circuit

[0282] 18 NAND Interface (I / F) Circuit

[0283] 19 Encoding Circuit

[0284] 20 Hard Decision Decoding Circuit

[0285] 21 Soft-decision decoding circuit

[0286] 22 LLR conversion circuit

[0287] 23 Channel Matrix Generation Circuit

[0288] 24 Memory

[0289] 25 Dynamic LLR Estimation 2 (DLE2) Table Generation Circuit

[0290] 26 Channel Matrix Estimation Circuit

[0291] 30. Semiconductor memory devices (NAND flash memory)

[0292] 31. Memory cell array

[0293] 32 Input / Output Circuits

[0294] 33 Logic Control Circuit

[0295] 34 Ready / Busy Control Circuit

[0296] 35 Registers

[0297] 35A Command Register

[0298] 35B Address Register

[0299] 35C Status Register

[0300] 36 Sequencer

[0301] 37 Driver Module

[0302] 38-line decoder module

[0303] 39 Sensing Amplifier Module

Claims

1. A memory system, comprising: A semiconductor memory device comprising a plurality of memory cells, each memory cell being configured to store data in a non-volatile manner according to its threshold voltage and being connected to a word line; as well as The controller is configured as follows: Error correction is performed based on the hard bit data and soft bit data read from the plurality of memory primitives; A first table is generated based on the data that has been corrected through the error correction process. Determine the voltage difference between a first voltage and a second voltage, wherein the first voltage is the voltage applied to the word line when reading the corrected data; as well as Based on the voltage difference, correct the first table.

2. The memory system according to claim 1, wherein The controller is configured to determine the second voltage based at least on a first number of the plurality of memory cells having a threshold voltage within a first voltage range and storing corrected data with a first value, and a second number of the plurality of memory cells having a threshold voltage within the first voltage range and storing corrected data with a second value different from the first value.

3. The memory system according to claim 2, wherein The controller is configured to: further determine the second voltage based on a third number of the plurality of memory cells having a threshold voltage in a second voltage range different from the first voltage range and storing corrected data with the first value, and a fourth number of the plurality of memory cells having a threshold voltage in the second voltage range and storing corrected data with the second value.

4. The memory system according to claim 3, wherein The controller is configured to determine the voltage between the first voltage range and the second voltage range as the second voltage when the first quantity is greater than the second quantity and the third quantity is less than the fourth quantity.

5. The memory system according to claim 4, wherein The first table is configured to store a first set value corresponding to the first voltage range and a second set value corresponding to the second voltage range, and When the first voltage is greater than the second voltage, the controller corrects the first table by storing a third value as the second set value of the first table after correction, the third value having been stored as the first set value of the first table before correction.

6. The memory system according to claim 4, wherein The first table is configured to store a first set value corresponding to the first voltage range and a second set value corresponding to the second voltage range, and When the first voltage is less than the second voltage, the controller corrects the first table by storing a third value as the first set value of the first table after correction, the third value having been stored as the second set value of the first table before correction.

7. The memory system according to claim 1, wherein The semiconductor memory device includes multiple word lines and blocks as units of data erasure operations. The multiple word lines include first word lines connected to the plurality of memory cells and second word lines connected to another plurality of memory cells. The controller is configured to perform error correction on data read from the additional plurality of memory primitives connected to the second word line by applying the second voltage to the second word line using a corrected first table.

8. The memory system according to claim 1, wherein The first table is a table representing the relationship between the voltage range of the threshold voltages of the plurality of memory cells and the log-likelihood ratio (LLR). The first table before correction includes at least a first LLR corresponding to a first voltage range, a second LLR corresponding to a second voltage range, and a third LLR corresponding to a third voltage range. The controller is configured to: in the correction of the first table, calculate an integral value based on a first number of a plurality of memory cells having a threshold voltage within the first voltage range and storing corrected data with a first value, a second number of a plurality of memory cells having a threshold voltage within the first voltage range and storing corrected data with a second value different from the first value, a third number of a plurality of memory cells having a threshold voltage within the second voltage range and storing corrected data with the first value, and a fourth number of a plurality of memory cells having a threshold voltage within the second voltage range and storing corrected data with the second value; and in the first table after the correction, set the integral value to an LLR corresponding to the first voltage range, and set the integral value with an inverted sign to an LLR corresponding to the third voltage range.

9. The memory system according to claim 8, wherein The third voltage range includes a threshold voltage lower than the first voltage range and the second voltage range, and The first voltage range includes a threshold voltage that is higher than the second voltage range.

10. The memory system of claim 1, wherein The controller is configured to generate a second table based on data indicating unsuccessful error correction. Each of the first and second tables represents a relationship between the voltage range of the threshold voltages of the plurality of memory cells and the log-likelihood ratio (LLR). The first table prior to correction includes at least a first LLR corresponding to a first voltage range, a second LLR corresponding to a second voltage range, and a third LLR corresponding to a third voltage range. The second table includes at least a fourth LLR corresponding to the third voltage range. The controller is configured to: in the correction of the first table, calculate an integral value based on a first number of a plurality of memory cells having a threshold voltage within the first voltage range and storing corrected data with a first value, a second number of a plurality of memory cells having a threshold voltage within the first voltage range and storing corrected data with a second value different from the first value, a third number of a plurality of memory cells having a threshold voltage within the second voltage range and storing corrected data with the first value, and a fourth number of a plurality of memory cells having a threshold voltage within the second voltage range and storing corrected data with the second value; and in the first table after the correction, set the integral value to an LLR corresponding to the first voltage range, and set the fourth LLR to an LLR corresponding to the third voltage range.

11. The memory system of claim 10, wherein The third voltage range includes a threshold voltage lower than the first voltage range and the second voltage range, and The first voltage range includes a threshold voltage that is higher than the second voltage range.

12. The memory system according to claim 1, wherein The controller is configured to manage a second table, each of the first and second tables representing the relationship between the voltage range of the threshold voltages of the plurality of memory cells and the log-likelihood ratio (LLR). The first table before correction includes at least a first LLR corresponding to a first voltage range, a second LLR corresponding to a second voltage range, a third LLR corresponding to a third voltage range, a fourth LLR corresponding to a fourth voltage range, a fifth LLR corresponding to a fifth voltage range, and a sixth LLR corresponding to a sixth voltage range. The second table includes multiple modes, each of which includes at least a seventh LLR corresponding to the third voltage range, an eighth LLR corresponding to the fourth voltage range, a ninth LLR corresponding to the fifth voltage range, and a tenth LLR corresponding to the sixth voltage range. The controller is configured to, in the correction of the first table: An integral value is calculated based on a first number of multiple memory cells having a threshold voltage within the first voltage range and storing corrected data with a first value, a second number of multiple memory cells having a threshold voltage within the first voltage range and storing corrected data with a second value different from the first value, a third number of multiple memory cells having a threshold voltage within the second voltage range and storing corrected data with the first value, and a fourth number of multiple memory cells having a threshold voltage within the second voltage range and storing corrected data with the second value. In the first table after correction, the integral value is set to LLR corresponding to the first voltage range. Select a pattern that matches at least a portion of the first group of LLRs corresponding to the fourth to sixth voltage ranges of the first table and the second group of LLRs corresponding to the fourth to sixth voltage ranges of the second table; as well as In the first table after the correction, the seventh LLR of the selected mode is set to the LLR corresponding to the third voltage range.

13. The memory system of claim 12, wherein The third voltage range includes a threshold voltage lower than the first voltage range, the second voltage range, the fourth voltage range, the fifth voltage range, and the sixth voltage range, and The first voltage range includes a threshold voltage that is higher than the second voltage range, the fourth voltage range, the fifth voltage range, and the sixth voltage range.

14. The memory system of claim 1, wherein The first table is a table representing the relationship between the voltage range of the threshold voltages of the plurality of memory cells and the log-likelihood ratio (LLR). The first table before correction includes at least a first LLR corresponding to a first voltage range, a second LLR corresponding to a second voltage range, a third LLR corresponding to a third voltage range, a fourth LLR corresponding to a fourth voltage range, a fifth LLR corresponding to a fifth voltage range, a sixth LLR corresponding to a sixth voltage range, a seventh LLR corresponding to a seventh voltage range, and an eighth LLR corresponding to an eighth voltage range. The controller is configured to: in the correction of the first table, calculate an integral value based on a first number of a plurality of memory cells having a threshold voltage within the first voltage range and storing corrected data with a first value, a second number of a plurality of memory cells having a threshold voltage within the first voltage range and storing corrected data with a second value different from the first value, a third number of a plurality of memory cells having a threshold voltage within the second voltage range and storing corrected data with the first value, and a fourth number of a plurality of memory cells having a threshold voltage within the second voltage range and storing corrected data with the second value; and in the first table after the correction, set the integral value to correspond to the LLR of the first voltage range, and set a value calculated based on the ratio of the sum of the fourth LLR, the fifth LLR, and the sixth LLR to the sum of the seventh LLR, the eighth LLR, and the second LLR to correspond to the LLR of the third voltage range.

15. The memory system of claim 14, wherein The calculated value is obtained based on the ratio and the LLR corresponding to the first voltage range.

16. The memory system of claim 15, wherein The third voltage range includes a threshold voltage lower than the first voltage range, the second voltage range, the fourth voltage range, the fifth voltage range, the sixth voltage range, the seventh voltage range, and the eighth voltage range, and The first voltage range includes a threshold voltage that is higher than the second voltage range, the fourth voltage range, the fifth voltage range, the sixth voltage range, the seventh voltage range, and the eighth voltage range.

17. A method for performing error correction on data read from a plurality of memory bases, each memory base being configured to store data in a non-volatile manner according to its threshold voltage, the plurality of memory bases including a first memory base connected to a first word line and a second memory base connected to a second word line, the method comprising: Based on the hard bit data and soft bit data read from the first memory cell, perform the first error correction; A first table is generated based on the data that has been corrected through the first error correction. Determine the voltage difference between a first voltage and a second voltage, wherein the first voltage is the voltage applied to the first word line when acquiring corrected data; Based on the voltage difference, correct the first table; as well as Using the corrected first table, a second error correction is performed based on the hard bit data and soft bit data read from the second memory primitive.

18. The method of claim 17, wherein The second voltage is determined based at least on a first number of first memory cells having a threshold voltage within a first voltage range and storing corrected data with a first value, and a second number of first memory cells having a threshold voltage within the first voltage range and storing corrected data with a second value different from the first value.

19. The method of claim 18, wherein The second voltage is further determined based on a third number of first memory cells having a threshold voltage in a second voltage range different from the first voltage range and storing corrected data with the first value, and a fourth number of first memory cells having a threshold voltage in the second voltage range and storing corrected data with the second value.

20. The method according to claim 19, wherein, When the first quantity is greater than the second quantity and the third quantity is less than the fourth quantity, the voltage between the first voltage range and the second voltage range is determined as the second voltage.

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