Super junction trench gate mosfet device and method of manufacturing the same

Abstract

The application provides a trench gate MOSFET device and a preparation method thereof, wherein the preparation method comprises the following steps: providing a substrate comprising a cell region and a terminal region, forming an epitaxial layer on the substrate, and forming a trench gate structure in the epitaxial layer; forming a body region; forming a first column; forming a first heavily doped region; forming an interlayer dielectric layer; forming a first contact hole and a second contact hole; forming a second heavily doped region; forming a first column and a second column with lower ion energy than the first column; forming a first conductive plug and a second conductive plug. The application realizes the ion implantation of the second column by using the mask for forming the first contact hole and the second contact hole, and does not need to add a new mask, thereby reducing the device manufacturing cost. Further, the application forms the combined high-energy first column + low-energy second column, so that the cell region column and the body region are short-circuited to avoid the floating of the cell region column, and the terminal region column region is floated to improve the withstand voltage of the terminal region.

Description

Technical Field

[0001] This application relates to the field of semiconductor device manufacturing technology, specifically to a superjunction trench gate MOSFET device and its fabrication method. Background Technology

[0002] Trench gate MOSFETs are widely used in power conversion circuits, often as power switching devices. The on-resistance (R_sp) and breakdown voltage (BV) of the trench gate are among its important parameters; achieving higher breakdown voltage and lower on-resistance can improve product competitiveness. To improve the on-resistance of medium- to high-voltage (50V–200V) trench gates, the concept of a superjunction-trench gate achieved through ion implantation has been proposed.

[0003] Superjunction trench gate MOSFETs typically include a primitive cell region and a termination region. Taking an N-channel trench gate as an example, the P-pillar (PPL) of both the termination region and the primitive cell region is usually shorted to the P-type body region through injection. However, shorting the PPL of the termination to the body region will reduce the BV of the termination.

[0004] To improve the withstand voltage of the terminal area, the current common practice is to either form an independent floating PPL in the terminal area or form a floating or non-floating PPL in the unit cell area in one go. However, (1) if the PPL in the unit cell area adopts a floating design, it will directly affect the resistance of the device in AC operating state (increasing the on-resistance); (2) if the PPL in the unit cell area adopts a one-time non-floating design, that is, the overall lateral dimension of the PPL is consistent and the PPL is short-circuited with the body area, this will cause the lateral dimension of the upper surface of the PPL to be too wide, resulting in too many PPLs on the surface, which will reduce the current and increase the resistance of the device. Summary of the Invention

[0005] This application provides a superjunction trench gate MOSFET device and its fabrication method, which can solve at least one of the following problems in current superjunction trench gate MOSFET devices: BV is limited by the termination structure, floating PPL in the unit cell region leads to a large resistance of the device in AC operation, and non-floating PPL in the unit cell region leads to an increase in device resistance.

[0006] On one hand, embodiments of this application provide a method for fabricating a trench gate MOSFET device, including:

[0007] A substrate is provided, the substrate comprising a unit cell region and a terminal region, an epitaxial layer is formed on the substrate, a plurality of mutually spaced trenches are formed in the epitaxial layer, and a trench gate structure is formed in the trenches;

[0008] Global ion implantation is performed on the epitaxial layer to form a bulk region in the epitaxial layer between the trench gate structures;

[0009] Selective ion implantation is performed on the epitaxial layer to form a plurality of first pillars in the epitaxial layer, wherein the first pillars are not connected to the body region or the trench gate structure;

[0010] Selective ion implantation is performed on the epitaxial layer to form a plurality of first heavily doped regions in the bulk region of the unit cell region;

[0011] An interlayer dielectric layer is formed, which covers the epitaxial layer;

[0012] The interlayer dielectric layer, the first heavily doped region, and a partial thickness of the body region above the first pillar of the unit cell region are etched to form a first contact hole. At the same time, the interlayer dielectric layer and a partial thickness of the body region above the first pillar of the terminal region adjacent to the unit cell region are etched to form a second contact hole.

[0013] Ion implantation is performed on the bottom of the first contact hole and the bottom of the second contact hole to form a second heavily doped region in the bulk region;

[0014] Ion implantation is performed on the epitaxial layers at the bottom of the first contact hole and the bottom of the second contact hole to form second pillars connecting the second heavily doped region and the first pillar, respectively, wherein the ion implantation energy for forming the second pillar is lower than the ion implantation energy for forming the first pillar; and...

[0015] A first conductive plug and a second conductive plug are formed, wherein the first conductive plug fills the first contact hole and the second conductive plug fills the second contact hole.

[0016] Optionally, in the fabrication method of the trench gate MOSFET device, during the selective ion implantation of the epitaxial layer to form a plurality of first pillars in the epitaxial layer, the ion implantation energy is 500 keV to 4000 keV; the ion implantation dose is 5E11 / cm. 2 ~2E13 / cm 2 .

[0017] Optionally, in the fabrication method of the trench gate MOSFET device, during the process of ion implantation of the epitaxial layers at the bottom of the first contact hole and the bottom of the second contact hole to form a second pillar, the ion implantation energy is 200 keV to 1000 keV; the ion implantation dose is 5E11 / cm. 2 ~2E13 / cm 2 .

[0018] Optionally, in the method for fabricating the trench gate MOSFET device, the lateral dimension of the first pillar is larger than the lateral dimension of the second pillar.

[0019] Optionally, in the method for fabricating the trench gate MOSFET device, the step of forming the first conductive plug and the second conductive plug includes:

[0020] A first metal layer is formed, which covers the sidewalls and bottom wall of the first contact hole and the sidewalls and bottom wall of the second contact hole;

[0021] A second metal layer is formed, which covers the first metal layer;

[0022] Perform the hot annealing process;

[0023] A third metal layer is formed, which covers the second metal layer and fills the remaining space between the first contact hole and the second contact hole; and,

[0024] Remove the first metal layer, the second metal layer, and the third metal layer that extend beyond the surface of the first contact hole, the second contact hole, and the interlayer dielectric layer to obtain the first conductive plug in the first contact hole and the second conductive plug in the second contact hole.

[0025] Optionally, in the method for fabricating the trench gate MOSFET device, the trench gate structure includes: a gate dielectric layer and a polysilicon gate, wherein the gate dielectric layer covers the sidewalls and bottom wall of the trench, and the polysilicon gate covers the gate dielectric layer and fills the remaining space of the trench.

[0026] Optionally, in the fabrication method of the trench gate MOSFET device, the conductivity type of the first heavily doped region is different from that of the second heavily doped region.

[0027] On the other hand, embodiments of this application also provide a trench gate MOSFET device, including:

[0028] A substrate comprising a unit cell region and a terminal region, an epitaxial layer formed on the substrate, a plurality of mutually spaced trenches formed in the epitaxial layer, and a trench gate structure formed in the trenches;

[0029] The body region is located in the epitaxial layer between the trench gate structures;

[0030] The first pillar is located in the epitaxial layer and is not connected to the body region or the trench gate structure. The first pillar is obtained by selective ion implantation into the epitaxial layer.

[0031] The first doped region is located in the bulk region of the unit cell region;

[0032] An interlayer dielectric layer that covers the epitaxial layer;

[0033] The first contact hole is located in the interlayer dielectric layer, the first heavily doped region, and a partial thickness of the body region above the first pillar of the unit cell region. The second contact hole is located in the interlayer dielectric layer and a partial thickness of the body region above the first pillar of the terminal region adjacent to the unit cell region.

[0034] The second doped region is located in the body region at the bottom of the first contact hole and the bottom of the second contact hole;

[0035] The second pillar is located at the bottom of both the first and second contact holes, and connects the second heavily doped region to the first pillar. The second pillar is obtained by ion implantation into the epitaxial layers at the bottoms of the first and second contact holes, with the ion implantation energy for forming the second pillar being lower than that for forming the first pillar.

[0036] A first conductive plug and a second conductive plug, wherein the first conductive plug fills the first contact hole and the second conductive plug fills the second contact hole.

[0037] Optionally, in the trench gate MOSFET device, during the selective ion implantation of the epitaxial layer to obtain the first pillar, the ion implantation energy is 500 keV to 4000 keV; the ion implantation dose is 5E11 / cm. 2 ~2E13 / cm 2 .

[0038] Optionally, in the trench gate MOSFET device, during the process of obtaining the second pillar by ion implantation of the epitaxial layers at the bottom of the first contact hole and the bottom of the second contact hole, the ion implantation energy is 200 keV to 1000 keV; the ion implantation dose is 5E11 / cm. 2 ~2E13 / cm 2 .

[0039] The technical solution of this application has at least the following advantages:

[0040] First, by forming a second pillar with energy lower than that of the first pillar, this application obtains a combined pillar region in the unit cell region and a floating first pillar in the terminal region, which can realize different BV (breakdown voltage) designs between the terminal region and the unit cell region, and realize the disconnection between the first pillar in the terminal region and the body region, thereby improving the breakdown voltage of the entire device.

[0041] Second, this application combines a high-energy first pillar and a low-energy second pillar in the unit cell region to form a pillar region (PPL). This can achieve short-circuiting between the combined pillar region and the body region in the unit cell region, thereby reducing (improving) the resistance of the device in AC operating state. It can also reduce the surface area of ​​the combined pillar region and the body region, increase the current conduction area of ​​the device, and reduce the device resistance.

[0042] Third, by forming the second pillar after forming the first and second contact holes, this application is equivalent to using the photomask (mask template) used to form the first and second contact holes to achieve ion implantation of the second pillar. This eliminates the need to add a new photomask, reduces the number of photomasks, and lowers the fabrication cycle, manufacturing cost, and maintenance cost of the photomask template, thereby reducing device manufacturing costs and improving product competitiveness. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0044] Figure 1 This is a flowchart of a method for fabricating a trench gate MOSFET device according to an embodiment of the present invention;

[0045] Figures 2-10 This is a schematic diagram of the semiconductor structure in each process step of fabricating a trench gate MOSFET device according to an embodiment of the present invention;

[0046] The reference numerals in the attached figures are explained as follows:

[0047] 101-Substrate, 102-Epipolar layer, 103-First pillar, 104-Gate dielectric layer, 105-Polysilicon gate, 106-Bulk region, 107-Second heavily doped region, 108-First heavily doped region, 109-First conductive plug, 110-Interlayer dielectric layer, 201-Second pillar, 301-Second conductive plug, 302-First contact hole, 303-Second contact hole. Detailed Implementation

[0048] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0049] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0050] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0051] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0052] This application provides a method for fabricating a trench gate MOSFET device, referring to... Figure 1 , Figure 1 This is a flowchart of a method for fabricating a trench gate MOSFET device according to an embodiment of the present invention. The method for fabricating the trench gate MOSFET device includes:

[0053] Step S10: Provide a substrate, the substrate including a unit cell region and a terminal region, an epitaxial layer formed on the substrate, a plurality of mutually spaced trenches formed in the epitaxial layer, and a trench gate structure formed in the trenches;

[0054] Step S20: Perform global ion implantation on the epitaxial layer to form a bulk region in the epitaxial layer between the trench gate structures;

[0055] Step S30: Selective ion implantation is performed on the epitaxial layer to form a plurality of first pillars in the epitaxial layer, wherein the first pillars are not connected to the body region or the trench gate structure;

[0056] Step S40: Selectively implant ions into the epitaxial layer to form a plurality of first heavily doped regions in the bulk region of the unit cell region;

[0057] Step S50: Form an interlayer dielectric layer, wherein the interlayer dielectric layer covers the epitaxial layer;

[0058] Step S60: Etch the interlayer dielectric layer, the first heavily doped region, and a partial thickness of the body region above the first pillar of the unit cell region to form a plurality of first contact holes. At the same time, etch the interlayer dielectric layer and a partial thickness of the body region above the first pillar of the terminal region adjacent to the unit cell region to form second contact holes.

[0059] Step S70: Ion implantation is performed on the bottom of the first contact hole and the bottom of the second contact hole to form a plurality of second heavily doped regions in the body region;

[0060] Step S80: Ion implantation is performed on the epitaxial layers at the bottom of the first contact hole and the bottom of the second contact hole to form a second pillar that connects the second heavily doped region and the first pillar respectively, wherein the ion implantation energy for forming the second pillar is lower than the ion implantation energy for forming the first pillar;

[0061] Step S90: Form a first conductive plug and a second conductive plug, wherein the first conductive plug fills the first contact hole and the second conductive plug fills the second contact hole.

[0062] For details, please refer to Figures 2-10 , Figures 2-10 This is a schematic diagram of the semiconductor structure in each process step of fabricating a trench gate MOSFET device according to an embodiment of the present invention.

[0063] First, such as Figure 2 As shown, Figure 2 This is a schematic diagram of a semiconductor structure with a trench gate structure. A substrate 101 is provided, the substrate 101 includes a unit cell region and a terminal region, an epitaxial layer 102 is formed on the substrate 101, a plurality of mutually spaced trenches are formed in the epitaxial layer 102, and a trench gate structure is formed in the trenches.

[0064] The substrate 101 can be either heavily doped with N-type or heavily doped with P-type.

[0065] This embodiment takes an N-type channel superjunction-trench gate as an example, so the substrate 101 is a highly doped N-type substrate.

[0066] Furthermore, the epitaxial layer 102 can also be referred to as the drift region. In this embodiment, the doped ions in the epitaxial layer 102 are N-type. The doping concentration of the ions in the epitaxial layer 102 is 5E15 atoms / cm². 3 ~1E17atoms / cm 3 .

[0067] Preferably, the trench gate structure includes: a gate dielectric layer 104 and a polysilicon gate 105, wherein the gate dielectric layer 104 covers the sidewalls and bottom wall of the trench, and the polysilicon gate 105 covers the gate dielectric layer 104 and fills the remaining space of the trench.

[0068] Then, as Figure 3 As shown, Figure 3 This is a schematic diagram of the semiconductor structure after the formation of the body region. After global ion implantation and thermal diffusion of the epitaxial layer 102, a body region 106 is formed in the epitaxial layer 102 between the trench gate structures.

[0069] In this embodiment, the body region 106 is a P-type body region.

[0070] Next, as Figure 4 As shown, Figure 4 This is a schematic diagram of the semiconductor structure after the formation of the first pillar. Selective ion implantation is performed on the epitaxial layer 102 to form a plurality of floating first pillars 103 in the epitaxial layer 102. The first pillars 103 are not connected (in contact) with the body region 106, nor are they connected (in contact) with the trench gate structure.

[0071] Specifically, the first pillar 103 is located in the epitaxial layer 102 below the body region between the trench gate structures. During selective ion implantation of the epitaxial layer 102 to form a plurality of first pillars 103, the ion implantation energy is 500 keV to 4000 keV; the ion implantation dose is 5E11 / cm². 2 ~2E13 / cm 2 .

[0072] In this embodiment, the first column 103 is a P-shaped first column.

[0073] The first pillar 103 is used to assist the depletion of the N-type epitaxial layer 102 (drift region).

[0074] Furthermore, such as Figure 5 As shown, Figure 5 This is a schematic diagram of the semiconductor structure after the formation of the first heavily doped region. Selective ion implantation is performed on the epitaxial layer 102 to form a plurality of first heavily doped regions 108 in the bulk region 106 of the unit cell region.

[0075] In this embodiment, the first heavily doped region 108 is an N-type heavily doped region.

[0076] Next, as Figure 6 As shown, Figure 6This is a schematic diagram of the semiconductor structure after the formation of the interlayer dielectric layer, wherein the interlayer dielectric layer 110 is formed, and the interlayer dielectric layer 110 covers the epitaxial layer 102.

[0077] In some embodiments, the interlayer dielectric layer 110 may be made of silicon dioxide.

[0078] Furthermore, such as Figure 7 As shown, Figure 7 This is a schematic diagram of the semiconductor structure after the formation of the first contact hole and the second contact hole. The interlayer dielectric layer 110, the first heavily doped region 108 and the partial thickness of the body region 106 above the first pillar 103 of the unit cell region are etched to form a plurality of first contact holes 302. At the same time, the interlayer dielectric layer 110 and the partial thickness of the body region 106 above the first pillar 103 of the terminal region adjacent to the unit cell region are etched to form the second contact hole 303.

[0079] Next, as Figure 8 As shown, Figure 8 This is a schematic diagram of the semiconductor structure after the formation of the second doped region. Ion implantation is performed on the bottom of the first contact hole 302 and the bottom of the second contact hole 303 to form a plurality of second doped regions 107 in the body region 106.

[0080] Preferably, the conductivity type of the first heavily doped region 108 is different from that of the second heavily doped region 107.

[0081] In this embodiment, the second heavily doped region 107 is a P-type heavily doped region.

[0082] Furthermore, such as Figure 9 As shown, Figure 9 This is a schematic diagram of the semiconductor structure after the formation of the second pillar. Ion implantation is performed on the epitaxial layer 102 at the bottom of the first contact hole 302 and the bottom of the second contact hole 303 to form a second pillar 201 that connects the second heavily doped region 107 and the first pillar 103 respectively. That is, the top end of the second pillar 201 is connected to the second heavily doped region 107, the bottom end of the second pillar 201 is connected to the first pillar 103, and the second pillar 201 overlaps with the body region 106 at the bottom of the second heavily doped region 107.

[0083] In this application, by forming the second pillar 201 after forming the first contact hole 302 and the second contact hole 303, it is equivalent to using the photomask (mask template) formed by the first contact hole 302 and the second contact hole 303 to achieve ion implantation of the second pillar 201. There is no need to add a new photomask, which reduces the number of photomasks, reduces the fabrication cycle, fabrication cost and maintenance cost of the photomask, thereby reducing the device manufacturing cost and improving the competitiveness of the product.

[0084] The ion implantation energy for forming the second pillar 201 is lower than the ion implantation energy for forming the first pillar 103. Therefore, the high-energy first pillar 103 and the low-energy second pillar 201 combine to form a non-floating PPL in the unit cell region. Since the first pillar 103 in the terminal region is disconnected from the body region 106, the breakdown voltage of the terminal region can be increased, thereby increasing the overall breakdown voltage of the device (the breakdown voltage of the terminal region is less than the breakdown voltage of the unit cell region; increasing the breakdown voltage of the terminal region is equivalent to increasing the breakdown voltage of the entire device).

[0085] Furthermore, this application combines a high-energy first pillar and a low-energy second pillar in the unit cell region to form a pillar region (PPL). The lateral dimension of the second pillar is smaller than that of the first pillar, and the second pillar contacts the body region. The contact area between the first pillar and the body region is small. This not only achieves short-circuiting between the combined pillar region and the body region in the unit cell region, thereby reducing (improving) the resistance of the device in AC operating mode, but also reduces the surface area of ​​the combined pillar region and the body region, increasing the current conduction area of ​​the device and reducing the device resistance.

[0086] Specifically, during the process of ion implantation of the epitaxial layer 102 at the bottom of the first contact hole 302 and the bottom of the second contact hole 303 to form the second pillar 201, the ion implantation energy is 200 keV to 1000 keV; the ion implantation dose is 5E11 / cm. 2 ~2E13 / cm 2 .

[0087] It is worth noting that in the same preparation process (steps S10-S90), the ion implantation energy for forming the first column 103 is greater than (higher than) the ion implantation energy for forming the second column 201.

[0088] Preferably, the lateral dimension of the first column 103 is larger than the lateral dimension of the second column 201.

[0089] This application achieves a higher BV in the terminal region and a different BV (breakdown voltage) design in the cell region by forming a second pillar with a lower energy than the first pillar, thus obtaining a combined pillar region in the unit cell region, and forming a floating first pillar in the terminal region, ultimately achieving the goal of increasing the device BV.

[0090] Finally, as Figure 10 As shown, Figure 10 This is a schematic diagram of the semiconductor structure after the formation of the first conductive plug and the second conductive plug. The first conductive plug 109 and the second conductive plug 301 are formed. The first conductive plug 109 fills the first contact hole 302, and the second conductive plug 301 fills the second contact hole 303.

[0091] Specifically, the steps of forming the first conductive plug 109 and the second conductive plug 301 may include:

[0092] A first metal layer is formed, which covers the sidewalls and bottom wall of the first contact hole 302 and the sidewalls and bottom wall of the second contact hole 303.

[0093] A second metal layer is formed, which covers the first metal layer;

[0094] The thermal annealing process is performed to alloy the first metal layer / second metal layer with the epitaxial layer 102 and with the polysilicon gate 105;

[0095] A third metal layer is formed, which covers the second metal layer and fills the remaining space between the first contact hole and the second contact hole; and,

[0096] Remove the first metal layer, the second metal layer, and the third metal layer that extend beyond the surface of the first contact hole, the second contact hole, and the interlayer dielectric layer to obtain the first conductive plug 109 in the first contact hole 302 and the second conductive plug 301 in the second contact hole 303.

[0097] In this embodiment, the first metal layer can be a titanium layer; the second metal layer can be a titanium nitride layer; and the third metal layer can be a tungsten layer.

[0098] Based on the same inventive concept, embodiments of this application also provide a trench gate MOSFET device, such as... Figure 10 As shown, the trench gate MOSFET device includes:

[0099] The substrate 101 includes a unit cell region and a terminal region. An epitaxial layer 102 is formed on the substrate 101. A plurality of mutually spaced trenches are formed in the epitaxial layer 102. A trench gate structure is formed in the trenches.

[0100] Body region 106, the body region 106 being located in the epitaxial layer 102 between the trench gate structures;

[0101] The first pillar 103 is located in the epitaxial layer 102 and is not connected to the body region 106 or the trench gate structure. The first pillar 103 is obtained by selective ion implantation into the epitaxial layer 102.

[0102] The first doped region 108 is located in the bulk region 106 of the unit cell region;

[0103] Interlayer dielectric layer 110, wherein the interlayer dielectric layer 110 covers the epitaxial layer 102;

[0104] A first contact hole 302 and a second contact hole 303, wherein the first contact hole 302 is located in the interlayer dielectric layer 110, the first heavily doped region 108 and the partial thickness of the body region 106 above the first pillar 103 of the unit cell region, and the second contact hole 303 is located in the interlayer dielectric layer 110 and the partial thickness of the body region 106 above a first pillar 103 of the terminal region adjacent to the unit cell region.

[0105] The second doped region 107 is located in the body region 106 at the bottom of the first contact hole 302 and the bottom of the second contact hole 303.

[0106] The second pillar 201 is located at the bottom of the first contact hole 302 and the bottom of the second contact hole 303, and the second pillar 201 connects the second heavily doped region 107 and the first pillar 103, respectively. The second pillar 201 is obtained by ion implantation into the epitaxial layer 102 at the bottom of the first contact hole 302 and the bottom of the second contact hole 303. The ion implantation energy for forming the second pillar 201 is lower than the ion implantation energy for forming the first pillar 103.

[0107] A first conductive plug 109 and a second conductive plug 301, wherein the first conductive plug 109 fills the first contact hole 302 and the second conductive plug 301 fills the second contact hole 303.

[0108] In the process of selectively implanting ions into the epitaxial layer 102 to obtain the first pillar 103, the ion implantation energy is 500 keV to 4000 keV; the ion implantation dose is 5E11 / cm. 2 ~2E13 / cm 2 .

[0109] Furthermore, during the process of obtaining the second pillar 201 by ion implantation of the epitaxial layer 102 at the bottom of the first contact hole 302 and the bottom of the second contact hole 303, the ion implantation energy is 200 keV to 1000 keV; the ion implantation dose is 5E11 / cm. 2 ~2E13 / cm 2 .

[0110] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for fabricating a trench gate MOSFET device, characterized in that, include: A substrate is provided, the substrate comprising a unit cell region and a terminal region, an epitaxial layer is formed on the substrate, a plurality of mutually spaced trenches are formed in the epitaxial layer, and a trench gate structure is formed in the trenches; Global ion implantation is performed on the epitaxial layer to form a bulk region in the epitaxial layer between the trench gate structures; Selective ion implantation is performed on the epitaxial layer to form a plurality of first pillars in the epitaxial layer, wherein the first pillars are not connected to the body region or the trench gate structure; Selective ion implantation is performed on the epitaxial layer to form a plurality of first heavily doped regions in the bulk region of the unit cell region; An interlayer dielectric layer is formed, which covers the epitaxial layer; The interlayer dielectric layer, the first heavily doped region, and a partial thickness of the body region above the first pillar of the unit cell region are etched to form a first contact hole. At the same time, the interlayer dielectric layer and a partial thickness of the body region above the first pillar of the terminal region adjacent to the unit cell region are etched to form a second contact hole. Ion implantation is performed on the bottom of the first contact hole and the bottom of the second contact hole to form a second heavily doped region in the bulk region; Ion implantation is performed on the epitaxial layers at the bottom of the first contact hole and the bottom of the second contact hole to form a second pillar that connects the second heavily doped region and the first pillar respectively, wherein the ion implantation energy for forming the second pillar is lower than the ion implantation energy for forming the first pillar; as well as, A first conductive plug and a second conductive plug are formed, wherein the first conductive plug fills the first contact hole and the second conductive plug fills the second contact hole.

2. The method for fabricating a trench gate MOSFET device according to claim 1, characterized in that, During the selective ion implantation of the epitaxial layer to form a plurality of first pillars, the ion implantation energy is 500 keV to 4000 keV; the ion implantation dose is 5E11 / cm². 2 ~2E13 / cm 2 .

3. The method for fabricating a trench gate MOSFET device according to claim 1, characterized in that, During the process of ion implantation to form the second pillar by ion implantation into the epitaxial layers at the bottom of the first contact hole and the bottom of the second contact hole, the ion implantation energy is 200 keV to 1000 keV; the ion implantation dose is 5E11 / cm. 2 ~2E13 / cm 2 .

4. The method for fabricating a trench gate MOSFET device according to claim 1, characterized in that, The lateral dimension of the first column is larger than the lateral dimension of the second column.

5. The method for fabricating a trench gate MOSFET device according to claim 1, characterized in that, The steps for forming the first conductive plug and the second conductive plug include: A first metal layer is formed, which covers the sidewalls and bottom wall of the first contact hole and the sidewalls and bottom wall of the second contact hole; A second metal layer is formed, which covers the first metal layer; Perform the hot annealing process; A third metal layer is formed, which covers the second metal layer and fills the remaining space between the first contact hole and the second contact hole; and, Remove the first metal layer, the second metal layer, and the third metal layer that extend beyond the surface of the first contact hole, the second contact hole, and the interlayer dielectric layer to obtain the first conductive plug in the first contact hole and the second conductive plug in the second contact hole.

6. The method for fabricating a trench gate MOSFET device according to claim 1, characterized in that, The trench gate structure includes a gate dielectric layer and a polysilicon gate, wherein the gate dielectric layer covers the sidewalls and bottom wall of the trench, and the polysilicon gate covers the gate dielectric layer and fills the remaining space of the trench.

7. The method for fabricating a trench gate MOSFET device according to claim 1, characterized in that, The conductivity type of the first heavily doped region is different from that of the second heavily doped region.

8. A trench gate MOSFET device, characterized in that, include: A substrate comprising a unit cell region and a terminal region, an epitaxial layer formed on the substrate, a plurality of mutually spaced trenches formed in the epitaxial layer, and a trench gate structure formed in the trenches; The body region is located in the epitaxial layer between the trench gate structures; The first pillar is located in the epitaxial layer and is not connected to the body region or the trench gate structure. The first pillar is obtained by selective ion implantation into the epitaxial layer. The first doped region is located in the bulk region of the unit cell region; An interlayer dielectric layer that covers the epitaxial layer; The first contact hole is located in the interlayer dielectric layer, the first heavily doped region, and a partial thickness of the body region above the first pillar of the unit cell region. The second contact hole is located in the interlayer dielectric layer and a partial thickness of the body region above the first pillar of the terminal region adjacent to the unit cell region. The second doped region is located in the body region at the bottom of the first contact hole and the bottom of the second contact hole; A second pillar is located at the bottom of both the first and second contact holes, and connects the second heavily doped region to the first pillar. The second pillar is obtained by ion implantation into the epitaxial layers at the bottoms of the first and second contact holes, with the ion implantation energy for forming the second pillar being lower than that for forming the first pillar. A first conductive plug and a second conductive plug, wherein the first conductive plug fills the first contact hole and the second conductive plug fills the second contact hole.

9. The trench gate MOSFET device according to claim 8, characterized in that, During the selective ion implantation of the epitaxial layer to obtain the first pillar, the ion implantation energy is 500 keV to 4000 keV; the ion implantation dose is 5E11 / cm. 2 ~2E13 / cm 2 .

10. The trench gate MOSFET device according to claim 8, characterized in that, During the process of obtaining the second pillar by ion implantation of the epitaxial layers at the bottom of the first contact hole and the bottom of the second contact hole, the ion implantation energy is 200 keV to 1000 keV; the ion implantation dose is 5E11 / cm. 2 ~2E13 / cm 2 .

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