A semiconductor device and a manufacturing method thereof

Abstract

The application discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and aims to realize the manufacturing of NMOS ring-gate transistors and PMOS ring-gate transistors with different channel materials, and improve the working performance of CMOS devices. The semiconductor device comprises N-type ring-gate transistors and P-type ring-gate transistors which are distributed at intervals. The active structure of the N-type ring-gate transistors and the active structure of the P-type ring-gate transistors both have a source region, a drain region and at least one layer of nano structures between the source region and the drain region. The part of the at least one layer of nano structures of the P-type ring-gate transistors which is covered by a gate stack structure of the P-type ring-gate transistors is a channel part, and the part of the at least one layer of nano structures of the P-type ring-gate transistors which is covered by a gate sidewall of the P-type ring-gate transistors is a connecting part. The content of germanium in the channel part is greater than the content of germanium in the connecting part and the content of germanium in the at least one layer of nano structures of the N-type ring-gate transistors.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] Gate-around transistors (GMT-A) include gate stacks formed not only on the top and sidewalls of the channel but also on the bottom of the channel. Therefore, compared to planar transistors and fin field-effect transistors, GMT-A has advantages such as higher gate control capability. Furthermore, in CMOS devices, NMOS GMT-A typically uses strained silicon, germanium-silicon with low germanium content, or group III-V materials to fabricate the channel, while PMOS GMT-A typically uses high-mobility channel materials such as germanium-silicon to fabricate the channel. This reduces the difference in carrier mobility between NMOS and PMOS GMT-A, allowing both types of transistors to simultaneously possess good conductivity.

[0003] However, it is difficult to manufacture the aforementioned NMOS and PMOS gate ring transistors with different channel materials using existing manufacturing methods, which is not conducive to improving the operating performance of CMOS devices. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and its manufacturing method, which enables the fabrication of NMOS and PMOS gate ring transistors with different channel materials, thereby improving the performance of CMOS devices.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a semiconductor device comprising: an N-type gate-around transistor and a P-type gate-around transistor spaced apart. Both the active structures of the N-type and P-type gate-around transistors have a source region, a drain region, and at least one nanostructure located between the source and drain regions. Furthermore, the portion of the at least one nanostructure of the P-type gate-around transistor covered by a gate stack structure of the P-type gate-around transistor constitutes a channel portion, and the portion of the at least one nanostructure of the P-type gate-around transistor covered by a gate sidewall of the P-type gate-around transistor constitutes a connection portion. The germanium content in the channel portion is greater than the germanium content in the connection portion and the germanium content in the at least one nanostructure of the N-type gate-around transistor.

[0006] In the above-described technical solution, the at least one nanostructure layer of the P-type gate-around transistor is located between the source and drain regions of the P-type gate-around transistor. Furthermore, the portion of the at least one nanostructure layer of the P-type gate-around transistor covered by the gate stack structure of the P-type gate-around transistor constitutes a channel portion, and the portion of the at least one nanostructure layer of the P-type gate-around transistor covered by the gate sidewall of the P-type gate-around transistor constitutes a connection portion. Simultaneously, the germanium content in the aforementioned channel portion is greater than the germanium content in the at least one nanostructure layer of the N-type gate-around transistor. Based on this, since germanium-containing semiconductor materials such as silicon have higher carrier mobility than silicon or other semiconductor materials commonly used in the nanostructures of N-type gate-around transistors, when the germanium content in the channel of a P-type gate-around transistor is greater than the germanium content in at least one layer of the nanostructure of an N-type gate-around transistor, it is advantageous for the channel carrier mobility of the N-type gate-around transistor, which is also a gate-around transistor, to be better than that of the P-type gate-around transistor. The difference between the corresponding carrier mobilities can also be reduced by using the high-mobility channel material with higher germanium content to manufacture the channel of the PMOS transistor. At the same time, it can also prevent problems such as poor interface states and high source-drain contact resistance caused by germanium or high germanium content in the nanostructures of N-type gate-around transistors, so that both N-type and P-type gate-around transistors have good conductivity.

[0007] Furthermore, compared to semiconductor materials with higher germanium content, semiconductor materials with lower germanium content, such as silicon, have a larger bandgap, meaning they have a stronger ability to confine charge carriers. Based on this, the germanium content in the channel portion of a P-type gate-around transistor is greater than the germanium content in the connection portion. In this case, a connection portion with lower germanium content is provided between the higher germanium content channel portion and the source and drain regions, respectively. The presence of this connection portion can improve the carrier confinement ability between the channel portion and the source and drain regions, thereby reducing leakage current and further improving the electrical performance of the P-type gate-around transistor.

[0008] Secondly, the present invention also provides a method for manufacturing a semiconductor device, the method comprising: First, forming a first pre-formed structure and a second pre-formed structure spaced apart on a semiconductor substrate. Both the first and second pre-formed structures include at least one suspended channel layer and gate sidewalls spanning the two edge regions along the length direction of the at least one suspended channel layer. The second pre-formed structure further includes germanium-containing semiconductor layers located only on both sides of each suspended channel layer along its thickness direction. The germanium content in the germanium-containing semiconductor layers is greater than the germanium content in the suspended channel layers. Next, under the masking effect of the first mask layer and the gate sidewalls included in the second pre-formed structure, the exposed portions of the germanium-containing semiconductor layer and the at least one suspended channel layer included in the second pre-formed structure are subjected to a concentrated oxidation treatment. The first mask layer covers the first pre-formed structure. Next, an N-type gate-around transistor is formed based on the first pre-formed structure, and a P-type gate-around transistor is formed based on the second pre-formed structure after the concentrated oxidation treatment. The N-type gate-around transistor and the P-type gate-around transistor are spaced apart. Both the active structures of N-type and P-type gate-around transistors have a source region, a drain region, and at least one nanostructure located between the source and drain regions. The portion of the at least one nanostructure in a P-type gate-around transistor covered by the gate stack structure is a channel, and the portion of the at least one nanostructure in a P-type gate-around transistor covered by the gate sidewall is a connection. The germanium content in the channel is greater than the germanium content in the connection and the germanium content in the at least one nanostructure in the N-type gate-around transistor.

[0009] The beneficial effects of the second aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. Attached Figure Description

[0010] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 1 and indication Figure 2 ; Figure 2 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 3 and indication Figure 4 ; Figure 3Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 5 and indication Figure 6 ; Figure 4 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 7 and indication Figure 8 ; Figure 5 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 9 and indication Figure 10 ; Figure 6 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 10 One and illustration Figure 10 two; Figure 7 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 10 Three and diagram Figure 10 Four; Figure 8 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 10 Five and diagram Figure 10 six; Figure 9 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 10 Seven and symbol Figure 10 eight; Figure 10 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 Nine; Figure 11 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 ten; Figure 12 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 eleven; Figure 13 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 twelve; Figure 14 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 Thirteen; Figure 15 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 fourteen; Figure 16 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 fifteen; Figure 17 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 sixteen; Figure 18 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 Seventeen; Figure 19 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 eighteen; Figure 20 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 nineteen; Figure 21 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 3 Ten and symbol Figure 3 eleven; Figure 22 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 3 Twelve and symbol Figure 3 Thirteen.

[0011] Reference numerals: 11 Semiconductor substrate, 12 First fin structure, 13 Second fin structure, 14 Stacked layer, 15 Sacrificial layer, 16 First semiconductor material layer, 17 Second semiconductor material layer, 18 Germanium-containing semiconductor material layer, 19 Semiconductor isolation layer, 20 Shallow trench isolation structure, 21 Sacrificial gate, 22 Gate sidewall, 23 Notch, 24 Inner sidewall, 25 Source region, 26 Drain region, 27 Dielectric isolation layer, 28 Interlayer dielectric layer, 29 Second mask layer, 30 Floating channel layer, 31 Germanium-containing semiconductor layer, 32 First preformed structure, 33 Second preformed structure, 34 First mask layer, 35 Nanostructure, 36 Channel portion, 37 Connector portion, 38 Gate stacked structure. Detailed Implementation

[0012] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0013] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0014] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0015] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0016] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0017] Gate-around transistors (GMT-A) include gate stacks formed not only on the top and sidewalls of the channel but also on the bottom of the channel. Therefore, compared to planar transistors and fin field-effect transistors, GMT-A offers advantages such as higher gate control capability. Based on this, when both NMOS and PMOS transistors in a CMOS device are GMT-A, the operating performance of the CMOS device can be improved.

[0018] In a gate-around transistor (GMT) the channel orientation is typically

[100] . In this case, the channel is favorable for electron transport but unfavorable for hole transport. Therefore, since the channel carriers of an NMOS transistor are electrons and those of a PMOS transistor are holes, when a GMT with a

[100] oriented channel is applied to the aforementioned CMOS device, the GMT only improves the electron mobility of the NMOS transistor but not the hole mobility of the PMOS transistor, resulting in poor performance of the CMOS device using the GMT structure. Based on the above, since high-mobility channel materials such as germanium and silicon have higher carrier mobility, when the channel of a PMOS transistor has at least one nanostructure, the channel can be manufactured using high-mobility channel materials such as germanium and silicon to improve the hole mobility of the PMOS transistor. However, when the conductive channel in an NMOS transistor is manufactured using the aforementioned high-mobility material, problems such as poor interface states and high source-drain contact resistance arise. Therefore, germanium-silicon or high-mobility germanium materials are generally used as the channel for PMOS transistors, while NMOS transistors use strained silicon, germanium-silicon with lower germanium content, or group III-V materials to fabricate the channel. Based on this, even when the device structures of both NMOS and PMOS transistors in a CMOS device are the aforementioned gate-around transistors, and the channel carrier mobility of the NMOS transistor is superior to that of the PMOS transistor, the difference between their corresponding carrier mobilities can be reduced by fabricating the PMOS transistor channel using the aforementioned high-mobility channel materials. This allows both types of transistors to simultaneously possess good conductivity.

[0019] However, in actual manufacturing processes, when fabricating the aforementioned CMOS devices using the channel materials of NMOS and PMOS transistors as both channel and sacrificial layers, the selection of the Germanium-silicon PMOS transistor's channel is relatively low during the removal of the silicon sacrificial layer after releasing the PMOS transistor's channel. This results in poor channel formation quality. Furthermore, one of the NMOS or PMOS transistors may have a thicker channel, and the gate stack of a transistor with a thicker channel is difficult to fill in the regions between adjacent nanostructures and between the nanostructures and the semiconductor substrate, thus affecting the transistor's performance. Therefore, it is difficult to fabricate NMOS and PMOS transistors with different channel materials using existing manufacturing methods.

[0020] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same. In the semiconductor device provided by these embodiments, the germanium content in the channel portion of a P-type gate-around transistor is greater than the germanium content in at least one nanostructure layer of an N-type gate-around transistor, resulting in both N-type and P-type gate-around transistors exhibiting good conductivity. Furthermore, the germanium content in the channel portion of the P-type gate-around transistor is greater than the germanium content in the connection portion, thereby reducing leakage current.

[0021] like Figures 20 to 22 As shown in sections (1) and (2) of the present invention, the semiconductor device provided in this embodiment includes: an N-type gate-around transistor and a P-type gate-around transistor spaced apart. Both the active structures of the N-type gate-around transistor and the P-type gate-around transistor have a source region 25, a drain region 26, and at least one nanostructure 35 located between the source region 25 and the drain region 26. Furthermore, as... Figure 22 As shown in parts (1) and (2), the portion of the P-type gate ring transistor whose at least one nanostructure 35 is covered by the gate stack structure 38 is the channel portion 36, and the portion of the P-type gate ring transistor whose at least one nanostructure 35 is covered by the gate sidewall 22 is the connection portion 37. Figures 20 to 22 As shown in parts (1) and (2), the germanium content in the channel portion 36 is greater than the germanium content in the connection portion 37 and the germanium content in the at least one nanostructure 35 included in the N-type ring gate transistor.

[0022] Specifically, in practical applications, such as Figures 20 to 22 As shown in sections (1) and (2) above, the semiconductor device may further include a semiconductor substrate 11. Figure 20As shown, N-type gate-around transistors and P-type gate-around transistors can be spaced apart on the semiconductor substrate 11 along a direction parallel to the surface of the semiconductor substrate 11. Alternatively, as... Figure 22 As shown in part (2), N-type gate ring transistors and P-type gate ring transistors can also be distributed at intervals on the semiconductor substrate 11 along the thickness direction of the semiconductor substrate 11.

[0023] The semiconductor substrate can be a silicon substrate, a germanium-silicon substrate, a germanium substrate, or a silicon-on-insulator substrate, etc., on which no structure is formed.

[0024] Alternatively, a semiconductor substrate with certain structures can be formed on the semiconductor substrate. Specifically, the structures formed on the semiconductor substrate can be determined according to the actual application scenario, and are not specifically limited here. For example, when the semiconductor device provided in the embodiments of the present invention is applied to a second or higher layer of semiconductor devices in an integrated circuit, the semiconductor substrate includes a semiconductor substrate, at least one layer of semiconductor devices located below the semiconductor device provided in the embodiments of the present invention, and an interlayer dielectric layer that isolates different layers of semiconductor devices.

[0025] Additionally, it should be noted that when N-type and P-type gate-around transistors are spaced apart on the semiconductor substrate along its thickness direction, they constitute a CFET device. In this CFET device, the N-type gate-around transistor can be located below the P-type gate-around transistor; or, as... Figure 22 As shown in part (2), the P-type gate ring transistor can also be located below the N-type gate ring transistor. Furthermore, the semiconductor device may also include a dielectric isolation layer 27 located between the N-type gate ring transistor and the P-type gate ring transistor. This dielectric isolation layer 27 is situated between the source region 25 and drain region 26 of the N-type gate ring transistor and the source region 25 and drain region 26 of the P-type gate ring transistor, respectively. The material of the dielectric isolation layer 27 can be an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The thickness of the dielectric isolation layer 27 is not specifically limited in this embodiment of the invention.

[0026] Structurally, both the N-type and P-type gate-around transistors described above can include an active structure, a gate stack structure, and gate sidewalls. Specifically, the gate sidewalls of the N-type gate-around transistor are formed on at least both sides of the gate stack structure along its length. The gate stack structure surrounds the periphery of each nanostructure layer of the N-type gate-around transistor, and the gate sidewalls span the edge regions of the nanostructure along its length. More specifically, the gate stack structure of the N-type gate-around transistor includes a gate dielectric layer that surrounds at least the periphery of each nanostructure layer, and a gate located on the gate dielectric layer. The portion of the nanostructure covered by the gate sidewalls of the N-type gate-around transistor is integrally formed with the portion covered by the gate stack structure and is made of the same or substantially the same material.

[0027] As for P-type gate-around transistors, such as Figure 22 As shown in part (1), the gate sidewall 22 of the P-type gate ring transistor is formed on at least both sides of the gate stack structure 38 of the P-type gate ring transistor along its length. The gate stack structure 38 of the P-type gate ring transistor surrounds the outer periphery of the channel portion 36 included in each nanostructure 35 of the P-type gate ring transistor, and the gate sidewall 22 of the P-type gate ring transistor spans the connection portion 37 included in the nanostructure 35 of the P-type gate ring transistor. Specifically, the gate stack structure 38 of the P-type gate ring transistor includes a gate dielectric layer that surrounds at least the outer periphery of each nanostructure 35 of the P-type gate ring transistor, and a gate located on the gate dielectric layer.

[0028] In terms of materials, the source and drain regions of N-type and P-type gate-around transistors can be made of semiconductor materials such as silicon, silicon germanium, or germanium. The gate sidewalls of N-type and P-type gate-around transistors can be made of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The gate dielectric layer of N-type and P-type gate-around transistors can be made of materials with high dielectric constants such as HfO2, ZrO2, TiO2, or Al2O3. The gate material of N-type and P-type gate-around transistors can be conductive materials such as TiN, TaN, or TiSiN.

[0029] As for the materials of the nanostructures included in the N-type gate ring transistor and the materials of the channel and the connection portion in the nanostructures included in the P-type gate ring transistor, they can be determined according to the actual application scenario, as long as the germanium content in the channel portion of the P-type gate ring transistor is greater than the germanium content in the connection portion and the germanium content in at least one layer of the nanostructure included in the N-type gate ring transistor.

[0030] For example, the germanium content in the channel portion can be greater than or equal to 10% and less than or equal to 60%. For instance, the germanium content in the channel portion can be 10%, 20%, 30%, 40%, 50%, or 60%. In this case, with the germanium content in the channel portion within the above range, it can prevent a smaller increase in the carrier mobility of the nanostructures included in the P-type gate ring transistor due to a lower germanium content in the channel portion, ensuring a smaller difference in carrier mobility between the nanostructures included in the N-type gate ring transistor and the P-type gate ring transistor in the semiconductor device. Furthermore, in the actual manufacturing process, a concentrated oxidation process is used to ensure that the germanium content in the channel portion of the P-type gate ring transistor is greater than the germanium content in the interconnect portion. Based on this, with the germanium content in the channel portion within the above range, it can prevent a larger germanium content in the channel portion from causing greater manufacturing difficulty for the nanostructures included in the P-type gate ring transistor, thus facilitating the production of semiconductor devices.

[0031] Specifically, the channel material can be any semiconductor material containing germanium. For example, the channel material can be germanium silicon, silicon germanium gallium, or silicon germanium indium, etc.

[0032] For the at least one nanostructure included in the N-type gate-around transistor and the interconnect included in the P-type gate-around transistor, the germanium content in the material of at least one of them can be 0. In this case, the material of the at least one nanostructure included in the N-type gate-around transistor and / or the interconnect included in the P-type gate-around transistor can be a semiconductor material such as silicon, silicon carbide, silicon-arsenic carbide, or antimony-silicon-silicon carbide.

[0033] Alternatively, the material of the connection portion of the P-type gate-around transistor and / or the at least one nanostructure layer of the N-type gate-around transistor can also be a semiconductor material with a low germanium content. The specific germanium content in this semiconductor material can be determined based on the germanium content in the channel portion of the P-type gate-around transistor, as long as it can be applied to the semiconductor device provided in the embodiments of the present invention. The aforementioned semiconductor material with a low germanium content can be germanium-silicon, silicon-germanium-gallium, or silicon-germanium-indium, etc.

[0034] For example, the N-type gate ring transistor includes at least one layer of nanostructure and / or interconnects made of germanium silicon, and the germanium content in the germanium silicon is less than 10%.

[0035] It should be noted that, as Figure 20 ,as well as Figure 22 As shown in part (1), when the N-type gate ring transistor and the P-type gate ring transistor are spaced apart along a direction parallel to the surface of the semiconductor substrate 11, the materials of the nanostructure 35 included in the N-type gate ring transistor and the materials of the connection portion 37 and the channel portion 36 included in the P-type gate ring transistor are of the same type except for germanium. At this time, as... Figures 1 to 9 Part (1) of the text, and Figures 10 to 20 As shown, the nanostructures 35 included in N-type gate ring transistors and P-type gate ring transistors can be fabricated based on the same suspended channel layer 30, which simplifies the semiconductor device manufacturing process and reduces the manufacturing difficulty of semiconductor devices.

[0036] like Figure 22 As shown in section (2), when the N-type gate ring transistor and the P-type gate ring transistor are spaced apart along the direction parallel to the thickness of the semiconductor substrate 11, the material of the nanostructure 35 included in the N-type gate ring transistor may differ from that of the nanostructure 35 included in the P-type gate ring transistor in at least some elemental composition, except for germanium. For example, the material of the nanostructure 35 included in the N-type gate ring transistor may be silicon carbide, the material of the channel portion 36 included in the P-type gate ring transistor may be germanium-silicon, and the material of the connection portion 37 may be silicon. Alternatively, the materials of the nanostructure 35 included in the N-type gate ring transistor and the materials of the connection portion 37 and the channel portion 36 included in the P-type gate ring transistor may contain the same elements other than germanium. For example, the material of the nanostructure 35 included in the N-type gate ring transistor may be silicon, the material of the channel portion 36 included in the P-type gate ring transistor may be germanium-silicon, and the material of the connection portion 37 may be silicon.

[0037] As can be seen from the above, such as Figure 22As shown in sections (1) and (2), the at least one nanostructure 35 of the P-type gate-around transistor is located between the source region 25 and the drain region 26 of the P-type gate-around transistor. Furthermore, the portion of the at least one nanostructure 35 of the P-type gate-around transistor covered by the gate stack structure 38 of the P-type gate-around transistor forms the channel portion 36, and the portion of the at least one nanostructure 35 of the P-type gate-around transistor covered by the gate sidewall 22 of the P-type gate-around transistor forms the connection portion 37. Simultaneously, the germanium content in the channel portion 36 is greater than the germanium content in the at least one nanostructure 35 of the N-type gate-around transistor. Based on this, since germanium-containing semiconductor materials such as germanium-silicon or germanium have higher carrier mobility compared to silicon, when the germanium content in the channel portion 36 of a P-type gate-around transistor is greater than the germanium content in the at least one nanostructure 35 of an N-type gate-around transistor, the channel carrier mobility of the N-type gate-around transistor, which is also a gate-around transistor, is superior to that of the P-type gate-around transistor. Furthermore, by using the aforementioned high-mobility channel material with higher germanium content to manufacture the channel of a PMOS transistor, the difference between the corresponding carrier mobilities can be reduced. This also prevents problems such as poor interface states and high source-drain contact resistance that can occur when the nanostructure 35 of the N-type gate-around transistor contains germanium or a high amount of germanium. This allows both N-type and P-type gate-around transistors to possess good conductivity. In addition, compared to semiconductor materials with higher germanium content, semiconductor materials with lower germanium content, such as silicon, have a larger bandgap, meaning that semiconductor materials with lower germanium content, such as silicon, have a stronger ability to confine carriers. Based on this, the germanium content in the channel portion 36 of the P-type gate ring transistor is greater than the germanium content in the connection portion 37. At this time, a connection portion 37 with a lower germanium content is provided between the channel portion 36 with a higher germanium content and the source region 25 and the drain region 26, respectively. The presence of the connection portion 37 can improve the carrier binding capacity between the channel portion 36 and the source region 25 and the drain region 26, thereby reducing leakage current and further improving the electrical performance of the P-type gate ring transistor.

[0038] In one example, such as Figure 22 As shown in parts (1) and (2) above, the P-type gate-around transistor includes inner walls 24 located between the source region 25 and the gate stack structure 38, and between the drain region 26 and the gate stack structure 38. The inner walls 24 of the P-type gate-around transistor have the same length at each portion along the thickness direction of the gate stack structure 38, and the length direction of the inner walls 24 is parallel to the length direction of the gate stack structure 38. Alternatively, as... Figure 22As shown in parts (1) and (2), the length of a portion of the inner wall 24 of the P-type gate ring transistor along the thickness direction of the gate stack structure 38 is greater than the length of the remaining portion, and the length direction of the inner wall 24 of the P-type gate ring transistor is parallel to the length direction of the gate stack structure 38.

[0039] Specifically, in the actual manufacturing process, such as Figure 5 and Figure 6 As shown in parts (1) and (2), when etching the edge region of the germanium-containing semiconductor material layer 18 and the sacrificial layer 15 to form a notch 23, if the etching rate of the etchant on the sacrificial layer 15 is greater than its etching rate on the germanium-containing semiconductor material layer 18, then the length of a portion of the inner sidewall 24 of the P-type gate ring transistor along the thickness direction of the gate stack structure 38 is greater than the length of the remaining regions. Furthermore, the portion of the inner sidewall 24 protruding towards the gate stack structure 38 corresponds to the area released by the etched portion of the sacrificial layer 15. However, if the etching rates of the etchant on the sacrificial layer 15 and the germanium-containing semiconductor material layer 18 are approximately the same, then the lengths of each portion of the inner sidewall 24 of the P-type gate ring transistor along the thickness direction of the gate stack structure are all the same.

[0040] The length of each region of the inner wall of the P-type gate ring transistor along the thickness direction of the gate stack structure can be determined based on the sacrificial layer and the germanium-containing semiconductor material, as well as the actual manufacturing process, and is not specifically limited here.

[0041] It is worth noting that when the length of the gate stack structure included in the P-type gate ring transistor is fixed, a portion of the inner wall protrudes towards the gate stack structure along the thickness direction. This can increase the distance between the source region and the gate stack structure on both sides of the protruding portion of the inner wall, as well as between the drain region and the gate stack structure. This can reduce the parasitic capacitance between the source region and the gate stack structure, as well as between the drain region and the gate stack structure, thereby further improving the operating performance of the P-type gate ring transistor.

[0042] In one example, such as Figure 22 As shown in part (2), the aforementioned N-type gate-around transistor includes inner walls 24 located between the source region 25 and the gate stack structure 38, and between the drain region 26 and the gate stack structure 38. The inner walls 24 of the N-type gate-around transistor have the same length at each portion along the thickness direction of the gate stack structure 38, and the length direction of the inner walls 24 is parallel to the length direction of the gate stack structure 38. Alternatively, as... Figure 22 As shown in part (2), the length of a portion of the inner sidewall 24 of the N-type gate ring transistor along the thickness direction of the gate stack structure 38 is greater than the length of the remaining portion, and the length direction of the inner sidewall 24 of the N-type gate ring transistor is parallel to the length direction of the gate stack structure 38.

[0043] Specifically, when N-type gate ring transistors and P-type gate ring transistors are spaced apart along a direction parallel to the surface of the semiconductor substrate, the specific details of the inner sidewalls of the N-type gate ring transistors can be referred to the specific details of the inner sidewalls of the P-type gate ring transistors described above.

[0044] And such Figure 22 As shown in part (2), when N-type gate ring transistors and P-type gate ring transistors are spaced apart along the thickness direction parallel to the semiconductor substrate 11, if the nanostructure 35 included in the N-type gate ring transistor is manufactured with only a sacrificial layer 15 between the semiconductor substrate 11 and the bottom film layer used to manufacture the nanostructure 35, and between adjacent film layers used to manufacture the nanostructure 35, the inner sidewall 24 included in the N-type gate ring transistor has the same length in each part along the thickness direction of the gate stack structure 38. If the nanostructure included in the N-type gate ring transistor is manufactured with not only a sacrificial layer but also a germanium-containing semiconductor material layer between the semiconductor substrate and the bottom film layer used to manufacture the nanostructure, and between adjacent film layers used to manufacture the nanostructure, then the specific situation of the inner sidewall included in the N-type gate ring transistor is approximately the same as that of the inner sidewall included in the P-type gate ring transistor.

[0045] In some cases, the semiconductor device provided in the embodiments of the present invention may further include a shallow trench isolation structure and an interlayer dielectric layer. For example... Figure 3 As shown in parts (1) and (2), a shallow trench isolation structure 20 is formed on the isolation region of the semiconductor substrate 11 to isolate different active regions of the semiconductor substrate 11 and prevent leakage. Figure 22 As shown in part (1), when the N-type gate ring transistor and the P-type gate ring transistor are spaced apart along a direction parallel to the surface of the semiconductor substrate 11, the interlayer dielectric layer 28 covers the N-type gate ring transistor, the P-type gate ring transistor, and the semiconductor substrate 11, and the top of the interlayer dielectric layer 28 is flush with the top of the gate stack structure 38 included in the N-type gate ring transistor and the P-type gate ring transistor, respectively. Figure 22 As shown in section (2), when the N-type gate ring transistor and the P-type gate ring transistor are spaced apart along a direction parallel to the thickness of the semiconductor substrate 11, the interlayer dielectric layer 28 covers the semiconductor substrate 11 and the uppermost one of the N-type gate ring transistor and the P-type gate ring transistor. Furthermore, the top of the interlayer dielectric layer 28 is flush with the top of the gate stack structure 38 included in the uppermost one of the N-type gate ring transistor and the P-type gate ring transistor. The materials of the shallow trench isolation structure 20 and the interlayer dielectric layer 28 can be silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0046] Secondly, embodiments of the present invention provide a method for manufacturing a semiconductor device. The following will describe a method based on... Figures 1 to 22The perspective or cross-sectional view of the operation shown in parts (1) and (2) describes the manufacturing process. Specifically, the method for manufacturing this semiconductor device includes the following steps: First, such as Figure 18 As shown, a first preformed structure 32 and a second preformed structure 33 are formed at intervals on a semiconductor substrate 11. Both the first preformed structure 32 and the second preformed structure 33 include at least one suspended channel layer 30 and gate sidewalls 22 spanning the two edge regions along the length direction of the at least one suspended channel layer 30. The second preformed structure 33 also includes germanium-containing semiconductor layers 31 located only on both sides of each suspended channel layer 30 along its thickness direction. The germanium content in the germanium-containing semiconductor layers 31 is greater than the germanium content in the suspended channel layers 30.

[0047] Specifically, the suspended channel layer included in the first pre-formed structure is used to fabricate the nanostructure included in the N-type gate-around transistor. Therefore, the number of layers, material, and size of the suspended channel layer included in the first pre-formed structure can be determined based on the number of layers, material, and size of the nanostructure included in the N-type gate-around transistor. Furthermore, the suspended channel layer included in the second pre-formed structure is used to fabricate the nanostructure included in the P-type gate-around transistor. Specifically, the portion of the suspended channel layer included in the second pre-formed structure located below the gate sidewall is used to fabricate the connection portion in the nanostructure included in the P-type gate-around transistor, while the remaining portion of the suspended channel layer included in the second pre-formed structure is used to fabricate the channel portion in the nanostructure included in the P-type gate-around transistor. Based on this, the number of layers, size, and material of the suspended channel layer included in the first pre-formed structure can be determined based on the number of layers and size of the nanostructure included in the N-type gate-around transistor, and the material of the connection portion, respectively. For example, when all the other elements in the nanostructure of the N-type gate ring transistor and the nanostructure of the P-type gate ring transistor are the same except for germanium, the materials of at least one suspended channel layer in the first preformed structure and the second preformed structure can be the same.

[0048] Furthermore, under the masking effect of the first mask layer, the exposed portions of the germanium-containing semiconductor layer and at least one suspended channel layer included in the second pre-formed structure are subjected to a concentration oxidation process. During the concentration oxidation process, germanium in the germanium-containing semiconductor layer diffuses inward into the portion of the suspended channel layer included in the second pre-formed structure exposed outside the gate sidewall. After the concentration oxidation process, the remaining portion of the suspended channel layer included in the second pre-formed structure forms the nanostructure included in the P-type gate ring transistor. Based on this, the germanium content and thickness in the germanium-containing semiconductor layer can be determined according to the germanium content in the channel portion of the nanostructure included in the P-type gate ring transistor; no specific limitations are made here.

[0049] Secondly, in the actual manufacturing process, when the relative distribution positions of N-type gate ring transistors and P-type gate ring transistors in a semiconductor device are different, the relative distribution positions of the first pre-formed structure used to manufacture the N-type gate ring transistor and the second pre-formed structure used to manufacture the P-type gate ring transistor are also different.

[0050] Specifically, when N-type gate-around transistors and P-type gate-around transistors are spaced apart along a direction parallel to the surface of the semiconductor substrate, such as... Figure 18 As shown, the first preformed structure 32 and the second preformed structure 33 are also spaced apart along a direction parallel to the surface of the semiconductor substrate 11. When the N-type gate ring transistor and the P-type gate ring transistor are spaced apart along a thickness direction parallel to the semiconductor substrate, the first preformed structure and the second preformed structure are also spaced apart along a thickness direction parallel to the semiconductor substrate.

[0051] Furthermore, the first pre-formed structure may consist only of a suspended channel layer and a gate sidewall, and the second pre-formed structure may consist only of a suspended channel layer, a germanium-containing semiconductor layer, and a gate sidewall. Alternatively, both the first and second pre-formed structures may further include a source region and a drain region located on opposite sides of the length of at least one suspended channel layer.

[0052] For example, forming the first pre-formed structure and the second pre-formed structure with a spacing distribution on the semiconductor substrate may include the following steps: like Figure 3 As shown in parts (1) and (2), at least a first fin structure 12 and a second fin structure 13 are formed at intervals on a semiconductor substrate 11. Both the first fin structure 12 and the second fin structure 13 include at least one stack 14. Each stack 14 includes a sacrificial layer 15 and a first semiconductor material layer 16 located on the sacrificial layer 15. The first semiconductor material layer included in the second fin structure 13 includes a second semiconductor material layer 17 and germanium-containing semiconductor material layers 18 located on both sides of the second semiconductor material layer 17 along its thickness direction.

[0053] In actual manufacturing processes, when the relative distribution positions of N-type gate ring transistors and P-type gate ring transistors in semiconductor devices are different, the structures of the first fin structure used to manufacture the N-type gate ring transistor and the second fin structure used to manufacture the P-type gate ring transistor may also be different.

[0054] Specifically, when N-type gate-around transistors and P-type gate-around transistors are spaced apart along a direction parallel to the surface of the semiconductor substrate, such as... Figure 3As shown in part (1), the first fin structure 12 and the second fin structure 13 have the same structure. The first fin structure 12 includes a first semiconductor material layer, a second semiconductor material layer 17, and germanium-containing semiconductor material layers 18 located on both sides of the second semiconductor material layer 17 along the thickness direction.

[0055] For example, when N-type gate-around transistors and P-type gate-around transistors are spaced apart along a direction parallel to the surface of the semiconductor substrate 11, such as Figure 1 As shown in part (1), films stacked on the semiconductor substrate 11 and used to fabricate a sacrificial layer, a second semiconductor material layer, and a germanium-containing semiconductor material layer can be formed using processes such as epitaxy. Next, as... Figure 2 As shown in part (1), the film layers used to fabricate the sacrificial layer, the second semiconductor material layer, and the germanium-containing semiconductor material layer, as well as a portion of the semiconductor substrate 11, can be patterned using processes such as photolithography and etching to form the first fin and the second fin on the semiconductor substrate 11. Next, as... Figure 3 As shown in part (1), a shallow trench isolation structure 20 can be formed on the semiconductor substrate 11 using processes such as deposition and etching. The top of the shallow trench isolation structure 20 is less than the bottom height of the underlying sacrificial layer 15. The portions of the first fin and the second fin exposed outside the shallow trench isolation structure 20 are the first fin structure 12 and the second fin structure 13, respectively.

[0056] When N-type and P-type gate ring transistors are spaced apart along a thickness direction parallel to the semiconductor substrate, the first fin structure and the second fin structure can have the same structure. Or, as... Figure 3 As shown in part (2), the first fin structure 12 includes a first semiconductor material layer of the same material in each part, excluding the germanium-containing semiconductor material layer 18. In this case, when releasing the nanostructure 35 included in the N-type gate ring transistor, it is not necessary to remove the germanium-containing semiconductor material layer 18 included in the second fin structure 13, which simplifies the manufacturing process of the N-type gate ring transistor and improves the manufacturing efficiency of the N-type gate ring transistor.

[0057] Secondly, when N-type gate-around transistors and P-type gate-around transistors are spaced apart along a thickness direction parallel to the semiconductor substrate, such as Figure 3 As shown in part (2), the above-mentioned formation of at least a spaced first fin structure 12 and a second fin structure 13 on the semiconductor substrate 11 includes the steps of: forming at least a spaced first fin structure 12 and a second fin structure 13 on the semiconductor substrate 11, and a semiconductor isolation layer 19 located between the first fin structure 12 and the second fin structure 13.

[0058] For example, taking the first semiconductor material layer of the first fin structure as not including germanium-containing semiconductor material, and assuming that the P-type gate ring transistor is located below the N-type gate ring transistor, the following example will be used for illustration: Figure 1 As shown in part (2), epitaxy or other processes can be used to form a film layer stacked on the semiconductor substrate 11, which is used to manufacture the sacrificial layer, the second semiconductor material layer, and the germanium-containing semiconductor material layer included in the second fin structure; and a film layer for manufacturing a semiconductor isolation layer and a film layer for manufacturing the sacrificial layer and the first semiconductor material layer included in the first fin structure are sequentially formed on the currently top-layer film layer for the germanium-containing semiconductor material layer. Next, as Figure 2 As shown in section (2), the film layers used to fabricate the sacrificial layer, the second semiconductor material layer, the germanium-containing semiconductor material layer, and the semiconductor isolation layer, as well as a portion of the semiconductor substrate 11, can be patterned using processes such as photolithography and etching to form fins on the semiconductor substrate 11 along its thickness direction. Next, as... Figure 3 As shown in part (1), a shallow trench isolation structure 20 can be formed on the semiconductor substrate 11 using processes such as deposition and etching. The top of the shallow trench isolation structure 20 is lower than the bottom height of the underlying sacrificial layer 15. In the portion of the fins exposed outside the shallow trench isolation structure 20, the portion below the semiconductor isolation layer 19 is the second fin structure 13, and the portion above the semiconductor isolation layer 19 is the first fin structure 12.

[0059] After the formation of the first fin-like structure and the second fin-like structure, such as Figure 4 As shown in sections (1) and (2), a sacrificial gate 21 and a gate sidewall 22 can be sequentially formed, spanning at least across the first fin structure 12 and the second fin structure 13, using processes such as deposition and etching. The gate sidewall 22 is located at least on both sides of the sacrificial gate 21 along its length. The material of the sacrificial gate 21 can be an easily removable material such as polysilicon. The material of the gate sidewall 22 can be referred to above.

[0060] Next, as Figure 5 As shown in parts (1) and (2), dry etching or wet etching processes can be used, and at least the first fin structure and the second fin structure can be etched under the masking effect of the sacrificial gate 21 and the gate sidewall 22.

[0061] Among them, such as Figure 5 As shown in part (1), when the N-type gate ring transistors and P-type gate ring transistors are spaced apart along a direction parallel to the surface of the semiconductor substrate 11, only the first fin structure and the second fin structure can be etched under the masking effect of the sacrificial gate 21 and the gate sidewall 22. However, when the N-type gate ring transistors and P-type gate ring transistors are spaced apart along a direction parallel to the thickness of the semiconductor substrate 11, as shown in part (1), when the N-type gate ring transistors and P-type gate ring transistors are spaced apart along a direction parallel to the thickness of the semiconductor substrate 11, when the N-type gate ring transistors and P-type gate ring transistors are spaced apart ... Figure 5As shown in part (2), the first fin structure, the second fin structure and the semiconductor isolation layer 19 need to be etched by dry etching or wet etching processes under the masking effect of the sacrificial gate 21 and the gate sidewall 22.

[0062] Next, in one example, if the manufactured P-type gate-around transistor further includes inner sidewalls 24, then after etching the second fin structure and before forming the source and drain regions of the P-type gate-around transistor on both sides along the length of the remaining portion of the second fin structure, the method for manufacturing the semiconductor device further includes: Figure 6 As shown in parts (1) and (2), wet etching or dry etching processes can be used to etch the two side edge regions of the remaining portion of the sacrificial layer 15 and the two side edge regions of the remaining portion of the germanium-containing semiconductor material layer 18 of the second fin structure along the length direction of the sacrificial gate 21 to form the notch 23. Next, as... Figure 7 As shown in parts (1) and (2), processes such as deposition and etching can be used to form the inner wall 24 that fills the notch.

[0063] In one example, if the manufactured N-type gate-around transistor further includes inner sidewalls, then after etching the first fin structure and before forming the source and drain regions of the N-type gate-around transistor on both sides along the length of the remaining portion of the first fin structure, the manufacturing method of the above semiconductor device further includes: Figure 6 As shown in parts (1) and (2), wet etching or dry etching processes can be used to etch at least the two side edge regions of the remaining portion of the sacrificial layer 15 included in the first fin structure along the length direction of the sacrificial gate 21 (when the first semiconductor material layer 16 in the first fin structure also includes a germanium-containing semiconductor material layer 18, the two side edge regions of the remaining portion of the germanium-containing semiconductor material layer 18 in the first fin structure also need to be etched) to form the notch 23. Then, as... Figure 7 As shown in parts (1) and (2), processes such as deposition and etching can be used to form the inner wall 24 that fills the notch.

[0064] Next, as Figure 8 As shown in parts (1) and (2), an N-type ring gate transistor including a source region 25 and a drain region 26 is formed on both sides of the remaining portion of the first fin structure along the length direction, and a P-type ring gate transistor including a source region 25 and a drain region 26 is formed on both sides of the remaining portion of the second fin structure along the length direction.

[0065] Specifically, when N-type and P-type gate-around transistors are spaced apart along a direction parallel to the semiconductor substrate surface, the source and drain regions of the N-type gate-around transistors and the source and drain regions of the P-type gate-around transistors can be fabricated respectively under the masking effect of the corresponding mask layers. For example: First, a third mask layer is formed covering the remaining portion of the second fin structure. Then, under the masking effect of the third mask layer, the source and drain regions of the N-type gate-around transistors are formed using epitaxial growth or other processes. Next, the third mask layer is removed, and a fourth mask layer is formed covering the source and drain regions of the N-type gate-around transistors. Then, under the masking effect of the fourth mask layer, the source and drain regions of the P-type gate-around transistors are formed using epitaxial growth or other processes. Finally, the fourth mask layer is removed.

[0066] When N-type and P-type gate-around transistors are spaced apart along a thickness direction parallel to the semiconductor substrate, epitaxial growth and other processes can be used to form a material layer for fabricating the source and drain regions of the lower N-type and P-type gate-around transistors. This material layer is then etched back to form the source and drain regions of the lower N-type and P-type gate-around transistors. Next, deposition and etching processes are used to form a dielectric isolation layer. Finally, epitaxial growth and other processes are used to form the source and drain regions of the upper N-type and P-type gate-around transistors.

[0067] Next, as Figure 9 As shown in sections (1) and (2), the interlayer dielectric layer 28 of the semiconductor device can be formed by deposition and planarization processes. The thickness and material of the interlayer dielectric layer 28 can be referred to the preceding text and will not be repeated here.

[0068] Next, as Figure 10 As shown, at least the sacrificial gate and the remaining portion of the sacrificial layer are removed. The remaining portion of the second semiconductor material layer forms the suspended channel layer 30, and the remaining portion of the germanium-containing semiconductor material layer 18 forms the germanium-containing semiconductor layer 31.

[0069] In actual manufacturing processes, when N-type gate-around transistors and P-type gate-around transistors are spaced apart along a direction parallel to the semiconductor substrate surface, dry etching or wet etching processes are required to remove the sacrificial gate and any remaining portion of the sacrificial layer. Furthermore, as... Figure 12 and Figure 16 As shown, it is also necessary to remove the remaining portion of the germanium-containing semiconductor material layer 18 included in the first fin structure under the masking effect of the second mask layer 29. The second mask layer 29 covers at least the remaining portion of the germanium-containing semiconductor material layer 18 included in the second fin structure.

[0070] Specifically, when N-type gate-around transistors and P-type gate-around transistors are spaced apart along a direction parallel to the surface of the semiconductor substrate, such as... Figure 10 As shown, dry etching or wet etching processes can be used to simultaneously remove the sacrificial gate spanning the outer periphery of the first and second fin structures, as well as the remaining portion of the sacrificial layer included in the first and second fin structures. Next, as... Figure 11 and Figure 12 As shown, under the masking effect of the second mask layer 29, the remaining portion of the germanium-containing semiconductor material layer 18 included in the first fin structure is removed using processes such as dry etching or wet etching. Then, as... Figure 13 As shown, the second mask layer is removed.

[0071] Alternatively, when N-type gate-around transistors and P-type gate-around transistors are spaced apart along a direction parallel to the semiconductor substrate surface, the sacrificial gate spanning the outer periphery of the first and second fin structures can be removed simultaneously using processes such as dry etching or wet etching. Then, as... Figure 15 As shown, a second mask layer 29 is formed, covering at least the remaining portion of the second fin structure. Next, as... Figure 16 As shown, under the masking effect of the second mask layer 29, the remaining portion of the sacrificial layer and the germanium-containing semiconductor material layer included in the first fin structure is first removed. Then, as... Figure 17 As shown, remove the second mask layer. Then, as... Figure 18 As shown, the remaining portion of the sacrificial layer included in the second fin structure is removed.

[0072] When N-type gate ring transistors and P-type gate ring transistors are spaced apart along the thickness direction parallel to the semiconductor substrate, dry etching or wet etching processes can be used to remove the remaining parts of the sacrificial gate, sacrificial layer, and semiconductor isolation layer.

[0073] After the first preformed structure and the second preformed structure are formed, as Figure 14 As shown, a first mask layer 34 covering the first preformed structure 32 can be formed using processes such as deposition and etching. The material of the first mask layer 34 can be photoresist or spin-coated carbon, etc.

[0074] Specifically, when N-type gate ring transistors and P-type gate ring transistors are spaced apart along a direction parallel to the surface of the semiconductor substrate, a first mask layer can be formed using processes such as photolithography.

[0075] When N-type gate-around transistors and P-type gate-around transistors are spaced apart along a thickness direction parallel to the semiconductor substrate, if the N-type gate-around transistor is located below the P-type gate-around transistor, a mask material can be formed by deposition or other processes to fill the outer periphery of the suspended channel layer included in the first pre-formed structure and the outer periphery of the suspended channel layer and the germanium-containing semiconductor layer included in the second pre-formed structure. An etching process is then used to etch back the mask material to expose the suspended channel layer and the germanium-containing semiconductor layer included in the second pre-formed structure, thus obtaining the first mask layer. If the N-type gate-around transistor is located above the P-type gate-around transistor, a fifth mask layer can be formed by using the same method as the first mask layer to fill the outer periphery of the suspended channel layer and the germanium-containing semiconductor layer included in the second pre-formed structure. Then, a first mask layer is formed surrounding the outer periphery of the suspended channel layer included in the first pre-formed structure. The material of the fifth mask layer is different from the material of the first mask layer. Then, the fifth mask layer is removed.

[0076] Next, as Figure 19 As shown, under the masking effect of the gate sidewall 22 included in the first mask layer 34 and the second preformed structure 33, the exposed portions of the germanium-containing semiconductor layer 31 and at least one suspended channel layer included in the second preformed structure 33 are subjected to concentrated oxidation treatment.

[0077] Specifically, the conditions for the above-mentioned concentration oxidation treatment can be determined according to the actual application scenario, and are not specifically limited here. For example, in an oxygen-containing atmosphere and at an environment of 600°C to 800°C, the exposed portions of the germanium-containing semiconductor layer and the suspended channel layer included in the second pre-formed structure are subjected to concentration oxidation treatment. The treatment time can be 1 hour to 6 hours.

[0078] In this process, after the exposed portions of the germanium-containing semiconductor layer and the suspended channel layer included in the second pre-formed structure are subjected to a concentrated oxidation treatment, the remaining portion of the suspended channel layer included in the second pre-formed structure forms the nanostructure included in the P-type gate ring transistor.

[0079] Next, as Figures 20 to 22As shown in sections (1) and (2), an N-type gate-around transistor is formed based on a first pre-formed structure 32, and a P-type gate-around transistor is formed based on a second pre-formed structure 33 after concentrated oxidation treatment. The N-type and P-type gate-around transistors are spaced apart. Both the active structures of the N-type and P-type gate-around transistors have a source region 25, a drain region 26, and at least one nanostructure 35 located between the source region 25 and the drain region 26. The portion of the at least one nanostructure 35 of the P-type gate-around transistor covered by the gate stack structure 38 is the channel portion 36, and the portion of the at least one nanostructure 35 covered by the gate sidewall 22 is the connection portion 37. The germanium content in the channel portion 36 is greater than the germanium content in the connection portion 37 and the germanium content in the at least one nanostructure 35 of the N-type gate-around transistor.

[0080] Specifically, such as Figure 20 and Figure 21 As shown in parts (1) and (2), dry etching or wet etching processes can be used to remove the silicon oxide layer formed around the nanostructure 35 of the P-type gate ring transistor after concentrated oxidation treatment, and to remove the first mask layer. Next, as... Figure 22 As shown in sections (1) and (2), the gate stack structure 38 included in the formation of the N-type ring gate transistor and the gate stack structure 38 included in the P-type ring gate transistor are shown.

[0081] The gate stacking structures of the N-type gate ring transistor and the P-type gate ring transistor can be formed simultaneously or in stages. This embodiment of the invention does not impose a specific limitation on the formation order of the gate stacking structures of the N-type and P-type gate ring transistors.

[0082] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0083] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0084] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: Interleaved N-type gate ring transistors and P-type gate ring transistors; The active structure of the N-type gate ring transistor and the active structure of the P-type gate ring transistor both have a source region, a drain region, and at least one nanostructure located between the source region and the drain region. The portion of the at least one nanostructure included in the P-type gate ring transistor that is covered by the gate stack structure included in the P-type gate ring transistor is a channel portion, and the portion of the at least one nanostructure included in the P-type gate ring transistor that is covered by the gate sidewall included in the P-type gate ring transistor is a connection portion; the germanium content in the channel portion is greater than the germanium content in the connection portion and the germanium content in the at least one nanostructure included in the N-type gate ring transistor.

2. The semiconductor device according to claim 1, characterized in that, The germanium content within the channel is greater than or equal to 10% and less than or equal to 60%; and / or, The channel section is made of germanium-silicon.

3. The semiconductor device according to claim 1, characterized in that, The germanium content in the at least one layer of the nanostructure included in the connecting portion and the N-type gate ring transistor is 0.

4. The semiconductor device according to claim 1, characterized in that, The material of the connecting part is silicon or germanium-silicon; when the material of the connecting part is germanium-silicon, the germanium content in the connecting part is less than 10%; and / or, The material of the at least one nanostructure included in the N-type gate ring transistor is silicon.

5. The semiconductor device according to claim 1, characterized in that, The P-type gate-around transistor includes an inner wall located between the source region and the gate stack structure, and between the drain region and the gate stack structure; The inner wall of the P-type gate ring transistor has the same length in all portions along the thickness direction of the gate stack structure, and the length direction of the inner wall of the P-type gate ring transistor is parallel to the length direction of the gate stack structure; or, a portion of the inner wall of the P-type gate ring transistor has a longer length than the remaining portion along the thickness direction of the gate stack structure, and the length direction of the inner wall of the P-type gate ring transistor is parallel to the length direction of the gate stack structure.

6. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a semiconductor substrate; The N-type gate ring transistor and the P-type gate ring transistor are spaced apart on the semiconductor substrate along a direction parallel to the surface of the semiconductor substrate; or, the N-type gate ring transistor and the P-type gate ring transistor are spaced apart on the semiconductor substrate along the thickness direction of the semiconductor substrate.

7. A method for manufacturing a semiconductor device, characterized in that, include: A first pre-formed structure and a second pre-formed structure are formed on a semiconductor substrate at intervals; both the first pre-formed structure and the second pre-formed structure include at least one suspended channel layer and gate sidewalls spanning the two edge regions along the length direction of the at least one suspended channel layer; the second pre-formed structure also includes germanium-containing semiconductor layers located only on both sides along the thickness direction of each suspended channel layer; the germanium content in the germanium-containing semiconductor layers is greater than the germanium content in the suspended channel layers. Under the masking effect of the first mask layer and the gate sidewall included in the second pre-formed structure, the exposed portions of the germanium-containing semiconductor layer and the at least one suspended channel layer included in the second pre-formed structure are subjected to concentrated oxidation treatment; The first mask layer covers the first preformed structure; An N-type gate-ring transistor is formed based on the first pre-formed structure, and a P-type gate-ring transistor is formed based on the second pre-formed structure after the concentrated oxidation treatment; wherein... The N-type gate-around transistor and the P-type gate-around transistor are spaced apart. Both the active structures of the N-type and P-type gate-around transistors have a source region, a drain region, and at least one nanostructure located between the source and drain regions. The portion of the at least one nanostructure of the P-type gate-around transistor covered by the gate stack structure of the P-type gate-around transistor is a channel portion, and the portion of the at least one nanostructure of the P-type gate-around transistor covered by the gate sidewall of the P-type gate-around transistor is a connection portion. The germanium content in the channel portion is greater than the germanium content in the connection portion and the germanium content in the at least one nanostructure of the N-type gate-around transistor.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The first preformed structure and the second preformed structure include at least one suspended channel layer made of the same material; and / or, Both the first preformed structure and the second preformed structure further include a source region and a drain region located on both sides of the length direction of the at least one suspended channel layer.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, The first and second pre-formed structures, which are spaced apart on a semiconductor substrate, include: At least a first fin structure and a second fin structure are formed at intervals on the semiconductor substrate; both the first fin structure and the second fin structure include at least one stacked layer; each stacked layer includes a sacrificial layer and a first semiconductor material layer located on the sacrificial layer; the first semiconductor material layer included in the second fin structure includes a second semiconductor material layer and germanium-containing semiconductor material layers located on both sides of the second semiconductor material layer along the thickness direction; A sacrificial gate and a gate sidewall are sequentially formed, at least spanning the first fin structure and the second fin structure; the gate sidewall is located at least on both sides of the sacrificial gate along its length. Under the masking effect of the sacrificial gate and the gate sidewall, at least the first fin structure and the second fin structure are etched; The source and drain regions of an N-type gate ring transistor are formed on both sides of the remaining portion of the first fin structure along the length direction, and the source and drain regions of a P-type gate ring transistor are formed on both sides of the remaining portion of the second fin structure along the length direction. At least the sacrificial gate and the remaining portion of the sacrificial layer are removed; the remaining portion of the second semiconductor material layer forms a suspended channel layer, and the remaining portion of the germanium-containing semiconductor material layer forms a germanium-containing semiconductor layer.

10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The N-type gate ring transistor and the P-type gate ring transistor are spaced apart on the semiconductor substrate along a direction parallel to the surface of the semiconductor substrate; The first fin structure and the second fin structure have the same structure; the first semiconductor material layer included in the first fin structure includes a second semiconductor material layer and germanium-containing semiconductor material layers located on both sides of the second semiconductor material layer along the thickness direction; After removing the remaining portion of the sacrificial layer included in the first fin structure, before performing concentrated oxidation treatment on the germanium-containing semiconductor layer and part of the at least one suspended channel layer included in the second pre-formed structure under the masking action of the first mask layer and the gate sidewall included in the second pre-formed structure, the method for manufacturing the semiconductor device further includes: removing the remaining portion of the germanium-containing semiconductor material layer included in the first fin structure under the masking action of the second mask layer. The second mask layer covers at least the remainder of the germanium-containing semiconductor material layer included in the second fin structure.

11. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The N-type gate ring transistor and the P-type gate ring transistor are distributed at intervals on the semiconductor substrate along the thickness direction of the semiconductor substrate; The method of forming at least a spaced first fin structure and a second fin structure on the semiconductor substrate includes: forming at least a spaced first fin structure and a second fin structure on the semiconductor substrate, and a semiconductor isolation layer located between the first fin structure and the second fin structure; The step of etching at least the first fin structure and the second fin structure under the masking effect of the sacrificial gate and the gate sidewall includes: etching the first fin structure, the second fin structure and the semiconductor isolation layer under the masking effect of the sacrificial gate and the gate sidewall; The method for manufacturing the semiconductor device further includes: forming a dielectric isolation layer between the source and drain regions of the N-type gate-around transistor formed on both sides of the remaining portion of the first fin structure along the length direction, and between the source and drain regions of the P-type gate-around transistor formed on both sides of the remaining portion of the second fin structure along the length direction; the dielectric isolation layer is used to isolate the source and drain regions of the N-type gate-around transistor from the source and drain regions of the P-type gate-around transistor.

12. The method for manufacturing a semiconductor device according to claim 9, characterized in that, After etching the second fin structure under the masking action of the sacrificial gate and the gate sidewall, and before forming the source and drain regions of the P-type ring gate transistor on both sides along the length direction of the remaining portion of the second fin structure, the method for manufacturing the semiconductor device further includes: Along the length direction of the sacrificial gate, the two side edge regions of the remaining portion of the sacrificial layer of the second fin structure and the two side edge regions of the remaining portion of the germanium-containing semiconductor material layer are etched to form a notch; An inner wall is formed that fills the recess.

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