High-voltage ldmos

Abstract

The application discloses a high-voltage LDMOS, comprising: in a plan view, one or more U-shaped structures in a partial region of the high-voltage LDMOS, at a U-shaped end of the U-shaped structure, a drift region is in a U shape, an inner side of the drift region is close to a source region, and an outer side is close to a drain region; and a high voltage of a drain region is wrapped around the source region at the U-shaped end. An electric field dispersion structure is arranged at the U-shaped end, comprising one or more doped strips of a second conductive type formed at a bottom of the drift region, the doped strips are grounded, the doped strips extend from the source region to the drain region, an electric field generated by the high voltage of the drain region is dispersed into the doped strips, and the electric field lines are changed from two-dimensional concentration to three-dimensional dispersion, so that the electric field generated by the high voltage of the drain region is prevented from being concentrated on the source region, and the electric field dispersion is realized. The application can have a plan view structure of the U-shaped structure to increase the current of the device, meanwhile, the defects of electric field concentration caused by the U-shaped structure are avoided, and the breakdown voltage of the device is improved.

Description

Technical Field

[0001] This invention relates to a semiconductor integrated circuit, and more particularly to a high-voltage LDMOS. Background Technology

[0002] In a half-bridge driver circuit, a high-voltage isolation ring (HV-ring) is used to integrate the high-voltage and low-voltage circuits onto the same chip. Typically, the high-voltage power supply needs to withstand voltages of 600V or higher. High-voltage LDMOS transistors are generally used for isolation between the high-voltage and low-voltage circuits, forming a high-voltage isolation ring. This high-voltage LDMOS transistors are usually wrapped around the high-voltage circuit area. Some high-voltage devices, such as those between high-voltage LDMOS transistors or between high-voltage LDMOS transistors and devices in the high-voltage circuit, require isolation using doped rings, such as P-type rings. Within the high-voltage isolation ring, some high-voltage LDMOS transistors function as level shifters, while others function as boost diodes. The operating voltage of the LDMOS transistors used for level shifting is usually lower than that of the devices in the high-voltage circuit area, hence the need for a P-type ring for isolation. A P-type ring is also used for isolation between the level shifter and the boost diode.

[0003] A boost diode raises the voltage of a capacitor; the higher the current of the boost diode, the faster the charging speed. To increase the current of the boost diode, a U-shaped high-voltage LDMOS is typically added to one side of the high-voltage isolation ring surrounding the high-voltage circuit as the boost diode.

[0004] like Figure 1 The diagram shown is a schematic of the P-type ring structure between high-voltage devices in an existing high-voltage isolation ring. Figure 2A This is a top view of the existing high-voltage isolation ring structure; Figure 2B yes Figure 2A Enlarged view of the U-shaped end; Figure 2C yes Figure 2A Corresponding real map; Figure 3A It is along Figure 2A Schematic diagram of the cross-sectional structure of line AA in the middle; Figure 3B It is along Figure 2B A cross-sectional view of the DD line; the existing high-voltage isolation ring is composed of high-voltage LDMOS and is isolated between high-voltage circuit 3 and low-voltage circuit 2.

[0005] The high-voltage circuit 3 and the voltage circuit 2 are in Figure 2A It was marked, but the specific structure was not described.

[0006] The operating voltage of the high-voltage circuit 3 is greater than that of the low-voltage circuit 2, and the operating voltage of the high-voltage LDMOS is also greater than that of the low-voltage circuit 2.

[0007] A P-type ring 108 is provided to isolate the high-voltage LDMOS between them or between the high-voltage LDMOS and the devices of the high-voltage circuit 3.

[0008] Please refer directly to the structure of the P-ring 108. Figure 1 As shown, an N-type doped first epitaxial layer 104 is formed on a semiconductor substrate 101.

[0009] Figure 1 The image shows region 102 and regions 103a and 103b on either side. Region 102 is the formation region of the P-ring 108, and regions 103a and 103b are the formation regions of two high-voltage devices that need to be isolated, such as the high-voltage LDMOS or the devices in the high-voltage circuit 3. Figure 1 The specific structures in regions 103a and 103b are omitted, and only the doped region 110 with N-type heavy doping and the field oxygen 111 in regions 103a and 103b are shown.

[0010] The P-type ring 108 includes a second buried layer 105, a second doped layer 106, and a second well region 107 stacked sequentially, wherein the second doped layer 106 connects the second well region 107 and the second buried layer 105.

[0011] The second buried layer 105 is formed in a selected region between the semiconductor substrate 101 and the first epitaxial layer 104.

[0012] The second doped layer 106 and the second well region 107 are both formed in the first epitaxial layer 104.

[0013] The top of the second well region 107 is covered with a first field oxygen 111b. The first field oxygen 111b has the same structure as the field oxygen 111, except that the field oxygen of the second well region 107 is marked separately with the label 111b.

[0014] An N-type doped buried layer 109 is also formed in a selected region between the semiconductor substrate 101 and the first epitaxial layer 104 on both sides of the P-type ring 108.

[0015] To explain this clearly, the following will be combined with... Figure 2A The territory and Figure 3A To further illustrate, a cross-sectional structural diagram is provided:

[0016] like Figure 2AAs shown, the high-voltage circuit 3 is located inside the high-voltage isolation ring. From a top view, the high-voltage isolation ring has a ring-shaped structure. Figure 2A As shown, the high-voltage LDMOS is located in the dashed box 202. It can be seen that the high-voltage LDMOS will surround the high-voltage circuit 3, thereby forming the high-voltage isolation ring.

[0017] Typically, the high-voltage LDMOS in certain regions constitutes a level-shifting device. Figure 2A In the area shown by the dashed box 201, the high-voltage LDMOS is used as the voltage level. Figure 3A The cross-section along line AA at dashed frame 201 shows the same high-voltage LDMOS structure as the cross-section along line BB at dashed frame 202, but the P-ring 108 is provided around the high-voltage LDMOS at dashed frame 201. Figure 1 compared to, Figure 3A The high-voltage device in region 103a is specifically described as the high-voltage LDMOS, which serves as the level-changing device. Figure 2A In this configuration, a portion of the high-voltage LDMOS acts as a boost diode. For example, all high-voltage LDMOS outside the level converter function as boost diodes, or a portion of them function as boost diodes. To increase the current of the boost diode, a U-shaped structure is also provided outside the surrounding structure of the high-voltage LDMOS. The U-shaped end of the U-shaped structure corresponds to... Figure 2A The area shown in dashed box 204 is the same as the high-voltage LDMOS along line BB at dashed box 203 in dashed box 204. Since the top view includes the multi-layer structure of the device, further details are provided for a clearer description of the device structure. Figure 2A The structure of the metal layer is omitted, while Figure 2B The metal layer structure is shown separately in the middle. Figure 2B This is a schematic diagram of the metal layer structure in the area shown in the dashed box 204. Figure 2C That is Figure 2A The corresponding real map Figure 2C The outline of some of the figures can be seen, because Figure 2C It includes multiple layers of superimposed graphics, therefore Figure 2C Only the clearly distinguishable parts of the graphics are marked. For example... Figure 3A As shown, please also refer to the top view structure. Figure 2A As shown, the high-voltage LDMOS includes:

[0018] An N-type heavily doped drain region 6 is formed in the surface region of the first epitaxial layer 104, and the drain region 6 is located on the side close to the high voltage circuit 3.

[0019] The first well region 5, which is P-type doped, is located near the side of the low-voltage circuit 2.

[0020] The drift region of the high-voltage LDMOS is composed of the first epitaxial layer 104 located between the first well region 5 and the drain region 6. Figure 2A In the dashed box 201, the drift region of the high-voltage LDMOS, which serves as the level conversion device, is represented by a separate label 4, while the drift region of the high-voltage LDMOS outside the dashed box 201 is represented by a separate label 1.

[0021] A drift region field oxygen 111a is formed on the surface of the drift region of the high-voltage LDMOS.

[0022] The gate structure covers the surface of the first well region 5 and the second side of the gate structure extends onto the drift region field oxygen 111a.

[0023] The N-type heavily doped source region 7 is formed on the surface of the first well region 5 and is self-aligned with the second side of the gate structure.

[0024] A P-ring 108 is provided around the level converter to achieve isolation between the level converter and the high-voltage LDMOS and the high-voltage circuit 3 outside the level converter.

[0025] In top view, the P-ring 108 includes a first side and a second side extending along the direction from the drain region 6 to the source region 7 of the level conversion device. A first end of the first side and a first end of the second side are both connected to the first well region 5. Please refer to the top view structure of the P-ring 108. Figure 2A As shown, Figure 2A Only the second well region 107 at the top of the P-ring 108 is shown.

[0026] The third side of the P-ring 108 is close to the side of the high-voltage circuit 3, and the second end of the first side and the second end of the second side are both connected to the third side.

[0027] A third buried layer 105a with P-type doping is formed in the bottom region of the first well region 5, and the third buried layer 105a and the first well region 5 are connected by a second buried layer 106a with P-type doping.

[0028] Typically, the gate structure is formed by stacking a gate dielectric layer (not shown) and a polysilicon gate 10. The gate dielectric layer includes a gate oxide layer.

[0029] A first polysilicon field plate 10a is also formed on the drift region field oxygen 111a. The first polysilicon field plate 10a is close to the drain region 6, and there is a gap between the first side of the first polysilicon field plate 10a and the second side of the polysilicon gate 10.

[0030] In a selected region of the first well region 5, an N-type third well region 8 is also formed, the junction depth of the third well region 8 being less than the junction depth of the first well region 5, and the source region 7 is formed in the third well region 8.

[0031] A P-type heavily doped bulk contact region 9 is also formed in a selected region of the first well region 5.

[0032] The drain area 6 is connected to the drain electrode 13a, which is composed of a front metal layer, through a contact hole 12 at the top that passes through the interlayer membrane 11.

[0033] The top of the polysilicon gate 10 is connected to the gate 13c, which is composed of a front metal layer, through a contact hole 12.

[0034] The source region 7 is connected to the source electrode 13b, which is composed of a front metal layer, through the contact hole 12 at the top.

[0035] The body contact area 9 is connected to the body electrode 13d, which is composed of a front metal layer, through the contact hole 12 at the top.

[0036] The first polycrystalline silicon field plate 10a is connected to the drain electrode 13a through the contact hole 12 at the top.

[0037] like Figure 2B As shown, at the U-shaped end, the drain 13a surrounds the head of the source 13b. In this way, the electric field generated by the high voltage of the drain 13a will converge to the head of the source 13b. The convergence of the electric field can easily reduce the breakdown voltage of the device.

[0038] like Figure 3B As shown, it is along Figure 2B A cross-sectional view of the DD line shows that at the U-shaped end, the drain 13a covers the drift region of the high-voltage LDMOS corresponding to the bottom mark 1. Summary of the Invention

[0039] The technical problem to be solved by the present invention is to provide a high-voltage LDMOS that has a U-shaped top view structure to increase the current of the device, while avoiding the defects of electric field concentration caused by the U-shaped structure and improving the breakdown voltage of the device.

[0040] To solve the above-mentioned technical problems, the high-voltage LDMOS provided by the present invention includes:

[0041] A heavily doped drain region of the first conductivity type is formed in the surface region of the first epitaxial layer, which is formed on a semiconductor substrate and has the first conductivity type doping.

[0042] The first well region is doped with the second conductivity type.

[0043] The drift region is composed of the first epitaxial layer located between the first well region and the drain region.

[0044] Drift region field oxygen is formed on the surface of the drift region of the high-voltage LDMOS.

[0045] A gate structure covers the surface of the first well region and a second side of the gate structure extends onto the drift region field oxygen; the gate structure is composed of a gate dielectric layer and a polysilicon gate stacked together.

[0046] A heavily doped source region of the first conductivity type is formed on the surface of the first well region and is self-aligned with the second side of the gate structure.

[0047] The drain area is connected to the drain electrode, which is composed of a front metal layer, through a contact hole at the top.

[0048] The top of the polysilicon gate is connected to the gate, which is composed of a front metal layer, through a contact hole.

[0049] The source region is connected to the source electrode, which is composed of a front metal layer, through a contact hole at the top.

[0050] On the top view, a portion of the high-voltage LDMOS has one or more U-shaped structures. At the U-shaped end of the U-shaped structure, the drift region is U-shaped. The inner side of the drift region is located near the source region, and the outer side of the drift region is near the drain region. The drain electrode is pressed inward to cover the source electrode at the U-shaped end.

[0051] An electric field dispersion structure is provided at the U-shaped end. This structure includes one or more doped strips of a second conductivity type formed at the bottom of the drift region. These doped strips are grounded and extend from the source to the drain. The electric field generated by the high voltage at the drain is dispersed into the doped strips, changing the electric field lines at the U-shaped end from a two-dimensional distribution concentrated towards the source to a three-dimensional dispersed distribution. This effectively prevents the electric field generated by the high voltage at the drain from concentrating at the source, thus achieving electric field dispersion.

[0052] A further improvement is that the doped strip is formed by superimposing a first buried layer and a first doped layer doped with a second conductivity type.

[0053] The first buried layer is formed in a selected region between the semiconductor substrate and the first epitaxial layer.

[0054] The first doped layer is located in the bottom region of the first epitaxial layer on top of the first buried layer.

[0055] A further improvement is that the electric field dispersion structure consists of a single doped strip that extends from the inner vertex to the outer vertex of the drift region.

[0056] A further improvement is that the high-voltage LDMOS surrounds the high-voltage circuit and serves as a high-voltage isolation ring, while the low-voltage circuit is located outside the high-voltage isolation ring. The high-voltage isolation ring achieves isolation between the high-voltage circuit and the low-voltage circuit.

[0057] The operating voltage of the high-voltage circuit is greater than that of the low-voltage circuit, and the operating voltage of the high-voltage LDMOS is also greater than that of the low-voltage circuit.

[0058] A second conductivity type ring is used to isolate the high-voltage LDMOS between them or between the high-voltage LDMOS and the devices in the high-voltage circuit.

[0059] The second conductivity type ring includes a second buried layer, a second doped layer, and a second well region that are stacked sequentially with the second conductivity type doped. The second doped layer connects the second well region and the second buried layer.

[0060] The second buried layer is formed in a selected region between the semiconductor substrate and the first epitaxial layer.

[0061] Both the second doped layer and the second well region are formed in the first epitaxial layer.

[0062] A further improvement is that, on a top view, the high-voltage isolation ring includes an annular structure that surrounds the high-voltage circuit and has multiple sides, with the U-shaped structure provided on one or more sides of the annular structure.

[0063] The high-voltage LDMOS at the U-shaped structure serves as a boost diode, and the U-shaped structure is used to increase the current of the boost diode.

[0064] A further improvement is that the high-voltage circuit is located inside the ring structure.

[0065] A further improvement is that a third buried layer doped with a second conductivity type is formed in the bottom region of the first well region, and the third buried layer and the first well region are connected by the third doped layer doped with a second conductivity type.

[0066] A further improvement is that the first well region and the second well region have the same process structure and are formed simultaneously.

[0067] The first, second, and third buried layers have the same process structure and are formed simultaneously.

[0068] The first doped layer, the second doped layer, and the third doped layer have the same process structure and are formed simultaneously.

[0069] A further improvement is that a first polysilicon field plate is formed on the drift region field oxygen, the first polysilicon field plate being close to the drain region, and a gap being formed between the first side of the first polysilicon field plate and the second side of the polysilicon gate.

[0070] A further improvement is that the gate dielectric layer includes a gate oxide layer.

[0071] A further improvement is that a third well region of a first conductivity type is formed in a selected region of the first well region, the junction depth of the third well region being less than the junction depth of the first well region, and the source region being formed in the third well region.

[0072] A bulk contact region heavily doped with a second conductivity type is also formed in a selected region of the first well region.

[0073] A further improvement is that the body contact area is connected to the body electrode, which is composed of a front metal layer, through a contact hole at the top.

[0074] A further improvement is that, at the U-shaped end, the first buried layer of the doped strip and the third buried layer at the bottom of the source region are connected, the first doped layer and the third doped layer at the bottom of the source region are connected, and the doped strip is grounded through the body electrode.

[0075] A further improvement is that the first polycrystalline silicon field plate is connected to the drain electrode through a contact hole at the top.

[0076] A further improvement is that the top of the second trap region is covered with the first field oxygen.

[0077] A further improvement is that the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type and the second conductivity type is N-type.

[0078] This invention sets the top view structure of a portion of a high-voltage LDMOS as one or more U-shaped structures. The U-shaped structure increases the channel width, thereby increasing the device current. However, at the end of the U-shaped structure, the high-voltage drain covers the inner source, so the electric field tends to concentrate at the head of the source. This invention solves this problem by setting a doped strip of a second conductivity type at the bottom of the drift region at the U-shaped end and grounding the doped strip. The doped strip crosses the drift region from the bottom of the source to the bottom of the drain. In this way, the electric field generated by the high voltage of the drain is dispersed into the doped strip, and the electric field lines change from two-dimensional concentration to three-dimensional dispersion, thereby achieving electric field dispersion. Therefore, this invention can also avoid the defects of electric field concentration caused by the U-shaped structure and improve the breakdown voltage of the device.

[0079] The high-voltage LDMOS of this invention can be well applied in high-voltage isolation rings. By adopting a U-shaped high-voltage LDMOS, the current of the boost diode in the high-voltage isolation ring can be increased. At the same time, the first buried layer of the doped strip at the U-shaped end can be formed simultaneously with the third buried layer at the source region and the second buried layer of the second conductivity type ring. Similarly, the first doped layer can also be formed simultaneously with the second and third doped layers with the same process structure. Moreover, the grounding of the doped strip can be directly achieved through contact with the third buried layer and the third doped layer. Therefore, the embodiments of this invention only require changes to the layout, and the process is simple and low-cost. Attached Figure Description

[0080] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0081] Figure 1 This is a schematic diagram of the structure of the P-type ring between high-voltage devices in an existing high-voltage isolation ring;

[0082] Figure 2A This is a top view of the existing high-voltage isolation ring structure;

[0083] Figure 2B yes Figure 2A Enlarged view of the U-shaped end;

[0084] Figure 2C yes Figure 2A The corresponding map;

[0085] Figure 3A It is along Figure 2A Schematic diagram of the cross-sectional structure of line AA in the middle;

[0086] Figure 3B It is along Figure 2B Schematic diagram of the cross-sectional structure of the DD line;

[0087] Figure 4A This is a top view structural diagram of the high-voltage isolation ring according to an embodiment of the present invention;

[0088] Figure 4B yes Figure 4A Enlarged view of the U-shaped end;

[0089] Figure 4C yes Figure 4A The corresponding map;

[0090] Figure 5 It is along Figure 4B A schematic diagram of the cross-sectional structure of the DD line. Detailed Implementation

[0091] Please also refer to the high-voltage LDMOS embodiment of this invention. Figure 3A As shown, the high-voltage LDMOS in this embodiment of the invention includes:

[0092] A heavily doped drain region 6 of the first conductivity type is formed in the surface region of the first epitaxial layer 104, which is formed on the semiconductor substrate 101 and has the first conductivity type doping.

[0093] The first well region 5 is doped with the second conductivity type.

[0094] In some embodiments, a third buried layer 105a doped with a second conductivity type is formed in the bottom region of the first well region 5, and the third buried layer 105a and the first well region 5 are connected by a third doped layer 106a doped with a second conductivity type.

[0095] The drift region is composed of the first epitaxial layer 104 located between the first well region 5 and the drain region 6. Figure 3A In this context, the drift region is also represented by the symbol 4.

[0096] Drift region field oxide 111a is formed on the surface of the drift region of the high voltage LDMOS.

[0097] A gate structure covers the surface of the first well region 5 and the second side of the gate structure extends onto the drift region field oxygen 111a; the gate structure is formed by stacking a gate dielectric layer (not shown) and a polysilicon gate 10.

[0098] In some embodiments, a first polysilicon field plate 10a is also formed on the drift region field oxygen 111a, the first polysilicon field plate 10a is close to the drain region 6, and there is a gap between the first side of the first polysilicon field plate 10a and the second side of the polysilicon gate 10.

[0099] The gate dielectric layer includes a gate oxide layer.

[0100] A source region 7, heavily doped with a first conductivity type, is formed on the surface of the first well region 5 and is self-aligned with the second side of the gate structure.

[0101] In some embodiments, a third well region 8 of a first conductivity type is further formed in a selected region of the first well region 5, the junction depth of the third well region 8 being less than the junction depth of the first well region 5, and the source region 7 being formed in the third well region 8.

[0102] A bulk contact region 9 of a second conductivity type is also formed in a selected region of the first well region 5.

[0103] The drain area 6 is connected to the drain electrode 13a, which is composed of a front metal layer, through the contact hole 12 at the top.

[0104] The top of the polysilicon gate 10 is connected to the gate 13c, which is composed of a front metal layer, through a contact hole 12.

[0105] The source region 7 is connected to the source electrode 13b, which is composed of a front metal layer, through the contact hole 12 at the top.

[0106] The first polycrystalline silicon field plate 10a is connected to the drain electrode 13a through the contact hole 12 at the top.

[0107] The body contact area 9 is connected to the body electrode 13d, which is composed of a front metal layer, through the contact hole 12 at the top.

[0108] like Figure 4A The area shown in the dashed box 204 and Figure 4B As shown, Figure 4A In the dashed box 201, the drift region of the high-voltage LDMOS, which serves as the level conversion device, is separately indicated by the symbol 4. The drift region of the high-voltage LDMOS outside the dashed box 201 is separately indicated by the symbol 1. On the top view, a portion of the high-voltage LDMOS has more than one U-shaped structure. At the U-shaped end of the U-shaped structure, the drift region is U-shaped. The inner side of the drift region is located near the source region 7, and the outer side of the drift region is near the drain region 6. The drain 13a wraps around the source 13b inward at the U-shaped end.

[0109] An electric field dispersion structure is provided at the U-shaped end. The electric field dispersion structure includes one or more doped strips 301 of the second conductivity type formed at the bottom of the drift region. The doped strips 301 are grounded and extend from the source 13b to the drain 13a. The electric field generated by the high voltage of the drain 13a is dispersed into the doped strips 301, so that the electric field lines at the U-shaped end change from a two-dimensional distribution structure concentrated towards the source 13b to a three-dimensional dispersion distribution structure. Thus, the doped strips 301 prevent the electric field generated by the high voltage of the drain 13a from being concentrated at the source 13b, thereby achieving electric field dispersion.

[0110] In embodiments of the present invention, such as Figure 5 As shown, it is along Figure 4B A schematic diagram of the cross-sectional structure of the DD line. The doped strip 301 is formed by stacking a first buried layer 105b and a first doped layer 106b doped with a second conductivity type.

[0111] The first buried layer 105b is formed in a selected region between the semiconductor substrate 101 and the first epitaxial layer 104. Figure 5 In the diagram, the drift region formed by the first epitaxial layer 104 is marked separately with label 1.

[0112] The first doped layer 106b is located in the bottom region of the first epitaxial layer 104, which is above the first buried layer 105b.

[0113] In some embodiments, the electric field dispersion structure consists of a doped strip 301 that extends from the inner vertex to the outer vertex of the drift region. Figure 4B Only one doped strip 301 is shown in the image. Multiple doped strips may be provided in other embodiments.

[0114] Depend on Figure 5 As shown, the electric field generated by the high voltage of the drain 13a will be dispersed onto the doped strip 301. Figure 5 Arrow 302 in the diagram indicates electric field dispersion. This reduces the convergence of the electric field formed at the drain 13a towards the source 13b.

[0115] In this embodiment of the invention, the high-voltage LDMOS surrounds the periphery of the high-voltage circuit 3 and serves as a high-voltage isolation ring. The low-voltage circuit is located outside the high-voltage isolation ring, and the high-voltage isolation ring achieves isolation between the high-voltage circuit 3 and the low-voltage circuit. Figure 4A The diagram shown is a top view of the high-voltage isolation ring according to an embodiment of the present invention. Figure 4B yes Figure 4A Enlarged view of the U-shaped end; Figure 4C yes Figure 4A The corresponding map;

[0116] The operating voltage of the high-voltage circuit 3 is greater than that of the low-voltage circuit, and the operating voltage of the high-voltage LDMOS is also greater than that of the low-voltage circuit.

[0117] A second conductivity type ring 108 is provided to isolate the high-voltage LDMOS devices between them or between the high-voltage LDMOS devices and the devices in the high-voltage circuit 3. The structure of the second conductivity type ring 108 is also described in [reference needed]. Figure 1 As shown, a first epitaxial layer 104 doped with a first conductivity type is formed on a semiconductor substrate 101. Figure 1The image shows region 102 and two adjacent regions 103a and 103b. Region 102 is the formation region of the second conductivity type ring 108, and regions 103a and 103b are the formation regions of two high-voltage devices that need to be isolated, such as the high-voltage LDMOS or the devices in the high-voltage circuit 3. Figure 2A The specific structures in regions 103a and 103b are omitted, and only the doped region 110 and field oxygen 111 with heavy doping of the first conductivity type in regions 103a and 103b are shown.

[0118] The second conductivity type ring 108 includes a second buried layer 105, a second doped layer 106, and a second well region 107 that are stacked sequentially with the second conductivity type doped. The second doped layer 106 connects the second well region 107 and the second buried layer 105.

[0119] The second buried layer 105 is formed in a selected region between the semiconductor substrate 101 and the first epitaxial layer 104.

[0120] The second doped layer 106 and the second well region 107 are both formed in the first epitaxial layer 104.

[0121] The top of the second well region 107 is covered with a first field oxygen 111b. The first field oxygen 111b has the same structure as the field oxygen 111, except that the field oxygen of the second well region 107 is marked separately with the label 111b.

[0122] A first conductivity type doped buried layer 109 is also formed in a selected region between the semiconductor substrate 101 and the first epitaxial layer 104 on both sides of the second conductivity type ring 108.

[0123] In this embodiment of the invention, the first well region 5 and the second well region 107 have the same process structure and are formed simultaneously.

[0124] The first buried layer 105b, the second buried layer 105, and the third buried layer 105a have the same process structure and are formed simultaneously.

[0125] The first doped layer 106b, the second doped layer 106, and the third doped layer 106a have the same process structure and are formed simultaneously.

[0126] In some preferred embodiments, at the U-shaped end, the first buried layer 105b of the doped strip 301 is connected to the third buried layer 105a at the bottom of the source region 7, the first doped layer 106b is connected to the third doped layer 106a at the bottom of the source region 7, and the doped strip 301 is grounded through the body electrode 13d.

[0127] In this embodiment of the invention, a portion of the high-voltage LDMOS forms a level-switching device. Figure 4A In the area shown in dashed box 201, the high-voltage LDMOS serves as the level-changing device. Figure 3A The cross-section along line AA at dashed frame 201 shows the same high-voltage LDMOS structure as the cross-section along line BB at dashed frame 202. However, a second conductivity type ring 108 is provided around the high-voltage LDMOS at dashed frame 201. Figure 3A As shown, the second conductivity type ring 108 surrounds the periphery of the high-voltage LDMOS, which serves as a level-shifting device. Figure 1 compared to, Figure 3A The high-voltage device in region 103a is specifically described as the high-voltage LDMOS, which serves as the level-changing device.

[0128] In this embodiment of the invention, from a top view, the high-voltage isolation ring includes an annular structure, which surrounds the high-voltage circuit and has multiple sides. The U-shaped structure is provided on one or more sides of the annular structure.

[0129] Depend on Figure 4A and Figure 4C As shown, the interior of the annular structure is the region where the high-voltage circuit 3 is formed, and a U-shaped structure is formed on one side of the annular structure. The high-voltage LDMOS at the U-shaped structure serves as a boost diode, and the U-shaped structure is used to increase the current of the boost diode.

[0130] In this embodiment of the invention, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type can also be P-type and the second conductivity type can be N-type.

[0131] In this embodiment of the invention, the top view structure of a portion of the high-voltage LDMOS is configured as one or more U-shaped structures. The U-shaped structure can increase the channel width, thereby increasing the device current. However, at the end of the U-shaped structure, the high-voltage drain 13a will cover the inner source 13b, so the electric field is easily concentrated at the head of the source 13b. In this embodiment of the invention, a doped strip 301 of the second conductivity type is set at the bottom of the drift region at the U-shaped end and the doped strip 301 is grounded. The doped strip 301 will cross the drift region from the bottom of the source 13b to the bottom of the drain 13a. In this way, the electric field generated by the high voltage of the drain 13a will be dispersed into the doped strip 301, thereby achieving electric field dispersion. Therefore, this embodiment of the invention can also avoid the defect of electric field concentration caused by the U-shaped structure and improve the breakdown voltage of the device.

[0132] The high-voltage LDMOS of this invention can be well applied in high-voltage isolation rings. By adopting a U-shaped high-voltage LDMOS, the current of the boost diode in the high-voltage isolation ring can be increased. At the same time, the first buried layer 105b of the doped strip 301 at the U-shaped end can be formed simultaneously with the third buried layer 105a at the source region 7 and the second buried layer 105 of the second conductivity type ring 108. Similarly, the first doped layer 106b can also be formed simultaneously with the second doped layer 106 and the third doped layer 106a. Moreover, the grounding of the doped strip can be directly achieved through contact with the third buried layer 105a and the third doped layer 106a. Therefore, this invention can be implemented by only modifying the layout, which is simple and low-cost.

[0133] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A high-voltage LDMOS, characterized in that, include: A drain region heavily doped with a first conductivity type is formed in the surface region of a first epitaxial layer, the first epitaxial layer being formed on a semiconductor substrate and having a first conductivity type doping; The first well region is doped with a second conductivity type; The drift region is composed of the first epitaxial layer located between the first well region and the drain region; Drift region field oxygen is formed on the surface of the drift region of the high-voltage LDMOS; A gate structure covers the surface of the first well region and a second side of the gate structure extends onto the field oxygen of the drift region; the gate structure is composed of a gate dielectric layer and a polysilicon gate stacked together. A source region heavily doped with a first conductivity type is formed on the surface of the first well region and is self-aligned with the first side of the gate structure. The drain area is connected to the drain electrode, which is composed of a front metal layer, through a contact hole at the top; The top of the polysilicon gate is connected to the gate composed of a front metal layer through a contact hole; The source region is connected to the source electrode, which is composed of a front metal layer, through a contact hole at the top; On the top view, a portion of the high-voltage LDMOS has one or more U-shaped structures. At the U-shaped end of the U-shaped structure, the drift region is U-shaped. The inner side of the drift region is located near the source region, and the outer side of the drift region is near the drain region. The drain electrode wraps around the source electrode inward at the U-shaped end. An electric field dispersion structure is provided at the U-shaped end. The electric field dispersion structure includes one or more doped strips of a second conductivity type formed at the bottom of the drift region. The doped strips are grounded and extend from the source to the drain side. The electric field generated by the high voltage of the drain is dispersed into the doped strips, so that the electric field lines at the U-shaped end change from a two-dimensional distribution structure concentrated towards the source to a three-dimensional dispersion distribution structure, thereby avoiding the electric field generated by the high voltage of the drain from concentrating at the source and thus achieving electric field dispersion.

2. The high-voltage LDMOS as described in claim 1, characterized in that: The doped strip is formed by superimposing a first buried layer and a first doped layer doped with a second conductivity type; The first buried layer is formed in a selected region between the semiconductor substrate and the first epitaxial layer; The first doped layer is located in the bottom region of the first epitaxial layer on top of the first buried layer.

3. The high-voltage LDMOS as described in claim 2, characterized in that: The electric field dispersion structure consists of a doped strip that extends from the inner vertex to the outer vertex of the drift region.

4. The high-voltage LDMOS as described in claim 2, characterized in that: The high-voltage LDMOS is surrounded by the high-voltage circuit and serves as a high-voltage isolation ring. The low-voltage circuit is located outside the high-voltage isolation ring, and the high-voltage isolation ring achieves isolation between the high-voltage circuit and the low-voltage circuit. The operating voltage of the high-voltage circuit is greater than that of the low-voltage circuit, and the operating voltage of the high-voltage LDMOS is also greater than that of the low-voltage circuit. A second conductivity type ring is provided to isolate the high-voltage LDMOS between them or between the high-voltage LDMOS and the devices in the high-voltage circuit; The second conductivity type ring includes a second buried layer, a second doped layer, and a second well region that are sequentially stacked with the second conductivity type doped. The second doped layer connects the second well region and the second buried layer. The second buried layer is formed in a selected region between the semiconductor substrate and the first epitaxial layer; Both the second doped layer and the second well region are formed in the first epitaxial layer.

5. The high-voltage LDMOS as described in claim 4, characterized in that: From a top view, the high-voltage isolation ring includes a ring structure that surrounds the high-voltage circuit and has multiple sides, with the U-shaped structure provided on one or more sides of the ring structure. The high-voltage LDMOS at the U-shaped structure serves as a boost diode, and the U-shaped structure is used to increase the current of the boost diode.

6. The high-voltage LDMOS as described in claim 5, characterized in that: The high-voltage circuit is located inside the ring structure.

7. The high-voltage LDMOS as described in claim 4, characterized in that: A third buried layer of the second conductivity type is formed in the bottom region of the first well region, and the third buried layer and the first well region are connected by the third doped layer of the second conductivity type.

8. The high-voltage LDMOS as described in claim 7, characterized in that: The first well region and the second well region have the same process structure and are formed simultaneously; The first buried layer, the second buried layer, and the third buried layer have the same process structure and are formed simultaneously; The first doped layer, the second doped layer, and the third doped layer have the same process structure and are formed simultaneously.

9. The high-voltage LDMOS as described in claim 1, characterized in that: A first polysilicon field plate is also formed on the field oxygen in the drift region. The first polysilicon field plate is close to the drain region, and there is a gap between the first side of the first polysilicon field plate and the second side of the polysilicon gate.

10. The high-voltage LDMOS as described in claim 1, characterized in that: The gate dielectric layer includes a gate oxide layer.

11. The high-voltage LDMOS as described in claim 8, characterized in that: A third well region of a first conductivity type is also formed in a selected region of the first well region, the junction depth of the third well region is smaller than the junction depth of the first well region, and the source region is formed in the third well region; A bulk contact region heavily doped with a second conductivity type is also formed in a selected region of the first well region.

12. The high-voltage LDMOS as described in claim 11, characterized in that: The body contact area is connected to the body electrode, which is composed of a front metal layer, through a contact hole at the top.

13. The high-voltage LDMOS as described in claim 12, characterized in that: At the U-shaped end, the first buried layer of the doped strip and the third buried layer at the bottom of the source region are connected, the first doped layer and the third doped layer at the bottom of the source region are connected, and the doped strip is grounded through the body electrode.

14. The high-voltage LDMOS as described in claim 9, characterized in that: The first polycrystalline silicon field plate is connected to the drain electrode through a contact hole at the top.

15. The high-voltage LDMOS according to any one of claims 1-14, characterized in that: The first conductivity type is N-type, and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.

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