Method for improving continuity of ultra-thin metal floating gate

Abstract

This invention provides a method for improving the continuity of ultrathin metal floating gates. The semiconductor structure includes multiple trenches, and a tunneling oxide layer is deposited to cover the surface of the trenches. A first ALD SiN layer, a floating gate TiN layer, and a first ALD oxide layer are sequentially deposited on the tunneling oxide layer. A memory region is defined by photolithography. The first ALD oxide layer and the floating gate TiN layer are removed from the non-memory region. The first ALD oxide layer on the memory region and the floating gate TiN layer outside the trench sidewalls of the memory region are removed. A second ALD SiN layer, a second ALD oxide layer, and a silicon nitride layer are sequentially deposited on the semiconductor structure. The silicon nitride layer, the second ALD oxide layer, the second ALD SiN layer, the first ALD SiN layer, and the tunneling oxide layer on the upper surface of the semiconductor structure and the bottom of the trenches are removed, exposing the bottom of the trenches and the surface of the semiconductor structure. From a process integration perspective, this method facilitates compatibility with existing processes and is easy to implement in terms of process technology.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for improving the continuity of ultrathin metal floating gates. Background Technology

[0002] Current processes use vertical TiN as the floating gate material, and horizontal electric field-guided write operations and voltage-coupled erase operations at the tip TIN can greatly improve write and erase efficiency. However, using TiN metal as the floating gate structure can easily cause TiN discontinuity problems after subsequent high-temperature process steps, which will have an adverse effect on the storage of the entire circuit. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for improving the continuity of ultrathin metal floating gates, so as to solve the problem of poor circuit storage caused by the discontinuity of floating gate materials in the prior art.

[0004] To achieve the above and other related objectives, the present invention provides a method for improving the continuity of ultrathin metal floating gates, comprising at least:

[0005] Step 1: Provide a semiconductor structure, the semiconductor structure including a plurality of grooves, a polycrystalline silicon structure disposed between the plurality of grooves, and an oxide covering the polycrystalline silicon structure filling the grooves;

[0006] Step 2: Deposit a tunneling oxide layer to cover the surface of the groove and the surface of the oxide;

[0007] Step 3: Deposit the first ALD SiN layer on the tunneling oxide layer;

[0008] Step 4: Deposit a floating gate TiN layer on the first ALD SiN layer;

[0009] Step 5: Deposit the first ALD oxide layer on the floating gate TiN layer;

[0010] Step 6: Photolithography defines the storage area, which is covered by photoresist, while the photoresist on the non-storage area is removed;

[0011] Step 7: Remove the first ALD oxide layer and the floating gate TiN layer on the non-memory area;

[0012] Step 8: Remove the first ALD oxide layer on the storage area and the floating gate TiN layer outside the groove sidewall of the storage area;

[0013] Step 9: Deposit a second ALD SiN layer on the semiconductor structure;

[0014] Step 10: Deposit a second ALD oxide layer on the second ALD SiN layer;

[0015] Step 11: Deposit a silicon nitride layer on the second ALD oxide layer;

[0016] Step 12: Remove the silicon nitride layer, second ALD oxide layer, second ALD SiN layer, first ALD SiN layer and tunneling oxide layer from the upper surface of the oxide layer and the bottom of the trench of the semiconductor structure, exposing the bottom of the trench and the oxide surface of the semiconductor structure.

[0017] Preferably, rapid annealing is performed after depositing the tunneling oxide layer in step two.

[0018] Preferably, the thickness of the first ALD SiN layer in step three is

[0019] Preferably, in step three, the first ALD SiN layer is deposited by atomic layer deposition.

[0020] Preferably, in step four, the floating gate TiN layer is deposited using PVD, and the thickness of the floating gate TiN layer is [missing information].

[0021] Preferably, the thickness of the first ALD oxide layer in step five is The first ALD oxide layer is used as a mask layer for photolithography.

[0022] Preferably, in step eight, the first ALD oxide layer on the storage region is removed by dry etching, and the floating gate TiN layer outside the recess sidewall of the storage region is removed by wet etching.

[0023] Preferably, the thickness of the second ALD SiN layer in step nine is

[0024] Preferably, the thickness of the second ALD oxide layer in step ten is

[0025] Preferably, the thickness of the silicon nitride layer in step eleven is

[0026] As described above, the method for improving the continuity of ultrathin metal floating gates of the present invention has the following beneficial effects: The method of the present invention deposits a layer of silicon nitride before depositing TiN for the metal floating gate, then deposits TiN for the metal floating gate by PVD, and deposits another layer of silicon nitride after depositing TiN for the metal floating gate. The uniformity and continuity of the ultrathin metal floating gate after high-temperature processing is improved by protecting it with SiN on both sides. Finally, the TiN and SiN in the non-storage area are removed by an additional dry process step without affecting the existing process. From the perspective of process integration, this method is easy to achieve compatibility with existing processes and is easy to implement in the process. Attached Figure Description

[0027] Figures 1 to 6 The diagram shows the structural schematics of each process stage of the method for improving the continuity of ultrathin metal floating grids in this invention.

[0028] Figure 7 The diagram shown is a flowchart of the method for improving the continuity of ultrathin metal floating grids according to the present invention. Detailed Implementation

[0029] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0030] Please see Figures 1 to 7 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0031] This invention provides a method for improving the continuity of ultrathin metal floating gates, such as... Figure 7 As shown, the method includes at least the following steps:

[0032] Step 1: Provide a semiconductor structure, the semiconductor structure including a plurality of grooves, a polycrystalline silicon structure disposed between the plurality of grooves, and an oxide covering the polycrystalline silicon structure filling the grooves;

[0033] like Figure 1 As shown, step one provides a semiconductor structure, which includes a plurality of grooves 01, a polycrystalline silicon structure 02 between the plurality of grooves 01, and an oxide 03 covering the polycrystalline silicon structure filling the grooves 01.

[0034] Step 2: Deposit a tunneling oxide layer to cover the surface of the groove and the surface of the oxide;

[0035] In a further step of this invention, in step two of this embodiment, the tunneling oxide layer is deposited followed by rapid annealing. For example... Figure 1 As shown, in step two, a tunneling oxide layer 04 is deposited to cover the surface of the groove and the surface of the oxide.

[0036] Step 3: Deposit a first ALD SiN layer on the tunneling oxide layer; as shown in the figure. Figure 1 As shown, in step three, a first ALD SiN layer 05 is deposited on the tunneling oxide layer 04.

[0037] Furthermore, in step three of this embodiment, the thickness of the first ALD SiN layer is...

[0038] In a further step of this embodiment, the first ALD SiN layer is deposited by atomic layer deposition.

[0039] Step 4: Deposit a floating gate TiN layer on the first ALD SiN layer; as shown Figure 1 As shown, step four involves depositing a floating gate TiN layer 06 on the first ALD SiN layer 05.

[0040] In a further step of this invention, in step four of this embodiment, the floating gate TiN layer is deposited using PVD, and the thickness of the floating gate TiN layer is [missing information].

[0041] Step 5: Deposit a first ALD oxide layer on the floating gate TiN layer; as shown Figure 1 As shown, in step five, a first ALD oxide layer 07 is deposited on the floating gate TiN layer 06.

[0042] Furthermore, in step five of this embodiment, the thickness of the first ALD oxide layer is... The first ALD oxide layer is used as a mask layer for photolithography.

[0043] Step Six: Photolithography defines the memory area, which is covered by photoresist, while the photoresist on the non-memory areas is removed; as shown... Figure 2 As shown, step six involves photolithography to define a memory cell, which is covered by photoresist (08), while the photoresist on the non-memory cell is removed. The semiconductor structure also includes P-wells and N-wells located at the boundary between the memory cell and the non-memory cell, and a source contact region (SL strap) and a word line contact region (WL strap) are provided on the silicon substrate of the non-memory cell.

[0044] Step 7: Remove the first ALD oxide layer and the floating gate TiN layer on the non-memory area; as shown Figure 3 As shown, in step seven, the first ALD oxide layer 07 and the floating gate TiN layer 06 on the non-memory area are removed, exposing the first ALD SiN layer 05 on the non-memory area.

[0045] Step 8: Remove the first ALD oxide layer on the storage area and the floating gate TiN layer outside the groove sidewall of the storage area;

[0046] In a further embodiment of the present invention, in step eight, the first ALD oxide layer on the storage region is removed by dry etching, and the floating gate TiN layer outside the groove sidewall of the storage region is removed by wet etching.

[0047] like Figure 4 As shown, step eight removes the first ALD oxide layer on the storage area and the floating gate TiN layer other than the groove sidewall of the storage area, leaving only the floating gate TiN layer O6 on the groove sidewall of the storage area.

[0048] Step 9: Deposit a second ALD SiN layer on the semiconductor structure; as shown Figure 5 As shown, step nine involves depositing a second ALD SiN layer 09 on the semiconductor structure.

[0049] Furthermore, in step nine of this embodiment, the thickness of the second ALD SiN layer is...

[0050] Step 10: Deposit a second ALD oxide layer on the second ALD SiN layer; as shown Figure 5 As shown, in step ten, a second ALD oxide layer 10 is deposited on the second ALD SiN layer 09.

[0051] Furthermore, in step ten of this embodiment, the thickness of the second ALD oxide layer is...

[0052] Step 11: Deposit a silicon nitride layer on the second ALD oxide layer; as shown in the figure. Figure 5 As shown, a silicon nitride layer 11 is deposited on the second ALD oxide layer 10.

[0053] Furthermore, in this embodiment, the thickness of the silicon nitride layer in step eleven is...

[0054] Step 12: Remove the silicon nitride layer, second ALD oxide layer, second ALD SiN layer, first ALD SiN layer, and tunneling oxide layer from the upper surface of the oxide layer and the bottom of the trench of the semiconductor structure, exposing the bottom of the trench and the oxide surface of the semiconductor structure. Figure 6 As shown, step 12 removes the silicon nitride layer 11, the second ALD oxide layer 10, the second ALD SiN layer 09, the first ALD SiN layer 05, and the tunneling oxide layer 01 from the upper surface of the oxide 03 of the semiconductor structure and the bottom of the trench, exposing the bottom of the trench and the oxide surface of the semiconductor structure.

[0055] In summary, the method of this invention involves depositing a layer of silicon nitride before depositing the TiN metal floating gate, followed by PVD deposition of the TiN metal floating gate, and then depositing another layer of silicon nitride after the TiN metal floating gate deposition. Double-sided SiN protection enhances the uniformity and continuity of the ultra-thin metal floating gate after high-temperature processing. Finally, an additional dry process step removes the TiN and SiN in non-memory regions without affecting existing processes. From a process integration perspective, this method facilitates compatibility with existing processes and is easy to implement. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0056] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving the continuity of ultrathin metal floating gates, characterized in that, At least including: Step 1: Provide a semiconductor structure, the semiconductor structure including a plurality of grooves, a polycrystalline silicon structure disposed between the plurality of grooves, and an oxide covering the polycrystalline silicon structure filling the grooves; Step 2: Deposit a tunneling oxide layer to cover the surface of the groove and the surface of the oxide; Step 3: Deposit the first ALD SiN layer on the tunneling oxide layer; Step 4: Deposit a floating gate TiN layer on the first ALD SiN layer; Step 5: Deposit the first ALD oxide layer on the floating gate TiN layer; Step 6: Photolithography defines the storage area, which is covered by photoresist, while the photoresist on the non-storage area is removed; Step 7: Remove the first ALD oxide layer and the floating gate TiN layer on the non-memory area; Step 8: Remove the first ALD oxide layer on the storage area and the floating gate TiN layer outside the groove sidewall of the storage area; Step 9: Deposit a second ALD SiN layer on the semiconductor structure; Step 10: Deposit a second ALD oxide layer on the second ALD SiN layer; Step 11: Deposit a silicon nitride layer on the second ALD oxide layer; Step 12: Remove the silicon nitride layer, second ALD oxide layer, second ALD SiN layer, first ALD SiN layer and tunneling oxide layer from the upper surface of the oxide layer and the bottom of the groove of the semiconductor structure, exposing the bottom of the groove and the oxide surface of the semiconductor structure.

2. The method for improving the continuity of ultrathin metal floating gates according to claim 1, characterized in that: In step two, the tunneling oxide layer is deposited and then rapidly annealed.

3. The method for improving the continuity of ultrathin metal floating grids according to claim 1, characterized in that: The thickness of the first ALD SiN layer in step three is 4. The method for improving the continuity of ultrathin metal floating grids according to claim 1, characterized in that: In step three, the first ALD SiN layer is deposited using atomic layer deposition.

5. The method for improving the continuity of ultrathin metal floating grids according to claim 1, characterized in that: In step four, the floating gate TiN layer is deposited using PVD, and the thickness of the floating gate TiN layer is [missing information].

6. The method for improving the continuity of ultrathin metal floating gates according to claim 1, characterized in that: The thickness of the first ALD oxide layer in step five is The first ALD oxide layer is used as a mask layer for photolithography.

7. The method for improving the continuity of ultrathin metal floating gates according to claim 1, characterized in that: In step eight, the first ALD oxide layer on the storage region is removed by dry etching, and the floating gate TiN layer outside the recess sidewall of the storage region is removed by wet etching.

8. The method for improving the continuity of ultrathin metal floating gates according to claim 1, characterized in that: The thickness of the second ALD SiN layer in step nine is 9. The method for improving the continuity of ultrathin metal floating gates according to claim 1, characterized in that: The thickness of the second ALD oxide layer in step ten is 10. The method for improving the continuity of ultrathin metal floating gates according to claim 1, characterized in that: The thickness of the silicon nitride layer in step eleven is

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