Wafer integrated with ldmos device

Abstract

The application discloses a wafer integrated with LDMOS devices, which comprises a substrate and a plurality of cell devices formed on the substrate, the plurality of cell devices are arranged in an array, and each cell device comprises: a gate formed above the substrate, a gate dielectric layer is formed between the gate and the substrate, and the gate is annular; an STI structure is formed in the substrate and below the gate, the STI structure is annular, the STI structure is located in an area surrounded by the gate, and the STI structure and the gate have an overlapping area; a first heavily doped region is formed in the substrate in an area surrounded by the STI structure, at least one second heavily doped region is formed in the substrate on the side of the gate, a third heavily doped region is formed in the second heavily doped region, the gate is electrically connected with the gate of an adjacent cell device through the second heavily doped region, and the number of the second heavily doped regions is the same as the number of the adjacent cell devices; wherein the first heavily doped region and the second heavily doped region are doped with a first type of impurities, and the third heavily doped region is doped with a second type of impurities.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit technology, and specifically to a wafer integrating an LDMOS device. Background Technology

[0002] Double-diffused metal-oxide-semiconductor field-effect transistors (DMOSFETs, referred to as "DMOS" in this application) are widely used in power management circuits due to their high voltage resistance, high current drive capability, and extremely low power consumption.

[0003] There are two main types of DMOS: vertical double-diffused metal-oxide-semiconductor field-effect transistor (VDMOSFET, which can be simply referred to as "VDMOS") and lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET, which can be simply referred to as "LDMOS" in this application). Among them, LDMOS devices are widely used in power transistors.

[0004] For LDMOS devices, reducing their specific on-resistance (on-resistance × active area (AA) area) has become the main development direction for medium and high voltage devices while meeting the withstand voltage requirements. In related technologies, LDMOS devices typically employ a strip layout, where the active area is arranged in rows or columns of long strips. However, with this strip layout, the specific on-resistance of LDMOS devices cannot be effectively improved, and the chip area cannot be utilized efficiently, thus hindering the improvement of the device's electrical performance. Summary of the Invention

[0005] This application provides a wafer integrating LDMOS devices, which solves the problem in related technologies where the LDMOS device-integrated wafers are arranged in rows or columns, making it difficult to improve their electrical performance. The wafer includes a substrate and a plurality of LDMOS devices formed on the substrate. Viewed from a top angle, the plurality of LDMOS devices are arranged in an array. For any given LDMOS device, it includes:

[0006] A gate is formed above the substrate, and a gate dielectric layer is formed between the gate and the substrate. When viewed from a top view, the gate is ring-shaped.

[0007] An STI structure is formed in the substrate and located below the gate. When viewed from a top view, the STI structure is ring-shaped and located in the region surrounded by the gate. The STI structure and the gate have overlapping regions.

[0008] A first heavily doped region is formed in the substrate within the region surrounded by the STI structure. At least one second heavily doped region is formed in the substrate on the periphery of the gate. A third heavily doped region is formed in the second heavily doped region. The gate is electrically connected to the gate of an adjacent cell device through the second heavily doped region. The number of the second heavily doped regions is the same as the number of adjacent cell devices.

[0009] The first and second heavily doped regions are doped with impurities of the first type, and the third heavily doped region is doped with impurities of the second type. The first type of impurities and the second type of impurities are impurities with different conductivity types.

[0010] In some embodiments, a first doped region is formed in the substrate below the gate, and a second doped region is formed in the substrate around the gate, the second doped region encompassing the second heavily doped region and the third heavily doped region;

[0011] Wherein, the first doped region is doped with a first type of impurity, the second doped region is doped with a second type of impurity, and the impurity concentration in the first heavily doped region, the second heavily doped region, and the third heavily doped region is greater than the impurity concentration in the first doped region and the second doped region.

[0012] In some embodiments, the substrate is doped with a second type of impurity, and the impurity concentration in the substrate is less than the impurity concentration in the first heavily doped region, the second heavily doped region, and the third heavily doped region.

[0013] In some embodiments, when the LDMOS device is in operation, the first heavily doped region is the drain of the LDMOS device, the second heavily doped region is the body region of the LDMOS device, and the third heavily doped region is the source of the LDMOS device.

[0014] In some embodiments, when the LDMOS device is operating, the first doped region is a drift region and the second doped region is a well region.

[0015] In some embodiments, a DTI structure is also formed in the substrate. Viewed from top, the DTI structure is ring-shaped, surrounds a cell device, and is used to isolate the active region of each cell device.

[0016] In some embodiments, when viewed from a top view, the gate is annular, square, rectangular, elliptical, circular, or polygonal.

[0017] The technical solution of this application has at least the following advantages:

[0018] By arranging the cell devices of an LDMOS device in an array on a substrate, and placing the first heavily doped region (drain) at the center of the ring gate and the second heavily doped region (source) on the periphery of the gate, a multi-directional current is formed between the drain and source, resulting in a more uniform power dissipation distribution. This leads to better heat dissipation performance and improved reliability and stability of the device. Simultaneously, the width of the STI structure determines the voltage rating of the device. The overlapping area between the gate and the STI structure serves as the field plate of the device, and its width directly affects the electric field distribution. Therefore, the size of the field plate can be defined according to different voltage rating requirements, thereby improving the applicability of the LDMOS device. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 This is a top view of a wafer integrating an LDMOS device provided in an exemplary embodiment of this application;

[0021] Figure 2 This is a cross-sectional schematic diagram of an LDMOS device provided in an exemplary embodiment of this application. Detailed Implementation

[0022] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0024] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal connection between two components; and they can refer to wireless connections or wired connections. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0025] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0026] refer to Figure 1 It shows a top view of a wafer integrating LDMOS devices according to an exemplary embodiment of this application; Reference Figure 2 It shows a schematic cross-sectional view of an LDMOS device provided in an exemplary embodiment of this application. The schematic cross-sectional view is along... Figure 1 A cross-sectional view along the AA' direction.

[0027] For example, such as Figure 1 and Figure 2 As shown, the wafer includes a substrate 110 and a plurality of cell devices formed on the substrate 110. Viewed from a top angle, the plurality of cell devices are arranged in an array. For any cell device, it includes:

[0028] A gate 130 is formed above a substrate 110, and a gate dielectric layer 120 is formed between the gate 130 and the substrate 110. When viewed from a top view, the gate 130 is ring-shaped.

[0029] A shallow trench isolation (STI) structure 111 is formed in the substrate 110 and located below the gate 130. When viewed from above, the STI structure 111 is annular. The STI structure 111 is located in the region surrounded by the gate 130 and has an overlapping region 131 with the gate 130.

[0030] In the substrate 110, a first heavily doped region 141 is formed in the region surrounded by the STI structure 111. At least one second heavily doped region 142 is formed in the substrate 110 on the periphery of the gate 130. A third heavily doped region 143 is formed in the second heavily doped region 142. The gate 130 is electrically connected to the gate 130 of the adjacent cell device through the second heavily doped region 142. The number of second heavily doped regions 142 is the same as the number of adjacent cell devices.

[0031] For example, such as Figure 1 As shown, the cell device located in the top left corner has two adjacent cell devices. Therefore, two second heavily doped regions 142 are formed in the substrate 110 surrounding its gate 130. Its gate 130 is electrically connected to the gates 130 of its adjacent cell devices through the two second heavily doped regions 142. In addition, as Figure 1 As shown, the cell device located in the central region has four adjacent cell devices. Therefore, four second heavily doped regions 142 are formed in the substrate 110 around the gate 130. The gate 130 is electrically connected to the gate 130 of the adjacent cell devices through the four second heavily doped regions 142. Since a large number of cell devices are integrated on the wafer, it is more common to form four second heavily doped regions 142 in the substrate 110 around the gate 130.

[0032] The first doped region 141 and the second doped region 142 are doped with impurities of type 1, and the third doped region 143 is doped with impurities of type 2. The impurities of type 1 and type 2 are impurities with different conductivity types. When the impurity of type 1 is an N (negative) type impurity, the impurity of type 2 is a P (positive) type impurity; when the impurity of type 1 is a P type impurity, the impurity of type 2 is an N type impurity.

[0033] In some embodiments, such as Figure 1 and Figure 2 As shown, a first doped region 101 is formed in the substrate 110 below the gate 130, and a second doped region 102 is formed in the substrate 110 around the gate 130. The second doped region 102 encloses the second heavily doped region 142 and the third heavily doped region 143.

[0034] In this design, the first doped region 101 is doped with a first type of impurity, the second doped region 102 is doped with a second type of impurity, and the substrate 110 is doped with a second type of impurity. The impurity concentrations in the first heavily doped region 141, the second heavily doped region 142, and the third heavily doped region 143 are greater than the impurity concentrations in the first doped region 101, the second doped region 102, and the substrate 110. When the LDMOS device is operating, the first heavily doped region 141 is the drain of the LDMOS device, the second heavily doped region 142 is the body region of the LDMOS device, and the third heavily doped region 143 is the source region of the LDMOS device. The first doped region 101 is the drifting region, and the second doped region 102 is the well region.

[0035] In some embodiments, such as Figure 1 As shown, a DTI structure 112 is also formed in the substrate 110. Viewed from a top angle, the DTI structure 112 is ring-shaped. The DTI structure 112 surrounds a cell device and is used to isolate the active area of ​​each cell device.

[0036] In this embodiment of the application, viewed from a top-down angle, the gate 130 can be annular, square, rectangular, elliptical, circular, or polygonal. Figure 1 The circular square is used as an example for illustration.

[0037] In summary, in this embodiment, by arranging the cell devices of the LDMOS device in an array on the substrate, and placing the first heavily doped region, which serves as the drain, at the center of the ring gate, and the second heavily doped region, which serves as the source, at the periphery of the gate, a multi-directional current is formed between the drain and the source. This results in a more uniform power dissipation distribution, thereby improving the device's heat dissipation performance and enhancing its reliability and stability. Simultaneously, the width of the STI structure determines the device's voltage rating. The overlapping area between the gate and the STI structure can serve as the device's field plate, and its width directly affects the electric field distribution. Therefore, the size of the field plate can be defined according to different device voltage requirements, thereby improving the applicability of the LDMOS device.

[0038] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A wafer integrating LDMOS devices, characterized in that, The wafer includes a substrate and a plurality of cellular devices formed on the substrate. Viewed from a top angle, the plurality of cellular devices are arranged in an array. For any given cellular device, it includes: A gate is formed above the substrate, and a gate dielectric layer is formed between the gate and the substrate. When viewed from a top view, the gate is ring-shaped. An STI structure is formed in the substrate and located below the gate. When viewed from a top view, the STI structure is ring-shaped and located in the region surrounded by the gate. The STI structure and the gate have overlapping regions. A first heavily doped region is formed in the substrate within the region surrounded by the STI structure. At least one second heavily doped region is formed in the substrate on the periphery of the gate. A third heavily doped region is formed in the second heavily doped region. The gate is electrically connected to the gate of an adjacent cell device through the second heavily doped region. The number of the second heavily doped regions is the same as the number of adjacent cell devices. The first and second heavily doped regions are doped with impurities of the first type, and the third heavily doped region is doped with impurities of the second type. The first type of impurities and the second type of impurities are impurities with different conductivity types.

2. The wafer according to claim 1, characterized in that, A first doped region is formed in the substrate below the gate, and a second doped region is formed in the substrate around the gate, the second doped region encompassing the second heavily doped region and the third heavily doped region; Wherein, the first doped region is doped with a first type of impurity, the second doped region is doped with a second type of impurity, and the impurity concentration in the first heavily doped region, the second heavily doped region, and the third heavily doped region is greater than the impurity concentration in the first doped region and the second doped region.

3. The wafer according to claim 2, characterized in that, The substrate is doped with a second type of impurity, and the impurity concentration in the substrate is less than the impurity concentration in the first heavily doped region, the second heavily doped region, and the third heavily doped region.

4. The wafer according to claim 3, characterized in that, When the LDMOS device is working, the first heavily doped region is the drain of the LDMOS device, the second heavily doped region is the body region of the LDMOS device, and the third heavily doped region is the source of the LDMOS device.

5. The wafer according to claim 4, characterized in that, When the LDMOS device is working, the first doped region is the drift region and the second doped region is the well region.

6. The wafer according to any one of claims 1 to 5, characterized in that, A DTI structure is also formed in the substrate. Viewed from above, the DTI structure is ring-shaped, surrounds a cell device, and is used to isolate the active region of each cell device.

7. The wafer according to claim 6, characterized in that, Viewed from above, the gate is a ring-shaped square, rectangle, ellipse, circle, or polygon.

Images