Vcsel chip with high uniformity light power, lidar and preparation method thereof

Abstract

The application belongs to the technical field of semiconductor, and particularly relates to a VCSEL chip with high uniformity of light power, which comprises a plurality of VCSEL light-emitting areas, each of which has a plurality of light-emitting points; each of the VCSEL light-emitting areas is provided with a first electrode structure and a second electrode structure matched with the first electrode structure, wherein the VCSEL light-emitting areas are divided into a plurality of light-on areas, wherein the plurality of light-on areas at least comprise a first light-on area and a second light-on area adjacent to the first light-on area; the first electrode structure comprises a first electrode layer and a second electrode layer, wherein the first electrode layer and the second electrode layer are connected in parallel; the first electrode layer is connected to at least the first light-on area, and the second electrode layer is connected to the second light-on area.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a VCSEL chip with high uniformity optical power. Background Technology

[0002] A VCSEL (Vertical-Cavity Surface-Emitting Laser) is a semiconductor laser that emits laser light in a direction perpendicular to the substrate. VCSELs feature small divergence angle, beam symmetry, high wavelength thermal stability, stable beam quality, single longitudinal mode output, high photoelectric conversion efficiency, small size, low threshold current, low power consumption, and ease of integration. They are suitable for widespread application as a light source, for example, as a laser source for lidar.

[0003] Laser radar (LiDAR) is a device that uses laser light to detect the position, velocity, and other characteristics of a target object. Specifically, LiDAR detects the relative position of the target object and the LiDAR by emitting a laser beam towards the target object and receiving the reflected signal, thereby enabling the detection, tracking, and identification of the target object. For example, using Time-of-Flight (TOF) technology, a laser pulse is emitted towards a target area in a very short time. A detector receives the laser pulse reflected back from obstacles within the target area. The time difference between half the emitted pulse and the received pulse, multiplied by the speed of light, gives the distance between the obstacle and the LiDAR.

[0004] In recent years, LiDAR has been widely used in intelligent transportation, environmental monitoring, military security, and other fields. For example, LiDAR can be applied to new technologies such as autonomous driving, driver assistance, and active braking, enabling vehicles to automatically avoid obstacles under computer control to ensure driving safety. Correspondingly, LiDAR can also enable obstacle avoidance for unmanned aerial vehicles (UAVs). LiDAR uses a VCSEL light source as its laser source. Benefiting from the excellent light output performance of the VCSEL, its detection capability is effectively enhanced. Furthermore, LiDAR can use the VCSEL light source to scan the target object in sections step by step. Compared to scanning the target object by rotating the VCSEL light source with a rotating motor, this improves scanning stability and simplifies the subsequent 3D modeling.

[0005] One-dimensional addressable VCSELs used in pure solid-state lidar emitting components traditionally have relatively long channels to increase the scanning range and angle of a single channel. However, longer channels also result in longer channel metal electrodes and excessive parasitic inductance. This leads to uneven current distribution when the VCSEL chip is lit, resulting in uneven optical power of the light-emitting apertures at different positions within a single channel (typically, the light-emitting apertures closer to the bond pad have higher optical power, while those farther from the bond pad have lower optical power). Summary of the Invention

[0006] One advantage of this application is that it provides a VCSEL chip with high uniformity optical power, wherein the traditional single-layer metal electrode is replaced with a multi-layer stacked electrode, which reduces the parasitic inductance of the metal electrode and allows the current to be evenly distributed, thus forming the advantage of a highly uniform addressable VCSEL chip.

[0007] Another advantage of this application is that it provides a VCSEL chip with high uniformity of optical power, wherein the total current is input by a single-sided bondpad (i.e., the part where the first electrode layer and the second electrode layer are connected in parallel), and the current is shunted through multiple metal electrode layers, which is equivalent to connecting the parasitic inductance of the multiple metal electrode layers in parallel, so that the total inductance is reduced and the VCSEL chip lit by the first electrode structure has better light emission uniformity.

[0008] Another advantage of this application is that it provides a VCSEL chip with high uniformity of optical power, wherein the total current is input from both sides. Because the current directions are opposite, the inductance of the first electrode layer and the inductance of the second electrode layer can be partially canceled, reducing the total inductance effect and improving the uniformity of light emission of the VCSEL chip.

[0009] To achieve at least one of the aforementioned advantages or other advantages and objectives, according to one aspect of this application, a VCSEL chip with high uniform optical power is provided, comprising multiple VCSEL light-emitting regions. Each of the VCSEL light-emitting regions is provided with a first electrode structure and a second electrode structure that cooperates with the first electrode structure, wherein, The VCSEL light-emitting region is divided into multiple illuminated areas, wherein each illuminated area includes at least one light-emitting point; the multiple illuminated areas include at least a first illuminated area and a second illuminated area adjacent to the first illuminated area; the first electrode structure includes a first electrode layer and a second electrode layer, wherein... The first electrode layer and the second electrode layer are connected in parallel; The first electrode layer is connected to at least the first illuminated area, and the second electrode layer is connected to the second illuminated area.

[0010] In the VCSEL chip with high uniform optical power according to this application, the first electrode layer is connected to both the first illuminated area and the second illuminated area, and the second electrode layer is connected to the second illuminated area.

[0011] In the VCSEL chip with high uniformity optical power according to this application, the flow direction of the current entering the first electrode layer is the same as the flow direction of the current entering the second electrode layer.

[0012] In the VCSEL chip with high uniformity optical power according to this application, the flow direction of the current entering the first electrode layer is opposite to the flow direction of the current entering the second electrode layer.

[0013] In the VCSEL chip with high uniform optical power according to this application, the first electrode layer is located below the second electrode layer.

[0014] In the VCSEL chip with high uniform optical power according to this application, the VCSEL light-emitting region includes, from bottom to top, a substrate layer, a first Bragg mirror, an active region, a confinement layer with oxide holes, and a second Bragg mirror, wherein the second electrode structure is in ohmic contact with the substrate layer.

[0015] In the high uniformity optical power VCSEL chip according to this application, an insulating layer 106 is provided on the second Bragg reflector, and the first electrode layer and the second electrode layer partially pass through the insulating layer 106 and contact the second Bragg reflector.

[0016] In the VCSEL chip with high uniform optical power according to this application, the insulating layer 106 is one of the light-transmitting silicon dioxide, silicon nitride, hafnium dioxide, and aluminum oxide.

[0017] In the VCSEL chip with high uniform optical power according to this application, the first electrode layer and the second electrode layer are connected in parallel through a plurality of spaced conductor layers.

[0018] In the VCSEL chip with high uniformity optical power according to this application, the first electrode structure material is one or more of platinum, gold, silver, copper, and aluminum.

[0019] According to another aspect of this application, a lidar is provided, comprising: A laser projection device for projecting laser light, wherein the laser projection device comprises any of the high uniformity optical power VCSEL chips described above; A laser receiving device for receiving laser signals; and A processor communicatively connected to the laser projection device and the laser receiving device.

[0020] The further objectives and advantages of this application will become fully apparent from the following description and accompanying drawings.

[0021] According to another aspect of this application, a method for fabricating a VCSEL chip with high uniformity optical power is proposed, comprising: S1. Epitaxial growth; S2. On the epitaxial waferPhotoresist is applied and the metal anode (P-Metal) pattern of the VCSEL is defined to form the required anode (P-Metal) range. The photoresist is then removed completely, and an insulating layer is deposited to protect the surface of the device. S3. High-temperature oxidation forms oxide pores with confined pores; Photoresist is applied and the Mesa pattern is defined. Subsequent etching of areas not protected by photoresist requires an etching depth deeper than the oxide layer. The photoresist is then completely removed. After water oxidation, the high-aluminum-concentration AlGaAs layer forms an oxide layer. S4. Formation After the oxide layer is deposited, an insulating layer is deposited to protect the component surface; photoresist is applied and the pattern of the openings is defined, then the silicon nitride protective layer above the metal anode is etched away to expose the metal anode of the VCSEL. The photoresist is then completely removed. Thus, the first through hole is obtained. ; S5. The process involves applying photoresist and defining the pattern of the anode metal layer for the final VCSEL. Gold electroplating is then used to form the desired anode metal layer for the VCSEL. The photoresist is then completely removed. Forming the first electrode layer ; S6. Repeat steps S4 to S5. Deposit an insulating layer, define and etch to form a second via and a second electrode. layer; S7. Repeat steps S4 to S5. Depositing an insulating layer, defining and etching to form a third via and a third electrode. layer; S8. Photoresist is applied to protect the front side of the wafer. The wafer is then ground to the required thickness using a grinding process. Next, the cathode metal layer is deposited. Finally, the photoresist on the front side is completely removed. Forming a second electrode structure on the crystal back .

[0022] These and other objects, features and advantages of this application are fully apparent from the following detailed description, the accompanying drawings and the claims. Attached Figure Description

[0023] Figure 1 This is a schematic diagram showing the first electrode layer, second electrode layer, and third electrode layer of the VCSEL chip with high uniformity optical power according to this application, corresponding to the first illuminated area, the second illuminated area, and the third illuminated area, respectively.

[0024] Figure 2 for Figure 1 The first electrode layer, second electrode layer, and third electrode layer of the VCSEL chip with high uniformity optical power of this application are cross-sectional schematic diagrams along the AA line corresponding to the first illuminated area, the second illuminated area, and the third illuminated area, respectively.

[0025] Figure 3 for Figure 1 The first electrode layer, second electrode layer, and third electrode layer of the VCSEL chip with high uniformity optical power of this application are cross-sectional schematic diagrams of the BB lines corresponding to the first illuminated area, the second illuminated area, and the third illuminated area, respectively.

[0026] Figure 4 This is a schematic diagram of the first electrode layer of the VCSEL chip with high uniform optical power of this application, which simultaneously connects to the first illuminated area, the second illuminated area and the third illuminated area, and shares the same metal layer.

[0027] Figure 5 This is a CC-line cross-sectional view of the first electrode layer of the VCSEL chip with high uniform optical power of this application, which simultaneously connects the first illuminated area, the second illuminated area, and the third illuminated area, and shares the same metal layer.

[0028] Figure 6 This is a DD-line cross-sectional view of the first electrode layer of the VCSEL chip with high uniform optical power of this application, which simultaneously connects the first illuminated area, the second illuminated area and the third illuminated area, and shares the same metal layer.

[0029] Figure 7 This is a schematic diagram of the first electrode layer of the VCSEL chip with high uniform optical power of this application, which is simultaneously connected to the first illuminated area, the second illuminated area and the third illuminated area, wherein the second illuminated area uses a single metal layer.

[0030] Figure 8 This is a schematic diagram of the first electrode layer of the VCSEL chip with high uniform optical power of this application, which simultaneously connects the first illuminated area, the second illuminated area and the third illuminated area, wherein the second illuminated area uses a metal layer alone for the cross-sectional view of the EE line.

[0031] Figure 9 This is a schematic diagram of the first electrode layer of the VCSEL chip with high uniform optical power of this application, which simultaneously connects the first illuminated area, the second illuminated area and the third illuminated area, wherein the second illuminated area uses a separate metal layer for the FF line cross-section. Detailed Implementation

[0032] The terms and words used in the following specification and claims are not limited to their literal meaning, but are used by the applicant only to enable a clear and consistent understanding of this application. Therefore, it will be apparent to those skilled in the art that the following description of various embodiments of this application is provided for illustrative purposes only and not for the purpose of limiting this application as defined in the appended claims and their equivalents.

[0033] It is understood that the term "a" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element can be one, while in another embodiment, the number of the element can be multiple, and the term "a" should not be understood as a limitation on the number.

[0034] While ordinal numbers such as "first," "second," etc., will be used to describe various components, there is no limitation on which components are used herein. The term is used only to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the teachings of this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0035] The terminology used herein is for the purpose of describing various embodiments only and is not intended to be limiting. As used herein, the singular form also includes the plural form, unless the context clearly indicates otherwise. It will also be understood that the terms “comprising” and / or “having” as used in this specification specify the presence of the described features, numbers, steps, operations, components, elements or combinations thereof, without excluding the presence or addition of one or more other features, numbers, steps, operations, components, elements or groups thereof.

[0036] Application Overview Existing VCSEL chips are divided into multiple VCSEL light-emitting regions by multiple electrodes, with each region containing multiple light-emitting points. When a lidar is operating, current is input to the VCSEL light-emitting regions through the electrodes, thereby illuminating the corresponding regions and enabling solid-state scanning. However, due to the relatively long length of the lidar electrodes, the parasitic inductance is excessive, resulting in uneven current distribution when current is input from one end. Specifically, as the current flows along the electrodes, it gradually decreases, leading to the highest light power at the light-emitting point closest to the current input end and the lowest light power at the light-emitting point furthest from the current input end.

[0037] For the reasons mentioned above, this application proposes to subjectively divide each VCSEL light-emitting area into multiple illuminated regions, each of which contains at least one light-emitting point. Then, by dividing the current entering the VCSEL light-emitting area into multiple branch currents, each branch current is input into a corresponding illuminated region, ensuring that the optical power of each illuminated region is the same. This solves the problem of large differences in optical power among individual light-emitting points of the VCSEL chip, improves the light-emitting effect of the VCSEL chip, and enhances the detection performance of the lidar composed of VCSEL light-emitting areas.

[0038] Specifically, this application proposes a VCSEL chip with high uniformity optical power. This VCSEL chip illuminates itself by conducting current through a first electrode structure and a second electrode structure. The VCSEL chip is divided into multiple VCSEL light-emitting regions by multiple first electrode structures; each VCSEL light-emitting region is connected to a corresponding first electrode structure. The total current flows into the first electrode structure, then into the VCSEL light-emitting region, and finally flows out through the second electrode structure, thus illuminating the corresponding VCSEL light-emitting region.

[0039] Each VCSEL light-emitting area is subjectively divided into two illuminated regions, and each illuminated region contains at least one light-emitting point. The two illuminated regions are divided into a first illuminated region and a second illuminated region; of course, the VCSEL light-emitting area can also be divided into three or more illuminated regions, and the specific number can be reasonably divided according to the total length of the VCSEL light-emitting area.

[0040] The first electrode structure is divided into multiple electrode layers, the number of which is equal to the number of illuminated areas, and each electrode layer corresponds to one illuminated area. That is, the first electrode structure includes a first electrode layer and a second electrode layer. In one embodiment, the first electrode layer supplies current to the first illuminated area, and the second electrode layer supplies current to the second illuminated area.

[0041] In another approach, the first electrode layer simultaneously inputs current to the first and second illuminated areas; the second electrode layer inputs current only to the second illuminated area to compensate for the insufficient current input from the first electrode layer to the second illuminated area, thereby maintaining the optical power of the first and second illuminated areas consistent.

[0042] In this application, the direction of current flow is adjusted to divide the total current into two parts. One part of the current is input from the metal disk of the first electrode layer, and the other part of the current is input from the metal disk of the second electrode layer. The current input to the first electrode layer and the current input to the second electrode layer flow in opposite directions. The two currents flowing in opposite directions can cancel each other out the inductance generated by the first electrode layer and the inductance generated by the second electrode layer, thereby reducing the total inductance effect and improving the uniformity of light emission of the VCSEL chip.

[0043] The following examples illustrate in detail the VCSEL chip with high uniformity optical power of this application: like Figure 1 , Figure 2 as well as Figure 3As shown, this application provides a high-uniformity optical power VCSEL chip. The VCSEL chip includes multiple VCSEL light-emitting regions 10. A first electrode structure 20a is deposited on each VCSEL light-emitting region 10 by one of the following methods: evaporation, sputtering, or electroplating. The first electrode structure 20a is one or more combinations of platinum, gold, silver, copper, and aluminum. A second electrode structure 30 is deposited on the bottom of the VCSEL chip by one of the following methods: evaporation, sputtering, or electroplating. Multiple VCSEL light-emitting regions 10 can share the same second electrode structure 30, achieving one-dimensional addressability; alternatively, multiple second electrode structures 30 can be disposed on the bottom of the VCSEL chip, with spacing between them, and each second electrode structure 30 connects to all VCSEL light-emitting regions 10, achieving two-dimensional addressability. The second electrode structure 30 is one or more combinations of platinum, gold, silver, copper, and aluminum.

[0044] In addition, multiple first electrode structures 20a are respectively disposed on the wafer, dividing the numerous light-emitting points 100 on the wafer of the second electrode structure 30 into multiple VCSEL light-emitting regions 10, that is, each VCSEL light-emitting region 10 contains multiple light-emitting points 100.

[0045] Each light-emitting point 100 of the VCSEL light-emitting region 10 includes, from bottom to top, a substrate layer 101, a first Bragg mirror 102, an active region 103, a confinement layer 104 with oxide holes, and a second Bragg mirror 105. The substrate layer 101 is an N-type gallium arsenide substrate, and the first Bragg mirror 102 is grown on the substrate layer 101. The first Bragg mirror 102 and the second Bragg mirror 105 are a system composed of alternating layers of materials with different refractive indices, forming a distributed Bragg reflector (DBR). The material selection of the alternating layers depends on the desired operating wavelength of the laser. In this embodiment, the first Bragg mirror 102 is an N-DBR, and the second Bragg mirror 105 is a P-DBR; or in other embodiments, the first Bragg mirror is a P-DBR, and the second Bragg mirror is an N-DBR. For example, in a specific example of this application, the P-DBR and the N-DBR can be formed by alternating layers of AlGaAs with high aluminum content and AlGaAs with low aluminum content. It is worth mentioning that the optical thickness of the alternating layers is equal to or approximately equal to 1 / 4 of the laser operating wavelength λ. Specifically, in the embodiments of this application, the P-DBR is a P-type doped distributed Bragg reflector, and the N-DBR is an N-type doped distributed Bragg reflector.

[0046] The active region 103 is sandwiched between the second Bragg reflector 105 and the first Bragg reflector 102 to form a resonant cavity. Photons, after being excited, are repeatedly amplified by reflection within the resonant cavity to form laser oscillations, thereby generating a laser beam. Those skilled in the art will understand that the laser emission direction can be selectively controlled by configuring and designing the second Bragg reflector 105 and the first Bragg reflector 102. For example, the laser can be emitted from the second Bragg reflector 105 (i.e., from the top surface of the VCSEL laser) or from the first Bragg reflector 102 (i.e., from the bottom surface of the VCSEL laser). In this embodiment, the second Bragg reflector 105 and the first Bragg reflector 102 are designed such that after oscillation within the resonant cavity, the laser is emitted from the second Bragg reflector 105; that is, the VCSEL laser is a front-emitting semiconductor laser. In this embodiment, the second Bragg reflector 105, the confinement layer 104, the active region 103, and the first Bragg reflector 102 constitute the epitaxial structure of the light-emitting point 100.

[0047] To limit the light emission aperture of the light-emitting point 100, in this embodiment of the application, the light-emitting point 100 is limited by an oxide confinement layer 104 located above the active region 103. The oxide confinement layer 104 has oxide openings for limiting the light emission aperture of the light-emitting point 100. Specifically, the confinement is formed in the bottom region of the P-DBR by an oxidation process; that is, the oxide layer is formed by oxidizing a portion of the material in the bottom region of the P-DBR.

[0048] Each VCSEL light-emitting area 10 is subjectively divided into three illuminated areas (in other embodiments, the VCSEL light-emitting area 10 can also be divided into four, five, or even more illuminated areas). The three illuminated areas are the first illuminated area 110, the second illuminated area 120, and the third illuminated area 130. The first electrode structure 20a is used to input current. After the current passes through the VCSEL light-emitting area 10, it illuminates the light-emitting point 100 within the VCSEL light-emitting area 10. Then, the current flows out from the second electrode structure 30, thereby illuminating the VCSEL light-emitting area 10. The first electrode structure 20a is connected to the upper end face of the second Bragg reflector 105, while the second electrode structure 30 is connected to the bottom of the substrate layer 101.

[0049] The first electrode structure 20a includes a first electrode layer 21a, a second electrode layer 22a, and a third electrode layer 23a. In this embodiment, the first electrode structure 20a has only one metal plate (bondpad) for total current input. The first electrode layer 21a, the second electrode layer 22a, and the third electrode layer 23a share the same metal plate 24a. The first electrode layer 21a is connected to the first illuminated area 110 to input current to the first illuminated area 110. The second electrode layer 22a is connected to the second illuminated area 120 to input current to the second illuminated area 120. Similarly, the third electrode layer 23a is connected to the third illuminated area 130 to input current to the third illuminated area 130. The first electrode layer 21a, the second electrode layer 22a, and the third electrode layer 23a are all connected to the same metal plate, that is, the first electrode layer 21a, the second electrode layer 22a, and the third electrode layer 23a are connected in parallel on the same metal plate. After the total current is input through the metal disk, it is divided into three equivalent currents. The three equivalent currents flow into the first electrode layer 21a, the second electrode layer 22a, and the third electrode layer 23a, respectively. As a result, the current input to the first illumination area 110, the second illumination area 120, and the third illumination area 130 is basically consistent. Therefore, the light power of the light-emitting point 100 in the entire VCSEL light-emitting area 10 is uniform, thereby improving the performance of the lidar.

[0050] Furthermore, the first electrode layer 21a, the second electrode layer 22a, and the third electrode layer 23a are stacked. Specifically, the first electrode layer 21a is at the bottom, the second electrode layer 22a is above the first electrode layer 21a, and there is a certain distance between the first electrode layer 21a and the second electrode layer 22a. The first electrode layer 21a and the second electrode layer 22a are connected in parallel at the metal disk through multiple through-holes with a certain distance between them. Similarly, the third electrode layer 23a is located above the second electrode layer 22a, and there is a certain distance between the second electrode layer 22a and the third electrode layer 23a. The second electrode layer 22a and the third electrode layer 23a are connected in parallel at the metal disk through multiple through-holes with a certain distance between them.

[0051] To ensure accurate alignment of the first electrode layer 21a, the second electrode layer 22a, and the third electrode layer 23a with their respective illuminated areas, an insulating layer 106 is provided between the second Bragg reflector 105 and the first electrode layer 21a. Similarly, insulating layers are provided between the second electrode layer 22a and the first electrode layer 21a, and between the second electrode layer and the third electrode layer. The insulating layer 106 is one of the following: transparent silicon dioxide, silicon nitride, hafnium dioxide, and aluminum oxide. The first electrode layer 21a, the second electrode layer 22a, and the third electrode layer 23a partially pass through the insulating layer 106, thereby illuminating the corresponding first illuminated area 110, the second illuminated area 120, and the third illuminated area 130.

[0052] Other exemplary expressions like Figure 4 , Figure 5 as well as Figure 6 As shown, the first electrode structure 20b includes a first electrode layer 21b, a second electrode layer 22b, and a third electrode layer 23b. In this embodiment, the first electrode structure 20b has only one metal disk 24b (bondpad) for total current input. The first electrode layer 21b, the second electrode layer 22b, and the third electrode layer 23b share the same metal disk 24b. The first electrode layer 21b is correspondingly connected to the first illuminated area 110, the second illuminated area 120, and the third illuminated area 130, thereby simultaneously inputting current to these three areas. The second electrode layer 22b is correspondingly connected to the second illuminated area 120 and the third illuminated area 130, thereby inputting current to both areas. This input current compensates for the current loss from the first electrode layer 21b inputting to the second illuminated area 120 and the third illuminated area 130. The third electrode layer 23b is connected to the third illumination area 130 to input current into the third illumination area 130. The current input into the third electrode layer 23b is used to compensate for the current loss of the first electrode layer 21b and the second electrode layer 22b input into the third illumination area 130.

[0053] The first electrode layer 21b, the second electrode layer 22b, and the third electrode layer 23b are all connected to the same metal disk 24b, meaning they are connected in parallel on the same metal disk 24b. After the total current is input through the metal disk 24b, it is divided into three equivalent currents, which flow into the first electrode layer 21b, the second electrode layer 22b, and the third electrode layer 23b, respectively. As a result, the current input to the first illuminated area 110, the second illuminated area 120, and the third illuminated area 130 is basically consistent, thus ensuring uniform optical power at the light-emitting points 100 of the entire VCSEL light-emitting area, thereby improving the performance of the lidar.

[0054] Furthermore, the first electrode layer 21b, the second electrode layer 22b, and the third electrode layer 23b are stacked. Specifically, the first electrode layer 21b is at the bottom, the second electrode layer 22b is above the first electrode layer 21b, and there is a certain distance between the first electrode layer 21b and the second electrode layer 22b. The first electrode layer 21b and the second electrode layer 22b are connected at the metal disk 24b through multiple through-holes with a certain distance between them, thereby realizing the parallel connection of the first electrode layer 21b and the second electrode layer 22b. The metal of the through-holes can be gold wire or other high-conductivity noble metals. Similarly, the third electrode layer 23b is located above the second electrode layer 22b, and there is a certain distance between the second electrode layer 22b and the third electrode layer 23b. The second electrode layer 22b and the third electrode layer 23b are connected at the metal disk 24b through multiple through-holes with a certain distance between them, thereby realizing the parallel connection of the second electrode layer 22b and the third electrode layer 23b.

[0055] To ensure accurate alignment between the first electrode layer 21b, the second electrode layer 22b, and the third electrode layer 23b with their respective illuminated areas, an insulating layer 106 is provided on the second Bragg reflector. The insulating layer 106 is one of the following: transparent silicon dioxide, silicon nitride, hafnium dioxide, and aluminum oxide. The first electrode layer 21b partially penetrates the insulating layer 106, thereby illuminating the corresponding first illuminated area 110, second illuminated area 120, and third illuminated area 130.

[0056] Other exemplary expressions like Figure 7 , Figure 8 as well as Figure 9As shown, the first electrode structure 20c includes a first electrode layer 21c, a second electrode layer 22c, and a third electrode layer 23c. In this embodiment, the first electrode structure 20c is provided with two metal pads for total current input. The first electrode layer 21c and the third electrode layer 23c share the same metal pad 24c; the second electrode layer 22c uses a different metal pad. The first electrode layer 21c is correspondingly connected to the first illuminated area 110, the second illuminated area 120, and the third illuminated area 130, thereby simultaneously inputting current to these three areas. The second electrode layer 22c is correspondingly connected to the second illuminated area 120 and the third illuminated area 130, thereby inputting current to both areas. This input current compensates for the current loss from the first electrode layer 21c inputting to the second illuminated area 120 and the third illuminated area 130. The third electrode layer 23c is connected to the third illumination area 130 to input current into the third illumination area 130. The current input into the third electrode layer 23c is used to compensate for the current loss of the first electrode layer 21c and the second electrode layer 22c input into the third illumination area 130.

[0057] The first electrode layer 21c and the third electrode layer 23c are both connected to the same metal disk, while the second electrode layer 22c is connected to another metal disk. Since the total current is input through both metal disks, the total current input to one metal disk is split into the first electrode layer 21c and the third electrode layer 23c, and then flows into the corresponding illuminated areas. The current from the other metal disk flows into the second electrode layer 22c. At this time, the current in the first electrode layer 21c and the current in the third electrode layer 23c flow in the same direction, while the current in the second electrode layer 22c flows in the opposite direction to the current in the first electrode layer 21c and the third electrode layer 23c. The opposite current flow directions can cancel each other out, thereby improving the uniformity of the laser emitted by the VCSEL chip and thus improving the performance of the lidar.

[0058] Furthermore, the first electrode layer 21c, the second electrode layer 22c, and the third electrode layer 23c are stacked. Specifically, the first electrode layer 21c is at the bottom, the second electrode layer 22c is above the first electrode layer 21c, and there is a certain distance between the first electrode layer 21c and the second electrode layer 22c. The first electrode layer 21c and the second electrode layer 22c are connected in the metal disk through multiple through holes with a certain distance between them, thereby realizing the parallel connection of the first electrode layer 21c and the second electrode layer 22c. Similarly, the third electrode layer 23c is located above the second electrode layer 22c, and there is a certain distance between the second electrode layer 22c and the third electrode layer 23c. The second electrode layer 22c and the third electrode layer 23c are connected in the metal disk through multiple through holes with a certain distance between them, thereby realizing the parallel connection of the second electrode layer 22c and the third electrode layer 23c.

[0059] To ensure accurate alignment between the first electrode layer 21c, the second electrode layer 22c, and the third electrode layer 23c with their respective illuminated areas, an insulating layer 106 is provided on the second Bragg reflector. The insulating layer 106 is one of transparent silicon dioxide, silicon nitride, hafnium dioxide, or aluminum oxide. The first electrode layer 21c partially passes through the insulating layer 106, thereby illuminating the corresponding first illuminated area 110, second illuminated area 120, and third illuminated area 130. A first insulating layer is provided between the first and second electrode layers, and a second insulating layer is provided between the second and third electrode layers.

[0060] Schematic vehicle-mounted lidar According to another aspect of this application, a lidar is also provided. The lidar works by emitting a laser beam towards the target and receiving the laser beam reflected from the target. Based on the time difference between the emitted and received laser pulses (or the phase difference between the emitted and received reflected laser pulses), the relative position and distance between the target and the lidar are obtained, thereby enabling the detection, tracking, and identification of the object within the target area.

[0061] Accordingly, the lidar includes: a laser projection device for projecting laser light, a laser receiving device for receiving laser signals, and a processor communicatively connected to the laser projection device and the laser receiving device, wherein the laser projection device includes a VCSEL chip with high uniformity optical power as described above.

[0062] Schematic fabrication method of VCSEL chip with high uniformity optical power According to another aspect of this application, a method for fabricating a VCSEL chip with high uniformity optical power is also provided, which is used to fabricate the VCSEL chip with high uniformity optical power as described above. It is worth mentioning that, in the embodiments of this application, the fabrication process of the high uniformity optical power VCSEL chip can still utilize existing VCSEL fabrication processes, preserving the original VCSEL production line and equipment as much as possible, effectively reducing the production line modification cost of VCSEL devices, and thus reducing the fabrication cost of the VCSEL chip.

[0063] The specific method for fabricating a VCSEL chip with high uniform optical power includes the following steps: S1. Epitaxial growth; S2. Definition and formation of p-type contact metal area: Photoresist is applied and the P-Metal pattern of the VCSEL is defined, ultimately forming the desired P-Metal area. The photoresist is then completely removed, and an insulating layer (silicon nitride) is deposited to protect the device surface. S3. Definition and etching trenches, high-temperature oxidation to form oxide holes with confined pores. The photoresist is applied and the Mesa pattern is defined. Subsequent etching will not protect the areas from the photoresist, and the etching depth needs to be deeper than the oxide layer. The photoresist is then completely removed. After a water oxidation process, the high aluminum concentration AlGaAs layer will form an oxide layer. S4. Deposit insulating layer, define and etch, forming the first via: during the formation of... After the oxide layer is deposited, an insulating layer (silicon nitride) is deposited to protect the component surface. Photoresist is then applied and the pattern of the openings is defined. The insulating layer (silicon nitride) above the metal anode is etched away to expose the metal anode. Subsequently, the photoresist is completely removed. S5. Definition and Formation of the First Electrode Layer: Photoresist is applied and the pattern of the final anode metal layer (including the location of the metal bonding area) is defined. The desired anode metal layer is then formed by electroplating gold. The photoresist is then completely removed. S6. Repeat steps S4 to S5, combining different regions and different shaped patterns to form the second via, the second electrode layer, and the third via and the third electrode layer;

[0064] It should be noted that in the apparatus and method of this application, the components or steps in different embodiments can be disassembled and / or recombined without departing from the principles of this application. These disassemblies and / or recombinations should be considered as included within the concept of this application.

[0065] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

Claims

1. A VCSEL chip with high uniform optical power, comprising multiple VCSEL light-emitting regions, characterized in that, Each of the VCSEL light-emitting regions is provided with a first electrode structure and a second electrode structure that cooperates with the first electrode structure, wherein, The VCSEL light-emitting region is divided into multiple illuminated areas, wherein each illuminated area includes at least one light-emitting point; the multiple illuminated areas include at least a first illuminated area and a second illuminated area adjacent to the first illuminated area; the first electrode structure includes a first electrode layer and a second electrode layer, wherein... The first electrode layer and the second electrode layer are connected in parallel; The first electrode layer is connected to at least the first illuminated area, and the second electrode layer is connected to the second illuminated area; The first electrode layer is connected to both the first illuminated area and the second illuminated area, and the second electrode layer is connected to the second illuminated area.

2. The VCSEL chip with high uniform optical power according to claim 1, characterized in that, The direction of current flow into the first electrode layer is the same as the direction of current flow into the second electrode layer.

3. The VCSEL chip with high uniform optical power according to claim 1, characterized in that, The direction of current flow entering the first electrode layer is opposite to the direction of current flow entering the second electrode layer.

4. A VCSEL chip with high uniform optical power according to claim 1, characterized in that, The first electrode layer is located below the second electrode layer.

5. A VCSEL chip with high uniform optical power according to claim 1, characterized in that, The VCSEL light-emitting area includes, from bottom to top, a substrate layer, a first Bragg mirror, an active region, a confinement layer with oxide holes, and a second Bragg mirror. The second electrode structure is in ohmic contact with the substrate layer.

6. A VCSEL chip with high uniform optical power according to claim 5, characterized in that, The second Bragg reflector has an insulating layer, and the first electrode layer and the second electrode layer partially pass through the insulating layer and contact the second Bragg reflector.

7. A VCSEL chip with high uniform optical power according to claim 6, characterized in that, The insulating layer is one of the following: transparent silicon dioxide, silicon nitride, hafnium dioxide, and aluminum oxide.

8. A VCSEL chip with high uniform optical power according to claim 1, characterized in that, The first electrode layer and the second electrode layer are connected in parallel through a plurality of spaced conductor layers.

9. A VCSEL chip with high uniform optical power according to claim 1, characterized in that... The first electrode structure material is one or more of platinum, gold, silver, copper, and aluminum.

10. A lidar, characterized in that, include: A laser projection device for projecting laser light, wherein the laser projection device includes any of the high uniformity optical power VCSEL chips as described in claims 1 to 9; A laser receiving device for receiving laser signals; and A processor communicatively connected to the laser projection device and the laser receiving device.

11. A method for fabricating a VCSEL chip with high uniformity optical power, characterized in that, include: S1. Epitaxial growth; S2. Coat photoresist on the epitaxial wafer and define the anode contact metal (P-Metal) pattern of the VCSEL to form the required anode contact metal (P-Metal) range. Then remove the photoresist and deposit an insulating layer to protect the surface of the component. S3. Apply photoresist and define the Mesa pattern. The area not protected by the photoresist will be etched later. The etching depth needs to be deeper than the oxide layer. Then remove the photoresist completely. After water oxidation, the high aluminum concentration AlGaAs layer will form an oxide layer, forming oxide pores with confined pores, and then an insulating layer will be deposited to protect the surface of the component. S4. Apply photoresist and define the pattern of the opening. Etch away the silicon nitride protective layer above the metal anode to expose the anode contact metal of the VCSEL. Then remove the photoresist completely to obtain the first through hole. S5. Coat the photoresist and define the pattern of the anode metal layer of the VCSEL. Form the required anode metal layer of the VCSEL by electroplating gold. Then remove the photoresist to form the first electrode layer. S6. Deposit an insulating layer, repeat steps S4 to S5, define and etch to form a second via and a second electrode layer; S7. Deposit an insulating layer, repeat steps S4 to S5, define and etch to form the third via and the third electrode layer, forming the first electrode structure of the crystal plane; S8. Apply photoresist to protect the front side of the wafer. Grind the wafer to the required thickness for the product. First, deposit and form the cathode contact metal (N-Metal). Then, electroplat gold to form the required cathode metal layer for the VCSEL. Finally, remove the photoresist from the front side to form the second electrode structure on the back side. The VCSEL chip includes multiple VCSEL light-emitting regions, which are divided into multiple illuminated areas. The multiple illuminated areas include at least a first illuminated area, a second illuminated area, and a third illuminated area. The first electrode layer is connected to the first illuminated area, the second illuminated area, and the third illuminated area. The second electrode layer is connected to the second illuminated area and the third illuminated area. The third electrode layer is connected to the third illuminated area.

Images