High voltage direct current voltage modulation circuit

Abstract

The application provides a high-voltage direct-current voltage modulation circuit, which comprises an output control module, an output adjustment module and an output negative feedback module. The output adjustment module can adjust the output degree of the first voltage and the output degree of the second voltage respectively by adjusting the current, so as to adjust the size of the target voltage. The output adjustment module can also adjust the output current corresponding to the first voltage and the output current corresponding to the second voltage respectively by adjusting the current, so that the output current corresponding to the first voltage and the output current corresponding to the second voltage respectively change adaptively with the target voltage, and then the rising edge and the falling edge of the output target voltage are symmetrical when the target voltage is adjusted to one end of the first voltage or the second voltage, which can effectively reduce the power consumption of the circuit and speed up the adjustment speed. Based on the structural design of the output negative feedback module, the output target voltage and the input control voltage form a negative feedback, which can effectively reduce the noise of the output target voltage.

Description

Technical Field

[0001] This invention relates to the field of high voltage DC voltage modulation technology, and in particular to a high voltage DC voltage modulation circuit. Background Technology

[0002] Currently, high-voltage DC voltage modulation is generally achieved using dual NMOS transistor modulation circuits. In traditional dual NMOS high-voltage DC voltage modulation circuits, the high-side NMOS transistor (hereinafter referred to as the upper transistor) is in a fixed on state (i.e., a fixed constant current state) throughout the entire output range. The output voltage is modulated by controlling the conduction degree of the low-side NMOS transistor (hereinafter referred to as the lower transistor) through an operational amplifier, thereby linearly amplifying the input low-voltage DC voltage by hundreds of times to the output.

[0003] In traditional dual-NMOS modulation circuits, the upper transistor remains in a constant current state throughout the entire modulation range. When the output voltage is adjusted towards the high end, the conduction level of the lower transistor decreases, and the maximum output current is approximately equal to the constant current of the upper transistor. Conversely, when the output voltage is adjusted towards the low end, the conduction level of the lower transistor increases, and the maximum output current is approximately equal to the supply current of the low-end power supply. Typically, the constant current of the upper transistor is much smaller than the supply current, leading to an asymmetry between the rising and falling edges when adjusting the output voltage towards the high and low ends, with the falling edge being significantly faster than the rising edge. Increasing the constant current of the upper transistor can accelerate the rise time, but this also increases circuit power consumption. The best solution to this problem is to use a dual-terminal control circuit composed of an NMOS transistor and a PMOS transistor with identical parameters, ensuring perfect synchronization of the rising and falling edges. However, the manufacturing process of PMOS transistors on the market currently does not reach the level of NMOS transistors, and the voltage rating of PMOS transistors is generally lower than that of NMOS transistors. Therefore, high-voltage DC regulation circuits mostly employ dual-NMOS transistor regulation.

[0004] Therefore, there is an urgent need for a high-voltage DC voltage modulation technology based on dual NMOS transistors, which enables the constant current of the upper transistor to adapt to different output voltages, thereby reducing power consumption and accelerating the adjustment speed. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a high voltage DC voltage modulation technology solution, which enables the constant current of the upper tube to adapt to different output voltages, so as to reduce power consumption and speed up the adjustment speed, while introducing an appropriate amount of negative feedback to reduce the noise of the output voltage.

[0006] To achieve the above and other related objectives, the technical solution provided by this invention is as follows.

[0007] A high-voltage DC voltage modulation circuit, comprising:

[0008] The output control module is connected to the control voltage and generates an adjustment current based on the control voltage.

[0009] The output adjustment module is connected to a first voltage and a second voltage, and superimposes the first voltage and the second voltage to obtain a target voltage. It is also connected to the adjustment current, and adjusts the output levels of the first voltage and the second voltage respectively to adjust the magnitude of the target voltage. The adjustment current is also used to adjust the output current corresponding to the first voltage and the second voltage respectively, so that the output current corresponding to the first voltage and the output current corresponding to the second voltage adapt to the target voltage.

[0010] An output negative feedback module is connected to the output control module and the output adjustment module respectively, so that the target voltage and the control voltage form negative feedback, and the target voltage after negative feedback is output to the outside.

[0011] Optionally, the output control module includes an operational amplifier unit, a voltage-controlled current unit, and a voltage limiting protection unit. The operational amplifier unit is connected to the control voltage and compares the control voltage with a reference voltage to obtain a voltage-controlled current voltage. The voltage-controlled current unit is connected to the voltage-controlled current voltage and generates the adjustment current based on the voltage-controlled current voltage. The voltage limiting protection unit is connected to the operational amplifier unit to limit the magnitude of the control voltage connected to the operational amplifier unit.

[0012] Optionally, the operational amplifier unit includes an operational amplifier, a first resistor, and a first capacitor. The inverting input terminal of the operational amplifier is connected to the control voltage via the first resistor connected in series. The non-inverting input terminal of the operational amplifier is grounded. One end of the first capacitor is connected to the inverting input terminal of the operational amplifier, and the other end of the first capacitor is connected to the output terminal of the operational amplifier. The output terminal of the operational amplifier outputs the voltage-controlled current voltage.

[0013] Optionally, the voltage-controlled current unit includes a PNP transistor and a second resistor. The emitter of the PNP transistor is grounded, the base of the PNP transistor is connected to the output terminal of the operational amplifier via the second resistor in series, and the collector of the PNP transistor outputs the adjustment current.

[0014] Optionally, the voltage limiting protection unit includes a first diode and a second diode. The anode of the first diode is grounded, and the cathode of the first diode is connected to the inverting input terminal of the operational amplifier. The anode of the second diode is connected to the inverting input terminal of the operational amplifier, and the cathode of the second diode is grounded.

[0015] Optionally, the output adjustment module includes a voltage output adjustment unit and an adjustment current transmission conversion unit. The first input terminal of the voltage output adjustment unit is connected to the first voltage, the second input terminal of the voltage output adjustment unit is connected to the second voltage, the output terminal of the voltage output adjustment unit outputs the target voltage, the first control terminal of the voltage output adjustment unit is connected to the first output terminal of the adjustment current transmission conversion unit, the second control terminal of the voltage output adjustment unit is connected to the second output terminal of the adjustment current transmission conversion unit, the input terminal of the voltage output adjustment unit is connected to the adjustment current, the adjustment current transmission conversion unit performs transmission conversion on the adjustment current to obtain a first voltage adjustment voltage difference and a second voltage adjustment voltage difference, the voltage output adjustment unit adjusts the output level of the first voltage and the output current corresponding to the first voltage according to the first voltage adjustment voltage difference, and the voltage output adjustment unit adjusts the output level of the second voltage and the output current corresponding to the second voltage according to the second voltage adjustment voltage difference.

[0016] Optionally, the first voltage is greater than the second voltage. The voltage output adjustment unit includes a first NMOS transistor, a second NMOS transistor, a first Zener diode, a second Zener diode, a third resistor, and a fourth resistor. The drain of the first NMOS transistor is connected to the first voltage. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor via the third resistor connected in series. The source of the second NMOS transistor is connected to the second voltage via the fourth resistor connected in series. The anode of the first Zener diode is connected to the source of the first NMOS transistor. The cathode of the first Zener diode is connected to the gate of the first NMOS transistor. The anode of the second Zener diode is connected to the source of the second NMOS transistor. The cathode of the second Zener diode is connected to the gate of the second NMOS transistor. The drain of the second NMOS transistor outputs the target voltage.

[0017] Optionally, the voltage output adjustment unit further includes two CRCπ type filters. The drain of the first NMOS transistor is connected to the first voltage after passing through the first CRCπ type filter connected in series, and the drain of the second NMOS transistor is connected to the second voltage after passing through the fourth resistor and the second CRCπ type filter connected in series.

[0018] Optionally, the current transfer conversion unit includes a third NMOS transistor, a fourth NMOS transistor, a third Zener diode, a fourth Zener diode, a fifth Zener diode, a sixth Zener diode, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor. The drain of the third NMOS transistor is connected to the drain of the first NMOS transistor. The gate of the third NMOS transistor is connected to the drain of the third NMOS transistor via the fifth resistor connected in series. The source of the third NMOS transistor is connected to the gate of the first NMOS transistor via the sixth resistor connected in series. One end of the seventh resistor is connected to the gate of the first NMOS transistor, and the other end of the seventh resistor is connected to the drain of the second NMOS transistor. The anode of the third Zener diode is connected to the source of the third NMOS transistor, and the cathode of the third Zener diode is connected to the gate of the third NMOS transistor. The fourth Zener diode... The anode of the fourth Zener diode is connected to the gate of the first NMOS transistor, the cathode of the fourth Zener diode is connected to the gate of the third NMOS transistor, the drain of the fourth NMOS transistor is connected to the gate of the first NMOS transistor, the gate of the fourth NMOS transistor is connected to the anode of the fifth Zener diode, the cathode of the fifth Zener diode is connected to the adjustment current, the source of the fourth NMOS transistor is connected to the gate of the second NMOS transistor, one end of the eighth resistor is connected to the gate of the second NMOS transistor, the other end of the eighth resistor is connected to the end of the fourth resistor connected to the second voltage, the anode of the sixth Zener diode is connected to the source of the fourth NMOS transistor, the cathode of the sixth Zener diode is connected to the gate of the fourth NMOS transistor, one end of the ninth resistor is connected to the gate of the fourth NMOS transistor, and the other end of the ninth resistor is connected to the end of the fourth resistor connected to the second voltage.

[0019] Optionally, the output negative feedback module includes an RC filter and a tenth resistor. One end of the tenth resistor is connected to the inverting input of the operational amplifier, and the other end of the tenth resistor is connected to the target voltage. The other end of the tenth resistor is also connected to the input of the RC filter. The target voltage after negative feedback is output to the outside through the output of the RC filter.

[0020] As described above, the high-voltage DC voltage modulation circuit of the present invention has at least the following beneficial effects:

[0021] A high-voltage DC voltage modulation circuit is designed by combining an output control module, an output adjustment module, and an output negative feedback module. The output adjustment module can adjust the output levels of the first voltage and the second voltage respectively through the adjustment current output by the output control module to adjust the target voltage. The output adjustment module can also adjust the output current corresponding to the first voltage and the second voltage respectively through the adjustment current output by the output control module, so that the output current corresponding to the first voltage and the second voltage adapts to the target voltage. This makes the rising and falling edges of the output target voltage symmetrical when adjusted towards the first voltage or the second voltage, which can effectively reduce circuit power consumption and speed up the adjustment. Based on the structural design of the output negative feedback module, the output target voltage and the input control voltage form negative feedback, which can effectively reduce the noise of the output target voltage. Attached Figure Description

[0022] Figure 1 The diagram shown is a circuit diagram of the high-voltage DC voltage modulation circuit in this invention.

[0023] Explanation of reference numerals in the attached figures

[0024] 1—Output control module, 2—Output adjustment module, 3—Output negative feedback module, U1—Operational amplifier, R1—First resistor, R2—Second resistor, R3—Third resistor, R4—Fourth resistor, R5—Fifth resistor, R6—Sixth resistor, R7—Seventh resistor, R8—Eighth resistor, R9—Ninth resistor, R10—Tenth resistor, R01—First filter resistor, R02—Second filter resistor, R03—Third filter resistor, C1—First capacitor, C2—Second capacitor, C3—Third capacitor, C4—Fourth capacitor, C01—First filter capacitor, C02—Second filter capacitor, C03—Third filter capacitor, C04—Fourth filter capacitor, C05—Fifth filter capacitor, Q1 —PNP transistor, Q2—First NMOS transistor, Q3—Second NMOS transistor, Q4—Third NMOS transistor, Q5—Fourth NMOS transistor, D1—First diode, D2—Second diode, D3—First Zener diode, D4—Second Zener diode, D5—Third Zener diode, D6—Fourth Zener diode, D7—Fifth Zener diode, D8—Sixth Zener diode, Vset—Control voltage, Iset—Adjustment current, +HV—First voltage, -HV—Second voltage, Vout—Target voltage, Vout'—Final target voltage, GND—Ground, V01—Voltage-controlled current voltage, V02—First voltage adjustment differential, V03—Second voltage adjustment differential. Detailed Implementation

[0025] As mentioned in the background section, the inventors discovered that in traditional dual-NMOS modulation circuits, the upper transistor remains in a constant current state throughout the entire modulation range. When the output voltage is adjusted towards the higher end, the conduction level of the lower transistor decreases, and the maximum output current is approximately equal to the constant current of the upper transistor. Conversely, when the output voltage is adjusted towards the lower end, the conduction level of the lower transistor increases, and the maximum output current is approximately equal to the supply current of the lower-end power supply. Typically, the constant current of the upper transistor is much smaller than the supply current, resulting in an asymmetry between the rising and falling edges when adjusting the output towards the higher or lower ends, with the falling edge being significantly faster than the rising edge. Increasing the constant current of the upper transistor can accelerate the rise time, but it also increases circuit power consumption. The best solution to this problem is to use NMOS and PMOS transistors with identical parameters to form a dual-terminal control circuit, which can make the rising and falling edges perfectly synchronized. However, the manufacturing process of PMOS transistors on the market currently does not reach the level of NMOS transistors, and the voltage rating of PMOS transistors is generally lower than that of NMOS transistors. Therefore, high-voltage DC regulation circuits generally still mostly use dual-NMOS transistor regulation.

[0026] Based on this, the inventors proposed a high-voltage DC voltage modulation technology based on dual NMOS transistors: A high-voltage DC voltage modulation circuit is designed by combining an output control module, an output adjustment module, and an output negative feedback module. The adjustment current output by the output control module adjusts the output level of the first voltage and the corresponding output current in the output adjustment module. Simultaneously, the adjustment current output by the output control module adjusts the output level of the second voltage and the corresponding output current in the output adjustment module. While adjusting the target voltage, the output currents corresponding to the first and second voltages adaptively change with the target voltage, thus making the rising and falling edges of the output target voltage symmetrical when adjusted towards either the first or second voltage, reducing circuit power consumption and accelerating the adjustment speed. Based on the structural design of the output negative feedback module, the output target voltage forms negative feedback with the input control voltage to reduce noise in the output target voltage.

[0027] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0028] Please see Figure 1It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. The structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives of the present invention, should still fall within the scope of the technical content disclosed in the present invention.

[0029] like Figure 1 As shown, the present invention proposes a high-voltage DC voltage modulation circuit, which includes:

[0030] Output control module 1 is connected to control voltage Vset and generates adjustment current Iset based on control voltage Vset;

[0031] Output adjustment module 2 is connected to a first voltage +HV and a second voltage -HV. It superimposes the first voltage +HV and the second voltage -HV to obtain the target voltage Vout. It is also connected to an adjustment current Iset. The adjustment current Iset is used to adjust the output levels of the first voltage +HV and the second voltage -HV respectively to adjust the magnitude of the target voltage Vout. The adjustment current Iset is also used to adjust the output current corresponding to the first voltage +HV and the second voltage -HV respectively, so that the output current corresponding to the first voltage +HV and the second voltage -HV respectively adapt to the target voltage Vout.

[0032] The output negative feedback module 3 is connected to the output control module 1 and the output adjustment module 2 respectively, so that the target voltage Vout and the control voltage Vset form negative feedback, and outputs the negative feedback target voltage Vout to the outside.

[0033] Wherein, the first voltage +HV is greater than the second voltage -HV. For example, the first voltage +HV is a positive voltage of +1000V and the second voltage -HV is a negative voltage of -1000V. The specific values ​​can be flexibly selected and are not limited here.

[0034] In detail, such as Figure 1As shown, the output control module 1 includes an operational amplifier unit, a voltage-controlled current unit, and a voltage limiting protection unit. The operational amplifier unit is connected to the control voltage Vset and compares the control voltage Vset with the reference voltage (GND, 0V) to obtain the voltage-controlled current voltage V01. The voltage-controlled current unit is connected to the voltage-controlled current voltage V01 and generates an adjustment current Iset based on the voltage-controlled current voltage V01. The voltage limiting protection unit is connected to the operational amplifier unit to limit the magnitude of the control voltage Vset connected to the operational amplifier unit.

[0035] More in detail, such as Figure 1 As shown, the operational amplifier unit includes an operational amplifier U1, a first resistor R1, and a first capacitor C1. The inverting input terminal of the operational amplifier U1 is connected to the control voltage Vset via the first resistor R1 connected in series. The non-inverting input terminal of the operational amplifier U1 is grounded to GND. One end of the first capacitor C1 is connected to the inverting input terminal of the operational amplifier, and the other end of the first capacitor C1 is connected to the output terminal of the operational amplifier U1. The output terminal of the operational amplifier U1 outputs a voltage-controlled current voltage V01. The first capacitor C1 is a feedback capacitor.

[0036] More in detail, such as Figure 1 As shown, the voltage-controlled current unit includes a PNP transistor Q1 and a second resistor R2. The emitter of the PNP transistor Q1 is grounded to GND, and the base of the PNP transistor Q1 is connected to the output terminal of the operational amplifier U1 via the second resistor R2 connected in series. The collector of the PNP transistor Q1 outputs an adjustment current Iset.

[0037] More in detail, such as Figure 1 As shown, the voltage limiting protection unit includes a first diode D1 and a second diode D2. The anode of the first diode D1 is grounded to GND, and the cathode of the first diode D1 is connected to the inverting input terminal of operational amplifier U1. The anode of the second diode D2 is connected to the inverting input terminal of operational amplifier U1, and the cathode of the second diode D2 is grounded to GND. Based on the structural design of the first diode D1 and the second diode D2, the magnitude of the control voltage Vset is limited to -Vth. D1 ~Vth D2 Within a certain range, it can effectively prevent the control voltage Vset from becoming too large, thereby damaging the operational amplifier U1. Wherein, Vth... D1 Vth is the forward voltage drop of the first diode D1. D2 This is the forward voltage drop of the second diode D2.

[0038] In detail, such as Figure 1As shown, the output adjustment module 2 includes a voltage output adjustment unit and an adjustment current transmission conversion unit. The first input terminal of the voltage output adjustment unit is connected to a first voltage +HV, and the second input terminal of the voltage output adjustment unit is connected to a second voltage -HV. The output terminal of the voltage output adjustment unit outputs a target voltage Vout. The first control terminal of the voltage output adjustment unit is connected to the first output terminal of the adjustment current transmission conversion unit, and the second control terminal of the voltage output adjustment unit is connected to the second output terminal of the adjustment current transmission conversion unit. The input terminal of the voltage output adjustment unit is connected to the adjustment current Iset. The adjustment current transmission conversion unit performs transmission conversion on the adjustment current Iset to obtain a first voltage adjustment voltage difference V02 and a second voltage adjustment voltage difference V03. The voltage output adjustment unit adjusts the output level of the first voltage +HV and the corresponding output current of the first voltage +HV according to the first voltage adjustment voltage difference V02. The voltage output adjustment unit adjusts the output level of the second voltage -HV and the corresponding output current of the second voltage -HV according to the second voltage adjustment voltage difference V03.

[0039] More in detail, such as Figure 1 As shown, the voltage output adjustment unit includes a first NMOS transistor Q2, a second NMOS transistor Q3, a first Zener diode D3, a second Zener diode D4, a third resistor R3, and a fourth resistor R4. The drain of the first NMOS transistor Q2 is connected to a first voltage +HV. The source of the first NMOS transistor Q2 is connected to the drain of the second NMOS transistor Q3 via the third resistor R3 in series. The source of the second NMOS transistor Q3 is connected to a second voltage -HV via the fourth resistor R4 in series. The anode of the first Zener diode D3 is connected to the source of the first NMOS transistor Q2, and the cathode of the first Zener diode D3 is connected to the gate of the first NMOS transistor Q2. The anode of the second Zener diode D4 is connected to the source of the second NMOS transistor Q3, and the cathode of the second Zener diode D4 is connected to the gate of the second NMOS transistor Q3. The drain of the second NMOS transistor Q3 outputs the target voltage Vout.

[0040] More in detail, such as Figure 1 As shown, the voltage output adjustment unit also includes two CRCπ type filters. The drain of the first NMOS transistor Q2 is connected to the first voltage +HV after passing through the first CRCπ type filter in series. The drain of the second NMOS transistor Q3 is connected to the second voltage -HV after passing through the fourth resistor R4 and the second CRCπ type filter in series.

[0041] More in detail, such as Figure 1As shown, the first CRCπ-type filter includes a first filter resistor R01, a first filter capacitor C01, and a second filter capacitor C02. One end of the first filter resistor R01 is connected to the first voltage +HV, and the other end of the first filter resistor R01 is connected to the drain of the first NMOS transistor Q2. One end of the first filter capacitor C01 is connected to the first voltage +HV, and the other end of the first filter capacitor C01 is grounded to GND. One end of the second filter capacitor C02 is connected to the drain of the first NMOS transistor Q2, and the other end of the second filter capacitor C02 is grounded to GND. The first CRCπ-type filter serves as the input filter for the first voltage +HV.

[0042] More in detail, such as Figure 1 As shown, the second CRCπ-type filter includes a second filter resistor R02, a third filter capacitor C03, and a fourth filter capacitor C04. One end of the second filter resistor R02 is connected to the second voltage -HV, and the other end of the second filter resistor R02 is connected to the source of the second NMOS transistor Q3 via the fourth resistor R4 connected in series. One end of the third filter capacitor C03 is connected to the common terminal of the second filter resistor R02 and the fourth resistor R4, and the other end of the third filter capacitor C03 is grounded to GND. One end of the fourth filter capacitor C04 is connected to the second voltage -HV, and the other end of the fourth filter capacitor C04 is grounded to GND. The second CRCπ-type filter serves as the input filter for the second voltage -HV.

[0043] In detail, such as Figure 1As shown, the current transfer conversion unit includes a third NMOS transistor Q4, a fourth NMOS transistor Q5, a third Zener diode D5, a fourth Zener diode D6, a fifth Zener diode D7, a sixth Zener diode D8, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9. The drain of the third NMOS transistor Q4 is connected to the drain of the first NMOS transistor Q2. The gate of the third NMOS transistor Q4 is connected to the drain of the fourth NMOS transistor Q5 via the fifth resistor R5 in series. The source of the third NMOS transistor Q4 is connected to the gate of the first NMOS transistor Q2 via the sixth resistor R6 in series. One end of the seventh resistor R7 is connected to the gate of the first NMOS transistor Q2, and the other end of the seventh resistor R7 is connected to the drain of the second NMOS transistor Q3. The anode of the third Zener diode D5 is connected to the source of the third NMOS transistor Q4, and the cathode of the third Zener diode D5 is connected to the gate of the third NMOS transistor Q4. The anode of the fourth Zener diode D6 is connected to the gate of the first NMOS transistor Q2. The cathode of the fourth Zener diode D6 is connected to the gate of the third NMOS transistor Q4. The drain of the fourth NMOS transistor Q5 is connected to the gate of the first NMOS transistor Q2. The gate of the fourth NMOS transistor Q5 is connected to the anode of the fifth Zener diode D7. The cathode of the fifth Zener diode D7 is connected to the adjustment current Iset. The source of the fourth NMOS transistor Q5 is connected to the gate of the second NMOS transistor Q3. One end of the eighth resistor R8 is connected to the gate of the second NMOS transistor Q3. The other end of the eighth resistor R8 is connected to the end of the fourth resistor R4 connected to the second voltage -HV. The anode of the sixth Zener diode D8 is connected to the source of the fourth NMOS transistor Q5. The cathode of the sixth Zener diode D8 is connected to the gate of the fourth NMOS transistor Q5. One end of the ninth resistor R9 is connected to the gate of the fourth NMOS transistor Q5. The other end of the ninth resistor R9 is connected to the end of the fourth resistor R4 connected to the second voltage -HV.

[0044] Among them, the first Zener diode D3 is the protection Zener diode for the first NMOS transistor Q2, and it should satisfy Vgsth(Q2) < Uz(D3) < Vgss(Q2). Similarly, the second Zener diode D4 is the protection Zener diode for the second NMOS transistor Q3, and it should satisfy Vgsth(Q3) < Uz(D4) < Vgss(Q3). The third Zener diode D5 is the protection Zener diode for the third NMOS transistor Q4. The protection Zener diode should satisfy Vgsth(Q4) < Uz(D5) < Vgss(Q5). The sixth Zener diode D8 is the protection Zener diode for the fourth NMOS transistor Q5, and it should satisfy Vgsth(Q5) < Uz(D8) < Vgss(Q5). The fourth Zener diode D6 is a constant current Zener diode, and it should satisfy Vgsth(Q4) < Uz(D6) < Vgss(Q4).

[0045] In detail, such as Figure 1As shown, the current transmission conversion unit also includes a second capacitor C2 and a third capacitor C3. The second capacitor C2 is connected in parallel with the fourth Zener diode D6, which is a constant current Zener diode. The second capacitor C2 is the Zener capacitor for the fourth Zener diode D6, which can improve the Zener voltage regulation accuracy of the fourth Zener diode D6 and improve the transmission speed of the control voltage. The third capacitor C3 is connected in parallel with the fifth Zener diode D7, which is a voltage transmission Zener diode. The third capacitor C3 is the Zener capacitor for the fifth Zener diode D7.

[0046] In detail, such as Figure 1 As shown, the output negative feedback module 3 includes an RC filter, a tenth resistor R10, and a fourth capacitor C4. One end of the tenth resistor R10 is connected to the inverting input of the operational amplifier U1, and the other end of the tenth resistor R10 is connected to the target voltage Vout. The other end of the tenth resistor R10 is also connected to the input of the RC filter. The target voltage Vout after negative feedback is output to the outside through the output of the RC filter. The fourth capacitor C4 is connected in parallel with the tenth resistor R10 and is the feedback capacitor.

[0047] More in detail, such as Figure 1 As shown, the RC filter includes a third filter resistor R03 and a fifth filter capacitor C05. One end of the third filter resistor R03 is connected to the drain of the second NMOS transistor Q3 (i.e., connected to the target voltage Vout), and the other end of the third filter resistor R03 outputs the final target voltage Vout'. One end of the fifth filter capacitor C05 is grounded to GND, and the other end of the fifth filter capacitor C05 is connected to the final target voltage Vout'. The RC filter is the output filter capacitor for the target voltage Vout.

[0048] More in detail, such as Figure 1 The working principle of the high-voltage DC voltage modulation circuit shown is as follows:

[0049] 1) When the circuit output is in steady state, based on the circuit structure analysis, Uz(D6) = V(R6) + Vgs(Q4), I(Q4) = I(R6) is the constant current of the third NMOS transistor Q4, which is a fixed value; V(R7) = V(R3) + Vgs(Q2), I(Q2) = I(R3) is the constant current of the first NMOS transistor Q2; the operational amplifier U1 controls the PNP transistor through the second resistor R2. The base current of transistor Q1 puts PNP transistor Q1 in the amplification region, which in turn controls I(D7) and V(R9). Since V(R9) = V(R8) + Vgs(Q5), I(Q5) = I(R8) is the constant current of the fourth NMOS transistor Q5, which is controllable by operational amplifier U1; V(R8) = V(R4) + Vgs(Q3), I(Q3) = I(R4) is the constant current of the second NMOS transistor Q3. At this time, I(R6) + I(D6) = I(Q5) + I(R7). Since I(D6) is usually less than 100nA, the change in I(D6) will be ignored in the following discussion; I(Q2) + I(R7) = I(Q3) + I(R03) + I(R10).

[0050] 2) When the control voltage Vset is a fixed value, ignoring the influence of the RC filter, Vout'≈Vout. At this point, due to the virtual short of operational amplifier U1, -Vout' / R10=Vset / R1, and Vout' / Vset=-R10 / R1 is the amplification factor. This forms an inverting amplifier circuit, creating negative feedback, which effectively reduces the noise of the final target output voltage Vout'. The lower the input offset voltage Voffset of operational amplifier U1, the higher the control accuracy of the final target voltage Vout'.

[0051] 3) When the control voltage Vset increases, the voltage V- at the inverting input of operational amplifier U1 increases. Since V- > V+, the voltage-controlled current V01 output by operational amplifier U1 decreases, the base current of PNP transistor Q1 decreases, the amplification of PNP transistor Q1 increases, and the adjustment current Iset output from its collector increases. I(D7) increases, and the current of I(D7) mainly flows through the ninth resistor R9, causing V(R9) to increase, which in turn causes V(R8) and Vgs(Q5) to increase. The conduction degree of the fourth NMOS transistor Q5 increases, and the current flowing through it increases, i.e., I(Q5) = I(R8) increases, V(R8) (which is the second voltage adjustment voltage difference V03) increases, causing V(R4) and Vgs(Q3) to increase. As the conduction level of MOSFET Q3 increases, the current flowing through it rises, i.e., I(Q3) = I(R4) increases. At the same time, the output of the second voltage -HV after passing through the second NMOS transistor Q3 increases. Since I(R6) + I(D6) = I(Q5) + I(R7) is a fixed value, I(R7) decreases. The voltage V(R7) across the seventh resistor R7 (which is the first voltage adjustment voltage difference V02) decreases, causing V(R3) and Vgs(Q2) to decrease. The conduction level of the first NMOS transistor Q2 decreases, and the current flowing through it decreases, i.e., I(Q2) = I(R3) decreases. At the same time, the output of the first voltage +HV after passing through the first NMOS transistor Q2 decreases. The target voltage Vout is adjusted towards the second voltage -HV end.

[0052] 4) When the control voltage Vset decreases, the voltage V- at the inverting input of operational amplifier U1 decreases. Since V- < V+, the voltage-controlled current V01 output by operational amplifier U1 increases, the base current of PNP transistor Q1 increases, the amplification of PNP transistor Q1 decreases, and the adjustment current Iset output from its collector decreases. I(D7) decreases, and the current of I(D7) mainly flows through the ninth resistor R9, causing V(R9) to decrease, which in turn causes V(R8) and Vgs(Q5) to decrease. The conduction degree of the fourth NMOS transistor Q5 decreases, and the current flowing through it decreases, i.e., I(Q5) = I(R8) decreases, V(R8) (which is the second voltage adjustment voltage difference V03) decreases, causing V(R4) and Vgs(Q3) to decrease. The conduction level of MOSFET Q3 decreases, and the current flowing through it decreases, i.e., I(Q3) = I(R4) decreases. At the same time, the output of the second voltage -HV after passing through the second NMOS transistor Q3 decreases. Since I(R6) + I(D6) = I(Q5) + I(R7) is a fixed value, I(R7) increases. The voltage V(R7) across the seventh resistor R7 (that is, the first voltage adjustment voltage difference V02) increases, which in turn increases V(R3) and Vgs(Q2). The conduction level of the first NMOS transistor Q2 increases, and the current flowing through it increases, i.e., I(Q2) = I(R3) increases. At the same time, the output of the first voltage +HV after passing through the first NMOS transistor Q2 increases. The target voltage Vout is adjusted towards the first voltage +HV end.

[0053] It should be noted that selecting appropriate third NMOS transistor Q4, sixth resistor R6, and fourth Zener diode D6 can reasonably set the circuit power consumption, appropriately reducing the circuit power consumption while meeting the circuit output requirements; selecting appropriate operational amplifier U1, and matching appropriate third resistor R3, fourth resistor R4, seventh resistor R7, eighth resistor R8, ninth resistor R9, first capacitor C1, and fourth capacitor C4 can prevent oscillation and eliminate overshoot. To further verify the technical effect of the present invention, in an optional embodiment of the present invention, the design is as follows... Figure 1 The high-voltage DC voltage modulation circuit shown was tested and found that its full-range output adjustment time was less than 200μS when the high-voltage power supply was +1000V (i.e., the first voltage +HV position +1000V) to -1000V (i.e., the second voltage -HV position -1000V), and the output noise of the target voltage Vout or the final target voltage Vout' was as low as 1mV.

[0054] In summary, this invention combines an output control module, an output adjustment module, and an output negative feedback module to design a high-voltage DC voltage modulation circuit. Based on the circuit structure design of the output adjustment module, the output control module can synchronously and complementaryly regulate the output switching transistors of the first voltage and the second voltage. While adjusting the output levels of the first and second voltages to adjust the target voltage, it can also adjust the output currents corresponding to the first and second voltages, making them adaptively change with the target voltage. This ensures that the rising and falling edges of the target voltage output by the high-voltage DC voltage modulation circuit are symmetrical when adjusted towards either the first or second voltage, effectively reducing circuit power consumption and accelerating adjustment speed. Based on the structural design of the output negative feedback module, the output target voltage forms negative feedback with the input control voltage, effectively reducing the noise of the output target voltage.

[0055] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A high-voltage DC voltage modulation circuit based on dual NMOS transistors, characterized in that, include: The output control module is connected to the control voltage and generates an adjustment current based on the control voltage. The output adjustment module is connected to a first voltage and a second voltage, and superimposes the first voltage and the second voltage to obtain a target voltage. It is also connected to the adjustment current, which adjusts the output levels of the first voltage and the second voltage respectively to adjust the magnitude of the target voltage. The adjustment current also adjusts the output current corresponding to the first voltage and the second voltage respectively, so that the output current corresponding to the first voltage and the output current corresponding to the second voltage adaptively change with the target voltage. When the target voltage is adjusted towards the first voltage or the second voltage, the first NMOS transistor in the output modulation module is turned on. An output negative feedback module is connected to the output control module and the output adjustment module respectively, so that the target voltage and the control voltage form negative feedback, and the target voltage after negative feedback is output to the outside. The output adjustment module includes a voltage output adjustment unit and an adjustment current transmission conversion unit. The first input terminal of the voltage output adjustment unit is connected to the first voltage, and the second input terminal is connected to the second voltage. The output terminal of the voltage output adjustment unit outputs the target voltage. The first control terminal of the voltage output adjustment unit is connected to the first output terminal of the adjustment current transmission conversion unit, and the second control terminal is connected to the second output terminal of the adjustment current transmission conversion unit. The input terminal of the adjustment current transmission conversion unit is connected to the adjustment current. The adjustment current transmission conversion unit performs transmission conversion on the adjustment current to obtain a first voltage adjustment voltage difference and a second voltage adjustment voltage difference. The voltage output adjustment unit adjusts the output level of the first voltage and the corresponding output current based on the first voltage adjustment voltage difference. The voltage output adjustment unit adjusts the output level of the second voltage and the corresponding output current based on the second voltage adjustment voltage difference.

2. The high-voltage DC voltage modulation circuit based on dual NMOS transistors according to claim 1, characterized in that, The output control module includes an operational amplifier unit, a voltage-controlled current unit, and a voltage limiting protection unit. The operational amplifier unit is connected to the control voltage and compares the control voltage with a reference voltage to obtain a voltage-controlled current voltage. The voltage-controlled current unit is connected to the voltage-controlled current voltage and generates the adjustment current based on the voltage-controlled current voltage. The voltage limiting protection unit is connected to the operational amplifier unit to limit the magnitude of the control voltage connected to the operational amplifier unit.

3. The high-voltage DC voltage modulation circuit based on dual NMOS transistors according to claim 2, characterized in that, The operational amplifier unit includes an operational amplifier, a first resistor, and a first capacitor. The inverting input terminal of the operational amplifier is connected to the control voltage via the first resistor connected in series. The non-inverting input terminal of the operational amplifier is grounded. One end of the first capacitor is connected to the inverting input terminal of the operational amplifier, and the other end of the first capacitor is connected to the output terminal of the operational amplifier. The output terminal of the operational amplifier outputs the voltage-controlled current voltage.

4. The high-voltage DC voltage modulation circuit based on dual NMOS transistors according to claim 3, characterized in that, The voltage-controlled current unit includes a PNP transistor and a second resistor. The emitter of the PNP transistor is grounded, and the base of the PNP transistor is connected to the output terminal of the operational amplifier via the second resistor in series. The collector of the PNP transistor outputs the adjustment current.

5. The high-voltage DC voltage modulation circuit based on dual NMOS transistors according to claim 3, characterized in that, The voltage limiting protection unit includes a first diode and a second diode. The anode of the first diode is grounded, and the cathode of the first diode is connected to the inverting input terminal of the operational amplifier. The anode of the second diode is connected to the inverting input terminal of the operational amplifier, and the cathode of the second diode is grounded.

6. The high-voltage DC voltage modulation circuit based on dual NMOS transistors according to claim 1, characterized in that, The first voltage is greater than the second voltage. The voltage output adjustment unit includes a first NMOS transistor, a second NMOS transistor, a first Zener diode, a second Zener diode, a third resistor, and a fourth resistor. The drain of the first NMOS transistor is connected to the first voltage. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor via the third resistor in series. The source of the second NMOS transistor is connected to the second voltage via the fourth resistor in series. The anode of the first Zener diode is connected to the source of the first NMOS transistor. The cathode of the first Zener diode is connected to the gate of the first NMOS transistor. The anode of the second Zener diode is connected to the source of the second NMOS transistor. The cathode of the second Zener diode is connected to the gate of the second NMOS transistor. The drain of the second NMOS transistor outputs the target voltage.

7. The high-voltage DC voltage modulation circuit based on dual NMOS transistors according to claim 6, characterized in that, The voltage output adjustment unit further includes two CRCπ type filters. The drain of the first NMOS transistor is connected to the first voltage after passing through the first CRCπ type filter in series. The source of the second NMOS transistor is connected to the second voltage after passing through the fourth resistor and the second CRCπ type filter in series.

8. The high-voltage DC voltage modulation circuit based on dual NMOS transistors according to claim 6, characterized in that, The current transfer conversion unit includes a third NMOS transistor, a fourth NMOS transistor, a third Zener diode, a fourth Zener diode, a fifth Zener diode, a sixth Zener diode, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor. The drain of the third NMOS transistor is connected to the drain of the first NMOS transistor. The gate of the third NMOS transistor is connected to the drain of the third NMOS transistor via the fifth resistor connected in series. The source of the third NMOS transistor is connected to the gate of the first NMOS transistor via the sixth resistor connected in series. One end of the seventh resistor is connected to the gate of the first NMOS transistor, and the other end of the seventh resistor is connected to the drain of the second NMOS transistor. The anode of the third Zener diode is connected to the source of the third NMOS transistor, and the cathode of the third Zener diode is connected to the gate of the third NMOS transistor. The anode of the fourth Zener diode is connected to the source of the third NMOS transistor. The fourth Zener diode has its cathode connected to the gate of the first NMOS transistor, its drain connected to the gate of the first NMOS transistor, its gate connected to the anode of the fifth Zener diode, its cathode connected to the adjustment current, its source connected to the gate of the second NMOS transistor, one end of the eighth resistor connected to the gate of the second NMOS transistor, the other end of the eighth resistor connected to the end of the fourth resistor connected to the second voltage, the anode of the sixth Zener diode connected to the source of the fourth NMOS transistor, its cathode connected to the gate of the fourth NMOS transistor, and one end of the ninth resistor connected to the gate of the fourth NMOS transistor, the other end of the ninth resistor connected to the end of the fourth resistor connected to the second voltage.

9. The high-voltage DC voltage modulation circuit based on dual NMOS transistors according to claim 3, characterized in that, The output negative feedback module includes an RC filter and a tenth resistor. One end of the tenth resistor is connected to the inverting input of the operational amplifier, and the other end of the tenth resistor is connected to the target voltage. The other end of the tenth resistor is also connected to the input of the RC filter. The target voltage after negative feedback is output to the outside through the output of the RC filter.

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