Burr removal circuit

Abstract

This application provides a low-latency glitch removal circuit. The glitch removal circuit includes a first signal edge detector, a second signal edge detector, a latch, and a control signal generator. The first signal edge detector is activated by a first control signal to detect the rising edge of the input signal and generate a first detection result. The second signal edge detector is activated by a second control signal to detect the falling edge of the input signal and generate a second detection result. The latch sets the generated output signal based on the first detection result and clears the generated output signal based on the second detection result. The control signal generator masks glitches on the input signal to generate a processed signal, and generates a first control signal and a second control signal based on the processed signal.

Description

Technical Field

[0001] This application relates to the field of analog integrated circuits, and more particularly to a low-latency signal glitches removal circuit. Background Technology

[0002] In chip applications, high-speed transmission protocols, such as the Improved Inter-Integrated Circuit (I3C) interface, are used for communication between integrated circuit devices. The key function of the I3C bus is to maximize data transmission speed while maintaining the basic functionality of the integrated circuit devices. However, in practical applications, integrated circuit devices participating in bus protocol communication can introduce noise coupling or ground bounce into the bus signal. These interferences can easily cause signal jitter, leading to uncontrollable signal glitches and resulting in abnormal logic functions of the integrated circuit devices. Due to the uncontrollable nature of these glitches, existing deglitch circuits typically require a large number of resistor-capacitor filters to remove them. These resistor-capacitor filters increase the delay time during signal transmission from input to output, significantly impacting the high-speed, low-latency data transmission specifications required by high-speed transmission protocols. Summary of the Invention

[0003] This application provides a low-latency glitch removal circuit that ensures the correctness and integrity of data transmission on the signal path while avoiding excessive time delay caused by glitch removal.

[0004] According to an embodiment of this application, the glitch removal circuit includes a first signal edge detector, a second signal edge detector, a latch, and a control signal generator. The first signal edge detector receives an input signal, and upon activation by a first control signal, detects the rising edge of the input signal and generates a first detection result. The second signal edge detector receives the input signal, and upon activation by a second control signal, detects the falling edge of the input signal and generates a second detection result. The latch, coupled to the first and second signal edge detectors, sets the generated output signal based on the first detection result and clears the generated output signal based on the second detection result. The control signal generator masks glitches on the input signal to generate a processed signal, and generates the first and second control signals based on the processed signal.

[0005] The glitch removal circuit in this embodiment generates multiple detection results by detecting the rising and falling edges of the input signal, and generates an output signal based on the generated detection results. In this way, the glitch removal circuit can generate an output signal by effectively filtering out glitches on the input signal with low latency, maintaining the real-time performance of signal transmission and meeting the specifications of high-speed signal transmission. Attached Figure Description

[0006] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0007] Figure 1 This is a schematic diagram of a burr removal circuit according to an embodiment of this application;

[0008] Figure 2 This is a circuit diagram of a burr removal circuit according to another embodiment of this application;

[0009] Figure 3 This is a circuit diagram of a burr removal circuit according to another embodiment of this application;

[0010] Figure 4 This is a signal waveform diagram of the burr removal circuit in an embodiment of this application;

[0011] Figure 5 This is a circuit diagram of a burr removal circuit according to another embodiment of this application;

[0012] Figure 6 This is a signal waveform diagram of the burr removal circuit in an embodiment of this application.

[0013] Explanation of icon numbers

[0014] 100, 200, 300, 500: Deburring circuit;

[0015] 111, 112, 211, 212, 311, 312, 511, 512: Signal edge detectors;

[0016] 120, 220, 320, 520: Control signal generator;

[0017] 130, 230, 330: Latches;

[0018] 221, 321, 521: Filters;

[0019] 222, 322, 522: Logic circuits;

[0020] AD1, AD2: AND gates;

[0021] BF: Buffer;

[0022] CK: Clock input;

[0023] D: Data terminal;

[0024] DFF1, DFF2: Triggers;

[0025] DS1, DS2: Detection results;

[0026] IN: Input signal;

[0027] INB: Inverting input signal;

[0028] IV1~IV9: Inverters;

[0029] N1, N2: Signals;

[0030] NO1, NO2: NOR gates;

[0031] ND1, ND2: NAND gates;

[0032] OUT: Output signal;

[0033] PIN: Processed signal;

[0034] Q: Output terminal;

[0035] R: Reset terminal;

[0036] RSTA, RSTB, PS, PSB: Control signals;

[0037] T1~T4: Time interval;

[0038] TP1~TP3: Time points;

[0039] VDD: Power supply voltage. Detailed Implementation

[0040] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0041] Please refer to Figure 1 , Figure 1This is a schematic diagram of a glitch removal circuit according to an embodiment of this application. The glitch removal circuit 100 includes signal edge detectors 111 and 112, a control signal generator 120, and a latch 130. Signal edge detector 111 receives the input signal IN. Signal edge detector 111 is activated according to the control signal RSTA to detect the rising edge of the input signal IN and generate a detection result DS1. Signal edge detector 112 also receives the input signal IN. Signal edge detector 112 is activated according to the control signal RSTB to detect the falling edge of the input signal IN and generate a detection result DS2. In this embodiment, the control signals RSTA and RSTB can be inverse signals. When signal edge detector 111 is activated, signal edge detector 112 is turned off; and when signal edge detector 112 is activated, signal edge detector 111 is turned off. That is, signal edge detectors 111 and 112 are not activated simultaneously.

[0042] Latch 130 is coupled to signal edge detectors 111 and 112. Latch 130 can receive detection results DS1 and DS2 generated by signal edge detectors 111 and 112, respectively. Latch 130 can generate an output signal OUT based on the detection results DS1 and DS2. Specifically, latch 130 can set the generated output signal OUT based on the detection result DS1 and clear the generated output signal OUT based on the detection result DS2.

[0043] Control signal generator 120 is coupled to signal edge detectors 111 and 112. Control signal generator 120 generates a processed signal by masking glitches on the input signal IN, and generates control signals RSTA and RSTB based on the processed signal. Specifically, based on the masking action of the input signal IN, control signal generator 120 may not react to glitches on the input signal IN, and may generate control signals RSTA and RSTB based on the logic value of the processed signal (without glitches). In one embodiment, when the processed signal is a logic value of 0, control signal generator 120 generates control signal RSTA to activate signal edge detector 111. Conversely, when the processed signal is a logic value of 1, control signal generator 120 generates control signal RSTB to activate signal edge detector 112.

[0044] Since the detection results DS1 and DS2 are generated based on the rising and falling edges of the input signal IN, respectively, the latch 130 sets the output signal OUT to logic 1 based on the detection result DS1 at the rising edge of the input signal IN; and the latch 130 clears the output signal OUT to logic 0 based on the detection result DS2 at the falling edge of the input signal IN.

[0045] It is worth mentioning that when a falling pulse glitch occurs near the rising edge of the input signal IN, this falling pulse wave can be shielded and will not appear in the processed signal. Therefore, the signal edge detector 112 will not be activated to generate the detection result DS2. In other words, the aforementioned falling pulse glitch will not affect the logic value of the output signal OUT. Conversely, when a rising pulse glitch occurs near the falling edge of the input signal IN, this rising pulse wave can also be shielded and will not appear in the processed signal. Therefore, the signal edge detector 111 will not be activated to generate the detection result DS1. In other words, the aforementioned rising pulse glitch will also not affect the logic value of the output signal OUT.

[0046] In this way, the glitch removal circuit 100 can effectively remove glitch on the input signal IN and quickly generate the output signal OUT, reducing the time delay between the output signal OUT and the input signal IN.

[0047] Incidentally, when the control signal RSTA is the first logic value and the control signal RSTB is the second logic value, the signal edge detector 111 can be activated and the signal edge detector 112 can be deactivated. When the control signal RSTA is the second logic value and the control signal RSTB is the first logic value, the signal edge detector 112 can be activated and the signal edge detector 111 can be deactivated. The first and second logic values ​​are complementary, and the first logic value can be either logic 0 or logic 1, without any particular restriction.

[0048] Please refer to Figure 2 , Figure 2This is a circuit diagram of a glitch removal circuit according to another embodiment of this application. The glitch removal circuit 200 includes signal edge detectors 211 and 212, a control signal generator 220, and a latch 230. The signal edge detector 211 includes a flip-flop DFF1, wherein the flip-flop DFF1 can be a D-type flip-flop. The flip-flop DFF1 has a data terminal D, a clock terminal CK, a reset terminal R, and an output terminal Q. The reset terminal R of the flip-flop DFF1 receives a control signal RSTA, the data terminal D of the flip-flop DFF1 receives a power supply voltage VDD as a first logic value, the clock terminal CK of the flip-flop DFF1 receives an input signal IN, and the output terminal Q of the flip-flop DFF1 generates a detection result DS1.

[0049] The signal edge detector 212 includes a flip-flop DFF2 and an inverter IV2. Flip-flop DFF2 can be a D-type flip-flop. Flip-flop DFF2 has a data terminal D, a clock terminal CK, a reset terminal R, and an output terminal Q. The reset terminal R of flip-flop DFF2 receives the control signal RSTB, the data terminal D of flip-flop DFF2 receives the power supply voltage VDD as the first logic value, the clock terminal CK of flip-flop DFF2 receives the inverted input signal INB, and the output terminal Q of flip-flop DFF2 generates the detection result DS2. Inverter IV2 receives the input signal IN and uses it to generate the inverted input signal INB.

[0050] In this embodiment, the first logic value received by the data terminal D of flip-flops DFF1 and DFF2 may not be provided by the power supply voltage VDD, but may be provided by any circuit component in the circuit that can generate the first logic value, without any specific restrictions.

[0051] In this embodiment, when the control signal RSTA is a first logic value (e.g., logic value 1), flip-flop DFF1 can be activated. Correspondingly, when the control signal RSTB is a second logic value (e.g., logic value 0), flip-flop DFF2 is reset and not activated. Conversely, when the control signal RSTB is a first logic value (e.g., logic value 1), flip-flop DFF2 can be activated. Correspondingly, when the control signal RSTA is a second logic value (e.g., logic value 0), flip-flop DFF1 is reset and not activated.

[0052] Flip-flop DFF1 is triggered at the rising edge of the input signal IN and generates a detection result DS1 based on the first logic value on the data terminal. Flip-flop DFF2 is triggered at the falling edge of the input signal IN and generates a detection result DS2 based on the first logic value on the data terminal. Furthermore, when the control signal RSTA prevents flip-flop DFF1 from being activated, flip-flop DFF1 can generate a detection result DS1 with the second logic value. Similarly, when the control signal RSTB prevents flip-flop DFF2 from being activated, flip-flop DFF2 can generate a detection result DS2 with the second logic value.

[0053] The latch 230 includes NOR gates NO1 and NO2 and an inverter IV1. NOR gates NO1 and NO2 are coupled to form an SR-Latch circuit. NOR gate NO1 receives the detection result DS1, signal N2, and control signal PSB to generate signal N1. NOR gate NO2 receives the detection result DS2 and signal N1 to generate signal N2. Inverter IV1 receives signal N1 and generates an output signal OUT. Specifically, when the detection result DS1 is a logic value of 1 (both control signal PSB and detection result DS2 are logic values ​​of 0), the output signal OUT can be set to a logic value of 1. Then, if the detection result DS1 is a logic value of 0 and the detection result DS2 changes to a logic value of 1, the output signal OUT can be cleared to a logic value of 0.

[0054] The control signal generator 220 includes a filter 221 and a logic circuit 222. The logic circuit 222 includes inverters IV3-IV5, AND gate AD1, and AND gate AD2. Filter 221 receives the input signal IN and filters out glitches on the input signal IN to generate the processed signal PIN. Inverters IV3 and IV4 are connected in series between filter 221 and AND gate AD1. AND gate AD1 receives the signal from the output of inverter IV4 and the control signal PS (i.e., the external reset input signal), and generates the control signal RSTB. AND gate AD2 receives the signal from the output of inverter IV3 and the control signal PS, and generates the control signal RSTA. The control signal PS can be the power-on reset signal for the circuit system. Inverter IV5 receives the control signal PS and generates the control signal PSB.

[0055] In this embodiment, filter 221 can be any type of resistor-capacitor filter without specific limitations. Filter 221 can be used to filter out glitches in the input signal IN with a width of less than 15 nanoseconds to generate the processed signal PIN.

[0056] Please refer to the following: Figure 3 , Figure 3This is a circuit diagram of a glitch removal circuit according to another embodiment of this application. The glitch removal circuit 300 includes signal edge detectors 311 and 312, a control signal generator 320, and a latch 330. The control signal generator 320 includes a filter 321 and logic circuit 322. The glitch removal circuit 300 is largely the same as the glitch removal circuit 200; the similarities will not be described in detail here. Figure 2 In embodiments different from the one described above, the latch 330 in this embodiment also includes inverters IV6 to IV9. An even number of inverters IV6 to IV7 are connected in series between the signal edge detector 311 and the NOR gate NO1. An even number of inverters IV8 to IV9 are connected in series between the signal edge detector 312 and the NOR gate NO2.

[0057] It is worth mentioning that in this embodiment, the number of inverters IV6 to IV7 connected in series between signal edge detector 311 and NOR gate NO1 is two. In other embodiments, the number of inverters connected in series between signal edge detector 311 and NOR gate NO1 can be any even number, without any limitation. Similarly, the number of inverters IV8 to IV9 connected in series between signal edge detector 312 and NOR gate NO2 is two. In other embodiments, the number of inverters connected in series between signal edge detector 312 and NOR gate NO2 can be any even number, without any limitation.

[0058] Please refer to the following as well. Figure 3 as well as Figure 4 ,in Figure 4 This is a signal waveform diagram of the glitch removal circuit according to an embodiment of this application. In the initial state, the control signal PS can be initially a logic value of 0 and then a logic value of 1 (the control signal PSB can be initially a logic value of 1 and then a logic value of 0), thus completing the initialization operation of the glitch removal circuit 300. Next, with the input signal IN at a logic value of 0, the control signals RSTA and RSTB can be logic values ​​of 1 and 0, respectively.

[0059] At time TP1, the input signal IN changes from logic 0 to logic 1, the signal edge detector 311 is activated, and can detect the rising edge of the input signal IN, generating a corresponding detection result DS1. It is noteworthy that in the time interval T2 following time interval T1, the input signal IN exhibits a falling pulse glitch, but since the signal edge detector 312 is not activated at this time, the falling edge of the input signal IN at this time will not be reflected in the detection result DS2.

[0060] Based on the state change action of the input signal IN (the logic value changes from 0 to 1), the latch signal 330 can generate signals N1 and N2 with logic values ​​of 0 and 1 respectively according to the detection result DS1, and set the output signal OUT to logic value 1.

[0061] At time point TP2, corresponding to the state transition of the input signal IN, the control signal generator 320 changes the control signal RSTA to logic value 0 and the control signal RSTB to logic value 1. Then, at time point TP3, the input signal IN changes from logic value 1 to logic value 0, the signal edge detector 312 is activated, and the falling edge of the input signal IN can be detected, generating the corresponding detection result DS2. It is noteworthy that in the time interval T4 following time interval T3, the input signal IN exhibits a rising pulse glitch, but since the signal edge detector 311 is not activated at this time, the rising edge of the input signal IN at this time will not be reflected in the detection result DS1.

[0062] Based on the state transition of the input signal IN (change from logic value 1 to logic value 0), the latch signal 330 can generate signals N1 and N2 with logic values ​​of 1 and 0 respectively according to the detection result DS2, and clear the output signal OUT to logic value 0.

[0063] As can be seen from the above explanation, the glitches on the input signal IN can be effectively eliminated through the operation of the glitch removal circuit 300. Furthermore, the time delay between the output signal OUT and the input signal IN can also be effectively reduced, improving the real-time performance and accuracy of signal transmission.

[0064] Please refer to Figure 5 , Figure 5 This is a circuit diagram of a glitch removal circuit according to another embodiment of this application. The glitch removal circuit 500 includes signal edge detectors 511 and 512, a control signal generator 520, and a latch 530. The control signal generator 520 includes a filter 521 and logic circuitry 522. The glitch removal circuit 500 is largely the same as the glitch removal circuit 300; the similarities will not be described in detail here. Figure 3 In embodiments that differ from the one described above, the latch 530 in this embodiment includes inverters IV6 and IV8, NAND gates ND1 and ND2, and a buffer BF.

[0065] In this circuit, inverter IV6 is positioned between signal edge detector 511 and NAND gate ND1, and inverter IV8 is positioned between signal edge detector 512 and NAND gate ND2. Inverters IV6 and IV8 invert the detection results DS1 and DS2, respectively. NAND gates ND1 and ND2, along with buffer BF, are coupled to form the circuit configuration of an SR latch, which generates an output signal OUT based on the inverted detection results DS1 and DS2. The three inputs of NAND gate ND1 receive the control signal PS, signal N2, and the inverted detection result DS1, respectively. The two inputs of NAND gate ND2 receive signal N1 and the inverted detection result DS2, respectively. NAND gates ND1 and ND2 generate signals N1 and N2, respectively.

[0066] When the detection result DS1 is logic value 0 and the detection result DS2 is logic value 1, the latch 530 can set the output signal OUT to logic value 1; when the detection result DS1 is logic value 1 and the detection result DS2 is logic value 0, the latch 530 can clear the output signal OUT to logic value 0.

[0067] It is worth mentioning that in this embodiment, the number of inverters IV6 connected in series between the signal edge detector 511 and the NAND gate ND1 is one. In other embodiments, the number of inverters connected in series between the signal edge detector 511 and the NAND gate ND1 can be any odd number, without any limitation. The number of inverters IV8 connected in series between the signal edge detector 512 and the NAND gate ND2 is one. In other embodiments, the number of inverters connected in series between the signal edge detector 512 and the NAND gate ND2 can be any odd number, without any limitation.

[0068] It is worth noting that in this embodiment, the latch 530 does not need to receive the inverted signal of the control signal PS (e.g., Figure 3 Therefore, the control signal generator 522 does not need to generate the control signal PSB.

[0069] Please refer to the following as well. Figure 5 as well as Figure 6 ,in Figure 6 This is a waveform diagram of the glitch removal circuit according to an embodiment of the present invention. In the initial state, the external reset input signal PS can first be a logic value of 0 and then a logic value of 1, thus completing the initialization operation of the glitch removal circuit 300. Next, with the input signal IN at a logic value of 0, the control signals RSTA and RSTB can be logic values ​​of 1 and 0, respectively.

[0070] At time TP1, the input signal IN changes from logic 0 to logic 1, the signal edge detector 511 is activated, and can detect the rising edge of the input signal IN, generating a corresponding detection result DS1. It is worth noting that in the time interval T2 following time interval T1, the input signal IN exhibits a falling pulse glitch, but since the signal edge detector 512 is not activated at this time, the falling edge of the input signal IN at this time will not be reflected in the detection result DS2.

[0071] Based on the state transition (or jump) action of the input signal IN (the logic value changes from 0 to 1), the latch signal 530 can generate signals N1 and N2 with logic values ​​of 1 and 0 respectively according to the detection result DS1, and set the output signal OUT to logic value 1.

[0072] At time point TP2, corresponding to the state transition of the input signal IN, the control signal generator 520 changes the control signal RSTA to logic value 0 and the control signal RSTB to logic value 1. Then, at time point TP3, the input signal IN changes from logic value 1 to logic value 0, the signal edge detector 512 is activated, and the falling edge of the input signal IN can be detected, generating the corresponding detection result DS2. It is noteworthy that in the time interval T4 following time interval T3, the input signal IN exhibits a rising pulse glitch, but since the signal edge detector 511 is not activated at this time, the rising edge of the input signal IN at this time will not be reflected in the detection result DS1.

[0073] Based on the state transition of the input signal IN (the logic value is changed from 1 to 0), the latch signal 330 can generate signals N1 and N2 with logic values ​​of 0 and 1 respectively according to the detection result DS2, and clear the output signal OUT to logic value 0.

[0074] Based on the above, the glitch removal circuit of this application embodiment can detect the rising and falling edges of the input signal and quickly generate the corresponding transition output signal, effectively reducing the time delay between the output signal and the input signal. Furthermore, the glitch removal circuit of this application embodiment uses two signal edge detectors to respectively activate the detection of the rising and falling edges of the input signal, eliminating the influence of glitches occurring during the transition of the input signal on the output signal, effectively eliminating input signal glitches, and maintaining the accuracy of the output signal.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A burr removal circuit, characterized in that, include: A first signal edge detector receives an input signal and, upon activation by a first control signal, detects the rising edge of the input signal and generates a first detection result. A second signal edge detector receives the input signal and, upon activation by a second control signal, detects the falling edge of the input signal and generates a second detection result. A latch, coupled to the first signal edge detector and the second signal edge detector, sets the generated output signal according to the first detection result and clears the generated output signal according to the second detection result; as well as A control signal generator that filters out glitches on the input signal to generate a processed signal, and generates the first control signal and the second control signal based on the processed signal. The control signal generator includes: A filter is used to receive the input signal and filter out glitches on the input signal to generate the processed signal; as well as A logic circuit, coupled to the filter, performs logical operations based on the processed signal and an external reset input signal to generate the first control signal and the second control signal.

2. The burr removal circuit according to claim 1, characterized in that, The first signal edge detector is a first flip-flop. The reset terminal of the first flip-flop receives the first control signal, the data terminal of the first flip-flop receives the first logic value, the clock terminal of the first flip-flop receives the input signal, and the output terminal of the first flip-flop generates the first detection result.

3. The burr removal circuit according to claim 2, characterized in that, The second signal edge detector includes: Inverter, receives the input signal and generates an inverted input signal; and The second flip-flop has a reset terminal that receives the second control signal, a data terminal that receives the first logic value, a clock terminal that receives the inverted input signal, and an output terminal that generates the second detection result.

4. The burr removal circuit according to claim 3, characterized in that, The first flip-flop and the second flip-flop are D-type flip-flops.

5. The burr removal circuit according to claim 1, characterized in that, When the first control signal is a first logic value, the first signal edge detector is activated; when the first control signal is a second logic value, the first signal edge detector is not activated. When the second control signal is the first logic value, the second signal edge detector is activated; when the second control signal is the second logic value, the second signal edge detector is not activated. The first logic value and the second logic value are not the same.

6. The burr removal circuit according to claim 1, characterized in that, The filter is used to filter out glitches with a width of less than 15 nanoseconds in the input signal to generate the processed signal.

7. The burr removal circuit according to claim 1, characterized in that, The filter is a resistor-capacitor filter.

8. The burr removal circuit according to claim 1, characterized in that, The logic circuit includes: The first inverter receives the processed signal and generates a first signal; The second inverter receives the first signal and generates the second signal; The third inverter receives the external reset input signal and generates a third control signal; A first AND gate receives the first signal and the external reset input signal, and generates the first control signal; and The second AND gate receives the second signal and the external reset input signal, and generates the second control signal.

9. The burr removal circuit according to claim 8, characterized in that, The latch includes: The first NOR gate performs NOR logic operation based on the first detection result, the third control signal, and the third signal to generate the fourth signal; The second NOR gate performs a NOR logic operation based on the second detection result and the fourth signal to generate the third signal; and The fourth inverter receives the fourth signal to generate the output signal.

10. The burr removal circuit according to claim 9, characterized in that, The latch also includes: An even number of fifth inverters are connected in series between the first signal edge detector and the first NOR gate; and An even number of sixth inverters are connected in series between the second signal edge detector and the second NOR gate.

11. The burr removal circuit according to claim 1, characterized in that, The logic circuit includes: The first inverter receives the processed signal and generates a first signal; The second inverter receives the first signal and generates the second signal; A first AND gate receives the first signal and the external reset input signal, and generates the first control signal; and The second AND gate receives the second signal and the external reset input signal, and generates the second control signal.

12. The burr removal circuit according to claim 11, characterized in that, The latch includes: An odd number of third inverters are connected in series and coupled together to receive the first detection result and generate the first inverted detection result; An odd number of fourth inverters are connected in series and coupled together to receive the second detection result and generate the second inverted detection result; The first NAND gate performs NAND logic operations based on the first inverted detection result, the external reset input signal, and the third signal to generate the fourth signal; The second NAND gate performs a NAND logic operation based on the second inversion detection result and the fourth signal to generate the third signal; and A buffer receives the fourth signal to generate the output signal.

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