QC-LDPC hierarchical decoding method and decoder for reducing pipeline conflicts
By implementing submatrix reordering and gain compensation techniques in the QC-LDPC hierarchical decoding method, the problems of reduced throughput and performance caused by pipeline conflicts are solved, thereby improving decoding efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI UNIV
- Filing Date
- 2023-07-03
- Publication Date
- 2026-07-31
AI Technical Summary
In existing technologies, layered decoding methods suffer from reduced throughput and performance due to data read/write conflicts caused by pipeline insertion during LLR updates.
By reordering the non-zero submatrices in the check matrix and delaying the use of updated contribution values in the overlapping submatrices, the number of conflicts is reduced. A gain compensation method is used to process variable node information, ensuring that the time when the contribution value is calculated by the previous layer does not lag behind the time when the variable node information is calculated by the current layer.
It effectively reduces pipeline conflicts, improves system throughput, and enhances decoding efficiency without affecting performance.
Smart Images
Figure CN116800278B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of information technology, and in particular to a QC-LDPC layered decoding method and decoder for reducing pipeline collisions. Background Technology
[0002] LDPC, with its near-Shannon limit characteristics, has made significant contributions to reliable communication and is widely used in various fields such as deep space communication, optical access networks, and data storage. Among numerous decoding algorithms, layered iterative decoding is more popular due to its superior decoding convergence. In hardware implementation, the clock frequency can be increased by inserting more pipeline stages, thereby increasing throughput. However, the addition of pipelines severely impacts the read / write conflict problem of message memory; when the next layer needs to utilize the updated LLR value, the corresponding update process of the previous layer has not yet completed.
[0003] Current solutions mainly involve several approaches. One is to insert stop-and-wait cycles during processing, only proceeding to the next layer after the previous layer has calculated the updated LLR value. These inserted stop-and-wait cycles are often numerous, severely impacting decoding throughput. Another approach is to process continuously without inserting stop-and-wait cycles, reading the old LLR value when encountering pipeline collisions and temporarily ignoring the contribution of the previous layer during current layer processing. However, an excessive number of collision submatrices can cause a significant performance degradation in the decoding method. Summary of the Invention
[0004] In view of the aforementioned shortcomings of existing technologies, the problem to be solved by this invention is the data read / write conflict caused by pipeline insertion during the actual LLR update process in the layered decoding method, resulting in problems such as decreased throughput and reduced performance. This invention provides a QC-LDPC layered decoding method and decoder to reduce pipeline conflicts. By reordering the processing of submatrices and delaying the use of updated contribution values, the number of conflicts is greatly reduced. When the time when the contribution value is calculated by the previous layer does not lag behind the time when the variable node information is calculated by the current layer, the decoding method can be guaranteed to have no difference from the theoretical performance. Even when this condition is not met, data update conflicts can be minimized, reducing performance loss and improving system throughput.
[0005] To achieve the above objectives, this invention provides a QC-LDPC layered decoding method for reducing pipeline collisions, comprising the following steps:
[0006] Before decoding, the processing order of the non-zero submatrices in the parity check matrix is reordered;
[0007] The submatrix is divided into non-overlapping submatrix and overlapping submatrix based on whether both adjacent layers need to be processed. The overlapping submatrix is defined as the one that needs to be processed by both the current layer and the previous layer. The gain contribution value generated by the overlapping submatrix is calculated during the process of updating the LLR in the previous layer.
[0008] When updating variable nodes, the variable node information of non-overlapping submatrices is obtained by subtracting the LLR value from the old check node information value of the previous round, and the overlapping submatrices are compensated by adding the gain contribution value.
[0009] The updated variable node information enters the verification node update module. The obtained verification node update value is multiplexed in three ways: one way is used directly to calculate the LLR update value, one way is cached for the next round of variable node information updates, and the other way is used to calculate the gain contribution value of this round.
[0010] Furthermore, before decoding, the processing order of the non-zero submatrices in the parity check matrix is reordered, specifically including:
[0011] The number of overlapping submatrices between any two layers of the parity check matrix is counted, and the processing order between layers is reordered to minimize the sum of the number of overlapping submatrices between adjacent layers.
[0012] Furthermore, the number of overlapping submatrices between any two layers of the parity-check matrix is counted, and the processing order between layers is reordered to minimize the sum of the number of overlapping submatrices between adjacent layers. Specifically, this includes:
[0013] The reordering of submatrices within a layer includes the read and write-back order of the LLR memory. The read order prioritizes processing submatrices that do not overlap with the previous layer, and then processes overlapping submatrices. The write-back order, on the other hand, requires ensuring that the current layer cannot read the updated value of the previous layer during the read operation, and then prioritizes processing submatrices that do not overlap with the previous layer.
[0014] Furthermore, the LLR values read from the LLR memory at each layer are values that have not been updated by the previous layer; the overlapping submatrix will have a corresponding gain contribution value added after the variable node computation unit has finished calculating to compensate for the use of unupdated LLR values. The calculation formula is as follows:
[0015]
[0016] in, Update the variable node values of the l-th layer in the it-th iteration after compensation. This indicates an LLR value that has not been updated. Gain represents the check node information value of the l-th layer in the (it-1)-th iteration. l-1,itThis represents the gain contribution value calculated in the (l-1)th layer during the it-th iteration.
[0017] Furthermore, the gain contribution value is obtained by subtracting the check node information of the current round from the corresponding cached check node information of the previous round. The calculation formula is as follows:
[0018]
[0019] Among them gain l，it This represents the gain contribution value calculated by layer l in the it-th iteration. and These represent the verification node information values calculated in the it-th and it-1th iterations, respectively.
[0020] Furthermore, the method for updating the verification node information is as follows:
[0021] The comparison module obtains the minimum, second minimum, and minimum index by comparing the absolute values of the variable node information corresponding to each non-zero submatrix. Simultaneously, it XORs the signs of each variable node information sequentially to obtain a total XOR sign. If the submatrix processing order index is equal to the minimum index, the absolute value of its check node information is the second minimum; otherwise, it is the minimum. The updated sign is the XOR result of the corresponding variable node sign and the obtained total XOR sign.
[0022] Furthermore, the system includes an LLR storage module, a barrel shifting module, a variable node calculation module, a gain compensation module, a check node processing module, a gain calculation module, and an LLR calculation module. The LLR value corresponding to the submatrix is read from the LLR storage module, shifted by the barrel shifting module, and then enters the variable node calculation module and the gain compensation module to obtain updated variable node information. The check node information obtained by the check node processing module is multiplexed in three ways: one way is used directly to calculate the updated LLR value, one way is cached for updating the variable node information in the next round, and the other way is used to calculate the gain contribution value in this round.
[0023] Technical effect
[0024] This invention provides a QC-LDPC layered decoding method to reduce pipeline conflicts. By reordering the processing order between layers, the number of overlapping submatrices is minimized. The processing order of submatrices within a layer is also reordered, and gain compensation is applied to variable node updates to postpone the use of gain contribution values. This overcomes the data update conflict problem caused by inserting multiple pipeline stages to increase the clock frequency, and avoids the problem of a serious decrease in the throughput of the decoding method due to the insertion of too many stop-wait cycles.
[0025] The following will further explain the concept, specific structure, and technical effects of the present invention in conjunction with the accompanying drawings, so as to fully understand the purpose, features, and effects of the present invention. Attached Figure Description
[0026] Figure 1 This is an example diagram of a production line conflict problem;
[0027] Figure 2 This is an overall architecture diagram of a QC-LDPC layered decoding method for reducing pipeline collisions according to a preferred embodiment of the present invention;
[0028] Figure 3 This is a specific processing example diagram of a QC-LDPC layered decoding method for reducing pipeline collisions according to the present invention. Detailed Implementation
[0029] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.
[0030] In the following description, specific details, such as particular internal procedures and techniques, are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will appreciate that the invention may be practiced in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of the invention with unnecessary detail.
[0031] like Figure 1 As shown, traditional methods can cause data update conflicts when processing submatrices at different levels consecutively. Figure 1 A three-stage pipeline is inserted, so that after three clock cycles, the updated LLR value can be obtained after all non-zero submatrices of each layer are read from memory. In the figure, the time when the LLR update value of the 2nd, 4th, and 6th submatrices of the first layer is obtained is significantly later than the time when the second layer is read.
[0032] like Figure 2As shown, this invention provides a QC-LDPC layered decoding method to reduce pipeline conflicts, including an LLR storage module, a barrel shifting module, a variable node calculation module, a gain compensation module, a check node calculation module, a gain calculation module, and an LLR calculation module. The LLR value corresponding to the submatrix is read from the storage module and shifted by the barrel shifting module before entering the variable node calculation module and the gain compensation module to obtain updated variable node information. The check node information obtained by the check node processing module is multiplexed in three ways: one way is used directly to calculate the updated LLR value, one way is cached for updating the variable node information in the next round, and the other way is used to calculate the gain contribution value in the current round.
[0033] Specifically, it includes:
[0034] S1. Before decoding, the processing order between layers of the parity check matrix needs to be reordered. Specifically, the number of overlapping submatrices between any two layers of the parity check matrix is counted, and the processing order between layers is reordered so that the sum of the number of overlapping submatrices between adjacent layers is minimized.
[0035] S2, after determining the inter-layer processing order, the processing order of submatrices within a layer is reordered. Specifically, the reordering of submatrices within a layer includes the read and write-back order of the LLR memory. The read order prioritizes processing submatrices that do not overlap with the previous layer in the current layer, then processes overlapping submatrices. The write-back order, on the other hand, requires ensuring that the current layer cannot read updated values from the previous layer during the read operation, and prioritizes processing submatrices that do not overlap with the previous layer in the next layer.
[0036] S3, the LLR values read from the LLR memory in each layer are values that have not been updated by the previous layer; the overlapping submatrix will be compensated for the use of unupdated LLR values by adding a corresponding gain contribution value after the variable node calculation unit has finished calculating. The calculation formula is:
[0037]
[0038] in, Update the variable node values of the first layer in the compensated itintimidated iteration. This indicates an LLR value that has not been updated. represents the verification node information value of layer 1 in the (it-1)th iteration, and gain represents the gain contribution value calculated by layer 1-1 in the (it)th iteration.
[0039] S4, the gain contribution value is obtained by subtracting the corresponding cached check node information from the check node information of the current round, and the calculation formula is:
[0040]
[0041] Where gainl,it represents the gain contribution value calculated in the first layer of the it-th iteration. and These represent the verification node information values calculated in the it-th and it-1th iterations, respectively.
[0042] S5, the method for updating the check node information is as follows: The comparison module obtains the minimum value, the second smallest value, and the minimum value index by comparing the absolute values of the variable node information corresponding to each non-zero submatrix. Simultaneously, it XORs the signs of each variable node information sequentially to obtain a total XOR sign. If the submatrix processing order index is equal to the minimum value index, then the absolute value of its check node information is the second smallest value; otherwise, it is the minimum value. The updated sign is the XOR result of the corresponding variable node sign and the obtained total XOR sign.
[0043] The following specific examples illustrate the detailed processing steps of a QC-LDPC layered decoding method for reducing pipeline collisions provided by this invention. Figure 3 As shown.
[0044] Step S1 involves counting the number of overlapping submatrices between any two layers and rearranging the processing order between layers. Since the number of layers and the number of non-zero submatrices in each layer are small in this example, reordering the layer processing order is not very effective and is not demonstrated here. However, it can achieve better results for the parity check matrices in various standard protocols used in practical applications.
[0045] Step S2 reorders the processing order of submatrices within a layer. For the LLR memory read order, the specific operation is as follows: The processing order of the first layer is determined by the overlapping submatrices between the first layer and its uppermost layer (the fourth layer). Since submatrices with indices 1, 2, and 4 overlap, submatrices with indices 5 and 6 are processed first, so the read order of the first layer is 6, 5, 1, 2, 4. Similarly, the processing order of the second layer is determined by the overlapping submatrices between the second and first layers, so the read order of the second layer is 7, 3, 6, 2, 4. For the LLR memory write order, the specific operation is as follows: To prevent data update conflicts between the first and third layers, the write-back order of the first layer is determined by the overlapping submatrices between the first and third layers. Since submatrices with indices 1, 4, and 5 overlap between the first and third layers, the LLR update values of submatrices 1, 4, and 5 are written back first, so the write-back order of the first layer's LLR update values is 1, 4, 5, 2, 6. Similarly, the write-back order for the second layer can be obtained as 2, 4, 3, 6, 7.
[0046] In step S3, starting from the second layer calculation of the first iteration, after passing through the variable node calculation unit, the overlapping submatrices of the current layer and the previous layer need to be compensated for by adding the gain contribution value.
[0047] In step S4, the compensated variable node information is directly fed into the verification node calculation module for verification node calculation, and simultaneously cached in RAM to await calculation of the LLR update value. To prevent read / write conflicts, the variable node information from adjacent layers is ping-pong cached sequentially into two different contiguous areas of RAM.
[0048] In step S5, the variable node information enters the check node calculation unit, yielding the minimum value, the second smallest value, the minimum value index, a total XOR symbol, and the symbol corresponding to each variable node. By comparing the submatrix processing order index with the minimum value index, and XORing the corresponding variable node symbol with the total XOR symbol, the corresponding check node update information can be obtained.
[0049] In step S6, the updated check node information is reused in three ways: one way directly participates in the calculation of the LLR update value; one way is cached into FIFO and used for the update calculation of the variable nodes in the next round; and the other way only needs to retrieve the check node information corresponding to the overlapping submatrix between the current layer and the next layer, and subtract it from the check node information cached in the previous round to obtain the gain contribution value of the current layer.
[0050] In step S7, the updated LLR values are rewritten into the LLR memory in sequence. This completes one iteration.
[0051] This invention provides a QC-LDPC layered decoding method to reduce pipeline collisions. Figure 3 In the illustrated embodiment, compared to the traditional layered decoding method with insertion wait cycles, the decoding time is reduced by 42.9% and the throughput is increased by 75% under the premise of successful decoding.
[0052] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.
Claims
1. A QC-LDPC layered decoding method for reducing pipeline collisions, characterized in that, Includes the following steps: Before decoding, the processing order of the non-zero submatrices in the parity check matrix is reordered; The submatrix is divided into non-overlapping submatrix and overlapping submatrix based on whether both adjacent layers need to be processed. The overlapping submatrix is defined as the one that needs to be processed by both the current layer and the previous layer. During the LLR update process of the previous layer, the gain contribution value generated by the overlapping submatrix is calculated at the same time. When updating variable nodes, the variable node information of non-overlapping submatrices is obtained by subtracting the LLR value from the old check node information value of the previous round, and the overlapping submatrices are compensated by adding the gain contribution value. The updated variable node information enters the verification node update module. The obtained verification node update value is multiplexed in three ways: one way is used directly to calculate the LLR update value, one way is cached for the next round of variable node information updates, and the other way is used to calculate the gain contribution value of this round.
2. The QC-LDPC layered decoding method for reducing pipeline collisions as described in claim 1, characterized in that, Before decoding, the processing order of the non-zero submatrices in the parity check matrix is reordered, specifically including: The number of overlapping submatrices between any two layers of the parity check matrix is counted, and the processing order between layers is reordered to minimize the sum of the number of overlapping submatrices between adjacent layers.
3. The QC-LDPC layered decoding method for reducing pipeline collisions as described in claim 2, characterized in that, The reordering of submatrices within a layer includes the read and write-back order of the LLR memory. The read order prioritizes processing submatrices that do not overlap with the previous layer in the current layer, and then processes overlapping submatrices. The write-back order requires ensuring that the current layer cannot read the updated value of the previous layer during the read operation, and then prioritizes processing submatrices that do not overlap with the previous layer in the next layer.
4. The QC-LDPC layered decoding method for reducing pipeline collisions as described in claim 3, characterized in that, Each layer reads an LLR value from the LLR memory that has not been updated by the previous layer; the overlapping submatrix is compensated for the use of unupdated LLR values by adding a corresponding gain contribution value after the variable node computation unit has finished calculating. The calculation formula is as follows: ， in, Update the variable node values of the l-th layer in the it-th iteration after compensation. This indicates an LLR value that has not been updated. This represents the verification node information value of the l-th layer in the (it-1)-th iteration. This represents the gain contribution value calculated in the (l-1)th layer during the it-th iteration.
5. The QC-LDPC layered decoding method for reducing pipeline collisions as described in claim 4, characterized in that, The gain contribution value is obtained by subtracting the corresponding cached check node information from the check node information of the current round. The calculation formula is as follows: ， in This represents the gain contribution value calculated by layer l in the it-th iteration. and These represent the verification node information values calculated in the it-th and it-1th iterations, respectively.
6. The QC-LDPC layered decoding method for reducing pipeline collisions as described in claim 1, characterized in that, The updated variable node information is entered into the verification node update module. The method for updating the verification node information is as follows: The comparison module obtains the minimum value, the second smallest value, and the minimum value index by comparing the absolute values of the variable node information corresponding to each non-zero submatrix. At the same time, it XORs the signs of each variable node information to obtain a total XOR sign. If the submatrix processing order index is equal to the minimum value index, the absolute value of its check node information is the second smallest value; otherwise, it is the minimum value. The updated sign is the XOR result of the corresponding variable node sign and the obtained total XOR sign.
7. The QC-LDPC layered decoding method for reducing pipeline collisions as described in claim 6, characterized in that, Both the LLR value and the gain contribution value need to be cyclically shifted to the left by a barrel shifter according to the offset value in the check matrix before subsequent calculations are performed.
8. A QC-LDPC layered decoder for reducing pipeline collisions applied to the method described in any one of claims 1-7, characterized in that, It includes an LLR storage module, a barrel shifting module, a variable node calculation module, a gain compensation module, a check node processing module, a gain calculation module, and an LLR calculation module. The LLR value corresponding to the submatrix is read from the LLR storage module and shifted by the barrel shifting module before entering the variable node calculation module and the gain compensation module to obtain updated variable node information. The check node information obtained by the check node processing module is multiplexed in three ways: one way is used directly to calculate the updated LLR value, one way is cached for the next round of variable node information updates, and the other way is used to calculate the gain contribution value of this round.