Method of forming a semiconductor memory structure

Abstract

A method for forming a semiconductor memory structure includes forming a first patterned hard mask layer on a conductive material, the first patterned hard mask layer including a plurality of first strip patterns and a plurality of mesa patterns connected to the first strip patterns, forming a second patterned hard mask layer on the first patterned hard mask layer, the second patterned hard mask layer including a plurality of second strip patterns overlapping the first strip patterns and a plurality of first wire patterns overlapping the mesa patterns, etching the first patterned hard mask layer using the second patterned hard mask layer, remaining portions of the first strip patterns forming a plurality of pad patterns and remaining portions of the mesa patterns forming a plurality of second wire patterns, and transferring the pad patterns and the second wire patterns to the conductive material. The present application can save the process cost of the semiconductor memory structure, reduce the process difficulty, and improve the manufacturing yield of the semiconductor device.

Description

Technical Field

[0001] This invention relates to a method for forming a semiconductor memory structure, and more particularly to a dynamic random access memory. Background Technology

[0002] To increase component density and improve overall performance within Dynamic Random Access Memory (DRAM) devices, current DRAM manufacturing technologies continue to focus on miniaturizing component sizes. Therefore, improving DRAM device manufacturing methods is a crucial issue that must be addressed. Summary of the Invention

[0003] This invention provides a method for forming a semiconductor memory structure. The method includes forming a conductive material on a dielectric structure and forming a first patterned hard mask layer on the conductive material. The first patterned hard mask layer includes a plurality of first strip patterns and pedestal patterns connected to the first strip patterns. The method further includes forming a second patterned hard mask layer on the first patterned hard mask layer. The second patterned hard mask layer includes a plurality of second strip patterns overlapping the first strip patterns and a plurality of first conductive patterns overlapping the pedestal patterns. The method further includes etching the first patterned hard mask layer using the second patterned hard mask layer, where the remaining portions of the first strip patterns form a plurality of pad patterns, and the remaining portions of the pedestal patterns form a plurality of second conductive patterns. The method further includes transferring the pad patterns and second conductive patterns to the conductive material.

[0004] This invention provides a method for forming a semiconductor memory structure. The method includes forming a first hard mask layer on a semiconductor substrate, the semiconductor substrate including a memory cell array region and a peripheral circuit region. The method further includes forming a plurality of first elongated patterns on the first hard mask layer, the first elongated patterns continuously extending in the memory cell array region and the peripheral circuit region. The method also includes forming a photoresist pattern on the first elongated patterns to cover the peripheral circuit region and expose the memory cell array region; etching the first hard mask layer using the photoresist pattern and the first elongated patterns to form a plurality of second elongated patterns in the memory cell array region and a raised platform pattern in the peripheral circuit region; and patterning the second elongated patterns and raised platform patterns of the first hard mask layer to form a plurality of pad patterns in the memory cell array region and a plurality of wire patterns in the peripheral circuit region, respectively.

[0005] This invention can save on the manufacturing costs of semiconductor memory structures, reduce the difficulty of the process, and improve the manufacturing yield of semiconductor devices. Attached Figure Description

[0006] To make the features and advantages of the present invention more apparent and understandable, different embodiments are described below in detail with reference to the accompanying drawings:

[0007] Figures 1 to 17 These are cross-sectional schematic diagrams showing different stages of forming a semiconductor memory structure according to some embodiments of the present invention.

[0008] Figure 5-1 , Figure 6-1 , Figure 8-1 , Figure 10-1 , Figure 12-1 , Figure 13-1 , Figure 15-1 , Figure 17-1 This is a planar schematic diagram of a semiconductor memory structure according to some embodiments of the present invention.

[0009] Icon labels:

[0010] 50A: Memory cell array area;

[0011] 50B: Peripheral circuit area;

[0012] 100: Semiconductor memory structure;

[0013] 102: Substrate;

[0014] 104: Dielectric structure;

[0015] 106: Opening;

[0016] 108, 160: Contact plugs;

[0017] 110: Conductive materials;

[0018] 112, 114, 116, 118, 120, 122, 124, 126, 128, 140, 142, 144, 146, 148, 150, 154, 156: Hard mask layer;

[0019] 112A, 112B, 114A, 114B, 116A, 116B, 116C, 116D, 118A, 118B, 120A, 120B, 122A, 124A, 126A, 140A, 140B, 142A, 142B, 144A, 144B, 146A, 146B, 154A, 154B, 156A, 156B: Patterned hard mask layers;

[0020] 130, 152, 158: Patterned photoresist layers;

[0021] 130A, 152A, 158A, 202, 204, 2041, 2042, 208A, 208A1, 208A2: Long striped patterns;

[0022] 132, 132A: Spacer layer;

[0023] 134, 134A, 138, 138A: Filler layer;

[0024] 136: Photoresist pattern;

[0025] 152B, 158B, 208B, 208B1, 208B2: Conductor patterns;

[0026] 152D, 158D, 208D: Dummy patterns;

[0027] 162: Conductive pad;

[0028] 162D: Dummy conductive pad;

[0029] 164: Wire;

[0030] 206: High platform pattern;

[0031] 210: Solder pad pattern;

[0032] 210D: Dummy solder pad pattern;

[0033] D1: First direction;

[0034] D2: Second direction;

[0035] D3: Third direction. Detailed Implementation

[0036] Please refer to this first. Figure 17 and Figure 17-1 The semiconductor memory structure 100 includes a substrate 102 and a dielectric structure 104 disposed on the substrate 102. The substrate 102 may define various device regions, such as a memory cell array region 50A, a peripheral circuit region 50B, and / or other applicable device regions. Figures 1-17 The left side shows memory cell array area 50A, which corresponds to section AA in the plan view; Figures 1-17 The right-hand portion shows the peripheral circuit area 50B, which corresponds to section BB in the plan view. The peripheral circuit area 50B may be disposed adjacent to the memory cell array area 50A. Memory cells (e.g., dynamic random access memory) are formed in the memory cell array area 50A for data storage. Peripheral circuitry is formed in the peripheral circuit area 50B for accessing and / or controlling the memory cells in the memory cell array area 50A, for example, performing read, write, and erase operations.

[0037] In some embodiments, substrate 102 may be or include a semiconductor substrate, which may be an elemental semiconductor substrate or a compound semiconductor substrate.

[0038] In the memory cell array region 50A of substrate 102, a memory cell may include a gate structure (acting as a word line) buried in the semiconductor substrate and a bit line disposed on the semiconductor substrate. The word line extends through the active region of substrate 102 and combines with the source / drain regions in the active region to form a buried transistor. The bit line may be electrically connected to the source / drain regions in the active region. A contact plug 160 is disposed in the dielectric structure 104 and electrically connected to another source / drain region in the active region. A conductive pad (or landing pad) 162 is disposed on the dielectric structure 104 and correspondingly disposed on the contact plug 160. In addition, a dummy conductive pad 162D is disposed at the edge of the memory cell array region 50A.

[0039] In the peripheral circuit region 50B of substrate 102, the peripheral circuit device may include planar transistors and / or multi-gate transistors, which include gate structures formed on the upper surface of the semiconductor substrate. A contact plug 108 is disposed in the dielectric structure 104, and a wire 164 is disposed on the dielectric structure 104. The wire 164 is electrically connected to the gate structure and / or source / drain region of the peripheral circuit device through the contact plug 108.

[0040] The conductive pads 162 in the memory cell array region 50A and the wires 164 in the peripheral circuit region 50B can be part of an interconnect structure and are metallized patterns located at the same level (e.g., a zero-layer metallization layer (M1)). In this embodiment of the invention, the conductive pads 162 and the wires 164 are simultaneously formed by transferring the pad pattern 210 and the wire pattern 208B to a conductive material using patterned hard mask layers 112A and 112B. The method for forming the conductive pads 162 in the memory cell array region 50A and the wires 164 in the peripheral circuit region 50B will be described in detail below.

[0041] Please refer to Figure 1 A dielectric structure 104 is formed on the substrate 102. The dielectric structure 104 may include one or more dielectric materials, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), the aforementioned multilayers, and / or combinations thereof. An opening 106 may be formed in the dielectric structure 104 in the memory cell array region 50A by a patterning process (e.g., including photolithography and etching processes).

[0042] Please refer to Figure 2 One or more conductive materials 110 are formed on the dielectric structure 104 to excessively fill the opening 106. The portion of the conductive material 110 formed in the opening 106 serves as… Figure 17The contact plug 160 is shown. The conductive material 110 may comprise polysilicon, metal silicides (e.g., cobalt silicide (CoSi), nickel silicide (NiSi), titanium silicide (TiSi), tungsten silicide (WSi)), metal nitrides (e.g., titanium nitride (TiN) or tantalum nitride (TaN)), metallic materials (e.g., tungsten (W), aluminum (Al), copper (Cu), cobalt (Co) or ruthenium (Ru)), the aforementioned multilayers, and / or combinations thereof.

[0043] Next, multiple hard masking layers 112-128 are sequentially formed on the conductive material 110. Hard masking layer 112 is made of a carbon-rich material, such as diamond-like carbon (DLC), a high-selectivity transparency (HST) film, and / or spin-on carbon (SOC). Hard masking layer 114 is made of a semiconductor material, such as polysilicon. Hard masking layer 116 is made of a silicon-rich dielectric material, such as silicon-rich silicon oxynitride (Si-SiON) and / or a silicon-rich antireflective layer (Si-BARC). Hard masking layer 118 is made of a carbon-rich material, such as a high-selectivity transparency film, diamond-like carbon, and / or spin-on carbon. Hard masking layer 120 is made of a nitride layer, such as silicon nitride. Hard masking layer 122 is made of an oxide layer, such as silicon oxide. Hard masking layer 124 is made of a semiconductor material, such as polysilicon. The hard mask layer 126 is made of a carbon-rich material, such as spin-coated carbon, diamond-like carbon, and / or a highly selective transparent film. The hard mask layer 128 is made of a silicon-rich dielectric material, such as a silicon-rich antireflective layer (Si-BARC) and / or silicon-rich silicon oxynitride (Si-SiON).

[0044] Next, a patterned photoresist layer 130 is formed on the hard mask layer 128 using a first photolithography process. The patterned photoresist layer 130 has elongated patterns 130A spaced approximately equidistant from each other and is arranged in the memory cell array region 50A and the peripheral circuit region 50B. In some embodiments, the first photolithography process employs immersion coating.

[0045] Please refer to Figure 3Using a patterned photoresist layer 130, an etching process is performed on the semiconductor memory structure 100 to sequentially etch away portions of hard mask layers 128, 126, and 124 that are not covered by the patterned photoresist layer 130. The patterned photoresist layer 130 and hard mask layer 128 can be completely consumed during the etching process or removed by additional processes, such as etching or ashing. The etching process transfers the elongated pattern 130A of the patterned photoresist layer 130 to the hard mask layers 126 and 124 to form patterned hard mask layers 126A and 124A. The patterned hard mask layers 126A and 124A constitute the elongated pattern 202, also known as the core pattern.

[0046] Please refer to Figure 4 A spacer layer 132 is formed along the sidewalls and top surface of the strip pattern 202 and the top surface of the hard mask layer 122. Next, a filler layer 134 is formed over the spacer layer 132, overfilling the gaps between the strip patterns 202. Then, the portions of the spacer layer 132 and the filler layer 134 above the top surface of the strip pattern 202 are removed to expose the patterned hard mask layer 126A. The spacer layer 132 is made of an oxide layer, such as silicon oxide. The filler layer 134 is made of spin-coated carbon.

[0047] Please refer to Figure 5 and Figure 5-1 The etching process removes portions of the spacer layer 132 not covered by the fill layer 134, and further removes portions of the hard mask layer 122 not covered by the fill layer 134 until the hard mask layer 120 is exposed. Because the material of the spacer layer 132 (e.g., silicon oxide) has a significant difference in etching selectivity compared to the materials of the fill layer 134 and the hard mask layer 126 (e.g., spin-coated carbon), the etching process can self-align the removal of the spacer layer 132 without the need to form an additional mask. The etching process also etches portions of the fill layer 134 and the patterned hard mask layer 126A.

[0048] After the etching process, the remaining portion of the hard mask layer 122 is designated as 122A, the remaining portion of the spacer layer 132 is designated as 132A, and the remaining portion of the fill layer 134 is designated as 134A. The patterned hard mask layers 126A and 124A, together with the underlying patterned hard mask layer 122A, form a strip pattern 2041; the fill layer 134A, the spacer layer 132A, and the underlying patterned hard mask layer 122A form a strip pattern 2042.

[0049] Long strip patterns 2041 and 2042 are alternately arranged in the memory cell array area 50A and the peripheral circuit area 50B. For example... Figure 5-1As shown, strip patterns 204 (including strip patterns 2041 and 2042) extend in a first direction D1 and are spaced approximately equidistant from each other in a second direction D2. In some embodiments, bit lines of memory cells extend along the second direction D2, while word lines of memory cells extend along a third direction D3. The first direction D1 is not perpendicular to the second direction D2, and the second direction D2 is approximately perpendicular to the third direction D3.

[0050] Then, the fill layer 134A and the patterned hard mask layer 126A can be removed.

[0051] Please refer to Figure 6 and Figure 6-1 A second photolithography process forms a photoresist pattern 136 covering the stripe pattern 204 in the peripheral circuit region 50B and exposing the stripe pattern 204 in the memory cell array region 50A. The photoresist pattern 136 is configured to prevent the stripe pattern 204 in the peripheral circuit region 50B from transferring to the underlying hard mask layer. In some embodiments, the second photolithography process uses a low-cost medium ultraviolet (MUV) mask technique.

[0052] Please refer to Figure 7 The semiconductor memory structure 100 is etched using a striped pattern 204 and a photoresist pattern 136 to sequentially etch the portions of the hard mask layer 120 and hard mask layer 118 not covered by the striped pattern 204 and the photoresist pattern 136. The spacer layer 132A and the patterned hard mask layer 124A in the memory cell array region 50A, and the photoresist pattern 136 in the peripheral circuit region 50B, can be completely consumed during the etching process or removed by an additional process. The etching process transfers the striped pattern 204 in the memory cell array region 50A to the hard mask layer 120 and hard mask layer 118 to form the patterned hard mask layer 120A and the patterned hard mask layer 118A. The patterned hard mask layer 120A and the patterned hard mask layer 118A have the striped pattern 204. Due to the coverage of the photoresist pattern 136, the strip pattern 204 is not transferred to the hard mask layer 120 and hard mask layer 118 in the peripheral circuit region 50B. The photoresist pattern 136 of the peripheral circuit region 50B is transferred to the hard mask layer 120 and hard mask layer 118 to form patterned hard mask layers 120B and 118B. The patterned hard mask layers 120B and 118B constitute the platform pattern 206.

[0053] Please refer to Figure 8 and Figure 8-1An etching process is performed on the semiconductor memory structure 100 to transfer the strip pattern 204 in the memory cell array region 50A to the hard mask layer 116 to form a patterned hard mask layer 116A, and to transfer the raised pattern 206 in the peripheral circuit region 50B to the hard mask layer 116 to form a patterned hard mask layer 116B. The patterned hard mask layers 122A and 120A in the memory cell array region 50A can be completely consumed during the etching process. The etching process can be controlled so that the strip pattern 204 in the peripheral circuit region 50B is completely consumed before being transferred to the patterned hard mask layer 118B, or the strip pattern 204 in the peripheral circuit region 50B can be removed by an additional process, thereby preventing the strip pattern 204 from being transferred to the raised pattern 206. The elevated pattern 206 is connected to multiple elongated patterns 204, and the width of the elevated pattern 206 in the second direction D2 is greater than the width of the elongated patterns 204 in the second direction D2.

[0054] Due to the loading effect of the etching process, during the etching process, the photoresist pattern 136 ( Figure 6 The portion near the boundary between the memory cell array region 50A and the peripheral circuit region 50B may be lost faster than the portion farther from the boundary. When the selectivity difference between the photoresist pattern 136 and the hard mask layer 120 and / or hard mask layer 118 is small, when the strip pattern 204 in the memory cell array region 50A is transferred to the hard mask layer 120 and hard mask layer 118, some strip patterns 204 in the peripheral circuit region 50B near the region boundary may also be transferred to the hard mask layer 120 and hard mask layer 118, and then further transferred to the hard mask layer 116. Thus, the conductor pattern 208B at the region boundary ( Figure 17 You may encounter a pattern fail problem (or array punch through).

[0055] According to an embodiment of the present invention, since the hard mask layer 116 is a planar layer that has not yet been patterned, the etching amount in the memory cell array region 50A can be increased by adjusting the parameters of the etching process (e.g., a larger bias power, a higher etchant flow rate, and / or other suitable parameters) while maintaining a lower etching amount for the photoresist pattern 136, resulting in a large selectivity difference between the photoresist pattern 136 and the hard mask layer 120 and / or the hard mask layer 118. Therefore, the risk of the strip pattern 204 at the region boundary being transferred to the hard mask layer 116 in the peripheral circuit region 50B can be significantly reduced. Thus, the pattern failure problem encountered by the wire pattern 208B at the boundary between the memory cell array region 50A and the peripheral circuit region 50B is avoided, thereby improving the manufacturing yield of the semiconductor device.

[0056] Then, the patterned hard mask layer 118A and the patterned hard mask layer 118B can be removed.

[0057] Please refer to Figure 9 A fill layer 138 is formed over the patterned hard mask layers 116A and 116B, excessively filling the gaps between the patterned hard mask layers 116A. Next, the portion of the fill layer 138 over the patterned hard mask layers 116A and 116B is removed to expose the patterned hard mask layers 116A and 116B. The fill layer 134 is made of an oxide layer, such as silicon oxide.

[0058] Please refer to Figure 10 Multiple hard masking layers 140-150 are sequentially formed over patterned hard masking layers 116A and 116B and filler layer 138. Hard masking layer 140 is made of carbon-rich materials, such as highly selective transparent films, diamond-like carbon, and / or spin-coated carbon. Hard masking layer 142 is made of nitride layers, such as silicon nitride. Hard masking layer 144 is made of oxide layers, such as silicon oxide. Hard masking layer 146 is made of semiconductor materials, such as polysilicon. Hard masking layer 148 is made of carbon-rich materials, such as spin-coated carbon, diamond-like carbon, and / or highly selective transparent films. Hard masking layer 150 is made of silicon-rich dielectric materials, such as silicon-rich antireflective layers (Si-BARC) and / or silicon-rich silicon oxynitride (Si-SiON).

[0059] Next, a patterned photoresist layer 152 is formed on the hard mask layer 150 using a third photolithography process, such as... Figure 10 and Figure 10-1 As shown. In the memory cell array region 50A, the patterned photoresist layer 152 has an elongated pattern 152A and a dummy pattern 152D located at the edge of the memory cell array region 50A. In the peripheral circuit region 50B, the patterned photoresist layer 152 has a wire pattern 152B. The elongated patterns 152A extend in the second direction D2 and are spaced approximately equidistant from each other. In some embodiments, the third photolithography process employs an dip-coating method.

[0060] Please refer to Figure 11Using a patterned photoresist layer 152, an etching process is performed on the semiconductor memory structure 100 to sequentially etch away portions of hard mask layers 150, 148, and 146 that are not covered by the patterned photoresist layer 152. The patterned photoresist layer 152, hard mask layers 150, and hard mask layer 148 can be completely consumed during the etching process or removed through an additional process. The etching process transfers the stripe pattern 152A and dummy pattern 152D of the patterned photoresist layer 152 to the hard mask layer 146 to form a patterned hard mask layer 146A. The patterned hard mask layer 146A has a stripe pattern 208A1 and a dummy pattern (not shown). A wire pattern 152B is transferred to the hard mask layer 146 to form a patterned hard mask layer 146B. The patterned hard mask layer 146B has a wire pattern 208B1.

[0061] Please refer to Figure 12 Hard masking layers 154 and 156 are sequentially formed on hard masking layer 144. Hard masking layer 154 is made of carbon-rich materials, such as spin-coated carbon, diamond-like carbon, and / or highly selective transparent films. Hard masking layer 156 is made of silicon-rich dielectric materials, such as silicon-rich antireflective layers (Si-BARC) and / or silicon-rich silicon oxynitride (Si-SiON).

[0062] Next, a patterned photoresist layer 158 is formed on the hard mask layer 156 using a fourth photolithography process, such as... Figure 12 and Figure 12-1 As shown. In the memory cell array region 50A, the patterned photoresist layer 158 has a stripe pattern 158A and a dummy pattern 158D located at the edge of the memory cell array region 50A. In the peripheral circuit region 50B, the patterned photoresist layer 158 has a wire pattern 158B. The stripe patterns 158A extend in the second direction D2 and are spaced approximately equidistant from each other. Furthermore, the stripe patterns 158A are offset from the stripe patterns 208A1 of the patterned hard mask layer 146A, and the wire patterns 158B are offset from the wire patterns 208B1 of the patterned hard mask layer 146B. In some embodiments, the fourth photolithography process employs an dip-coating method.

[0063] Please refer to Figure 13 and Figure 13-1Using a patterned photoresist layer 158, an etching process is performed on the semiconductor memory structure 100 to sequentially etch away portions of hard mask layers 156 and 154 not covered by the patterned photoresist layer 158. The patterned photoresist layer 158 can be completely consumed during the etching process or removed by an additional process. The etching process transfers the strip pattern 158A and dummy pattern 158D of the patterned photoresist layer 158 to the hard mask layers 156 and 154 to form patterned hard mask layers 156A and 154A. The patterned hard mask layers 156A and 154A have a strip pattern 208A2 and a dummy pattern 208D. A wire pattern 158B is transferred to the hard mask layers 156 and 154 to form patterned hard mask layers 156B and 154B. Patterned hard mask layer 156B and patterned hard mask layer 154B constitute conductor pattern 208B2.

[0064] Forming the strip pattern 208A (including strip pattern 208A1 and strip pattern 208A2) in the memory cell array region 50A and the wire pattern 208B (including wire pattern 208B1 and wire pattern 208B2) in the peripheral circuit region 50B using two photolithography processes can increase the pattern density, which helps in the miniaturization of semiconductor memory devices.

[0065] Please refer to Figure 14 An etching process is performed on the semiconductor memory structure 100 to transfer the strip pattern 208A in the memory cell array region 50A to hard mask layers 144, 142, and 140 to form patterned hard mask layers 144A, 142A, and 140A. Similarly, the wire pattern 208B in the peripheral circuit region 50B is transferred to hard mask layers 144, 142, and 140 to form patterned hard mask layers 144B, 142B, and 140B. Although not shown, a dummy pattern 208D is also transferred to hard mask layers 144, 142, and 140. Patterned hard mask layers 156A, 156B, 154A, 154B, 146A, and 146B can be completely consumed during the etching process or removed by an additional process.

[0066] Please refer to Figure 15 and Figure 15-1Next, using strip pattern 208A, dummy pattern 208D, and wire pattern 208B, an etching process is performed on the semiconductor memory structure 100 to etch away the patterned hard mask layers 116A and 116B, as well as the portions of the fill layer 138 not covered by the strip pattern 208A, dummy pattern 208D, and wire pattern 208B. The patterned hard mask layers 144A, 144B, 142A, and 142B can be completely consumed in the etching process or removed through an additional process.

[0067] The remaining portion of the patterned hard mask layer 116A after the etching process is designated as the patterned hard mask layer 116C. In the center of the memory cell array region 50A, the strip pattern 204 is patterned as a pad pattern 210, while at the edges of the memory cell array region 50A, the strip pattern 204 is patterned as a dummy pad pattern 210D. The remaining portion of the fill layer 138 after the etching process is designated as 138A. For simplicity and clarity, Figure 15-1 The fill layer 138A is not shown. In the peripheral circuit area 50B, the etching process transfers the conductor pattern 208B to the patterned hard mask layer 116B, and the remaining portion of the patterned hard mask layer 116B is marked as the patterned hard mask layer 116D.

[0068] According to an embodiment of the present invention, the solder pad pattern 210 is formed through two patterning processes. Specifically, the hard mask layer 116 is first patterned (through a first photolithography process and a second photolithography process) to form a strip pattern 204, and then a second patterning process (through a third and a fourth photolithography process) is performed to form the solder pad pattern 210. In some cases, if the hard mask layer 116 is first patterned into a strip pattern 208 through the third and fourth photolithography processes, and then the solder pad pattern 210 is patterned from the strip pattern 208 through the first and second photolithography processes, it is not possible to achieve the aforementioned results. Figure 8 The increased etching intensity in the memory cell array region 50A is because this could cause the pad pattern in the memory cell array region to deform due to excessive etching. Therefore, the process steps disclosed in this embodiment of the invention can relax the tolerance of the etching process for forming the pad pattern 210.

[0069] Please refer to Figure 16An etching process is performed on the semiconductor memory structure 100 to transfer the pad pattern 210 and dummy pad pattern 210D in the memory cell array region 50A to the hard mask layer 114 and hard mask layer 112 to form patterned hard mask layers 114A and 112A. Similarly, the wire pattern 208B in the peripheral circuit region 50B is transferred to the hard mask layer 114 and hard mask layer 112 to form patterned hard mask layers 114B and 112B. The patterned hard mask layers 140A and 140B can be completely consumed during the etching process or removed by an additional process. Furthermore, since the material of the fill layer 138 (e.g., silicon oxide) has a significant difference in etching selectivity compared to the hard mask layer 116 (e.g., silicon-rich silicon oxynitride), the fill layer 138A can be completely removed during the etching process.

[0070] Please refer to Figure 17 and Figure 17-1 An etching process is performed on the semiconductor memory structure 100 to transfer the pad pattern 210 and dummy pad pattern 210D in the memory cell array region 50A to the conductive material 110 to form conductive pad 162 and dummy conductive pad 162D. The wire pattern 208B in the peripheral circuit region 50B is also transferred to the conductive material 110 to form wire 164. The patterned hard mask layers 116C, 116D, 114A, and 114B can be completely consumed during the etching process or removed through an additional process.

[0071] Subsequently, the patterned hard mask layer 112A and patterned hard mask layer 112B can be removed by etching or ashing processes to expose the conductive pad 162, the dummy conductive pad 162D, and the wire 164. In some embodiments, a capacitor can be formed on the conductive pad 162. The capacitor may include a lower electrode layer contacting the conductive pad 162, a capacitor dielectric layer above the lower electrode layer, and an upper electrode layer above the capacitor dielectric layer. The lower electrode layer is electrically coupled to the source / drain region within the active region via the conductive pad 162 and the contact plug 160.

[0072] This invention utilizes a triple dip-coating process and a single medium-ultraviolet photomask technique to simultaneously form the pad pattern 210 of the memory cell array region 50A and the wire pattern 208B of the peripheral circuit region 50B. Therefore, compared to forming the pad pattern of the memory cell array region and the wire pattern of the peripheral circuit region separately, this invention saves at least one photolithography process (e.g., dip-coating). This reduces the process cost and complexity of the semiconductor memory structure.

[0073] Based on the above, the semiconductor memory structure formation method of this embodiment can significantly reduce the risk of pattern transfer from the memory cell array region to the peripheral circuit region. Therefore, it avoids pattern failure issues at the boundary between the memory cell array region and the peripheral circuit region, thereby improving the manufacturing yield of the semiconductor device.

[0074] While the present invention has been disclosed above with reference to the foregoing embodiments, it is not intended to limit the invention. Any person skilled in the art can make modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of patent protection for this invention shall be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor memory structure, characterized in that, include: A conductive material is formed on a dielectric structure; A first patterned hard mask layer is formed on the conductive material, wherein the first patterned hard mask layer includes a plurality of first strip patterns and a raised platform pattern connected to the plurality of first strip patterns; A second patterned hard mask layer is formed on the first patterned hard mask layer, wherein the second patterned hard mask layer includes a plurality of second strip patterns that overlap the plurality of first strip patterns, a plurality of first conductor patterns that overlap the platform pattern, and a plurality of fourth strip patterns that alternate with the plurality of second strip patterns. The first patterned hard mask layer is etched using the second patterned hard mask layer, wherein the remaining portions of the plurality of first strip patterns form a plurality of pad patterns, and the remaining portions of the platform patterns form a plurality of second conductor patterns. as well as The multiple pad patterns and the multiple second conductor patterns are transferred to the conductive material.

2. The method for forming a semiconductor memory structure as described in claim 1, characterized in that, The plurality of first elongated patterns extend in a first direction, and the plurality of second elongated patterns extend in a second direction, wherein the second direction is not parallel to the first direction.

3. The method for forming a semiconductor memory structure as described in claim 1, characterized in that, Furthermore, this includes the process before forming the second patterned hard mask layer over the first patterned hard mask layer: A filling layer is formed on and between the plurality of first elongated patterns; and Remove the portion of the fill layer that is above the plurality of first strip patterns.

4. The method for forming a semiconductor memory structure as described in claim 3, characterized in that, Including: Simultaneously, the filling layer is etched using the second patterned hard mask layer; and the first patterned hard mask layer is etched using the second patterned hard mask layer. The filler layer is completely removed before transferring the multiple pad patterns to the conductive material.

5. The method for forming a semiconductor memory structure as described in claim 1, characterized in that, Furthermore, this includes the process prior to forming the first patterned hard mask layer: A hard shielding layer is formed on the dielectric structure; Multiple third strip patterns are formed on the hard mask layer; a photoresist pattern is formed to cover a first portion of the multiple third strip patterns and expose a second portion of the multiple third strip patterns; as well as Using the plurality of third strip patterns and the photoresist pattern, the hard mask layer is etched, wherein the second portion exposed by the plurality of third strip patterns is transferred to the hard mask layer to form the plurality of first strip patterns, and the photoresist pattern is transferred to the hard mask layer to form the platform pattern.

6. The method for forming a semiconductor memory structure as described in claim 1, characterized in that, The dielectric structure has multiple openings, and the conductive material is formed in the multiple openings of the dielectric structure to form multiple contact plugs. Multiple pad patterns are transferred to the conductive material to form multiple conductive pads, and each conductive pad corresponds to a specific contact plug. The method for forming the semiconductor memory structure further includes: Remove the multiple solder pad patterns; and Multiple capacitor structures are formed on the multiple conductive pads.

7. The method for forming a semiconductor memory structure as described in claim 1, characterized in that, The plurality of second elongated patterns forming the second patterned hard mask layer include performing a first photolithography process, and the plurality of fourth elongated patterns forming the second patterned hard mask layer include performing a second photolithography process after the first photolithography process.

8. A method for forming a semiconductor memory structure, characterized in that, include: A first hard mask layer is formed on a semiconductor substrate, wherein the semiconductor substrate includes a memory cell array region and a peripheral circuit region; Multiple first strip patterns are formed on the first hard mask layer, wherein the multiple first strip patterns extend continuously in the memory cell array area and the peripheral circuit area; A photoresist pattern is formed on the plurality of first strip patterns to cover the peripheral circuit area and expose the memory cell array area; The first hard mask layer is etched using the photoresist pattern and the plurality of first strip patterns to form a plurality of second strip patterns in the memory cell array area and a platform pattern in the peripheral circuit area. as well as The plurality of second strip patterns and the platform pattern of the first hard mask layer are patterned to form a plurality of pad patterns in the memory cell array area and a plurality of wire patterns in the peripheral circuit area, respectively.

9. The method for forming a semiconductor memory structure as described in claim 8, characterized in that, The plurality of second long strip patterns connect to the platform pattern, and the width of the platform pattern is greater than that of the second long strip patterns.

10. The method for forming a semiconductor memory structure as described in claim 8, characterized in that, The steps for forming the plurality of first strip patterns include: Multiple core patterns are formed on the first hard mask layer; A spacer layer is formed along the multiple core patterns; A first filling layer is formed on the spacer layer, filling the gaps between the plurality of core patterns; and Remove the portion of the spacer layer not covered by the first filler layer, wherein the plurality of core patterns constitute a first group of the plurality of first strip patterns, and the remaining portion of the first filler layer and the spacer layer constitutes a second group of the plurality of first strip patterns.

11. The method for forming a semiconductor memory structure as described in claim 8, characterized in that, Including: A second filling layer is formed between the plurality of second strip patterns; A carbon-containing layer is formed on the second filler layer, the plurality of second strip patterns, and the platform pattern; and The carbon-containing layer is etched to form multiple third strip patterns in the memory cell array region.

12. The method for forming a semiconductor memory structure as described in claim 11, characterized in that, The step of patterning the plurality of second strip patterns of the first hard mask layer includes: etching away portions of the plurality of second strip patterns not covered by the plurality of third strip patterns, and the remaining portions of the plurality of second strip patterns forming the plurality of pad patterns.

13. The method for forming a semiconductor memory structure as described in claim 8, characterized in that, Including: A conductive material is formed on the semiconductor substrate, wherein the first hard mask layer is formed on the conductive material; and The conductive material is etched using the multiple pad patterns and the multiple wire patterns.

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