Semiconductor structure and method of manufacturing the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate and a word line structure, the substrate comprises parallel and spaced grooves, the word line structure is arranged in the grooves and comprises a dielectric layer and a conductive layer, the dielectric layer covers the bottom surface and the sidewall of the conductive layer, the conductive layer comprises a first conductive layer and a second conductive layer, and the second conductive layer is doped with a first component. The semiconductor structure has different work functions between the first conductive layer and the second conductive layer, can reduce the gate-induced drain current caused by the word line structure, the second conductive layer is doped with the first component, the work function of the second conductive layer is reduced, the repulsion of the second conductive layer to electrons is weakened, the gate-induced drain current caused by the word line structure can be further reduced, the leakage problem in the semiconductor device is alleviated, and the power consumption is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers and other electronic devices. It consists of an array of memory cells for storing data and peripheral circuitry surrounding the array. Each memory cell typically includes a transistor (word line), a bit line, and a capacitor. The word line voltage on the transistor (word line) controls the transistor's on and off states, allowing data to be read from or written to the capacitor via the bit line.

[0003] As manufacturing processes continue to advance, transistor sizes are shrinking, leading to a continuous increase in the channel electric field strength of MOS devices. With DRAM process nodes reaching 10nm and below, the energy density per unit area of ​​MOS devices is significantly increasing, making leakage current issues more prominent and power consumption consequently higher. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the above-mentioned problems.

[0005] This application discloses a semiconductor structure, including: a substrate, in which trenches are arranged in parallel intervals; a word line structure located inside the trenches, including a dielectric layer and a conductive layer; wherein the dielectric layer covers the bottom surface and sidewalls of the conductive layer; the conductive layer includes a first conductive layer and a second conductive layer, wherein the second conductive layer is doped with a first component.

[0006] In one embodiment, a second conductive layer is stacked on a first conductive layer, the second conductive layer including a horizontal portion and a raised portion, the raised portion being embedded in the first conductive layer.

[0007] In one embodiment, the first component includes an N-type dopant element.

[0008] In one embodiment, the doping concentration of the first component is 18 × 10⁻⁶. 20 cm -3 Up to 22×10 20 cm -3 .

[0009] In one embodiment, the doping concentration of the first component gradually varies along the thickness direction of the second conductive layer.

[0010] In one embodiment, the first conductive layer includes a metal layer and a metal barrier layer, the metal barrier layer covering the bottom surface and sidewalls of the metal layer and exposing the top of the metal layer, with protrusions embedded in the top of the metal layer.

[0011] In one embodiment, the metal layer includes a tungsten layer, the metal barrier layer includes a titanium nitride layer, and the second conductive layer includes a doped polysilicon layer.

[0012] In one embodiment, the semiconductor structure further includes a protective layer located on the upper surface of the second conductive layer and filling the trench.

[0013] This application also discloses a method for fabricating a semiconductor structure, comprising: providing a substrate and forming trenches arranged in parallel intervals in the substrate; forming a dielectric layer covering the bottom and sidewalls of the trenches; and forming a conductive layer in the trenches, the conductive layer comprising a first conductive layer and a second conductive layer, wherein the second conductive layer is doped with a first component.

[0014] In one embodiment, forming a conductive layer in the trench includes: forming a first conductive layer in the trench, the first conductive layer including a metal layer and a metal barrier layer; and forming a second conductive layer on the first conductive layer.

[0015] In one embodiment, forming a first conductive layer in a trench includes: forming a metal barrier material layer that covers the surface of a dielectric layer; forming a metal material layer that covers the surface of the metal barrier material layer and fills the trench; and removing a portion of the metal material layer and the metal barrier material layer to form a metal layer and a metal barrier layer, thereby obtaining the first conductive layer.

[0016] In one embodiment, an etching process is used to remove part of the metal material layer and the metal barrier material layer; wherein, the etching selectivity ratio of the metal material layer and the metal barrier material layer is adjusted to accelerate the etching rate of the metal material layer, forming an arc-shaped groove on the top surface of the first conductive layer.

[0017] In one embodiment, forming a second conductive layer on a first conductive layer includes: forming a second conductive material layer and doping the second conductive material layer with a first component; the second conductive material layer covering the top surface of the first conductive layer and filling the groove; and removing a portion of the second conductive material layer to form the second conductive layer.

[0018] In one embodiment, the doping concentration of the first component in the second conductive layer is 18 × 10⁻⁶. 20 cm -3 Up to 22×10 20 cm -3 .

[0019] In one embodiment, the doping concentration of the first component gradually varies along the thickness direction of the second conductive layer.

[0020] In one embodiment, a second conductive material layer is formed using a deposition process; the doping concentration of the first component is adjusted during the deposition process.

[0021] In one embodiment, after forming the second conductive layer, the method further includes forming a protective layer that covers the upper surface of the second conductive layer and fills the trench.

[0022] The above embodiments have at least the following beneficial effects:

[0023] In the semiconductor structure described above, the first conductive layer and the second conductive layer have different work functions, which can reduce the gate induced drain leakage (GIDL) caused by the word line structure. Furthermore, the second conductive layer is doped with the first component, which reduces the work function of the second conductive layer and weakens the repulsion effect of the second conductive layer on electrons. This can further reduce the gate induced drain leakage caused by the word line structure, alleviate the leakage problem in the semiconductor device, and reduce power consumption.

[0024] By providing protrusions in the second conductive layer, the contact area between the second conductive layer and the first conductive layer 221 can be increased, further reducing the gate-induced leakage current of the word line structure, reducing power consumption, and enhancing gate control capability.

[0025] In the above-mentioned semiconductor structure fabrication method, by forming a first conductive layer and a second conductive layer of different materials in the trench, the gate-induced leakage current of the word line structure is reduced by utilizing the difference in work function between the first conductive layer and the second conductive layer. Furthermore, by doping the second conductive layer with the first component, the work function of the second conductive layer is reduced, and the repulsion effect of the second conductive layer on electrons is weakened, which can further reduce the gate-induced leakage current caused by the word line structure, alleviate the leakage problem in the semiconductor device, and reduce power consumption. Attached Figure Description

[0026] Figure 1 This is a cross-sectional schematic diagram of a semiconductor structure in one embodiment of this application;

[0027] Figure 2 This is a cross-sectional schematic diagram of a semiconductor structure in another embodiment of this application;

[0028] Figure 3 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application;

[0029] Figure 4 This is a schematic cross-sectional view of a trench formed in a substrate according to an embodiment of this application;

[0030] Figure 5This is a cross-sectional schematic diagram of the semiconductor structure obtained after forming the dielectric layer in one embodiment of this application;

[0031] Figure 6 This is a schematic cross-sectional view of the semiconductor structure obtained after forming a metal barrier material layer in one embodiment of this application;

[0032] Figure 7 This is a cross-sectional schematic diagram of the semiconductor structure obtained after forming a metal material layer in one embodiment of this application;

[0033] Figure 8 This is a cross-sectional schematic diagram of the semiconductor structure obtained after forming the first conductive layer in one embodiment of this application;

[0034] Figure 9 This is a cross-sectional schematic diagram of the semiconductor structure obtained after forming the second conductive material layer in one embodiment of this application;

[0035] Figure 10 This is a cross-sectional schematic diagram of the semiconductor structure obtained after forming the second conductive layer in one embodiment of this application;

[0036] Figure 11 This is a cross-sectional schematic diagram of the semiconductor structure obtained after forming a protective layer in one embodiment of this application;

[0037] Figure 12 This is a schematic cross-sectional view of the semiconductor structure obtained by removing part of the dielectric layer after forming the first conductive layer in one embodiment of this application;

[0038] Figure 13 This is a cross-sectional schematic diagram of the semiconductor structure obtained by removing part of the dielectric layer after forming the first conductive layer in another embodiment of this application;

[0039] Figure 14 This is a cross-sectional schematic diagram of a semiconductor structure in another embodiment of this application.

[0040] Explanation of icon numbers:

[0041] 10. Substrate; 11. Trench; 20. Word line structure; 21. Dielectric layer; 22. Conductive layer; 221. First conductive layer; 221a. Metal layer; 221a'. Metal material layer; 221b. Metal barrier layer; 221b'. Metal barrier material layer; 222. Second conductive layer; 222'. Second conductive material layer; 30. Protective layer. Detailed Implementation

[0042] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0044] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another film layer, it may be directly on the other film layer or there may be intermediate film layers. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more intermediate layers. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intermediate layers.

[0045] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0046] With the continuous development of manufacturing processes, transistor sizes are becoming smaller and smaller, while the channel electric field strength of MOS devices is constantly increasing. As DRAM process nodes reach 10nm and below, the energy density per unit area of ​​MOS devices increases significantly, making leakage current problems more prominent. If the leakage current problem cannot be effectively solved, the power consumption of transistors will not only fail to decrease with the reduction in size, but will actually increase. Therefore, this invention provides a semiconductor structure and fabrication method to solve the technical problem of increased leakage current caused by device size reduction, thereby achieving the technical effect of reducing power consumption.

[0047] like Figure 1 As shown, one embodiment of this application discloses a semiconductor structure including a substrate 10 and a word line structure 20. The substrate 10 includes trenches 11 arranged in parallel intervals. The word line structure 20 is located inside the trenches 11 and includes a dielectric layer 21 and a conductive layer 22. The dielectric layer 21 covers the bottom surface and sidewalls of the conductive layer 22. The conductive layer 22 includes a first conductive layer 221 and a second conductive layer 222. The second conductive layer 222 is doped with a first component.

[0048] In the semiconductor structure described above, the first conductive layer 221 and the second conductive layer 222 have different work functions, which can reduce the gate induced drain leakage (GIDL) caused by the word line structure 20. Furthermore, the second conductive layer 222 is doped with the first component, which reduces the work function of the second conductive layer 222 and weakens the repulsion effect of the second conductive layer 222 on electrons. This can further reduce the gate induced drain leakage caused by the word line structure 20, alleviate the leakage problem in the semiconductor device, and reduce power consumption.

[0049] For example, substrate 10 may include, but is not limited to, silicon substrate 10. Substrate 10 includes an array of active regions and shallow trench isolation structures, with the active regions located between adjacent shallow trench isolation structures. Trench 11 intersects the active regions and shallow trench isolation structures, and word line structure 20 is located in trench 11, wherein a dielectric layer 21 covers the bottom surface and sidewalls of conductive layer 22 to separate conductive layer 22 from the active regions. Dielectric layer 21 may include, but is not limited to, a High-K material layer, such as a silicon dioxide layer. Conductive layer 22 includes a first conductive layer 221 and a second conductive layer 222, the second conductive layer 222 being doped with a first component. By doping the second conductive layer 222 with the first component, the work function of the second conductive layer 222 can be reduced, thereby decreasing the gate-induced leakage current (GIDL) of word line structure 20 and enhancing gate control capability.

[0050] In one embodiment, please refer to... Figure 1 A second conductive layer 222 is stacked on top of a first conductive layer 221. The second conductive layer 222 includes a horizontal portion and a raised portion, with the raised portion embedded in the first conductive layer 221. By providing a raised portion in the second conductive layer 222, the contact area between the second conductive layer 222 and the first conductive layer 221 can be increased, further reducing the gate-induced leakage current of the word line structure 20, reducing power consumption, and enhancing gate control capability.

[0051] In one embodiment, the first component includes an N-type dopant element, such as phosphorus, arsenic, or antimony, and the second conductive layer 222 may include, but is not limited to, a doped polysilicon layer. Doping the second conductive layer 222 with a certain concentration of N-type dopant element leads to an increase in the Fermi level. Since the work function is the difference between the vacuum level and the Fermi level, the work function of the second conductive layer 222 decreases as the Fermi level increases. Taking a doped polysilicon layer as an example, the decrease in work function due to phosphorus doping weakens the electron repulsion effect of the doped polysilicon layer, thereby reducing the gate-induced leakage current (GIDL), improving the gate control capability of the word line structure 20, and reducing power consumption. The Fermi level refers to the highest electron-filled energy level in the solid band structure at absolute zero, commonly denoted by EF; the vacuum level, also known as the free electron level, refers to the level where electrons are completely free and unaffected by the nucleus.

[0052] As an example, the doping concentration of the first component can be 18 × 10⁻⁶. 20 cm -3 Up to 22×10 20 cm -3 For example, 18×10 20 cm -3 19×10 20 cm -3 20×10 20 cm -3 21×10 20 cm -3 Or 22×10 20 cm -3 .

[0053] Optionally, in some embodiments, the doping concentration of the first component gradually varies along the thickness direction of the second conductive layer 222. For example, the doping concentration of the first component gradually decreases along the thickness direction of the second conductive layer 222, or the doping concentration of the first component gradually increases along the direction from the protrusion to the horizontal portion. By providing a first component with a gradually varying doping concentration in the second conductive layer 222, different positions of the second conductive layer 222 can have different work functions, further reducing the gate-induced leakage current (GIDL) and improving the gate control capability of the word line structure 20.

[0054] In one embodiment, please continue to participate Figure 1The first conductive layer 221 includes a metal layer 221a and a metal barrier layer 221b. The metal barrier layer 221b covers the bottom surface and sidewalls of the metal layer 221a, exposing the top surface of the metal layer 221a. A protrusion is embedded in the top surface of the metal layer 221a. The lateral dimension of the protrusion of the second conductive layer 222 is smaller than the lateral dimension of the horizontal portion of the second conductive layer 222, and the bottom surface of the horizontal portion contacts the top surface of the metal barrier layer 221b. The sidewall of the horizontal portion of the second conductive layer 222 contacts a portion of the sidewall of the dielectric layer 21. Since this portion of the dielectric layer 21 is damaged during the formation of the word line structure by etching or other methods, gate-induced leakage current is more likely to occur. This disclosure reduces the gate-induced leakage current by doping the second conductive layer 222 and adjusting its work function.

[0055] For example, metal layer 221a can be a low resistivity conductive metal material, such as a tungsten layer or a copper layer. Metal barrier layer 221b can be selected as a material layer that blocks the metal layer 221a, and it also needs to have high conductivity and good adhesion between the semiconductor and the metal. For example, metal barrier layer 221b can include, but is not limited to, titanium nitride, cobalt, platinum, or titanium-tungsten layers. Taking a tungsten layer as the metal layer 221a, a titanium nitride layer as the metal barrier layer 221b, and a phosphorus-doped polysilicon layer as an example, the protrusion is embedded in the top of the tungsten layer. Utilizing the difference in work function between the doped polysilicon layer and the tungsten layer, the gate-induced leakage current of the word line structure 20 is reduced, thereby reducing power consumption caused by leakage current and improving the gate control capability of the word line structure 20. Figure 1 As shown, the doped polycrystalline silicon layer includes a horizontal portion and a raised portion. The horizontal portion is located above the raised portion and the size of the horizontal portion is larger than that of the raised portion. The bottom surface of the horizontal portion is in contact with the top surface of the titanium nitride layer, and the raised surface of the raised portion is in contact with the top surface of the tungsten layer.

[0056] In one embodiment, such as Figure 1 As shown, the semiconductor structure also includes a protective layer 30 located on the upper surface of the second conductive layer 222 and filling the trench 11. The upper surface of the protective layer 30 is flush with the upper surface of the substrate 10. As an example, the material of the protective layer 30 may include, but is not limited to, silicon nitride or silicon oxynitride, etc. The protective layer 30 can isolate the conductive layer 22 from the outside world, thus protecting the conductive layer 22.

[0057] Alternatively, in some embodiments, such as Figure 2 As shown, the upper surface of the dielectric layer 21 is flush with the upper surface of the second conductive layer 222, and the protective layer 30 covers the upper surfaces of the dielectric layer 21 and the second conductive layer 222.

[0058] By placing the protective layer 30 above the dielectric layer 21, the dielectric layer 21 can be prevented from being damaged by other processes (such as wet etching or dry etching) in subsequent processes, thereby improving device stability.

[0059] like Figure 3 As shown, this application also discloses a method for fabricating a semiconductor structure, comprising:

[0060] S10: Provide a substrate 10, and form parallel-spaced trenches 11 in the substrate 10;

[0061] S20: Forming a dielectric layer 21, which covers the upper surface of the substrate 10 and the bottom and sidewalls of the trench 11;

[0062] S30: A conductive layer 22 is formed in the trench 11. The conductive layer 22 includes a first conductive layer 221 and a second conductive layer 222. The second conductive layer 222 is doped with a first component.

[0063] In the above-described semiconductor structure fabrication method, by forming a first conductive layer 221 and a second conductive layer 222 of different materials in the trench 11, the gate-induced leakage current of the word line structure 20 is reduced by utilizing the difference in work function between the first conductive layer 221 and the second conductive layer 222. Furthermore, by doping the second conductive layer 222 with a first component, the work function of the second conductive layer 222 is reduced, and the repulsion effect of the second conductive layer 222 on electrons is weakened, which can further reduce the gate-induced leakage current caused by the word line structure 20, alleviate the leakage problem in the semiconductor device, and reduce power consumption.

[0064] In one embodiment, a plurality of shallow trench isolation structures (not shown in the figure) are formed within the substrate 10 in step S10. These shallow trench isolation structures isolate multiple active regions (not shown in the figure) arranged in an array within the substrate 10. As an example, the material of the shallow trench isolation structures may include, but is not limited to, silicon oxide, silicon nitride, etc.; the substrate 10 may include, but is not limited to, a silicon substrate 10. For example, the step of forming trenches 11 in the substrate 10 includes: first, depositing a hard mask layer on the upper surface of the substrate 10; then, using a patterning process to form a pattern in the hard mask layer, defining the position and size of the trenches 11; and finally, using photolithography to etch the substrate 10 to form parallel, spaced trenches 11, such as... Figure 4 As shown. For example, trench 11 intersects with both the active region and the shallow trench isolation structure.

[0065] As an example, the depth of trench 11 can be 50nm-300nm, such as 50nm, 100nm, 150nm, 200nm or 300nm; the critical dimension (CD) of trench 11 can be 20nm-100nm, such as 20nm, 30nm, 50nm, 70nm or 100nm.

[0066] In some embodiments, the trench 11 has a first portion and a second portion, wherein the width of the first portion is greater than the width of the second portion. The wider first portion intersects with the active region, and the narrower second portion intersects with the shallow trench isolation structure.

[0067] In step S20, a dielectric layer 21 is formed, which covers the bottom and sidewalls of the trench 11, as well as the upper surface of the substrate 10, such as... Figure 5 As shown.

[0068] For example, the dielectric layer 21 may include, but is not limited to, a High-K material layer, such as a silicon dioxide layer. The dielectric layer 21 can be formed on the bottom and sidewalls of the trench 11 and on the upper surface of the substrate 10 using an in-situ steam generation (ISSG) process. Alternatively, the dielectric layer 21 can also be formed using atomic layer deposition, plasma vapor deposition, or rapid thermal oxidation (RTO) processes.

[0069] In step S30, a conductive layer 22 is formed in the trench 11. The conductive layer 22 includes a first conductive layer 221 and a second conductive layer 222. The second conductive layer 222 is doped with a first component, such as... Figure 6-10 As shown.

[0070] For example, the step of forming a conductive layer 22 in trench 11 includes:

[0071] S31: A first conductive layer 221 is formed in the trench 11. The first conductive layer 221 includes a metal layer 221a and a metal barrier layer 221b.

[0072] S32: A second conductive layer 222 is formed on the first conductive layer 221.

[0073] In step S31, the step of forming the first conductive layer 221 may include:

[0074] S311: Forming a metal barrier material layer 221b', the metal barrier material layer 221b' covers the surface of the dielectric layer 21, such as Figure 6 As shown.

[0075] For example, the metal barrier material layer 221b' can be a material layer that provides good barrier properties against both metals and semiconductors, such as a titanium nitride layer, a cobalt layer, a platinum layer, or a titanium-tungsten layer. Optionally, the metal barrier material layer 221b' can also have high conductivity and good adhesion between the semiconductor and the metal. As an example, the metal barrier material layer 221b' can be formed using chemical vapor deposition, atomic layer deposition, plasma vapor deposition, or rapid thermal oxidation processes.

[0076] S312: A metal material layer 221a' is formed, which covers the surface of the metal barrier material layer 221b' and fills the trench 11, such as... Figure 7 As shown.

[0077] For example, the metal material layer 221a' can be a low resistivity conductive metal material, such as, but not limited to, W (tungsten), molybdenum (Mo), Ti (titanium), Cu (copper), or Au (gold). As an example, the metal material layer 221a' can be formed on the surface of the metal barrier material layer 221b' using a chemical vapor deposition process, and the formed metal material layer 221a' fills the trench 11.

[0078] S313: Remove part of the metal material layer 221a' and the metal barrier material layer 221b' to form metal layer 221a and metal barrier layer 221b, thus obtaining the first conductive layer 221. Figure 8 As shown.

[0079] For example, an etching process can be used to remove part of the metal material layer 221a' and the metal barrier material layer 221b'. For instance, dry etching can be used to remove the metal material layer 221a' and the metal barrier material layer 221b' above the substrate 10, and etching can continue to reduce the thickness of the metal material layer 221a' and the metal barrier material layer 221b'. Etching stops when the distance between the top surface of the metal material layer 221a' and the metal barrier material layer 221b' and the top surface of the active region reaches a first preset distance. For example, the first preset distance can be 75nm-85nm, such as 75nm, 80nm, or 85nm. Any distance between the top surface of the metal material layer 221a' and the metal barrier material layer 221b' and the top surface of the active region within the range of 75nm-85nm meets the requirements of this invention, and will not be listed individually here. By controlling the distance between the top surface of the metal material layer 221a' and the metal barrier material layer 221b' and the top surface of the active region to maintain a first preset distance, the channel length can be controlled within a reasonable range, thereby improving the gate control capability.

[0080] Optionally, in some embodiments, the etching rate of the metal material layer 221a' can be accelerated by adjusting the etching selectivity ratio of the etching gas to the metal material layer 221a' and the metal barrier material layer 221b', thereby forming an arc-shaped groove on the top surface of the first conductive layer 221, such as... Figure 8 As shown. For example, a gas with a high etching rate for the metal material layer 221a' can be introduced near the end of the etching process.

[0081] As an example, the metal material layer 221a' is a tungsten layer, and the metal barrier material layer 221b' is a titanium nitride layer. Near the end of the dry etching process, chlorine gas (Cl2) is introduced into the chamber. Since chlorine gas etches the tungsten layer at a faster rate than other materials, the top of the tungsten layer depresses more rapidly as the etching process continues, gradually forming an arc-shaped groove. Optionally, the depth or morphology of the arc-shaped groove can be controlled by controlling the timing, rate, and duration of chlorine gas introduction. By forming an arc-shaped groove on the top of the first conductive layer, a downwardly convex protrusion can be formed in the second conductive layer 222 when it is formed on its upper surface, thereby increasing the contact area between the second and first conductive layers.

[0082] In step S32, the step of forming the second conductive layer 222 includes:

[0083] S321: A second conductive material layer 222' is formed, and a first component is doped into the second conductive material layer 222'; the second conductive material layer 222' covers the top surface of the first conductive layer 221 and the surface of the dielectric layer 21, and fills the groove, such as Figure 9 As shown.

[0084] S322: Remove part of the second conductive material layer 222' to form the second conductive layer 222, such as Figure 10 As shown.

[0085] For example, the second conductive material layer 222' may include, but is not limited to, a doped polycrystalline silicon layer. In step S321, the second conductive material layer 222' may be formed using chemical vapor deposition, atomic layer deposition, or plasma vapor deposition. Preferably, the second conductive material layer 222' may be formed on the upper surface of the first conductive layer 221 and the surface of the dielectric layer 21 using low-pressure chemical vapor deposition (LPCVD). The equipment used may be a furnace tube, a single-wafer operation chamber, or other equipment. The low-pressure chemical vapor deposition process performed in a furnace tube has advantages such as low deposition temperature, easy control of film composition and thickness, film thickness proportional to deposition time, good uniformity and repeatability, good step coverage, and convenient operation.

[0086] In some embodiments, a first component can be introduced into the furnace tube while the polycrystalline silicon layer is being grown to form a doped polycrystalline silicon layer doped with the first component. The first component can be, for example, an N-type dopant element, such as phosphorus, arsenic, or antimony.

[0087] Specifically, the steps for preparing a doped polycrystalline silicon layer using a furnace tube may include: placing a substrate 10 inside the furnace tube, introducing silane and phosphine into the furnace tube, and using phosphorus from the decomposition of phosphine to dope the silicon. The main chemical equation for generating the polycrystalline silicon layer is as follows: SiH4(g) → Si(s) + 2H2(g), and the chemical formula for the decomposition of phosphine is as follows: PH3 (phosphine) → P + 3H, where phosphorus from the decomposition of phosphine is doped into the silicon from the decomposition of silane. For example, the flow rate of silane introduced into the furnace tube is 200 sccm to 20000 sccm, and the flow rate of phosphine introduced into the equipment is 10 sccm to 500 sccm.

[0088] During the deposition of the polycrystalline silicon layer, silane gas is decomposed into various new particles: atoms, free radicals, and various ions. These new particles are deposited on the substrate 10 after a series of complex processes such as migration and dehydrogenation. As an example, the deposition temperature of the polycrystalline silicon layer is 400 to 600 degrees Celsius. The heated furnace tube can perform batch layer deposition, placing hundreds (e.g., 100, 150, or 200) wafers on a vertical boat at a time. A fixed amount of reactive gas is introduced into the furnace from the bottom of the reaction chamber or a quartz jet tube within a set time, and at a set temperature, doped polycrystalline silicon layers can be deposited simultaneously on all wafer surfaces. For example, such as... Figure 9 As shown, the doped polysilicon layer fills the trench 11 and covers the surface of the dielectric layer 21 on the substrate 10.

[0089] As an example, the doping concentration of the first component could be 18 × 10⁻⁶. 20 cm -3 Up to 22×10 20 cm -3 For example, 18×10 20 cm -3 19×10 20 cm -3 20×10 20 cm -3 21×10 20 cm -3 Or 22×10 20 cm -3 For all components with a doping concentration of 18 × 10⁻⁶, ... 20 cm -3 Up to 22×10 20 cm -3 All of these within the scope meet the requirements of this invention, and will not be listed individually here.

[0090] Optionally, in some embodiments, the doping concentration of the first component at different positions in the second conductive material layer 222' can be adjusted by changing the introduction rate of the first component, so that the doping concentration of the first component gradually varies along the thickness direction of the second conductive material layer 222'. As an example, silane is introduced into the furnace tube as a silicon source, and phosphine is introduced into the furnace tube as a phosphorus source. For example, in the initial stage of polycrystalline silicon layer growth, the flow rate of phosphine introduced into the equipment is 500 sccm; as the polycrystalline silicon layer grows and its thickness increases, the introduction rate of the first component gradually decreases; for example, at the end of polycrystalline silicon layer growth, the phosphine introduction flow rate is 50 sccm. During this period, the phosphine introduction flow rate decreases uniformly.

[0091] Optionally, in the initial stage of polysilicon layer growth, the first component can be introduced into the furnace tube at a low rate, and the introduction rate of the first component can be gradually increased as the polysilicon layer grows and its thickness increases. For example, in the initial stage of polysilicon layer growth, the flow rate of phosphine introduced into the equipment is 50 sccm; as the polysilicon layer grows and its thickness increases, the introduction rate of the first component gradually increases, for example, at the end of polysilicon layer growth, the phosphine flow rate is 500 sccm. During this period, the phosphine flow rate increases at a uniform rate.

[0092] Optionally, in the early stage of polycrystalline silicon layer growth, the first component can be introduced into the furnace tube at a low rate. As the polycrystalline silicon layer grows and its thickness increases, the introduction rate of the first component is gradually increased, a maximum doping concentration is set, and after reaching the maximum value, the introduction rate of the first component is gradually reduced. The doping concentration of the first component in the second conductive layer first increases and then decreases.

[0093] Optionally, in the early stage of polycrystalline silicon layer growth, the first component can be introduced into the furnace tube at a high rate. As the polycrystalline silicon layer grows and its thickness increases, the introduction rate of the first component is gradually reduced, a minimum doping concentration is set, and after reaching the minimum value, the introduction rate of the first component is gradually increased. The doping concentration of the first component in the second conductive layer first decreases and then increases.

[0094] By doping a polycrystalline silicon layer with N-type doping, the work function of the polycrystalline silicon layer can be altered. The work function is the minimum energy required to move an electron from the interior of a solid to its surface. A higher work function means a less likely electron to leave the solid. After N-type doping of the polycrystalline silicon layer, the Fermi level (Ef) increases. Since the work function Φ = the difference between the vacuum level (Ev) and the Fermi level (Ef), i.e., Φ = Ev - Ef, an increase in the Fermi level leads to a decrease in the work function. This decrease in the work function weakens the repulsive effect of the doped polycrystalline silicon layer on electrons, thereby reducing the gate-induced leakage current (GIDL) of the word line structure 20, lowering device power consumption, and improving gate control capability. Elements that can be used to achieve N-type doping of the second conductive layer include one or more combinations of arsenic, phosphorus, and antimony. Using multiple element doping methods can also adjust the work function of the second conductive layer, thereby improving the GIDL effect of the gate structure.

[0095] In step S322, for example, the second conductive material layer 222' above the substrate 10 can be removed by etching, and then the second conductive material layer 222' within the trench 11 can be etched to reduce the thickness of the second conductive material layer 222' until the distance between the top surface of the second conductive material layer 222' and the upper surface of the active region reaches a second preset distance, thus obtaining the second conductive layer 222. For example, the second preset distance can be 55nm-65nm, such as 55nm, 60nm, or 65nm. Any distance between the top surface of the second conductive material layer 222' and the upper surface of the active region within the range of 55nm-65nm meets the requirements of the present invention, and will not be listed individually here.

[0096] As an example, during the fabrication of the second conductive material layer 222', if the induction rate of the first component remains unchanged, the resulting second conductive layer 222 will have a uniform doping concentration; if the induction rate of the first component changes (increases or decreases) with the increase of the thickness of the polycrystalline silicon layer, then the first component will gradually vary along the thickness direction in the second conductive layer 222. For example, as... Figure 10 As shown, the upper surface of the second conductive layer 222 is lower than the upper surface of the substrate 10.

[0097] In some embodiments, after forming the second conductive layer 222, the method further includes:

[0098] S40: A protective layer 30 is formed, which covers the upper surface of the second conductive layer 222 and the surface of the dielectric layer 21, and fills the trench 11, such as... Figure 11 As shown.

[0099] For example, the protective layer 30 may be a High-K material layer, such as a silicon nitride layer or a silicon oxynitride layer. As an example, the protective layer 30 may be formed using atomic layer deposition or plasma vapor deposition processes. The protective layer 30 covers the upper surface of the second conductive layer 222 and fills the trench 11.

[0100] Preferably, the protective layer 30 can be formed inside the furnace tube using a low-pressure chemical vapor deposition (LPCVD) process. The protective layer 30 formed inside the furnace tube exhibits good uniformity and good density. For example, such as... Figure 11 As shown, a protective layer 30 is formed on the upper surface of the second conductive layer 222, the protective layer 30 fills the trench 11 and extends to the substrate 10.

[0101] Furthermore, wet etching, dry etching, chemical mechanical polishing, or planar etching processes can be used to planarize the protective layer 30 and the dielectric layer 21 along the thickness direction until the upper surface of the substrate 10 is exposed, such as... Figure 1 As shown in the diagram, the upper surfaces of the dielectric layer 21 and the protective layer 30 are flush with the upper surface of the substrate 10. The protective layer 30 isolates the conductive layer 22 from the outside environment, thus protecting the conductive layer 22.

[0102] This application also discloses a semiconductor structure fabrication direction to form Figure 2 The semiconductor structure is shown. The method includes steps S10, S20, S30, and 40 from the aforementioned embodiments, the difference being that an additional step is added before performing step S40: removing the exposed dielectric layer 21 within the trench 11, such as... Figure 12 As shown.

[0103] Specifically, after the conductive layer 22 is formed, the dielectric layer 21 exposed in the trench 11 can be removed by dry etching. For example, the dielectric layer 21 on the inner wall of the trench 11 can be etched in a plasma etching process to expose the sidewall of the active region. At this time, the top surface of the dielectric layer 21 is flush with the upper surface of the second conductive layer 222.

[0104] Optionally, in some embodiments, to prevent the top surface of the dielectric layer 21 from being excessively etched and falling below the upper surface of the second conductive layer 222, only the portion of the dielectric layer 21 exposed within the trench 11 can be removed, so that the top surface of the dielectric layer 21 is higher than the upper surface of the second conductive layer 222 but lower than the upper surface of the substrate 10, such as... Figure 13 As shown. By forming such a groove 11 Figure 13 The dielectric layer 21 shown can improve the process margin. When etching away the dielectric layer 21 on the sidewall of the trench 11, even if over-etching occurs, the dielectric layers 21 on both sides of the second conductive layer 222 will not be damaged, ensuring that the electrical performance of the word line structure 20 is not affected.

[0105] In some embodiments, the following is obtained: Figure 12 or Figure 13 Following the semiconductor structure shown, a protective layer 30 is formed using the process method in step 40 to obtain the desired result. Figure 2 The semiconductor structure shown or such Figure 14 The semiconductor structure shown is illustrated. The protective layer 30 can be, for example, a silicon nitride layer or a silicon oxynitride layer. Since the protective layer 30 completely covers the word line structure 20 within the substrate 10, there is no need to worry about damage to the word line structure 20 during other processes on the substrate 10, thus improving the stability and reliability of the device.

[0106] The word line structure 20 prepared by the above method can be called a buried word line structure 20. It has a first conductive layer 221 and a second conductive layer 222 with different materials. The difference in work function reduces the gate-induced leakage current caused by the buried word line structure 20. Furthermore, by doping the second conductive layer 222 with a first component (e.g., phosphorus), the work function of the second conductive layer 222 is reduced, the repulsion of the second conductive layer 222 on electrons is weakened, the gate-induced leakage current caused by the buried word line structure 20 is further reduced, power consumption is reduced, and gate control capability is improved.

[0107] It should be understood that, although Figure 3 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 3 At least some of the steps in the process may include multiple steps or multiple stages. For example, step S30 may include steps S31 and S32, and step S31 may be further subdivided into steps S311, S312, and S313. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least a portion of the steps or stages in other steps.

[0108] Optionally, the above-described semiconductor structure can be applied to DRAM or other semiconductor devices. By applying the semiconductor structure in the above embodiments to DRAM, leakage current in DRAM can be significantly reduced, thereby alleviating power consumption issues.

[0109] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation on this application.

[0110] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0111] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, wherein the substrate includes trenches arranged in parallel intervals; The word line structure, located inside the trench, includes a dielectric layer and a conductive layer; wherein the dielectric layer covers the bottom surface and sidewalls of the conductive layer; the conductive layer includes a first conductive layer and a second conductive layer, wherein the second conductive layer is doped with a first component, and the doping concentration of the first component gradually changes along the thickness direction of the second conductive layer; The second conductive layer is stacked on the first conductive layer, and the second conductive layer includes a horizontal portion and a protruding portion, wherein the protruding portion is embedded in the first conductive layer; Wherein, the lateral dimension of the protrusion of the second conductive layer is smaller than the lateral dimension of the horizontal portion of the second conductive layer.

2. The semiconductor structure according to claim 1, characterized in that, The first component includes N-type doped elements.

3. The semiconductor structure according to claim 1, characterized in that, The doping concentration of the first component is 18 × 10⁻⁶. 20 cm -3 Up to 22×10 20 cm -3 .

4. The semiconductor structure according to claim 1, characterized in that, The first conductive layer includes a metal layer and a metal barrier layer. The metal barrier layer covers the bottom surface and sidewalls of the metal layer and exposes the top of the metal layer. The protrusion is embedded in the top of the metal layer.

5. The semiconductor structure according to claim 4, characterized in that, The metal layer includes a tungsten layer, the metal barrier layer includes a titanium nitride layer, and the second conductive layer includes a doped polycrystalline silicon layer.

6. The semiconductor structure according to claim 1, characterized in that, Also includes: A protective layer is located on the upper surface of the second conductive layer and fills the trench.

7. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, and trenches arranged in parallel intervals are formed in the substrate; A dielectric layer is formed, which covers the bottom and sidewalls of the trench; A conductive layer is formed in the trench, the conductive layer including a first conductive layer and a second conductive layer, the second conductive layer being doped with a first component, and the doping concentration of the first component gradually changing along the thickness direction of the second conductive layer; The second conductive layer is stacked on the first conductive layer, and the second conductive layer includes a horizontal portion and a protruding portion, wherein the protruding portion is embedded in the first conductive layer; Wherein, the lateral dimension of the protrusion of the second conductive layer is smaller than the lateral dimension of the horizontal portion of the second conductive layer.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, Forming a conductive layer in the trench includes: The first conductive layer is formed in the trench, and the first conductive layer includes a metal layer and a metal barrier layer; The second conductive layer is formed on the first conductive layer.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The formation of the first conductive layer in the trench includes: A metal barrier material layer is formed, which covers the surface of the dielectric layer; A metal material layer is formed, which covers the surface of the metal barrier material layer and fills the trench; By removing a portion of the metal material layer and the metal barrier material layer, the metal layer and the metal barrier layer are formed to obtain the first conductive layer.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, A portion of the metal material layer and the metal barrier material layer are removed using an etching process; Specifically, the etching selectivity ratio of the metal material layer and the metal barrier material layer is adjusted to accelerate the etching rate of the metal material layer, thereby forming an arc-shaped groove on the top surface of the first conductive layer.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that, Forming a second conductive layer on the first conductive layer includes: A second conductive material layer is formed, and the first component is doped into the second conductive material layer; the second conductive material layer covers the top surface of the first conductive layer and fills the groove. A portion of the second conductive material layer is removed to form the second conductive layer.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that, The doping concentration of the first component in the second conductive layer is 18 × 10⁻⁶. 20 cm -3 Up to 22×10 20 cm -3 .

13. The method for preparing a semiconductor structure according to claim 11, characterized in that, The doping concentration of the first component gradually changes along the thickness direction of the second conductive layer.

14. The method for preparing a semiconductor structure according to claim 11, characterized in that, The second conductive material layer is formed using a deposition process; The doping concentration of the first component is adjusted during the deposition process.

15. The method for preparing a semiconductor structure according to any one of claims 12-14, characterized in that, After forming the second conductive layer, the method further includes: A protective layer is formed, which covers the upper surface of the second conductive layer and fills the trench.

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