Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, wherein the method comprises: forming a first active region on the first device region and a second active region on the second device region, the first active region and the second active region extend along a first direction, the first active region comprises a first functional region and a first shared region; forming a first gate and a second gate on the substrate, the first gate and the second gate are parallel to a second direction, the first direction and the second direction are perpendicular to each other, the first gate is located on the first device region and on part of the surface of the first active region, the second gate is located on the second device region and on part of the surface of the second active region, and the second gate also extends to the surface of the first shared region; and electrically connecting the second gate and the first active region in a device layer without occupying the space of the medium layer on the upper layer of the device layer, thereby improving the device density.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous development of microelectronics technology, memory is showing a trend towards high integration, high speed, and low power consumption. Compared to Dynamic Random Access Memory (DRAM), Static Random-Access Memory (SRAM) can retain data stored in its internal standard without a refresh circuit. Furthermore, unlike DRAM, it does not require periodic flushing and charging to prevent data loss. Therefore, SRAM offers superior performance. SRAM has experienced significant development in recent years and, as an important type of semiconductor memory, has been widely used in high-speed data exchange systems such as computers, communications, and multimedia.

[0003] However, static random access memory (SRAM) has a low integration density and requires a much larger volume compared to SRAM of the same capacity. Therefore, a key indicator of dynamic random access memory (DRAM) is its area. To improve integration density, shared contact via (Shared CT) technology is used to directly connect the gate and active region, thereby saving area by shortening the interconnection.

[0004] To further reduce the size of memory cells, existing techniques for forming shared contact holes need to be improved. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising: a substrate, the substrate including a base, the base including an adjacent first device region and a second device region; a first active region located on the first device region and a second active region located on the second device region, an isolation layer being provided between the first active region and the second active region, the first active region and the second active region extending along a first direction, the first active region including a first functional region and a first shared region; a first gate and a second gate located on the substrate, the first gate and the second gate being parallel to a second direction, the first direction and the second direction being perpendicular to each other, the first gate being located on the first device region and located on a portion of the surface of the first active region, the second gate being located on the second device region and located on a portion of the surface of the second active region, the second gate further extending to the surface of the first shared region.

[0007] Optionally, the second active region includes a second functional region and a second shared region; the first gate also extends to the surface of the second shared region.

[0008] Optionally, it includes: a first source / drain layer in the first active region located on both sides of the first gate, and a first channel layer in the first active region below the first gate and located between adjacent first source / drain layers; a second source / drain layer in the second active region located on both sides of the second gate, and a second channel layer in the second active region below the second gate and located between adjacent second source / drain layers.

[0009] Optionally, the substrate has an interlayer dielectric layer, and the first gate and the second gate are located in the interlayer dielectric layer; a first dielectric layer is located on the interlayer dielectric layer, and a plurality of contact layers are located within the first dielectric layer, the plurality of contact layers being located on the surfaces of the first gate, the second gate, the first source / drain layer, and the second source / drain layer, respectively; a second dielectric layer is located on the first dielectric layer, and a metal interconnect layer is located within the second dielectric layer, the metal interconnect layer being electrically connected to the plurality of contact layers.

[0010] Optionally, the material of the first gate includes a metal and its derivatives, wherein the metal and its derivatives include one or more combinations of titanium nitride, tantalum nitride, titanium, aluminum, tungsten, copper and lanthanide metal oxides; the material of the second gate includes a metal and its derivatives, wherein the metal and its derivatives include one or more combinations of titanium nitride, tantalum nitride, titanium, aluminum, tungsten, copper and lanthanide metal oxides.

[0011] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a base, the base including an adjacent first device region and a second device region; forming a first active region on the first device region, a second active region on the second device region, and an isolation layer between the first active region and the second active region, the first active region and the second active region extending along a first direction, the first active region including a first functional region and a first shared region; forming a first gate and a second gate on the substrate, the first gate and the second gate being parallel to a second direction, the first direction and the second direction being perpendicular to each other, the first gate being located on the first device region and located on a portion of the surface of the first active region, the second gate being located on the second device region and located on a portion of the surface of the second active region, the second gate further extending to the surface of the first shared region.

[0012] Optionally, a first source / drain layer is provided in the first active region located on both sides of the first gate, and a first channel layer is provided in the first active region below the first gate and between adjacent first source / drain layers; a second source / drain layer is provided in the second active region located on both sides of the second gate, and a second channel layer is provided in the second active region below the second gate and between adjacent second source / drain layers; the method for forming the first source / drain layer, the second source / drain layer, the first gate, and the second gate includes: forming a first dummy gate and a second dummy gate on the substrate, the first dummy gate and the second dummy gate being parallel to a second direction, the first dummy gate being located on the first device region and located in a portion of the... The first active region surface is described above, and the second dummy gate is located on the second device region and on a portion of the second active region surface, the second dummy gate also extending to the surface of the first shared region; a first source / drain layer is formed in the first active region on both sides of the first dummy gate; a second source / drain layer is formed in the second active region on both sides of the second dummy gate; after forming the first source / drain layer and the second source / drain layer, an interlayer dielectric layer is formed on the substrate surface, the interlayer dielectric layer exposing the top surfaces of the first dummy gate and the second dummy gate; after forming the interlayer dielectric layer, the first dummy gate is replaced by the first gate; after forming the interlayer dielectric layer, the second dummy gate is replaced by the second gate.

[0013] Optionally, after forming the first gate and the second gate, the method further includes: forming a first dielectric layer on the interlayer dielectric layer, the first dielectric layer having a plurality of contact layers, the plurality of contact layers being located on the surfaces of the first gate, the second gate, the first source / drain layer, and the second source / drain layer respectively; and after forming the first dielectric layer, forming a second dielectric layer on the first dielectric layer, the second dielectric layer having a metal interconnect layer, the metal interconnect layer being electrically connected to the plurality of contact layers.

[0014] Optionally, the method of forming a first gate in place of the first dummy gate and a second gate in place of the second dummy gate includes: removing the first dummy gate and forming a first gate recess in the interlayer dielectric layer; removing the second dummy gate and forming a first gate recess in the interlayer dielectric layer; forming the first gate in the first gate recess; and forming the second gate in the second gate recess.

[0015] Optionally, the method for forming the first gate and the second gate includes: forming a gate material layer on the surface of the first gate recess, the second gate recess and the interlayer dielectric layer; planarizing the gate material layer until the surface of the interlayer dielectric layer is exposed.

[0016] Optionally, a first gate oxide layer and a first gate dielectric layer are provided between the first active region and the first gate; a second gate oxide layer and a second gate dielectric layer are provided between the second active region and the second gate.

[0017] Optionally, the method for forming the first gate oxide layer, the first gate dielectric layer, the second gate oxide layer, and the second gate dielectric layer includes: before forming the gate material layer, forming a gate oxide layer and a gate dielectric layer on the surface of the first gate recess, the second gate recess, and the interlayer dielectric layer; removing the gate oxide layer and the gate dielectric layer on the first shared region exposed by the second gate recess; after forming the gate material layer, planarizing the gate dielectric layer and the gate oxide layer until the interlayer dielectric layer is exposed, forming the first gate oxide layer with the gate oxide layer in the first gate recess, forming the first gate dielectric layer with the gate dielectric layer in the first gate recess, forming the second gate oxide layer with the gate oxide layer in the second gate recess, and forming the second gate dielectric layer with the gate dielectric layer in the second gate recess.

[0018] Optionally, the process for removing the gate oxide material layer and the gate dielectric material layer on the first shared region exposed by the second gate groove includes a wet etching process.

[0019] Optionally, the process parameters for removing the gate dielectric material layer on the first shared region exposed by the second gate groove include: the etching solution comprising a mixture of hydrofluoric acid solution, hydrochloric acid solution and alcohol solution, wherein the ratio of hydrofluoric acid solution, hydrochloric acid solution and alcohol solution ranges from 1:1:99 to 1:20:80, wherein the concentration of hydrofluoric acid solution ranges from 1% to 10%, the concentration of hydrochloric acid solution ranges from 10% to 40%, and the concentration of alcohol solution ranges from 50% to 99%.

[0020] Optionally, the second active region includes a second functional region and a second shared region; the first gate also extends to the surface of the second shared region.

[0021] Optionally, after forming the gate oxide material layer and the gate dielectric material layer, the gate oxide material layer and the gate dielectric material layer on the second shared region exposed by the first gate recess are also removed.

[0022] Optionally, an isolation layer is provided between the first active region and the second active region.

[0023] Optionally, the top surface of the isolation layer is lower than the top surfaces of the first active region and the second active region; the method for forming the first active region and the second active region includes: etching the substrate to form the first active region and the second active region, and a groove between the first active region and the second active region; forming a dielectric material layer in the groove; and etching back the dielectric material layer to form the isolation layer.

[0024] Optionally, the material of the first gate includes a metal and its derivatives, wherein the metal and its derivatives include one or more combinations of titanium nitride, tantalum nitride, titanium, aluminum, tungsten, copper and lanthanide metal oxides; the material of the second gate includes a metal and its derivatives, wherein the metal and its derivatives include one or more combinations of titanium nitride, tantalum nitride, titanium, aluminum, tungsten, copper and lanthanide metal oxides.

[0025] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects: In the semiconductor structure formation method provided by the present invention, the first active region includes a first functional region and a first shared region. The second gate is extended to the surface of the first shared region, and the second gate and the first active region are electrically connected in the device layer. This does not occupy the space of the dielectric layer above the device layer, so it will not affect the arrangement of metal interconnects in the subsequent process, which is beneficial to improving device density.

[0026] Furthermore, the second active region includes a second functional region and a second shared region. The first gate is extended to the surface of the second shared region, and the first gate and the second active region are electrically connected in the device layer. This does not occupy the space of the dielectric layer above the device layer, so it will not affect the arrangement of metal interconnects in the subsequent process, which is beneficial to improving device density.

[0027] In the semiconductor structure provided by the present invention, the second gate is extended to the surface of the first shared region, and the second gate and the first active region are electrically connected in the device layer. This does not occupy the space of the dielectric layer above the device layer, so it will not affect the arrangement of metal interconnects in the subsequent process, which is beneficial to improving device density.

[0028] Furthermore, the second active region includes a second functional region and a second shared region. The first gate is extended to the surface of the second shared region, and the first gate and the second active region are electrically connected in the device layer. This does not occupy the space of the dielectric layer above the device layer, so it will not affect the arrangement of metal interconnects in the subsequent process, which is beneficial to improving device density. Attached Figure Description

[0029] Figure 1 and Figure 2 This is a schematic diagram of a semiconductor structure. Figures 3 to 14 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0030] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0031] As described in the background section, existing techniques for forming shared contact holes need further improvement to further reduce the size of memory cells. A semiconductor structure formation process will now be explained and analyzed.

[0032] Figure 1 and Figure 2 This is a schematic diagram of a semiconductor structure.

[0033] Please refer to Figure 1 and Figure 2 , Figure 1 This is a top view schematic diagram of a local area containing a shared contact hole in a static random access memory cell. Figure 2 for Figure 1A cross-sectional structural schematic diagram along the DD1 direction includes: a substrate, including a base 100 and fins 101 located on the base 100 and an isolation layer 109 between adjacent fins 101, the fins 101 extending along a first direction X, the top surface of the isolation layer 109 being lower than the top surface of the fins 101; a gate 102 spanning the fins 101, the gate 102 extending along a second direction Y, the second direction Y being perpendicular to the first direction X, the gate 102 also located on a portion of the sidewalls and top surface of the fins 101; source / drain layers 104 located within the fins 101 on both sides of the gate 102; and an interlayer dielectric layer 103 located on the substrate, the first dielectric layer... A dielectric layer 103 is located on the sidewall of the gate 102; a second dielectric layer 105 is located on the first dielectric layer 103, the second dielectric layer 105 having a shared contact hole (not shown in the figure), a first contact hole (not shown in the figure) and a second contact hole (not shown in the figure) located below the shared contact hole, the first contact hole exposing a portion of the gate 102, the second contact hole also being located within the first dielectric layer 103 and exposing a portion of the top surface of the source / drain layer 104, the shared contact hole extending along the first direction X, the shared contact hole having a shared contact layer 106, the first contact hole having a first conductive plug 107, and the second contact hole having a second conductive plug 108.

[0034] In the above structure, the shared contact layer 106 is used to connect the gate 102 and the source / drain layer 104. Its formation process is performed on the second dielectric layer 105 after the device layer is formed, which is the middle-of-line (MOL) process of semiconductor technology. In the subsequent process of forming the shared contact layer 106, a first metal interconnect layer located on the second dielectric layer 105 will be formed.

[0035] As device feature sizes continue to shrink, without changing the thickness of the second dielectric layer 105, it is necessary to reduce the feature size of the first metal interconnect layer to ensure a sufficient gap between the first metal interconnect layer and the shared contact layer 106. One solution is to use extreme ultraviolet (EUV) lithography to reduce the feature size of the first metal interconnect layer. However, under current circumstances, EUV lithography technology is difficult to promote in China.

[0036] To address the aforementioned issues, the present invention provides a semiconductor structure and its formation method in which the first active region includes a first functional region and a first shared region. The second gate is extended to the surface of the first shared region, and the second gate and the first active region are electrically connected in the device layer. This does not occupy the space of the dielectric layer above the device layer, thus not affecting the arrangement of metal interconnects in subsequent processes and facilitating improved device density.

[0037] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] Figures 3 to 14 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0039] Please refer to Figure 3 and Figure 4 , Figure 3 yes Figure 4 Top view structural diagram, Figure 4 yes Figure 3 A cross-sectional structural schematic diagram along the EE1 direction is provided, the substrate including a base 200, the base 200 including an adjacent first device region I and a second device region II; a first active region 201 located on the first device region I, a second active region 202 located on the second device region II, and an isolation layer 203 between the first active region 201 and the second active region 202 are formed, the first active region 201 and the second active region 202 extend along a first direction X, the first active region 201 includes a first functional region A1 and a first shared region S1.

[0040] In this embodiment, the first active region 201 and the second active region 202 are fin structures. In other embodiments, the first active region and the second active region can be planar structures or three-dimensional structures.

[0041] In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate is made of silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0042] In this embodiment, the material of the first active region 201 includes silicon; the material of the second active region 202 includes silicon. In other embodiments, the material of the first active region may be germanium-silicon; the material of the second active region may be germanium-silicon.

[0043] In this embodiment, the top surface of the isolation layer 203 is lower than the top surfaces of the first active region 201 and the second active region 202.

[0044] In this embodiment, the method for forming the first active region 201 and the second active region 202 includes: etching the substrate to form the first active region 201 and the second active region 202, and a groove (not shown in the figure) between the first active region 201 and the second active region 202; forming a dielectric material layer (not shown in the figure) in the groove; and etching back the dielectric material layer to form the isolation layer 203.

[0045] In this embodiment, the second active area 202 includes a second functional area A2 and a second shared area S2.

[0046] Subsequently, a first gate and a second gate are formed on the substrate 200. The first gate and the second gate are parallel to the second direction Y. The first direction X and the second direction Y are perpendicular to each other. The first gate is located on the first device region I and is located on a portion of the surface of the first active region 201. The second gate is located on the second device region II and is located on a portion of the surface of the second active region 202. The second gate also extends to the surface of the first shared region S1.

[0047] In this embodiment, a first source / drain layer is provided in the first active region 201 located on both sides of the first gate, and a first channel layer is provided in the first active region below the first gate and between adjacent first source / drain layers; a second source / drain layer is provided in the second active region 202 located on both sides of the second gate, and a second channel layer is provided in the second active region below the second gate and between adjacent second source / drain layers.

[0048] In this embodiment, the first device region I is used to form the first pull-up transistor of the SRAM device cell; the second device region II is used to form the second pull-up transistor of the SRAM device cell.

[0049] In this embodiment, the methods for forming the first source / drain layer, the second source / drain layer, the first gate, and the second gate are described in reference [reference needed]. Figures 5 to 14 .

[0050] Please refer to Figure 5 and Figure 6 , Figure 5 yes Figure 6 Top view structural diagram, Figure 6 yes Figure 5A cross-sectional view along the EE1 direction shows that a first dummy gate 204 and a second dummy gate 206 are formed on the substrate 200. The first dummy gate 204 and the second dummy gate 206 are parallel to the second direction Y. The first dummy gate 204 is located on the first device region I and on a portion of the surface of the first active region 201. The second dummy gate 206 is located on the second device region II and on a portion of the surface of the second active region 202. The second dummy gate 206 also extends to the surface of the first shared region S1.

[0051] In this embodiment, the first dummy gate 204 also extends to the surface of the second shared region S2.

[0052] The first dummy gate 204 is used to form the first gate occupying space; the second dummy gate 206 is used to form the second gate occupying space.

[0053] In this embodiment, the first dummy gate 204 has a first sidewall 205 on its sidewall; the second dummy gate 206 has a second sidewall 207 on its sidewall.

[0054] Please continue to refer to this. Figure 5 and Figure 6 A first source / drain layer 208 is formed in the first active region 201 on both sides of the first dummy gate 204; a second source / drain layer 209 is formed in the second active region 202 on both sides of the second dummy gate 206.

[0055] In this embodiment, the method for forming the first source / drain layer 208 includes: forming a first groove (not shown in the figure) in the first active region 201 on both sides of the first dummy gate 204; forming a first epitaxial layer (not shown in the figure) in the first groove; and implanting a first doped ion in the first epitaxial layer. Specifically, the conductivity type of the first doped ion is P-type.

[0056] In this embodiment, the method for forming the second source / drain layer 209 includes: forming a second groove (not shown in the figure) in the second active region 202 on both sides of the second dummy gate 206; forming a second epitaxial layer (not shown in the figure) in the second groove; and implanting a second doped ion in the second epitaxial layer. Specifically, the conductivity type of the second doped ion is P-type.

[0057] Please refer to Figure 7 and Figure 8 , Figure 7 yes Figure 8 Top view structural diagram, Figure 8 yes Figure 7A cross-sectional view along the EE1 direction shows that after the first source / drain layer 208 and the second source / drain layer 209 are formed, an interlayer dielectric layer 210 is formed on the surface of the substrate 200, and the interlayer dielectric layer 210 exposes the top surfaces of the first dummy gate 204 and the second dummy gate 206.

[0058] Subsequently, after the interlayer dielectric layer 210 is formed, the first gate is used to replace the first dummy gate 204; after the interlayer dielectric layer 210 is formed, the second gate is used to replace the second dummy gate 206.

[0059] In this embodiment, the method of forming the first dummy gate 204 by replacing the first gate and the second dummy gate 206 by replacing the second gate is described in reference [reference needed]. Figures 9 to 14 .

[0060] Please refer to Figure 9 and Figure 10 , Figure 9 yes Figure 10 Top view structural diagram, Figure 10 yes Figure 9 A cross-sectional view along the EE1 direction shows that the first dummy gate 204 is removed, and a first gate recess 211 is formed in the interlayer dielectric layer 210; the second dummy gate 206 is removed, and a second gate recess 212 is formed in the interlayer dielectric layer 210.

[0061] The process for removing the first dummy gate 204 is one or a combination of dry etching and wet etching; the process for removing the second dummy gate 206 is one or a combination of dry etching and wet etching.

[0062] In this embodiment, the process of removing the first dummy gate 204 and the second dummy gate 206 is a wet etching process, which is beneficial to reduce the number of process steps in the same process.

[0063] Subsequently, the first gate is formed in the first gate recess 211; and the second gate is formed in the second gate recess 212.

[0064] In this embodiment, a first gate oxide layer and a first gate dielectric layer are provided between the first active region 201 and the first gate; a second gate oxide layer and a second gate dielectric layer are provided between the second active region 202 and the second gate.

[0065] Subsequently, a gate material layer is formed on the surface of the first gate recess 211, the second gate recess 212 and the interlayer dielectric layer 210.

[0066] In this embodiment, before forming the gate material layer, please refer to... Figure 11 and Figure 12 .

[0067] Please refer to Figure 11 and Figure 12 , Figure 11 yes Figure 12 Top view structural diagram, Figure 12 yes Figure 11 A cross-sectional structural diagram along the EE1 direction shows that a gate oxide material layer (not shown in the figure) and a gate dielectric material layer 213 are formed on the surfaces of the first gate groove 211, the second gate groove 212 and the interlayer dielectric layer 210; the gate oxide material layer and the gate dielectric material layer 213 are removed from the first shared region S1 exposed by the second gate groove 212.

[0068] In this embodiment, the gate oxide material layer is formed using an in-situ water vapor generation process. The gate oxide material layer is made of SiON and is used to improve the interface states between the high-k dielectric material and the substrate silicon.

[0069] The gate dielectric material layer 213 is a high-k dielectric material. A high-k dielectric material refers to a dielectric material with a dielectric constant greater than 3.9. In this embodiment, the material of the gate dielectric material layer 213 is HfO2.

[0070] Removing the gate oxide material layer and the gate dielectric material layer 213 from the first shared region S1 exposed by the second gate groove 212 helps to increase the conductivity between the subsequently formed first gate and the first shared region S1.

[0071] The process of removing the gate oxide material layer and the gate dielectric material layer 213 on the first shared region S1 exposed by the second gate groove 212 includes a wet etching process.

[0072] The process parameters for removing the gate dielectric material layer 213 on the first shared region S1 exposed by the second gate groove 212 include: the etching solution comprising a mixture of hydrofluoric acid solution, hydrochloric acid solution, and alcohol solution, wherein the ratio of hydrofluoric acid solution, hydrochloric acid solution, and alcohol solution ranges from 1:1:99 to 1:20:80, wherein the concentration of hydrofluoric acid solution ranges from 1% to 10%, the concentration of hydrochloric acid solution ranges from 10% to 40%, and the concentration of alcohol solution ranges from 50% to 99%. In this embodiment, specifically, the ratio of hydrofluoric acid solution, hydrochloric acid solution, and alcohol solution ranges from 1:10:89.

[0073] In this embodiment, the process parameters for removing the gate oxide material layer on the first shared region S1 exposed by the second gate groove 212 include: the etching solution includes a hydrofluoric acid solution, and the concentration range of the hydrofluoric acid solution is 0.1% to 10%.

[0074] In this embodiment, after forming the gate oxide layer and the gate dielectric layer 213, the gate oxide layer and the gate dielectric layer 213 on the second shared region S2 exposed by the first gate recess 211 are also removed. Removing the gate oxide layer and the gate dielectric layer 213 on the second shared region S2 exposed by the first gate recess 211 helps to increase the conductivity between the subsequently formed second gate and the second shared region S2.

[0075] Specifically, removing the gate oxide material layer and the gate dielectric material layer 213 on the first shared area S1 exposed by the second gate groove 212, and removing the gate oxide material layer and the gate dielectric material layer 213 on the second shared area S2 exposed by the first gate groove 211 are completed in the same process, which helps to save process steps.

[0076] More specifically, the method for removing the gate oxide layer and the gate dielectric layer 213 on the first shared region S1 exposed by the second gate recess 212, and the method for removing the gate oxide layer and the gate dielectric layer 213 on the second shared region S2 exposed by the first gate recess 211, includes: forming a patterned layer on the surface of the first gate recess 211, the second gate recess 212, and the interlayer dielectric layer 210, wherein the patterned layer exposes the gate oxide layer and the gate dielectric layer 213 on the first shared region S1 and the second shared region S2; and after forming the patterned layer, etching the gate oxide layer and the gate dielectric layer 213.

[0077] Please refer to Figure 13 and Figure 14 , Figure 13 yes Figure 14 Top view structural diagram, Figure 14 yes Figure 13 A cross-sectional view along the EE1 direction shows that a gate material layer (not shown) is formed on the surfaces of the first gate recess 211, the second gate recess 212, and the interlayer dielectric layer 210; the gate material layer is planarized until the surface of the interlayer dielectric layer 210 is exposed, and the first gate 214 and the second gate 215 are formed from the gate material layer.

[0078] The second gate 215 is extended to the surface of the first shared region S1, and the second gate 215 and the first active region 201 are electrically connected in the device layer. This does not occupy the space of the dielectric layer above the device layer, so it will not affect the arrangement of metal interconnects in the subsequent process, which is beneficial to improving device density.

[0079] Specifically, in this embodiment, the second gate 215 of the second pull-up transistor is located on the first shared region S1 to connect the first source-drain layer 208 of the first pull-up transistor with the second gate 215 of the second pull-up transistor.

[0080] Furthermore, the first gate 214 is extended to the surface of the second shared region S2, and the first gate 214 and the second active region 202 are electrically connected in the device layer. This does not occupy the space of the dielectric layer above the device layer, so it will not affect the arrangement of metal interconnects in the subsequent process, which is beneficial to improving device density.

[0081] Specifically, the first gate 214 of the first pull-up transistor is located on the second shared region S2 to connect the second source-drain layer 209 of the second pull-up transistor with the first gate 214 of the first pull-up transistor.

[0082] In this embodiment, the gate dielectric material layer and the gate oxide material layer are further planarized, and the first gate oxide layer (not shown in the figure) is formed by the gate oxide material layer in the first gate groove 211, the first gate dielectric layer 216 is formed by the gate dielectric material layer in the first gate groove 211, the second gate oxide layer (not shown in the figure) is formed by the gate oxide material layer in the second gate groove 212, and the second gate dielectric layer 217 is formed by the gate dielectric material layer in the second gate groove 212.

[0083] The material of the first gate 214 includes metals and their derivatives, including one or more combinations of titanium nitride, tantalum nitride, titanium, aluminum, tungsten, copper and lanthanide metal oxides; the material of the second gate 215 includes metals and their derivatives, including one or more combinations of titanium nitride, tantalum nitride, titanium, aluminum, tungsten, copper and lanthanide metal oxides.

[0084] In this embodiment, after forming the first gate 214 and the second gate 215, a first dielectric layer (not shown in the figure) is formed on the interlayer dielectric layer 210. The first dielectric layer contains a plurality of contact layers (not shown in the figure), which are located on the surfaces of the first gate 214, the second gate 215, the first source / drain layer 208, and the second source / drain layer 209, respectively. After forming the first dielectric layer, a second dielectric layer (not shown in the figure) is formed on the first dielectric layer. The second dielectric layer contains a metal interconnect layer (not shown in the figure), which is electrically connected to the plurality of contact layers. The plurality of contact layers are used to connect the device layer to the upper metal interconnect layer.

[0085] Accordingly, one embodiment of the present invention also provides a semiconductor structure formed using the above method. Please refer to [the original text]. Figure 13 and Figure 14 The device includes: a substrate, the substrate including a base 200, the base 200 including adjacent first device region I and second device region II; a first active region 201 located on the first device region I and a second active region 202 located on the second device region II, an isolation layer 203 between the first active region 201 and the second active region 202, the first active region 201 and the second active region 202 extending along a first direction X, the first active region 201 including a first functional region A1 and a first shared region S1; a first gate 214 and a second gate 215 located on the substrate, the first gate 214 and the second gate 215 being parallel to a second direction Y, the first direction X and the second direction Y being perpendicular to each other, the first gate 214 being located on the first device region I and located on a portion of the surface of the first active region 201, the second gate 215 being located on the second device region II and located on a portion of the surface of the second active region 202, the second gate 215 also extending to the surface of the first shared region S1.

[0086] The second gate 215 is extended to the surface of the first shared region S1, and the second gate 215 and the first active region 201 are electrically connected in the device layer. This does not occupy the space of the dielectric layer above the device layer, so it will not affect the arrangement of metal interconnects in the subsequent process, which is beneficial to improving device density.

[0087] In this embodiment, the second active region 202 includes a second functional region A2 and a second shared region S2, and the first gate 214 extends to the surface of the second shared region S2.

[0088] The first gate 214 is extended to the surface of the second shared region S2, and the first gate 214 and the second active region 202 are electrically connected in the device layer. This does not occupy the space of the dielectric layer above the device layer, so it will not affect the arrangement of metal interconnects in the subsequent process, which is beneficial to improving device density.

[0089] In this embodiment, a first source / drain layer 208 is provided in the first active region 201 located on both sides of the first gate 214, and a first channel layer is provided in the first active region below the first gate and between adjacent first source / drain layers; a second source / drain layer 209 is provided in the second active region 202 located on both sides of the second gate 215, and a second channel layer is provided in the second active region below the second gate and between adjacent second source / drain layers.

[0090] In this embodiment, the substrate has an interlayer dielectric layer 210, and the first gate 214 and the second gate 215 are located on the interlayer dielectric layer 210; a first dielectric layer (not shown in the figure) is located on the interlayer dielectric layer 210, and a plurality of contact layers (not shown in the figure) are located within the first dielectric layer, and the plurality of contact layers are respectively located on the surfaces of the first gate 214, the second gate 215, the first source / drain layer 208, and the second source / drain layer 209; a second dielectric layer (not shown in the figure) is located on the first dielectric layer, and a metal interconnect layer (not shown in the figure) is located within the second dielectric layer, and the metal interconnect layer is electrically connected to the plurality of contact layers.

[0091] The material of the first gate 214 includes metals and their derivatives, including one or more combinations of titanium nitride, tantalum nitride, titanium, aluminum, tungsten, copper and lanthanide metal oxides; the material of the second gate 215 includes metals and their derivatives, including one or more combinations of titanium nitride, tantalum nitride, titanium, aluminum, tungsten, copper and lanthanide metal oxides.

[0092] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, the substrate including a base, the base including adjacent first device regions and second device regions; A first active region located on the first device region and a second active region located on the second device region, with an isolation layer between the first active region and the second active region, the first active region and the second active region extending along a first direction, the first active region including a first functional region and a first shared region; A first gate and a second gate are located on the substrate, the first gate and the second gate are parallel to a second direction, the first direction and the second direction are perpendicular to each other, the first gate is located on the first device region and on a portion of the surface of the first active region, the second gate is located on the second device region and on a portion of the surface of the second active region, and the second gate also extends to the surface of the first shared region, so that the second gate and the first active region are directly electrically connected in the device layer.

2. The semiconductor structure as described in claim 1, characterized in that, The second active region includes a second functional region and a second shared region; the first gate also extends to the surface of the second shared region.

3. The semiconductor structure as described in claim 1, characterized in that, include: The first active region located on both sides of the first gate has a first source / drain layer, and the first active region below the first gate and located between adjacent first source / drain layers has a first channel layer; the second active region located on both sides of the second gate has a second source / drain layer, and the second active region below the second gate and located between adjacent second source / drain layers has a second channel layer.

4. The semiconductor structure as described in claim 3, characterized in that, The substrate has an interlayer dielectric layer, and the first gate and the second gate are located in the interlayer dielectric layer; A first dielectric layer is located on the interlayer dielectric layer, and a plurality of contact layers are located within the first dielectric layer. The plurality of contact layers are respectively located on the surfaces of the first gate, the second gate, the first source / drain layer, and the second source / drain layer. A second dielectric layer is located on the first dielectric layer, and the second dielectric layer has a metal interconnect layer therein, the metal interconnect layer being electrically connected to the plurality of contact layers.

5. The semiconductor structure as described in claim 1, characterized in that, The material of the first gate includes metals and their derivatives, the metals and their derivatives including one or more combinations of titanium nitride, tantalum nitride, titanium, aluminum, tungsten, copper and lanthanide metal oxides; the material of the second gate includes metals and their derivatives, the metals and their derivatives including one or more combinations of titanium nitride, tantalum nitride, titanium, aluminum, tungsten, copper and lanthanide metal oxides.

6. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a base, the base including adjacent first device regions and second device regions; A first active region is formed on the first device region, a second active region is formed on the second device region, and an isolation layer is formed between the first active region and the second active region. The first active region and the second active region extend along a first direction. The first active region includes a first functional region and a first shared region. A first gate and a second gate are formed on the substrate. The first gate and the second gate are parallel to a second direction, and the first direction and the second direction are perpendicular to each other. The first gate is located on the first device region and on a portion of the surface of the first active region. The second gate is located on the second device region and on a portion of the surface of the second active region. The second gate also extends to the surface of the first shared region, so that the second gate and the first active region are directly electrically connected in the device layer.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, A first source / drain layer is provided in the first active region located on both sides of the first gate, and a first channel layer is provided in the first active region below the first gate and between adjacent first source / drain layers; a second source / drain layer is provided in the second active region located on both sides of the second gate, and a second channel layer is provided in the second active region below the second gate and between adjacent second source / drain layers. The method for forming the first source / drain layer, the second source / drain layer, the first gate, and the second gate includes: forming a first dummy gate and a second dummy gate on the substrate, the first dummy gate and the second dummy gate being parallel to a second direction, the first dummy gate being located on the first device region and located on a portion of the surface of the first active region, the second dummy gate being located on the second device region and located on a portion of the surface of the second active region, and the second dummy gate further extending to the surface of the first shared region; forming a first source / drain layer in the first active region on both sides of the first dummy gate; forming a second source / drain layer in the second active region on both sides of the second dummy gate; after forming the first source / drain layer and the second source / drain layer, forming an interlayer dielectric layer on the substrate surface, the interlayer dielectric layer exposing the top surfaces of the first dummy gate and the second dummy gate; after forming the interlayer dielectric layer, replacing the first dummy gate with the first gate; and after forming the interlayer dielectric layer, replacing the second dummy gate with the second gate.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, After forming the first gate and the second gate, the method further includes: forming a first dielectric layer on the interlayer dielectric layer, the first dielectric layer having a plurality of contact layers, the plurality of contact layers being located on the surfaces of the first gate, the second gate, the first source / drain layer, and the second source / drain layer respectively; after forming the first dielectric layer, forming a second dielectric layer on the first dielectric layer, the second dielectric layer having a metal interconnect layer, the metal interconnect layer being electrically connected to the plurality of contact layers.

9. The method for forming a semiconductor structure as described in claim 7, characterized in that, The method of replacing the first dummy gate with a first gate and the second dummy gate with a second gate includes: removing the first dummy gate and forming a first gate trench in the interlayer dielectric layer; removing the second dummy gate and forming a second gate trench in the interlayer dielectric layer; forming the first gate in the first gate trench; and forming the second gate in the second gate trench.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The method for forming the first gate and the second gate includes: forming a gate material layer on the surface of the first gate recess, the second gate recess and the interlayer dielectric layer; planarizing the gate material layer until the surface of the interlayer dielectric layer is exposed.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, A first gate oxide layer and a first gate dielectric layer are provided between the first active region and the first gate; a second gate oxide layer and a second gate dielectric layer are provided between the second active region and the second gate.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, A method for forming the first gate oxide layer, the first gate dielectric layer, the second gate oxide layer, and the second gate dielectric layer includes: before forming the gate material layer, forming a gate oxide layer and a gate dielectric layer on the surfaces of the first gate trench, the second gate trench, and the interlayer dielectric layer; removing the gate oxide layer and the gate dielectric layer on the first shared region exposed by the second gate trench; after forming the gate material layer, planarizing the gate dielectric layer and the gate oxide layer until the interlayer dielectric layer is exposed, forming the first gate oxide layer with the gate oxide layer in the first gate trench, forming the first gate dielectric layer with the gate dielectric layer in the first gate trench, forming the second gate oxide layer with the gate oxide layer in the second gate trench, and forming the second gate dielectric layer with the gate dielectric layer in the second gate trench.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The process for removing the gate oxide material layer and the gate dielectric material layer on the first shared region exposed by the second gate groove includes a wet etching process.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The process parameters for removing the gate dielectric material layer on the first shared region exposed by the second gate groove include: the etching solution is a mixture of hydrofluoric acid solution, hydrochloric acid solution and alcohol solution, the ratio of hydrofluoric acid solution, hydrochloric acid solution and alcohol solution is in the range of 1:1:99 to 1:20:80, wherein the concentration of hydrofluoric acid solution is in the range of 1% to 10%, the concentration of hydrochloric acid solution is in the range of 10% to 40%, and the concentration of alcohol solution is in the range of 50% to 99%.

15. The method for forming a semiconductor structure as described in claim 12, characterized in that, The second active region includes a second functional region and a second shared region; the first gate also extends to the surface of the second shared region.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, After the gate oxide layer and the gate dielectric layer are formed, the gate oxide layer and the gate dielectric layer on the second shared region exposed by the first gate recess are also removed.

17. The method for forming a semiconductor structure as described in claim 6, characterized in that, An isolation layer is provided between the first active region and the second active region.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The top surface of the isolation layer is lower than the top surfaces of the first active region and the second active region; the method for forming the first active region and the second active region includes: etching the substrate to form the first active region and the second active region, and a groove between the first active region and the second active region; forming a dielectric material layer in the groove; and etching back the dielectric material layer to form the isolation layer.

19. The method for forming a semiconductor structure as described in claim 6, characterized in that, The material of the first gate includes metals and their derivatives, the metals and their derivatives including one or more combinations of titanium nitride, tantalum nitride, titanium, aluminum, tungsten, copper and lanthanide metal oxides; the material of the second gate includes metals and their derivatives, the metals and their derivatives including one or more combinations of titanium nitride, tantalum nitride, titanium, aluminum, tungsten, copper and lanthanide metal oxides.

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