Memory, semiconductor structure and its fabrication method

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By setting up isolation and mask layers in the dynamic random access memory, the problem of damage to the peripheral area during the etching process is solved, the product yield is improved, and the risk of short circuits is reduced.

CN116801611BActive Publication Date: 2026-07-03CHANGXIN MEMORY TECH INC

Patent Information

Authority / Receiving Office: CN · China
Patent Type: Patents(China)
Current Assignee / Owner: CHANGXIN MEMORY TECH INC
Filing Date: 2022-03-15
Publication Date: 2026-07-03

AI Technical Summary

Technical Problem

In the current process of patterning the array region of dynamic random access memory, structural anomalies are prone to occur in the peripheral region, which leads to a decrease in device yield.

Method used

By setting an isolation layer between the bit line structure and the conductive contact plug, and forming a stacked film layer in the peripheral area, a mask layer is used to protect the surface of the peripheral area. During the etching process, the top of the isolation layer is exposed, which prevents the bit line structure from short-circuiting with the conductive contact plug and protects the peripheral area structure from damage.

Benefits of technology

This reduces the risk of device short circuits, improves product yield, avoids damage to the peripheral area during the etching process, and further enhances product yield.

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Figure CN116801611B_ABST

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Abstract

This disclosure relates to the field of semiconductor technology, and mainly to a memory, a semiconductor structure, and a method for fabricating the same. The fabrication method includes: providing a substrate comprising an array region and a peripheral region arranged side-by-side; the array region having an isolation layer, conductive contact plugs, and multiple spaced bit line structures extending perpendicular to the substrate; the isolation layer covering the sidewalls of the bit line structures; and conductive contact plugs formed in the regions enclosed by the isolation layers between adjacent bit line structures; a stacked film layer formed in the peripheral region; forming a mask layer covering the bit line structures, the isolation layer, the conductive contact plugs, and the stacked film layer; and etching the mask layer to expose the top of the isolation layer. This fabrication method can reduce the risk of damage to the peripheral region and improve product yield.

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