Semiconductor device

Abstract

A semiconductor device is disclosed. A semiconductor device includes a first memory block having a first block pitch, and a second memory block belonging to a same plane as the first memory block, the second memory block being closer to a plane edge than the first memory block, the plane edge being an edge of the plane, wherein the second memory block has a second block pitch greater than the first block pitch.

Description

Technical Field

[0001] Exemplary implementations relate to an electronic device, and more specifically, to a semiconductor device. Background Technology

[0002] The integration density of semiconductor devices is primarily determined by the area occupied by a single memory cell. Recently, as the integration density of semiconductor devices with memory cells formed as a single layer on a substrate has reached its limit, 3D semiconductor devices with memory cells stacked on a substrate have been proposed. Furthermore, various structures and manufacturing methods are being developed to improve the operational reliability of such semiconductor devices. Summary of the Invention

[0003] In one embodiment, a semiconductor device may include: a first memory block having a first block pitch; and a second memory block belonging to the same plane as the first memory block, the second memory block being closer to the edge of the plane than the first memory block, the edge of the plane being the edge of the plane, wherein the second memory block has a second block pitch greater than the first block pitch.

[0004] In one embodiment, a semiconductor device may include: a first stack comprising alternating layers of a first conductive layer and a first insulating layer; a first channel structure extending through the first stack; a second stack comprising alternating layers of a second conductive layer and a second insulating layer; a second channel structure extending through the second stack; and a slit structure located between the first and second stacks. The first channel structure and the slit structure may be spaced apart by a first distance. The second channel structure and the slit structure may be spaced apart by a second distance. The second distance may be greater than the first distance.

[0005] In one embodiment, a semiconductor device may include: a memory plane; and a plurality of memory blocks included in the memory plane and having different block pitches. The size of the block pitch of the memory blocks is inversely proportional to the distance of the memory blocks from the edge of the memory plane. Attached Figure Description

[0006] Figures 1A to 1C This is a diagram illustrating the structure of a semiconductor device according to one embodiment.

[0007] Figure 2A and Figure 2B This is a diagram illustrating the structure of a semiconductor device according to one embodiment.

[0008] Figure 3A and Figure 3B This is a diagram illustrating the structure of a semiconductor device according to one embodiment.

[0009] Figure 4This is a diagram illustrating the structure of a semiconductor device according to one embodiment.

[0010] Figure 5A and Figure 5B This is a diagram illustrating the structure of a semiconductor device according to one embodiment.

[0011] Figures 6A to 6C This is a diagram illustrating the structure of a semiconductor device according to one embodiment. Detailed Implementation

[0012] Various implementations involve semiconductor devices with stable structures and improved characteristics.

[0013] According to this embodiment, the integration density of a semiconductor device can be improved by stacking memory cells in a 3D manner. Furthermore, a semiconductor device with a stable structure and improved reliability can be provided.

[0014] The following description, with reference to the accompanying drawings, describes embodiments based on the technical spirit of this disclosure.

[0015] Figures 1A to 1C This is a diagram illustrating the structure of a semiconductor device according to one embodiment.

[0016] Reference Figure 1A and Figure 1B The semiconductor device may include a chip, and the chip may include multiple planes (PLs). The chip may be a semiconductor chip, a memory chip, etc. The planes (PLs) may be memory planes. The planes (PLs) may be arranged in one direction or in a matrix shape. In one embodiment, the planes (PLs) may be arranged along a first direction I and a second direction II intersecting the first direction I. Specifically, the first direction I may be perpendicular to the second direction II.

[0017] Each plane PL may include an edge region E and a central region C. The edge region E can be defined as having a predetermined width along the edge of the plane (plane edge PE). See reference... Figure 1A The edge region E can be defined along the farthest planar edge PE in the second direction II. (Refer to...) Figure 1B An edge region E can be defined along the planar edge PE near the chip edge CE. A central region C can be a region spaced further away from the planar edge PE than the edge region E. A plane PL can include both the edge region E and the central region C. Other regions of the plane PL besides the edge region E can be the central region C. Alternatively, a local region including the center of the plane PL can be defined as the central region C.

[0018] Reference Figure 1CPlane PL may include multiple storage blocks MB1 and MB2. Storage blocks MB1 and MB2 may each include memory cells for storing data. A storage block may be a unit for erasing data. In plane PL, storage blocks MB1 and MB2 may be arranged along a first direction I, along a second direction II, or along both directions II. In one embodiment, a first storage block MB1 may be adjacent to a second storage block MB2 along the second direction II.

[0019] The first storage block MB1 and the second storage block MB2 may belong to the same plane PL. The second storage block MB2 may be closer to the plane edge PE than the first storage block MB1. In one embodiment, the second storage block MB2 may be located in the edge region E, and the first storage block MB1 may be located in the central region C.

[0020] The first storage block MB1 and the second storage block MB2 can have different sizes. Here, "size" can refer to the physical size of the storage block and can correspond to the area of ​​a plane defined in the first direction I and the second direction II. In one embodiment, the first storage block MB1 and the second storage block MB2 can have different block pitches.

[0021] A first memory block MB1 may have a first block pitch P1, and a second memory block MB2 may have a second block pitch P2. The second block pitch P2 may be greater than the first block pitch P1. Specifically, the second block pitch P2 may be equal to or less than 1.5 times the first block pitch P1. The block pitch may indicate the width of each of memory blocks MB1 and MB2 along a second direction II. The first memory block MB1 may be adjacent to the second memory block MB2 along the block pitch direction (i.e., the second direction II).

[0022] The first storage block MB1 and the second storage block MB2 can have different functions. In one embodiment, the first storage block MB1 can be a real storage block, and the second storage block MB2 can be a dummy storage block. The real storage block can include memory cells for storing data. The dummy storage block can have the same or similar structure as the real storage block. However, data can be stored in the dummy storage block. Alternatively, the dummy storage block can be a redundant storage block and can include redundant memory cells for repair operations.

[0023] Based on the above structure, the storage block closer to the plane edge PE (e.g., Figure 1C Storage block MB2) can be farther from the plane edge PE than storage blocks (e.g., Figure 1CThe memory block MB1 has a larger block pitch. Therefore, defects that may occur during the manufacturing process of the memory block located in the edge region E can be minimized or prevented. In addition, the memory block located in the edge region E can have a stable structure.

[0024] Figure 2A , Figure 2B , Figure 3A and Figure 3B This is a diagram illustrating the structure of a semiconductor device according to one embodiment. Figure 2A It can be a floor plan, and Figure 2B It can be along Figure 2A A cross-sectional view taken from line A-A'. Figure 3A It can be a floor plan, and Figure 3B It can be along Figure 3A The cross-sectional view taken by line B-B'. In the following text, content repeated above will be omitted.

[0025] Reference Figure 2A and Figure 2B The semiconductor device may include a first memory block MB1. The first memory block MB1 may include a first stack ST1 and a first through-structure PS1. The first memory block MB1 may also include a first source structure 10, a first slit structure SL11, a second slit structure SL12, or a combination thereof.

[0026] The first stack ST1 may include alternating layers of a first conductive layer 11 and a first insulating layer 12. The first conductive layer 11 may be a word line, bit line, select line, etc. The first conductive layer 11 may include a conductive material, such as polysilicon, tungsten, molybdenum, and metal. The first insulating layer 12 may be used to insulate the stacked first conductive layers 11 from each other. The first insulating layer 12 may include oxides, nitrides, air gaps, etc.

[0027] The first through-structure PS1 may penetrate the first laminate ST1. The first through-structure PS1 may penetrate the first laminate ST1 along a third direction III. The third direction III may represent a direction protruding from or penetrating a plane defined by the first direction I and the second direction II. In one embodiment, the third direction III may indicate the lamination direction. The third direction III may be perpendicular to both the first direction I and the second direction II.

[0028] The first memory cell can be located at a corresponding intersection between the first through-structure PS1 and the first conductive layer 11. The first memory cell can be stacked along the first through-structure PS1. The first memory block MB1 can be a physical memory block, and the first memory cell can be a physical memory cell.

[0029] In one embodiment, the first through-structure PS1 may be a channel structure. The channel structure may include a channel layer 13 penetrating the first stack ST1. The channel structure may also include a memory layer 14 covering the outer wall of the channel layer 13, an insulating core 15 within the channel layer 13, or a combination thereof. The memory layer 14 may include a tunneling layer, a data storage layer, a barrier layer, or a combination thereof. The channel structure can be connected to the first source structure 10 via the first stack ST1. The channel layer 13 may be directly connected to the first source structure 10, or connected to the first source structure 10 via a semiconductor pattern grown via an epitaxial method.

[0030] In one embodiment, the first through-structure PS1 may be an electrode structure. The electrode structure may include an electrode layer penetrating the first laminate ST1, and may also include a memory layer covering the outer or inner wall of the electrode layer. The memory layer may include a variable resistance material.

[0031] A first slit structure SL11 can penetrate the first laminate ST1. The first slit structure SL11 can extend along a first direction. A second slit structure SL12 can be inserted into the first laminate ST1. The second slit structure SL12 can extend along the first direction I. The second slit structure SL12 can overlap with the first penetrating structure PS1. At least one second slit structure SL12 can be located between a pair of first slit structures SL11.

[0032] The first slit structure and the second slit structure SL12 can be inserted into the first stack ST1 to different depths. The second slit structure SL12 can be inserted into the first stack ST1 to a shallower depth than the first slit structure SL11. The second slit structure SL12 can be inserted into the first stack ST1 to a depth penetrating at least one of the uppermost first conductive layers 11.

[0033] Reference Figure 3A and Figure 3B The semiconductor device may include a second memory block MB2. The second memory block MB2 may include a second stack ST2 and a second through-hole structure PS2. The second memory block MB2 may also include a second source structure 20, a first slit structure SL21, a second slit structure SL22, or a combination thereof.

[0034] The second stack ST2 may include alternating layers of second conductive layers 21 and second insulating layers 22. The second conductive layer 21 may be a word line, bit line, select line, etc. The second conductive layer 21 may include conductive materials such as polysilicon, tungsten, molybdenum, and metals. The second insulating layer 22 may be used to insulate the stacked second conductive layers 21 from each other. The second insulating layer 22 may include oxides, nitrides, air gaps, etc.

[0035] The second through-structure PS2 can penetrate the second stack ST2. The second memory cell can be located at the corresponding intersection between the second through-structure PS2 and the second conductive layer 21. The second memory cell can be stacked along the second through-structure PS2. The second memory block MB2 can be a dummy memory block, and the second memory cell can be a dummy memory cell.

[0036] In one embodiment, the second through-structure PS2 may be a channel structure. The channel structure may include a channel layer 23 penetrating the second stack ST2. The channel structure may also include a memory layer 24 covering the outer wall of the channel layer 23, an insulating core 25 within the channel layer 23, or a combination thereof. The memory layer 24 may include a tunneling layer, a data storage layer, a barrier layer, or a combination thereof. The channel structure can be connected to the second source structure 20 via the second stack ST2. The channel layer 23 can be directly connected to the second source structure 20, or it can be connected to the second source structure 20 via a semiconductor pattern grown via an epitaxial method.

[0037] In one embodiment, the second through-structure PS2 may be an electrode structure. The electrode structure may include an electrode layer penetrating the second stack ST2, and may further include a memory layer covering the outer or inner wall of the electrode layer. The memory layer may include a variable resistance material.

[0038] The first slit structure SL21 can penetrate the second stack ST2. The first slit structure SL21 can extend along a first direction. The second slit structure SL22 can be inserted into the second stack ST2. The second slit structure SL22 can extend along the first direction I. The second slit structure SL22 can overlap with the second through structure PS2. At least one second slit structure SL22 can be located between a pair of first slit structures SL21.

[0039] The first slit structure and the second slit structure SL22 can be inserted into the second stack ST2 to different depths. The second slit structure SL22 can be inserted into the second stack ST2 to a shallower depth than the first slit structure SL21. The second slit structure SL22 can be inserted into the second stack ST2 to a depth penetrating at least one of the uppermost second conductive layers 21.

[0040] Reference Figure 2A and Figure 3A The first storage block MB1 may have a first block pitch P1, and the second storage block MB2 may have a second block pitch P2 different from the first block pitch P1. The second storage block MB2 may be closer to the edge of the plane than the first storage block MB1, and the second block pitch P2 may be greater than the first block pitch P1.

[0041] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3B In the first storage block MB1, the first through-structures PS1 can be spaced apart by a third distance D3. The first through-structure PS1 and the first slit structure SL11 can be spaced apart by a first distance D1. The distance between the first slit structure SL11 and the first through-structure PS1 closest to the first slit structure SL11 can be the first distance D1. In one embodiment, the first distance D1 can be the distance between the edge of the first through-structure PS1 and the edge of the first slit structure SL11 along the second direction II.

[0042] In the second memory block MB2, the second through structures PS2 can be spaced apart by a fourth distance D4. The third distance D3 and the fourth distance D4 can be substantially equal to or different from each other. The second through structure PS2 and the first slit structure SL21 can be spaced apart by a second distance D2 different from the first distance D1. The distance between the first slit structure SL21 and the second through structure PS2 closest to the first slit structure SL21 can be the second distance D2. In one embodiment, the second distance D2 can be the distance between the edge of the second through structure PS2 along the second direction II and the edge of the first slit structure SL21. The second distance D2 can be greater than the first distance D1. Specifically, the second distance D2 can be equal to or less than twice the first distance D1. This structure can sufficiently ensure the distance between the second through structure PS2 and the first slit structure SL21 in the second memory block MB2. Furthermore, this structure can selectively increase only the block pitch of the second memory block MB2, which is closer to the edge of the plane than the first memory block MB1, among the multiple memory blocks belonging to the plane.

[0043] Based on the above structure, a second storage block MB2, which is closer to the plane edge than the first storage block MB1, can have a second block pitch P2 larger than the first block pitch P1. In the second storage block MB2, the fourth distance D4 can be substantially equal to the third distance D3, and the second distance D2 can be greater than the first distance D1. Since the size of the storage blocks is adjusted according to their position, the storage blocks can have a stable structure. In particular, storage blocks located near the plane edge can have a stable structure.

[0044] Figure 4 This is a diagram illustrating the structure of a semiconductor device according to one embodiment. In the following text, content repeated above will be omitted.

[0045] Reference Figure 4 The semiconductor device may include a first stack ST1, a second stack ST2, a first through structure PS1, a second through structure PS2, a slit structure SL, or a combination thereof.

[0046] The first laminate ST1 may include alternating layers of a first conductive layer and a first insulating layer. A first through-structure PS1 may penetrate the first laminate ST1. The second laminate ST2 may include alternating layers of a second conductive layer and a second insulating layer. A second through-structure PS2 may penetrate the second laminate ST2. A slit structure SL may be located between the first laminate ST1 and the second laminate ST2. The slit structure SL electrically isolates the first laminate ST1 and the second laminate ST2 from each other.

[0047] The first through-structure PS1 and the slit structure SL can be spaced apart by a first distance D1. The second through-structure PS2 and the slit structure SL can be spaced apart by a second distance D2 greater than the first distance D1. The second stack ST2 can be closer to the plane edge than the first stack ST1. The first stack ST1 can belong to the first memory block MB1, and the second stack ST2 can belong to the second memory block MB2. The second memory block MB2 can have a larger block pitch than the first memory block MB1.

[0048] Figure 5A and Figure 5B This is a diagram illustrating the structure of a semiconductor device according to one embodiment.

[0049] Reference Figure 5A The semiconductor device may include a first source structure 30, a first stack ST1, a first through-structure PS1, a first slit structure SL1, or a combination thereof. The first stack ST1 and the first through-structure PS1 may belong to a first memory block MB1. The first through-structure PS1 may have a first axis X1. The first axis X1 may have a first angle θ1 relative to a reference axis RX, and the first through-structure PS1 may penetrate the first stack ST1 at the first angle θ1. In one embodiment, the reference axis RX may be parallel to a third direction III. The first axis X1 may be substantially the same as the third direction III. Here, "substantially" can mean that the measured values ​​are equal to each other and their differences may fall within the range including process tolerances.

[0050] Reference Figure 5B The semiconductor device may include a second source structure 40, a second stack ST2, a second through-hole structure PS2, a second slit structure SL2, or a combination thereof. The second stack ST2 and the second through-hole structure PS2 may belong to a second memory block MB2. The second memory block MB2 may be closer to the edge of the plane than the first memory block MB1.

[0051] The second through-structure PS2 may have a second axis X2. The second axis X2 may have a second angle θ2 relative to the reference axis RX, and the second through-structure PS2 may penetrate the second stack ST2 at the second angle θ2. The second angle θ2 may be different from the first angle θ1. The second angle θ2 may be greater than the first angle θ1.

[0052] The block pitch of a memory block can be determined by comparing the angle at which the through-structure penetrates the stack with a reference value. The reference value serves as a guide for determining whether to correct the block pitch. When the through-angle exceeds the reference value, the block pitch of the corresponding memory block can be increased. In this case, the gap between the through-structures can be maintained, and the distance between the slit structure and the through-structure can be increased based on the increase in block pitch. Furthermore, the increase in block pitch can be adjusted according to how much the through-angle exceeds the reference value.

[0053] Reference Figure 5A The reference axis RX and the first axis X1 can coincide with each other, and the first angle θ1 can be equal to or less than the reference value. In this case, the first storage block MB1 can have a first block pitch P1. (Reference) Figure 5B The second through-hole structure PS2 can be tilted toward the second slit structure SL2. The second angle θ2 can be greater than the reference value. In this case, the second storage block MB2 with a through-hole angle of the second angle θ2 can have a larger block pitch than the first storage block MB1 with a through-hole angle of the first angle θ1. The second storage block MB2 can have a second pitch P2 that is greater than the first block pitch P1.

[0054] When the first memory block MB1 and the second memory block MB2 have the same block pitch, defects may occur in the manufacturing process of the second memory block MB2. Due to process limitations, the second memory block MB2, which is relatively closer to the edge of the plane, may have a second angle θ2 greater than the reference value. In this case, the distance between the second through structure PS2 and the second slit structure SL2 may be too narrow. The distance D2_U between the upper surface of the second through structure PS2 and the second slit structure SL2 may not be adequately guaranteed. The distance D2_L between the lower surface of the second through structure PS2 and the second slit structure SL2 may not be adequately guaranteed. Therefore, the second through structure PS2 may be exposed or damaged during the process of forming the second slit structure SL2.

[0055] Therefore, according to one embodiment, the second storage block MB2, having a second angle θ2 greater than the reference value, can have a relatively large second block pitch P2. Even if the second through-structure PS2 is tilted due to process limitations, this structure can ensure a sufficient distance between the second through-structure PS2 and the second slit structure SL2.

[0056] Figures 6A to 6CThis is a diagram illustrating the structure of a semiconductor device according to one embodiment. In the following text, content repeated above will be omitted.

[0057] Reference Figure 6A A plane may include multiple memory blocks. Multiple memory blocks included in the same plane may have different block pitches. The multiple memory blocks may include at least one second memory block MB2 and other first memory blocks MB1 located near the plane edge PE. Each first memory block MB1 may have a first block pitch P11. The second memory block MB2 may have a second block pitch P12 that is greater than the first block pitch P11.

[0058] Reference Figure 6B Multiple memory blocks included in the same plane can be grouped according to their distance from the plane edge PE. The plane can include a first group G1 to an nth group Gn. The first group G1 can be the furthest from the plane edge PE, and the nth group Gn can be the closest to the plane edge PE. Here, n can be an integer equal to or greater than 2.

[0059] Each of groups G1 to Gn may include at least one storage block, and the number of storage blocks included in each group G1 to Gn may be equal to or different from each other. The first group G1 may include at least one first storage block MB1, the second group G2 may include at least one second storage block MB2, and the nth group may include at least one nth storage block MBn.

[0060] Groups G1 through Gn can have different block pitches. Storage blocks within the same group can have the same block pitch. First storage blocks MB1 can each have a first block pitch P21. Nth storage blocks MBn can each have an nth block pitch P2n greater than the first block pitch P21. Second storage blocks MB2 can each have a second block pitch P22 greater than the first block pitch P21 and less than the nth block pitch.

[0061] Reference Figure 6C Based on the distances between multiple memory blocks and the plane edge PE, memory blocks belonging to the same plane can have different block pitches. The distance to the plane edge PE can be inversely proportional to the block pitch. The size of the block pitch of a memory block can be inversely proportional to its distance from the edge of the memory plane. The first memory block MB1 can be farthest from the plane edge PE and can have the smallest first block pitch P31. The second memory block MB2 can be closer to the plane edge than the first memory block MB1 and can have a second block pitch P32 that is larger than the first block pitch P31. The nth memory block MBn can be closest to the plane edge PE and can have the largest nth block pitch P3n.

[0062] Based on the above structure, considering the distance from the plane edge, some memory blocks can have relatively large block pitches. Among memory blocks belonging to the same plane, those closer to the plane edge can have relatively large block pitches. Therefore, it is not necessary to increase the block pitch of all memory blocks; only the block pitch of the memory blocks requiring correction can be increased.

[0063] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit and scope of the invention as defined by the appended claims.

[0064] Cross-references to related applications

[0065] This application claims priority to Korean Patent Application No. 10-2022-0031881, filed on March 15, 2022, which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, the semiconductor device comprising: A first storage block, the first storage block having a first block pitch; as well as The second storage block belongs to the same plane as the first storage block, but is closer to the edge of the plane than the first storage block. The second storage block has a second block pitch that is greater than the pitch of the first block.

2. The semiconductor device according to claim 1, wherein, The first storage block is a real storage block, and The second storage block is a dummy storage block.

3. The semiconductor device according to claim 1, wherein, The first storage block is adjacent to the second storage block along the block pitch direction.

4. The semiconductor device according to claim 1, wherein, The pitch of the second block is equal to or less than 1.5 times the pitch of the first block.

5. The semiconductor device according to claim 1, wherein, The first storage block includes a first stack, a first slit structure penetrating the first stack, and a first through structure penetrating the first stack. The second storage block includes a second stack, a second slit structure penetrating the second stack, and a second through structure penetrating the second stack.

6. The semiconductor device according to claim 5, wherein, The first through-hole structure and the first slit structure are spaced apart by a first distance. Wherein, the second through structure and the second slit structure are spaced apart by a second distance, and Wherein, the second distance is greater than the first distance.

7. The semiconductor device according to claim 6, wherein, The second distance is equal to or less than twice the first distance.

8. The semiconductor device according to claim 5, wherein, The second through structure is inclined toward the second slit structure.

9. The semiconductor device according to claim 5, wherein, The first through-structure penetrates the first stack at a first angle relative to the reference axis, and The second through structure penetrates the second stacked body at a second angle greater than the first angle relative to the reference axis.

10. The semiconductor device of claim 1, further comprising a third memory block located between the first memory block and the second memory block, and the third memory block having a third block pitch greater than the first block pitch and less than the second block pitch.

11. The semiconductor device according to claim 10, wherein, The first storage block, the second storage block, and the third storage block belong to the same plane.

12. A semiconductor device, the semiconductor device comprising: A first laminate, the first laminate comprising alternating layers of a first conductive layer and a first insulating layer; The first channel structure penetrates the first laminate; The second laminate includes alternating layers of a second conductive layer and a second insulating layer. The second channel structure penetrates the second laminate; as well as A slit structure located between the first laminate and the second laminate. The first channel structure and the slit structure are spaced apart by a first distance. Wherein, the second channel structure and the slit structure are spaced apart by a second distance, and Wherein, the second distance is greater than the first distance.

13. The semiconductor device according to claim 12, wherein, The first and second stacked bodies belong to the same plane, and The second stacked body is closer to the edge of the plane than the first stacked body, and the edge of the plane is the edge of the plane.

14. The semiconductor device according to claim 12, wherein, The first channel structure penetrates the first laminate at a first angle relative to the reference axis, and The second channel structure penetrates the second stack at a second angle greater than the first angle relative to the reference axis.

15. The semiconductor device according to claim 12, wherein, The first stacked body belongs to the first storage block. The second stacked body belongs to the second storage block, and The second storage block has a larger block pitch than the first storage block.

16. A semiconductor device, the semiconductor device comprising: Memory plane; as well as Multiple memory blocks are included in the memory plane and have different block pitches. The block pitch of the storage block is inversely proportional to the distance of the storage block from the edge of the memory plane.

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