Unipolar modulation dual-mechanism organic memristive transistor and preparation method thereof

Abstract

The application belongs to the field of semiconductor technology and neuromorphic hardware, and discloses a unipolar regulated double-mechanism organic memristor transistor and a preparation method thereof. The double-mechanism organic memristor transistor is sequentially provided with a substrate layer containing a gate, an electrolyte layer, a charge capture layer, a semiconductor layer, a source and a drain from bottom to top, and has unipolar voltage amplitude-dependent plasticity. The conductance is adjusted to be enhanced or weakened by adjusting the size of the drain voltage, and the double-mechanism organic memristor transistor realizes the SVDP characteristic. The application realizes the SVDP characteristic in the memristor transistor, introduces a double-charge mechanism, utilizes the competition between the two mechanisms, realizes excitation under a small amplitude stimulus voltage and inhibition under a large amplitude stimulus voltage, realizes the SVDP characteristic in the drain of the memristor transistor, adjusts the SVDP characteristic by changing the voltage of the gate, and can simulate more abundant synaptic behaviors.

Description

Technical Field

[0001] This invention belongs to the fields of semiconductor technology and neuromorphic hardware, specifically relating to a unipolar-controlled dual-mechanism organic memristor transistor and its fabrication method. Background Technology

[0002] With the advancement of artificial intelligence at the hardware level, neuromorphic electronics has received increasing attention. Currently, the basic logical architecture of computer hardware systems is the von Neumann architecture, characterized by "program storage, shared data, and sequential execution." This architecture requires the CPU to fetch instructions and data from memory for corresponding calculations, leading to the "memory wall" effect between different types of memory, which limits the computer's operating speed. Therefore, significant breakthroughs in computer architecture and storage technology are urgently needed.

[0003] The human brain consists of approximately 10 11 10 neurons and 10 15 Composed of synapses, neuromorphic computing architectures are structurally massively parallel and functionally in-memory computing, consuming far less power than traditional computers. Brain-inspired neuromorphic computing architectures can surpass the classic von Neumann architecture in some aspects, playing a crucial role in advancing artificial intelligence capable of handling complex tasks. Synaptic devices are the cornerstone of neuromorphic computing. Currently, artificial synaptic devices mainly include memristors, synaptic transistors, and memristor transistors. Most current synaptic devices use bipolar voltage to adjust synaptic weights. In the circuit, the negative voltage is converted from the positive voltage through external circuitry. Therefore, large-scale integration requires complex external circuitry, increasing integration complexity and presenting certain limitations. Another method of synaptic weight adjustment uses two synaptic devices with opposite charge effects, which can function as inhibitory and excitatory synapses respectively under the same input signal. However, achieving the same synaptic function requires an even larger number of devices, leading to larger physical volume and higher power consumption during large-scale integration. These shortcomings hinder the development of neuromorphic computing. In this context, developing synaptic devices with unipolar voltage amplitude-dependent plasticity (SVDP) is a key step in advancing neuromorphic computing systems.

[0004] In summary, when using bipolar voltage to adjust synaptic weights in neuromorphic computing, complex peripheral circuitry is required, which increases the complexity of system integration. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a unipolar-controlled dual-mechanism organic memristor transistor and its fabrication method. The SVDP characteristic is achieved in the memristor transistor by introducing a dual charge mechanism and utilizing the competitive interaction between the two mechanisms. A small-amplitude stimulation voltage induces excitation, while a large-amplitude stimulation voltage induces inhibition. The SVDP characteristic is achieved at the drain of the memristor transistor. By changing the gate voltage, the SVDP characteristic can be adjusted, thus simulating richer synaptic behaviors.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solution:

[0007] This invention is a unipolar-controlled dual-mechanism organic memristor transistor. The dual-mechanism organic memristor transistor has, from bottom to top, a substrate layer including a gate, an electrolyte layer, a charge trapping layer, a semiconductor layer, a source, and a drain. The dual-mechanism organic memristor transistor has unipolar voltage amplitude-dependent plasticity (SVDP). The conductance is enhanced or weakened by adjusting the drain voltage, thus realizing the SVDP characteristic in the dual-mechanism organic memristor transistor.

[0008] A further improvement of the present invention is that the SVDP characteristics are dynamically adjusted by adjusting the voltage of the substrate layer.

[0009] A further improvement of the present invention is that the source and the drain are both made of gold or copper.

[0010] A further improvement of the present invention is that the substrate layer is a combination of silicon and silicon dioxide from bottom to top, or a combination of PET, ITO and Al2O3.

[0011] A further improvement of the present invention is that the charge trapping layer is one of PVN, PS, and Pyridrl-C, and the thickness of the charge trapping layer is 5 to 30 nm.

[0012] A further improvement of the present invention is that the semiconductor layer is made of pentacene.

[0013] A further improvement of the present invention is that the electrolyte layer material includes one of polymer electrolyte, ionic liquid, ionic gel or electrolyte solution.

[0014] A further improvement of the present invention is that the fabrication method of the dual-mechanism organic memristor transistor includes the following steps:

[0015] Step 1: Clean the substrate layer with acetone, ethanol and deionized water respectively for 5 to 20 minutes. After cleaning, dry it.

[0016] Step 2: Prepare the charge trapping layer solution by fully dissolving the charge trapping medium in an organic solvent such as 1,2-dichloroethane, toluene, or chlorobenzene.

[0017] Step 3: Prepare the electrolyte layer solution;

[0018] Step 4: Treat the substrate with ultraviolet ozone;

[0019] Step 5: Based on step 4, an electrolyte film is prepared by solution spin coating to generate the double layer effect;

[0020] Step 6: Based on step 5, a charge trapping layer film is prepared by solution spin coating to generate a charge trapping effect;

[0021] Step 7: Based on step 6, prepare the semiconductor layer and the metal top electrode.

[0022] A further improvement of the present invention is that, in step 7, the semiconductor material is pentacene, and the specific preparation method is thermal evaporation. During vacuum thermal evaporation of the semiconductor layer, the vacuum level is controlled at 5 × 10⁻⁶. -4 pa, evaporation rate controlled at

[0023] A further improvement of the present invention is that: the material of the metal top electrode in step 7 is either Cu or Au, and the metal top electrode is prepared by thermal evaporation. During vacuum thermal evaporation of the metal electrode, the vacuum degree is controlled at 5 × 10⁻⁶. -4 pa, evaporation rate controlled at

[0024] The beneficial effects of this invention are:

[0025] This invention proposes a unipolar-controlled dual-mechanism organic memristor transistor that achieves SVDP characteristics in a memristor transistor. When a small forward voltage is applied to the drain, the double-layer mechanism plays a dominant role, enhancing the channel conductance. When a large forward voltage is applied to the drain, charge trapping plays a dominant role, weakening the channel conductance. By applying voltages of different amplitudes to the drain, the channel conductance can be adjusted by the magnitude of the voltage. This device has unipolar voltage-regulated conductance characteristics.

[0026] This invention uses PS as the charge trapping layer and chitosan as the electrolyte layer to explore the combined mechanism of charge trapping and electric double layer effect. It utilizes the opposite control methods of electric double layer effect and charge trapping effect on the transport layer to explore the influence of the two charge effects on weight update and realize the modulation of channel conductance under unipolar electric pulse.

[0027] Meanwhile, the memristor transistor of the present invention has a unique gate electrode with a control terminal, realizing SVDP at the drain. The memory transistor has a gate control terminal, which lays the foundation for dynamically adjusting the SVDP characteristics. Dynamically adjusting the SVDP characteristics can realize more and more beneficial functions.

[0028] In memristor transistors, conductance can be adjusted using unipolar voltage, which is beneficial for the development of neuromorphic computing. Attached Figure Description

[0029] Figure 1 This is a structural diagram of the organic memristor transistor device of the present invention.

[0030] Figure 2 This is the hysteresis curve of the organic memristor transistor of the present invention when a unidirectional scanning voltage is applied.

[0031] Figure 3 This is the hysteresis curve of the organic memristor transistor of the present invention when a bidirectional scanning voltage is applied.

[0032] Figure 4 This is the PSC curve of the organic memristor transistor of the present invention when a unipolar voltage is applied. Detailed Implementation

[0033] The embodiments of the present invention will be disclosed below with reference to the drawings. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not essential.

[0034] This invention provides a method for fabricating a unipolar-controlled dual-mechanism organic memristor transistor, the method comprising the following steps:

[0035] I. Substrate Preprocessing

[0036] Substrate layer 1 was cleaned with acetone, ethanol and deionized water for 5 to 20 minutes respectively. After cleaning, the substrate was dried with a nitrogen gun and placed in a drying oven for drying. Then the substrate was treated with ultraviolet ozone.

[0037] II. Preparation of Electrolyte Thin Films by Solution Spin Coating

[0038] An electrolyte solution was prepared using chitosan as the solute, followed by the addition of deionized water. After shaking until the chitosan was evenly distributed, acetic acid was added. The mass ratio of chitosan to acetic acid was 2:1. An electrolyte layer was prepared using a spin-coating method. The thickness of the film obtained by the spin-coating method was approximately 180 nm.

[0039] III. Preparation of Charge-Trapping Thin Films by Solution Spin Coating

[0040] Prepare a charge-capturing layer solution with a concentration of 5 mg / ml; fully dissolve the charge-capturing medium in an organic solvent such as 1,2-dichloroethane, toluene, or chlorobenzene; prepare an electrolyte layer using a spin-coating method; and obtain a film thickness of approximately 10 nm using the spin-coating method.

[0041] IV. Preparation of Semiconductor Conductive Channels by Thermal Evaporation

[0042] The charge trapping layer film is placed in a thermal evaporation coating device, and a P-type semiconductor layer material and pentene are added; a P-type semiconductor layer film with a thickness of about 50 nm is obtained, thus obtaining a semiconductor conductive channel.

[0043] V. Preparation of source and drain electrodes by thermal evaporation method

[0044] A P-type semiconductor thin film is placed in a thermal evaporation deposition apparatus. Using a mask with a channel width W = 1500 μm and a length L = 150 μm, Cu is added to a metal source to obtain a copper electrode with a thickness of approximately 80 nm. This yields the organic memristor transistor of this invention, which exhibits unipolar voltage-regulated conductance characteristics based on a dual-mechanism effect. This organic memristor transistor possesses unipolar voltage amplitude-dependent plasticity (SVDP). By changing the amplitude of the pulse applied to the drain, the channel conductance can be switched between enhanced and weakened. Compared to memristors and synaptic transistors, memristor transistors possess unique inherent advantages. Achieving SVDP characteristics in memristor transistors has a beneficial effect on the development of neuromorphic hardware. The SVDP characteristics in memristor transistors originate from two competing charge effects in the device: the electrical double-layer effect and the charge trapping effect. The electrical double-layer effect and the charge trapping effect dominate under small and large positive voltages applied to the drain, respectively. When the electrical double-layer effect dominates, the channel conductance increases; when the charge trapping effect dominates, the channel conductance decreases. The channel conductance can be modulated by applying a unipolar pulse to the drain to achieve SVDP characteristics. The gate, as the control terminal, can adjust the SVDP characteristics, opening up new prospects for manufacturing neuromorphic computing with higher reliability and efficiency.

[0045] like Figure 1 As shown, the dual-mechanism organic memristor transistor of the present invention is provided from bottom to top with a substrate layer 1 including a gate, an electrolyte layer 2, a charge trapping layer 3, a semiconductor layer 4, a source 6, and a drain 5. The dual-mechanism organic memristor transistor has unipolar voltage amplitude-dependent plasticity (SVDP). The conductance is enhanced or weakened by adjusting the voltage of the drain 5, thereby realizing the SVDP characteristic in the dual-mechanism organic memristor transistor.

[0046] Figure 2 The unidirectional IV hysteresis curve of the organic memristor transistor of this invention is shown in the scan range of 0V to 8V, with 15 scans. The peak current continuously increases and the channel conductance continuously increases. The scan range of 0V to 30V is shown in the scan range of 15 scans. The peak current continuously decreases and the channel conductance continuously decreases.

[0047] Figure 3The diagram shows the bidirectional IV hysteresis curve of an organic memristor transistor based on a dual-mechanism effect. When a positive voltage is applied to the drain, the hysteresis curve corresponding to the positive voltage rotates counterclockwise under a small range of scanning voltages, indicating an increase in channel conductance. Under a large range of scanning voltages, the hysteresis curve corresponding to the positive voltage rotates clockwise, indicating a decrease in channel conductance.

[0048] Figure 4 The diagram shows a unipolar pulse modulation. When two consecutive 8V positive pulses are applied to the drain electrode of the device, the peak current generated by the second pulse is higher than that generated by the first pulse, resulting in a paired pulse excitation phenomenon. When two consecutive 30V positive pulses are applied to the drain electrode of the device, the peak current generated by the second pulse is lower than that generated by the first pulse, resulting in a paired pulse inhibition phenomenon.

[0049] It can be seen that the device utilizes the dual mechanisms of charge trapping effect and electric double layer effect. In the drain forward voltage region and IV hysteresis curve, the small voltage rotates counterclockwise and the large voltage rotates clockwise. Similarly, in the synapse test, the small voltage stimulates the conductance to increase and the large voltage stimulates the conductance to decrease. The SVDP phenomenon appears in both IV test and synapse test.

[0050] This invention realizes SVDP characteristics in synaptic devices. Their advantage is that synaptic weight adjustment can be achieved on a single device using a voltage pulse of a single polarity, which can effectively simplify the peripheral circuit without increasing the size of the device integrated system.

[0051] By implementing SVDP characteristics at the drain of a memristor transistor, the switching between synaptic weight enhancement and suppression can be achieved by using different voltage amplitudes at the drain. The gate serves as an independent control terminal, laying the foundation for further simulation of more complex synaptic behaviors.

[0052] The above description is merely an embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of the claims of the present invention.

Claims

1. A unipolar-controlled dual-mechanism organic memristor transistor, wherein the dual-mechanism organic memristor transistor is provided from bottom to top with a substrate layer (1) including a gate, an electrolyte layer (2), a charge trapping layer (3), a semiconductor layer (4), a source (6), and a drain (5), characterized in that: The dual-mechanism organic memristor transistor has unipolar voltage amplitude-dependent plasticity (SVDP). The conductance is enhanced or weakened by adjusting the voltage of the drain (5). The SVDP characteristic is realized in the dual-mechanism organic memristor transistor. The SVDP characteristic is dynamically adjusted by adjusting the voltage of the substrate layer (1). The material of the semiconductor layer (4) is pentacene. The charge trapping layer (3) is one of PVN, PS, and Pyridrl-C. The thickness of the charge trapping layer (3) is 5~30 nm.

2. The unipolar-controlled dual-mechanism organic memristor transistor according to claim 1, characterized in that: The source electrode (6) and the drain electrode (5) are both made of gold or copper.

3. The unipolar-controlled dual-mechanism organic memristor transistor according to claim 1, characterized in that: The substrate layer (1) is made of silicon (Si) and silicon dioxide (SiO2) stacked from bottom to top, or of PET, ITO and Al2O3 stacked.

4. The unipolar-controlled dual-mechanism organic memristor transistor according to claim 1, characterized in that: The electrolyte layer (2) material includes one of polymer electrolytes, ionic liquids, ionic gels, or electrolyte solutions.

5. The unipolar-controlled dual-mechanism organic memristor transistor according to claim 1, characterized in that: The fabrication method of this dual-mechanism organic memristor transistor includes the following steps: Step 1: Clean the substrate layer (1) with acetone, ethanol and deionized water respectively for 5 to 20 minutes. After cleaning, dry it. Step 2: Prepare the charge trapping layer solution by fully dissolving the charge trapping medium in an organic solvent such as 1,2-dichloroethane, toluene, or chlorobenzene. Step 3: Prepare the electrolyte layer solution; Step 4: Treat the substrate with ultraviolet ozone; Step 5: Based on step 4, an electrolyte film is prepared by solution spin coating to generate the double layer effect; Step 6: Based on step 5, a charge-trapping layer film is prepared by solution spin coating to generate a charge-trapping effect; Step 7: Based on step 6, prepare the semiconductor layer and the metal top electrode.

6. The unipolar-controlled dual-mechanism organic memristor transistor according to claim 5, characterized in that: In step 7, the semiconductor layer is made of pentacene and is prepared by thermal evaporation. During vacuum thermal evaporation of the semiconductor layer, the vacuum level is controlled at 5 × 10⁻⁶. -4 The evaporation rate was controlled at 0.2 Å / s.

7. The unipolar-controlled dual-mechanism organic memristor transistor according to claim 5, characterized in that: In step 7, the metal top electrode is made of either Cu or Au, and is prepared using a thermal evaporation method. During vacuum thermal evaporation of the metal electrode, the vacuum level is controlled at 5 × 10⁻⁶. -4 The evaporation rate was controlled at 0.5 Å / s.

Images