Method, system, storage medium and electronic device for fabricating a superconducting circuit

Abstract

The application discloses a superconducting circuit preparation method, system, storage medium and electronic device, and belongs to the technical field of superconducting circuits. The superconducting circuit preparation method comprises the following steps: providing a substrate, wherein a superconducting circuit with a short-circuit defect is formed on the substrate; determining a short-circuit position where the short-circuit defect is located, and determining an exposure layout according to the short-circuit position; forming a mask on the substrate, and patterning the mask according to the exposure layout; and etching the mask to disconnect the short-circuit position to obtain a superconducting circuit with the short-circuit defect removed. Compared with the prior art, the technical scheme provided by the application can realize short-circuit defect repair of a transmission line on a quantum chip.

Description

Technical Field

[0001] This application belongs to the field of superconducting circuits, especially the field of superconducting quantum computing technology. In particular, this application relates to a method for fabricating a superconducting circuit, a system, a storage medium, and an electronic device. Background Technology

[0002] The qubit, located on a quantum chip, is the fundamental unit for performing quantum computing. In superconducting quantum computing systems, various superconducting circuits with different functions exist around the qubit, such as drive control signal lines, flux modulation signal lines, and readout signal lines, mainly constructed from coplanar waveguide transmission lines. Quantum chips fabricated using current processes often experience unexpected short circuits in the coplanar waveguide transmission lines, leading to a complete short circuit in the superconducting circuit and rendering the qubits uncontrollable or unreadable. This significantly impacts the functionality of the quantum chip. Summary of the Invention

[0003] The purpose of this application is to provide a method, system, storage medium, and electronic device for fabricating superconducting circuits, which can repair short-circuited superconducting circuits on quantum chips.

[0004] One embodiment of this application provides a method for fabricating a superconducting circuit, which includes:

[0005] A substrate is provided on which a superconducting circuit with short-circuit defects is formed;

[0006] The location of the short circuit defect is determined, a conductive film is formed at the short circuit location to adhere to the superconducting circuit, and the exposure pattern is determined based on the short circuit location.

[0007] A mask is formed on the substrate, and the mask is patterned according to the exposure pattern; and,

[0008] The conductive film is removed by etching using the mask to obtain a superconducting circuit that removes the short-circuit defect.

[0009] In some embodiments of the preparation method described above, the step of determining the short-circuit location of the short-circuit defect includes: testing each of the superconducting circuits to determine the target circuit as being in an electrical short-circuit state; and inspecting the target circuit to determine the short-circuit location of the target circuit.

[0010] In some embodiments of the fabrication method described above, the step of testing each of the circuits includes: providing a test circuit, the test circuit including a probe; constructing a coordinate system to determine the coordinate values ​​of the ports of each of the superconducting circuits; and moving the probe to a target port according to the coordinate values ​​and performing a test, wherein when the probe is located at the target port, the superconducting circuit is connected to the test circuit.

[0011] In some embodiments of the preparation method described above, determining the exposure pattern based on the short-circuit location includes: determining the coordinate values ​​of the short-circuit location in the coordinate system, and determining the exposure pattern based on the coordinate values ​​of the short-circuit location in the coordinate system.

[0012] In some embodiments of the fabrication method described above, the step of determining the short-circuit location of the superconducting circuit includes: providing a standard image, the standard image including a standard circuit; acquiring a photograph of the substrate and performing grayscale processing to obtain a comparison photograph; determining the superconducting circuit corresponding to the standard circuit in the comparison photograph; and scanning the edge region corresponding to the superconducting circuit according to the standard circuit and obtaining grayscale values, identifying the location where the grayscale value is within a preset range as the short-circuit location.

[0013] In some embodiments of the preparation method described above, the standard diagram includes at least one of a photograph of a standard chip and a design diagram of a standard chip.

[0014] In some embodiments of the preparation method described above, the photographs include at least one of light micrographs and electron micrographs.

[0015] Another embodiment of this application provides a fabrication system for a superconducting circuit, comprising:

[0016] A sample supply module is used to provide a substrate on which a superconducting circuit with short-circuit defects is formed;

[0017] A determination module is used to determine the short-circuit location of the short-circuit defect, wherein a conductive film is formed at the short-circuit location to adhere to the superconducting circuit, and to determine the exposure pattern based on the short-circuit location;

[0018] A mask patterning module is used to form a mask on the substrate and pattern the mask according to the exposure pattern; and,

[0019] A short-circuit repair module is used to remove the conductive film by etching with the mask to obtain a superconducting circuit that removes the short-circuit defect.

[0020] Compared with the prior art, the method for fabricating a superconducting circuit provided in this application first provides a substrate, determines the short-circuit position of the superconducting circuit on the substrate, and determines an exposure pattern according to the short-circuit position. Then, a mask is formed on the substrate, and the mask is patterned according to the exposure pattern. Finally, the mask is used to deposit a film at the open circuit position to obtain a superconducting circuit with the short-circuit defect removed, thereby realizing the short-circuit repair of superconducting circuits on quantum chips. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of a superconducting circuit prepared in a related technology;

[0022] Figure 2 This is a schematic diagram of the superconducting circuit in one embodiment of this application;

[0023] Figure 3 A flowchart illustrating a method for fabricating a superconducting circuit in one embodiment provided in this application;

[0024] Figure 4 This is a structural diagram of a superconducting circuit fabrication system provided in one embodiment of this application.

[0025] Explanation of reference numerals in the attached figures:

[0026] 1 - First coplanar waveguide transmission line, 11 - First central transmission conductor, 12 - First grounding layer, 111 - First standard area conductor, 112 - Open circuit area conductor, 101 - First standard interval, 102 - First open circuit sensitive interval, 103 - Second open circuit sensitive interval.

[0027] 2 - Second coplanar waveguide transmission line, 21 - Second center transmission conductor, 22 - Second grounding layer, 211 - Second standard area conductor, 212 - Short circuit area conductor, 201 - Second standard interval, 202 - First short circuit sensitive interval, 203 - Second short circuit sensitive interval. Detailed Implementation

[0028] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0029] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, one or more embodiments are now described with reference to the accompanying drawings, wherein similar reference numerals are used throughout the text to refer to similar components. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that one or more embodiments may be practiced in various circumstances without these specific details, and the various embodiments may be combined with and referenced to each other without contradiction.

[0030] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0031] Additionally, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be located directly on another layer or substrate, and / or intercalation layers may also be present. Furthermore, it should be understood that when a layer is referred to as being "under" another layer, it can be located directly under that layer, and / or one or more intercalation layers may also be present. Additionally, references to "on" and "under" the layers may be made based on the accompanying drawings.

[0032] Quantum computing is a new discipline that considers computational processes from the perspective of fundamental quantum mechanics principles. The realization of a quantum computer requires qubits (qubits) as basic units that obey the laws of quantum mechanics. A qubit, as a two-level system following the laws of quantum mechanics, can exist in any superposition of 0 and 1 states. Depending on the physical system used to construct the qubit, there are different physical implementation methods. Superconducting quantum chips include qubits and superconducting circuit structures such as microwave resonant cavities. A qubit is a two-level system constructed using a capacitor and a Josephson junction with nonlinear inductive properties.

[0033] Around a qubit, there exist various circuit structures with different functions, such as the drive control signal line (xy-control line, also known as the xy control line or pulse modulation signal line) for XY rotation operations, couplers for inter-qubit coupling, a readout resonant cavity coupled to the qubit, and a readout signal line coupled to the readout cavity. Additionally, the Z-rotation operation of the qubit is performed by a control signal line near the superconducting quantum interference device (squid), called the flux control signal line (z-control line, also known as the z control signal line or frequency modulation signal line). The flux control signal line is arranged near the superconducting quantum interference device (squid) and is excited by current, coupling with the superconducting quantum interference device (squid) through magnetic flux. It should be noted that the readout signal line, flux control signal line, and drive control line are all part of the superconducting circuitry on the quantum chip, and generally employ a coplanar waveguide structure for transmitting microwave signals.

[0034] Figure 1 This is a schematic diagram of the structure of a superconducting circuit prepared in a related technology.

[0035] Combination Figure 1 As shown, the yield rate of quantum chip fabrication is difficult to reach 100%, and the fabrication process often encounters abnormalities in superconducting circuits, such as open circuits (e.g., Figure 1 The first coplanar waveguide transmission line 1) or short circuit (such as Figure 1 The first coplanar waveguide transmission line 1 is often open-circuited due to discontinuities in the thin film morphology of the first central transmission conductor 11 caused by the fabrication process. The second coplanar waveguide transmission line 2 is often short-circuited to ground due to adhesion between the thin film morphology of the second central transmission conductor 21 and ground caused by the fabrication process. These anomalies prevent the superconducting circuit from controlling or reading qubits, significantly impacting the functionality of the quantum chip. Therefore, this application provides a superconducting circuit and a superconducting quantum chip. This structure helps reduce the occurrence of superconducting circuit anomalies during fabrication and facilitates the fabrication of the superconducting circuit.

[0036] Figure 2 This is a schematic diagram of the structure of a superconducting circuit in one embodiment of the present application, and schematically shows that the coplanar waveguide transmission line includes a central transmission conductor and ground layers located on both sides of the central transmission conductor.

[0037] Based on the need for a focused description of the embodiments, Figure 1 and Figure 2 The middle part is omitted and not shown.

[0038] Combination Figure 2As shown, an embodiment of this application provides a superconducting circuit, which includes: a coplanar waveguide transmission line with a standard interval, such as a first coplanar waveguide transmission line 1 and a second coplanar waveguide transmission line 2. The coplanar waveguide transmission line includes a central transmission conductor and grounding layers located on both sides of the central transmission conductor. The coplanar waveguide transmission line also has the following characteristics:

[0039] It has at least one open-circuit sensitive interval; or, it has at least one short-circuit sensitive interval; or, it has at least one open-circuit sensitive interval and at least one short-circuit sensitive interval.

[0040] The shape and structure of the coplanar waveguide transmission line having at least one open-circuit sensitive section are described below by way of example.

[0041] See Figure 2 The first coplanar waveguide transmission line 1 includes a first central transmission conductor 11 and a first ground layer 12. A first standard section 101, a first open-circuit sensitive section 102, and a second open-circuit sensitive section 103 are distributed along the signal transmission direction of the first coplanar waveguide transmission line 1. The line width of the first standard section conductor 111 in the first standard section 101 is denoted as W10. The line width of the open-circuit section conductor 112 in the first open-circuit sensitive section 102 is denoted as W11. The line width of the central transmission conductor in the second open-circuit sensitive section 103 is denoted as W12. Both W11 and W12 are greater than W10.

[0042] In some embodiments of this application, the linewidth of the central transmission conductor within the circuit-sensitive region is greater than that within the standard region. By designing the linewidth of the central transmission conductor in the circuit-sensitive region to be greater than that in the standard region, this application helps to avoid breakage and discontinuity in the thin film used to form the transmission conductor during the fabrication process, thereby reducing the occurrence of unexpected circuit breaks.

[0043] In some embodiments of this application, the central transmission conductor includes a first portion located within the standard interval and a second portion located within the open-circuit sensitive interval. The first portion is located on the same film layer, and the second portion is located on another film layer. This structural form facilitates separate optimization of the linewidth design of the second portion and utilizes two coatings to form the first and second portions of the central transmission conductor, thereby avoiding the situation in the prior art where an open circuit easily occurs in a specific region (i.e., the open-circuit sensitive interval mentioned above) when the central transmission conductor is formed by a single coating. Specifically, the first portion of this coplanar waveguide transmission line can be referred to... Figure 2 The first standard area conductor 111 in the middle, the second part can be referred to Figure 2 Conductor 112 in the broken-circuit zone.

[0044] In some embodiments, the linewidth of the first standard area conductor 111 is the same. In other embodiments, the circuit breaker conductor 112 is a circular or rectangular film covering the first portion, and the circular or rectangular film contacts the first standard area conductor 111 to achieve electrical connection. In still other embodiments, when the coating process forms the central transmission conductor, the portion in the circuit breaker sensitive area is prone to discontinuity (this discontinuity may be caused by uneven coating or tearing during peeling, etc.), leading to a circuit breaker in the central transmission conductor. To increase the coating space in this area and facilitate increasing the linewidth of the circuit breaker conductor 112 in this space, in specific implementations, the first ground layer 12 in the first circuit breaker sensitive area 102 can be recessed away from the central transmission conductor. In one embodiment, the distance between the circuit breaker conductor 112 and the first ground layer 12 is the same as the distance between the first standard area conductor 111 and the first ground layer 12 in the standard area. In specific implementations, the central transmission conductor in the circuit breaker sensitive area protrudes towards the ground layer, and this protrusion and the recess of the ground layer are in the same direction and with the same amplitude.

[0045] The shape and structure of the coplanar waveguide transmission line having at least one short-circuit sensitive section are described below by way of example.

[0046] See Figure 2 The first coplanar waveguide transmission line 2 and the second coplanar waveguide transmission line 2 include a first center transmission conductor 11 and a first ground layer 12. A second standard interval 201, a first short-circuit sensitive interval 202, and a second short-circuit sensitive interval 203 are distributed along the signal transmission direction of the second coplanar waveguide transmission line 2. The distance between the second standard interval conductor 211 in the second standard interval 201 and the ground layer is denoted as S20. The distance between the short-circuit section conductor 212 in the first short-circuit sensitive interval 202 and the second ground layer 22 is denoted as S21. The distance between the center transmission conductor in the second short-circuit sensitive interval 203 and the first ground layer 12 is denoted as S22. In this embodiment, the second coplanar waveguide transmission line 2 also has the structural feature that S21 and S22 are both greater than S20.

[0047] In specific implementations, the form is not limited to the above. As long as the second coplanar waveguide transmission line 2 is a coplanar waveguide transmission line with a standard section and at least one short-circuit sensitive section, and the distance between the center transmission conductor and the ground layer in the short-circuit sensitive section is greater than the distance between the center transmission conductor and the ground layer in the standard section, it is acceptable. This application, by designing the linewidth of the center transmission conductor in the short-circuit sensitive section to be smaller than the linewidth of the center transmission conductor in the standard section, helps to avoid adhesion between the center transmission conductor and the ground layer formed during the coating process, thereby reducing the occurrence of accidental short circuits.

[0048] This structural form, where the spacing is greater than the spacing between the center transmission conductor and the grounding layer within the standard interval, can be achieved in the following way.

[0049] In some embodiments of this application, the grounding layer within the short-circuit sensitive region is recessed towards the side away from the central transmission conductor. For example, in conjunction with the foregoing, if the second grounding layer 22 within the first short-circuit sensitive region 202 adopts the aforementioned recessed structure, the linewidth of the short-circuit region conductor 212 can be consistent with that of the second standard region conductor 211. This allows for a relatively increased distance between the central transmission conductor and the grounding layer within the short-circuit sensitive region while maintaining a consistent linewidth for the central transmission conductor. In another example, in conjunction with… Figure 2 As shown, the second grounding layer 22 within the first short-circuit sensitive zone 202 adopts the aforementioned recessed structure, and the line width of the short-circuit zone conductor 212 can also adopt a structure that is smaller than the line width of the second standard zone conductor 211.

[0050] In some implementation examples, to maintain a consistent grounding layer topography, the structure of the center transmission conductor can be modified. For instance, the linewidth of the center transmission conductor located in the short-circuit sensitive section can be smaller than that of the center transmission conductor in the standard section. Specifically, in conjunction with... Figure 2 As shown, the short-circuit region conductor 212 has a linewidth smaller than that of the second standard region conductor 211. In some other embodiments, the center transmission conductor in the short-circuit sensitive area and the center transmission conductor in the standard area are located on the same layer; specifically, in conjunction with... Figure 2 As shown, the short-circuit region conductor 212 and the second standard region conductor 211 can be an integral structure, which facilitates the formation of a single coating.

[0051] In addition, the standard interval is the section of the coplanar waveguide transmission line where no abnormality occurs, the open circuit sensitive interval is the section of the coplanar waveguide transmission line where an open circuit occurs, and the short circuit sensitive interval is the section of the coplanar waveguide transmission line where a short circuit occurs. The center transmission conductor in the standard interval is referred to as the standard area conductor, the center transmission conductor in the open circuit sensitive interval is referred to as the open circuit conductor, and the center transmission conductor in the short circuit sensitive interval is referred to as the short circuit conductor.

[0052] Another embodiment of this application provides a superconducting quantum computing chip, which includes the superconducting circuit described above.

[0053] Superconducting circuits can be formed from superconducting materials that exhibit superconducting properties at temperatures equal to or below the critical temperature, such as approximately 10-100 milliklvin (mK) or approximately 4K, such as aluminum, niobium, tantalum, or titanium nitride, etc. In practice, they are not limited to these types. Any material that exhibits superconducting properties at temperatures equal to or below the critical temperature can be used to form the superconducting transmission line.

[0054] In the fabrication technology of quantum chips, short circuits often occur in the superconducting circuits on the quantum chips (such as...). Figure 1 In the case of the second coplanar waveguide transmission line 2), embodiments of this application also provide a method for fabricating a superconducting circuit.

[0055] Figure 3 A flowchart of a method for fabricating a superconducting circuit in one embodiment provided in this application.

[0056] See Figure 3 and combined Figures 1 to 2 As shown, an embodiment of this application provides a method for fabricating a superconducting circuit, comprising the following steps S301 to S304:

[0057] Step S301: Provide a substrate on which a superconducting circuit coupled to a quantum bit is formed. This superconducting circuit has a short-circuit defect, such as... Figure 1 The second coplanar waveguide transmission line 2 in the middle, wherein the structure of the qubit is not shown;

[0058] Step S302: Determine the location of the short circuit defect, where a conductive film adhering to the superconducting circuit is formed at the short circuit location. See [link to relevant documentation]. Figure 1 The portion where the second center transmission conductor 21 is adhered to the second ground layer 22 is shown, and the exposure pattern is determined according to the short-circuit location;

[0059] Step S303: Form a mask on the substrate and pattern the mask according to the exposure pattern; and,

[0060] Step S304: Use the mask to etch and remove the conductive film to obtain a superconducting circuit that has removed the short-circuit defect and has normal electrical conductivity, for example, Figure 2 The second central transmission conductor 21, the short-circuit zone conductor 212, the thin film located on the second short-circuit sensitive zone 203, and the second grounding layer 22 no longer adhere to each other.

[0061] In this embodiment, the superconducting circuit can be formed from a superconducting material that exhibits superconducting properties at temperatures equal to or below the critical temperature, such as approximately 10–100 millikrvin (mK) or approximately 4K, such as aluminum, niobium, tantalum, or titanium nitride, etc. In practice, the material is not limited to these; any material exhibiting superconducting properties at temperatures equal to or below the critical temperature can be used to form the superconducting circuit. These materials can be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), epitaxial techniques, and other deposition processes. Exemplary examples include ion beam assisted deposition (IBAD), vacuum evaporation, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), chemical vapor deposition (CVD), sol-gel deposition, and magnetron sputtering.

[0062] The superconducting circuits described in this application may require the removal of one or more materials from the device during the manufacturing process. Depending on the material to be removed, the removal process may include, for example, wet etching, dry etching, or lift-off processes. The materials forming the circuit elements described herein can be patterned using known lithographic techniques (e.g., photolithography or electron beam lithography).

[0063] In some embodiments provided in this application, the step of determining the short-circuit location of the short-circuit defect includes: testing the signal conduction state of each of the superconducting circuits, and determining the circuit in an electrical short-circuit state as the target circuit. The target circuit can be a sub-circuit of the superconducting circuit, for example, a coplanar waveguide transmission line among many coplanar waveguide transmission lines constituting the superconducting circuit. In specific implementations, it is combined with... Figure 1 As shown, a coplanar waveguide transmission line that is electrically short-circuited is identified as the target circuit based on the signal conduction state between the central transmission conductor and the ground layer; and the target circuit is inspected to determine the short-circuit location of the short-circuit defect in the target circuit.

[0064] In one embodiment, the step of testing each of the circuits includes: providing a test circuit, which may include two probes and a test signal source, both probes being connected to the test signal source; constructing a coordinate system to determine the coordinate values ​​of a port of each superconducting circuit, the port being used for electrical contact with the probe, specifically the end of the central transmission conductor or a specific location on the ground layer; and moving the probe to a target port according to the coordinate values ​​and performing a test, wherein when the probe is located at the target port, the superconducting circuit is connected to the test circuit for an electrical short-circuit test. In one embodiment, there are at least two ports located on two different membrane structures to determine whether they are short-circuited, combined with... Figure 1 As shown, during testing of the second coplanar waveguide transmission line 2, one probe is electrically connected to the second ground layer 22, and the other probe is electrically connected to one end of the second central transmission conductor 21. In another embodiment, the port includes both ends of the second central transmission conductor 21. After being connected to the test circuit, the measured current and resistance are used to determine whether the target circuit is in an electrical short circuit.

[0065] In another embodiment, to facilitate the design and determination of the exposure layout, the step of determining the exposure layout based on the short circuit location includes: determining the coordinate value of the short circuit location in the coordinate system, so that the exposure layout can be designed based on the coordinate value, which helps to accurately locate the short circuit location when determining the exposure layout.

[0066] In some embodiments provided in this application, the step of determining the short-circuit location of the superconducting circuit includes: providing a standard diagram of the quantum chip, the standard diagram including a standard circuit; acquiring a photograph of the substrate and performing grayscale processing to obtain a comparison photograph, wherein the grayscale-processed comparison photograph can be scanned to obtain the grayscale value of the scanned location of the superconducting circuit, and it is understood that the grayscale value of the location with a thin film on the substrate fluctuates in a first range, and the grayscale value of the location without a thin film fluctuates in a second range, the two ranges are clearly distinguishable and can be predetermined; determining the superconducting circuit corresponding to the standard circuit in the comparison photograph; and scanning the gap region corresponding to the superconducting circuit according to the standard circuit and obtaining the grayscale value, identifying the location of the grayscale value in the first range as the short-circuit location, the first range being a preset range, the gap region being located on the periphery of the path and not intended to form a thin film in the design, combined with Figure 1 and Figure 2 As shown, the gap region is the area where the gap between the second central transmission conductor 21 and the second ground layer 22 is located.

[0067] In one embodiment, the standard image includes at least one of a photograph of a standard quantum chip and a design drawing of a standard quantum chip. In another embodiment, the photograph includes at least one of an optical microscope photograph and an electron microscope photograph.

[0068] Figure 4 This is a schematic diagram of a superconducting circuit fabrication system provided in an embodiment of this application.

[0069] See Figure 4 The second aspect of this application provides a superconducting circuit fabrication system corresponding to the above-described superconducting circuit fabrication method, the system comprising the following modules:

[0070] The sample supply module 401 is used to provide a substrate on which a superconducting circuit coupled to a quantum bit is formed, and the superconducting circuit has a short-circuit defect;

[0071] The determination module 402 is used to determine the short circuit location of the short circuit defect, wherein a conductive film is formed at the short circuit location to adhere to the superconducting circuit, and to determine the exposure pattern based on the short circuit location.

[0072] Mask patterning module 403 is used to form a mask on the substrate and pattern the mask according to the exposure pattern; and,

[0073] The short-circuit repair module 404 is used to remove the conductive film by etching the mask to obtain a superconducting circuit that removes the short-circuit defect.

[0074] Corresponding to the method for fabricating a superconducting circuit provided in this application embodiment, in related fabrication technologies for quantum chips, short circuits often occur in the superconducting circuits on the quantum chip. This application embodiment provides a fabrication system for a superconducting circuit. The fabrication system provided in this application embodiment provides a substrate with a superconducting circuit formed on it through a sample supply module 401. Then, a determination module 402 determines the short-circuit location of the superconducting circuit and determines the exposure pattern based on the short-circuit location. Next, a mask is formed on the substrate using a mask patterning module 403, and the mask is patterned according to the exposure pattern. Finally, a short-circuit repair module 404 uses the mask to etch and remove the conductive film to obtain a connected superconducting circuit. This enables the short-circuit repair of the superconducting circuit on the quantum chip, specifically the short-circuit repair of a coplanar waveguide transmission line.

[0075] Based on the method for fabricating a superconducting circuit according to the above embodiments, this application also proposes a non-temporary computer storage medium storing a computer program thereon, wherein the computer base program, when executed, can realize the method for fabricating a superconducting circuit according to the above embodiments.

[0076] Specifically, in this embodiment, the storage medium can be configured to store a computer program for performing steps S301 to S304:

[0077] Step S301: Provide a substrate on which a superconducting circuit coupled to a quantum bit is formed, the superconducting circuit having a short-circuit defect;

[0078] Step S302: Determine the short circuit location of the short circuit defect, wherein a conductive film is formed at the short circuit location to adhere to the superconducting circuit, and determine the exposure pattern based on the short circuit location;

[0079] Step S303: Form a mask on the substrate and pattern the mask according to the exposure pattern; and,

[0080] Step S304: Use the mask to etch and remove the conductive film to obtain a superconducting circuit with the short-circuit defect removed.

[0081] Embodiments of this application also provide a storage medium storing a computer program, wherein the computer program is configured to execute the method described at runtime.

[0082] Specifically, in this embodiment, the storage medium may include, but is not limited to, USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks, and other media capable of storing computer programs.

[0083] As described above, based on the superconducting circuit fabrication method of the above embodiments, this application proposes an electronic device including a memory and a processor. The memory stores a computer program, and the processor is configured to run the computer program to implement the superconducting circuit fabrication method of the above embodiments when executed.

[0084] Specifically, the aforementioned electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the aforementioned processor, and the input / output device is connected to the aforementioned processor.

[0085] Specifically, in this embodiment, the processor can be configured to execute the following steps S301 to S304 via a computer program:

[0086] Step S301: Provide a substrate on which a superconducting circuit coupled to a quantum bit is formed, the superconducting circuit having a short-circuit defect;

[0087] Step S302: Determine the short circuit location of the short circuit defect, wherein a conductive film is formed at the short circuit location to adhere to the superconducting circuit, and determine the exposure pattern based on the short circuit location;

[0088] Step S303: Form a mask on the substrate and pattern the mask according to the exposure pattern; and,

[0089] Step S304: Use the mask to etch and remove the conductive film to obtain a superconducting circuit with the short-circuit defect removed.

[0090] It should be noted that the embodiments of the above systems, storage media, and electronic devices have the same beneficial effects as the embodiments of the superconducting circuit described above, and therefore will not be repeated. For technical details not disclosed in the embodiments of the systems, storage media, and electronic devices of this application, those skilled in the art should refer to the description of the preparation method above for understanding; for the sake of brevity, they will not be repeated here.

[0091] It should be noted that the technical solutions of this application embodiment can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this application embodiment. The aforementioned storage medium can be a non-transitory storage medium, including: USB flash drive, portable hard drive, read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk, and other media capable of storing program code; it can also be a transient storage medium.

[0092] In the description of this specification, the references to terms such as "an embodiment," "some embodiments," "embodiments of this application," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0093] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

[0094] The above description, based on the embodiments shown in the drawings, details the structure, features, and effects of this application. The above description is only a preferred embodiment of this application, but this application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of this application, or modifications to equivalent embodiments, that do not exceed the spirit covered by the specification and drawings, should be within the protection scope of this application.

Claims

1. A method for fabricating a superconducting circuit, characterized in that, include: A substrate is provided on which a superconducting circuit with short-circuit defects is formed; The location of the short circuit defect is determined, a conductive film is formed at the short circuit location to adhere to the superconducting circuit, and the exposure pattern is determined based on the short circuit location. A mask is formed on the substrate, and the mask is patterned according to the exposure pattern; as well as, The conductive film is removed by etching using the mask to obtain a superconducting circuit that removes the short-circuit defect; The superconducting circuit for removing the short-circuit defect includes: a coplanar waveguide transmission line having a standard section and at least one short-circuit sensitive section, wherein the standard section is a section of the coplanar waveguide transmission line in which no abnormality occurs, and the short-circuit sensitive section is a section of the coplanar waveguide transmission line in which a short circuit occurs. The coplanar waveguide transmission line includes a central transmission conductor and grounding layers located on both sides of the central transmission conductor, and the distance between the central transmission conductor and the grounding layer in the short-circuit sensitive section is greater than the distance between the central transmission conductor and the grounding layer in the standard section.

2. The preparation method according to claim 1, characterized in that, The step of determining the location of the short circuit defect includes: Test each of the superconducting circuits to determine the target circuit as one that is in an electrical short-circuit state; and, Inspect the target circuit to determine the location of the short circuit.

3. The preparation method according to claim 2, characterized in that, The steps for testing each of the circuits include: A test circuit is provided, the test circuit including probes; Construct a coordinate system to determine the coordinate values ​​of the ports of each of the superconducting circuits; and, The probe is moved to the target port according to the coordinate value and tested. When the probe is located at the target port, the superconducting circuit is connected to the test circuit.

4. The preparation method according to claim 3, characterized in that, Determining the exposure layout based on the short-circuit location includes: determining the coordinates of the short-circuit location in the coordinate system, and determining the exposure layout based on the coordinates of the short-circuit location in the coordinate system.

5. The preparation method according to claim 1, characterized in that, The step of determining the short-circuit location of the superconducting circuit includes: A standard diagram is provided, which includes a standard circuit. A photograph of the substrate is acquired and subjected to grayscale processing to obtain a comparison photograph; In the comparison photographs, the superconducting circuit corresponding to the standard circuit is identified; and, The edge region corresponding to the superconducting circuit is scanned according to the standard circuit and grayscale values ​​are obtained. Positions with grayscale values ​​within a preset range are identified as short circuit positions.

6. The preparation method according to claim 5, characterized in that, The standard diagram includes at least one of a photograph of a standard chip and a design diagram of a standard chip.

7. The preparation method according to claim 5, wherein the photograph includes at least one of an optical micrograph and an electron micrograph.

8. A fabrication system for a superconducting circuit, characterized in that, include: A sample supply module is used to provide a substrate on which a superconducting circuit with short-circuit defects is formed; A determination module is used to determine the short-circuit location of the short-circuit defect, wherein a conductive film is formed at the short-circuit location to adhere to the superconducting circuit, and to determine the exposure pattern based on the short-circuit location; A mask patterning module is used to form a mask on the substrate and pattern the mask according to the exposure pattern; as well as, A short-circuit repair module is used to remove the conductive film by etching the mask to obtain a superconducting circuit that removes the short-circuit defect; The superconducting circuit for removing the short-circuit defect includes: a coplanar waveguide transmission line having a standard section and at least one short-circuit sensitive section, wherein the standard section is a section of the coplanar waveguide transmission line in which no abnormality occurs, and the short-circuit sensitive section is a section of the coplanar waveguide transmission line in which a short circuit occurs. The coplanar waveguide transmission line includes a central transmission conductor and grounding layers located on both sides of the central transmission conductor, and the distance between the central transmission conductor and the grounding layer in the short-circuit sensitive section is greater than the distance between the central transmission conductor and the grounding layer in the standard section.

9. A storage medium, characterized in that, The storage medium stores a computer program, wherein the computer program is configured to execute the method described in any one of claims 1 to 7 when it is run.

10. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to perform the method according to any one of claims 1 to 7.

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