Circuitry and method for executing instructions in accordance with trigger conditions

Abstract

The invention relates to a circuit comprising processing circuitry configured to execute program instructions in accordance with respective trigger conditions matching a current trigger state and to set a next trigger state in response to program instruction execution; the processing circuitry comprising instruction storage means configured to selectively provide a set of two or more program instructions for parallel execution; and flip-flop circuitry responsive to a trigger state generated by execution of program instructions and responsive to trigger conditions associated with a given set of program instructions to control the instruction storage means to provide program instructions of the given set of program instructions for execution.

Description

Technical Field

[0001] This disclosure relates to circuits and methods. Background Technology

[0002] The so-called "spatial architecture" can accelerate applications by expanding or unfolding specific computations that can form the time-consuming part of application execution primarily in "space" rather than in time.

[0003] Computation is deployed in "space" by using multiple hardware units capable of operating simultaneously. In addition to leveraging the concurrency opportunities provided by distributed applications already spread across the chip, the spatial architecture utilizes distributed on-chip memory, associating each processing element with one or more adjacent memory blocks. Therefore, the spatial architecture can alleviate the so-called von Neumann bottleneck, which affects many traditional architectures and potentially hinders performance.

[0004] This disclosure relates to potential improvements to such arrangements. Summary of the Invention

[0005] In one exemplary arrangement, a circuit is provided that includes: A processing circuit configured to execute program instructions based on a corresponding trigger condition matching the current trigger state, and to set the next trigger state in response to the execution of the program instructions; the processing circuit includes: An instruction storage device configured to selectively provide a set of two or more program instructions for parallel execution; and A trigger circuit, which controls the instruction storage device to provide program instructions from the given set of program instructions for execution in response to a trigger state generated by executing program instructions and in response to a trigger condition associated with a given set of program instructions.

[0006] In another exemplary arrangement, a processing array is provided, comprising: an array of such circuits; and data communication circuitry for transmitting data between the circuits of the array.

[0007] In another exemplary arrangement, a method is provided that includes: The program instruction is executed according to the corresponding trigger condition that matches the current trigger state, and the next trigger state is set in response to the execution of the program instruction. A set of two or more program instructions is provided by an instruction storage device for parallel execution; and In response to a trigger state generated by executing program instructions and in response to a trigger condition associated with a given set of program instructions, the instruction storage device is controlled to provide program instructions from the given set of program instructions for execution.

[0008] In another exemplary arrangement, a computer-implemented method is provided, the method comprising: The program instructions are generated based on the corresponding trigger conditions for execution, and the execution of the program instructions sets the next trigger condition. Divide program instructions into multiple groups of program instructions, where at least some groups contain more than one program instruction, and the program instructions within a given group do not depend on the result of another program instruction in that given group; and For each group, an input trigger condition and an output trigger state are generated; the input trigger condition is a condition that enables the execution of the program instructions in that group when it is met, and the output trigger condition is a condition generated in response to the completion of the execution of all program instructions in that group.

[0009] In another exemplary arrangement, a compiler is provided that includes computer program code that, when executed by a computer, causes the computer to perform the methods described above. Attached Figure Description

[0010] The present invention will be further described by way of example only, with reference to embodiments shown in the accompanying drawings, wherein: Figure 1 An exemplary processing circuit array is schematically shown; Figure 2 The computational blocks are illustrated schematically; Figure 3 The memory blocks are illustrated schematically; Figure 4 A data flow diagram is shown schematically; Figure 5 An example illustrating memory usage; Figures 6 to 8 The various circuits are schematically shown; Figure 9 An exemplary data processing apparatus is schematically illustrated. Figure 10 This schematically illustrates the compiler's operations. Figure 11 and Figure 12 It is a schematic flowchart illustrating the corresponding method; and Figure 13 The simulated implementation scheme is illustrated schematically. Detailed Implementation

[0011] Exemplary processing array Referring to the attached diagram, in Figure 1 An exemplary instance of a spatial architecture is illustrated in the diagram.

[0012] In this exemplary arrangement, a two-dimensional array 100 of data processing element 110 is connected to a memory arrangement 120, such as a cache memory hierarchy or main memory, via a data transmission unit 130 called an interface block (IT).

[0013] In this example of spatial architecture, there are two types of data processing elements: a so-called computation block (CT) 112 that performs a large number of data processing operations and arithmetic calculations, and a so-called memory block (MT) 114 that is mainly responsible for data access to locally connected memory and data transfer to / from more remote memory regions and other processing elements.

[0014] In an exemplary implementation, a local memory block is provided ( Figure 1 Not shown in the image, but referenced below. Figure 3 (Described as a scratchpad), it is connected to or associated with each memory block (MT), and each MT has a direct connection to a corresponding computation block (CT).

[0015] Each MT-CT cluster represents a data processing element 110, and such elements are connected to an on-chip network 150 via a switch 140 (also referred to as a router in some examples). This on-chip network represents an example of data communication circuitry for transferring data between the data processing elements 110 of array 100 and, in this example, for transferring data between MTs and between each MT and an interface block (IT) 130. However, other configurations are also possible, such as having a single notepad memory shared among several MTs or having MTs with direct access to more than one notepad memory. A one-to-one correspondence between CTs and MTs is not mandatory in this architecture, and it is possible for one MT to be connected to more than one CT, or vice versa. In other words, each processing element is connected to the on-chip network via a set of input and output channels, which includes switches and data links between these switches, thus forming a network such as... Figure 1 The two-dimensional toroidal layout shown.

[0016] First-In-First-Out (FIFO) buffer (in) Figure 1 Not shown in the text, but referenced below. Figure 2 and Figure 3 (As described) is called a "channel," which is used to transmit data to the CT and MT, and to take the processed data away from the CT and MT.

[0017] The architectures of CT and MT are based on the so-called trigger instruction architecture [see reference 1 cited below], which has been extended to support vector processing and more advanced data transfer operations.

[0018] Trigger operation In some examples, each instruction has one or more "trigger conditions" or is associated with them, and each instruction will be issued or sent to the execution unit only if those trigger conditions are valid (that is, the trigger conditions match a trigger state generated by executing another program instruction). In fact, the execution of a program instruction depends not only on the corresponding trigger condition that matches the current trigger state, but it can also set the next trigger state itself.

[0019] The triggering condition is specific to a particular data processing element 110 and may depend on the execution result, channel occupancy, or some other specified state of the processing element. Upon completion, each instruction may set one or more predicate registers that affect the trigger, and these can then be used to determine whether other instructions are ready to execute. Notably, this type or architecture typically does not have an explicit program counter or dedicated branch instructions. Its main advantage is the simplification of the front-end circuitry of the processing element, avoiding pipeline bubbles caused by control flow conflicts without resorting to complex branch prediction mechanisms.

[0020] Trigger Command - Exemplary Format Generally, trigger commands have the following format: <operation><destination_operand>,<source_operand1> ,<source_operand2> ;<predicate_set_operation> when<trigger_condition> The destination and source operands can be vector registers, scalar registers, predicates, or channels. In other words, the instructions executed can be scalar instructions or vector instructions (in which case, the data processing elements or at least some of their circuitry may include vector processing circuitry configured to execute vector processing instructions, each vector processing instruction applying a corresponding processing operation to a corresponding vector of two or more data elements).

[0021] Therefore, for example, the following instructions can be used: add z2, ich2, ich3; set p = 1010: when p == 1001 It performs an addition ("add") on the two source operands located at the headers of input channels "ich2" and "ich3" respectively, and writes the result to the vector register "z2". The instruction is triggered when the predicate state is "1001", and upon completion, it sets the predicates together to "1010", which prepares another instruction whose trigger condition matches this state for execution.

[0022] Predicates can be maintained in, for example, a predicate memory or register 212 at execution circuit 210, and this predicate memory or register can be read by trigger circuit 250, which also receives from queue 240 information defining trigger conditions associated with queued program instructions (these trigger conditions may in turn be generated to populate the queue through compilation operations). Therefore, in the example given above, the detection of the condition "when p == 1001" is performed as follows: • Queue 240 provides trigger condition "p == 1001" (and trigger conditions applicable to other queuing instructions) to trigger circuit 250. • Trigger circuit 250 communicates with predicate memory or register 212; • Trigger circuit 250 detects when the predicate stored in predicate memory or register 212 equals 1001; • In response, the trigger circuit sends a control signal to queue 240 to prompt the queue to issue the associated instruction "add z2, ich2, ich3 ; set p = 1010" for decoding and execution; In response to the completion of this instruction, execution circuit 210 sets the predicate stored in predicate memory or register 212 to a new value of 1010. Again, following the process outlined above, the trigger circuit detects a match between this new predicate value and a trigger condition (transferred by queue 240) associated with another queued instruction. This process follows a trigger state chain that matches the next trigger condition established during compiler code compilation.

[0023] Note that a predicate memory or register 212 may be provided at trigger circuit 250, or the predicate memory may be provided as a separate circuit item that can be written to by execution circuit 210 and read by trigger circuit 250.

[0024] For the amount of computation that can be performed at any given location within the spatial architecture, there are several constraints. Such constraints can be the rate at which data can be transferred or removed from certain locations, as well as power or thermal constraints. Therefore, some exemplary implementations can be used to adjust the amount of processing performed at a given location based on the available network or data transmission bandwidth.

[0025] The exemplary embodiments disclosed herein may provide additional configuration options that may potentially provide more parallel opportunities and may potentially make it easier to balance the ratio of computation to network or memory bandwidth.

[0026] Exemplary computation blocks Figure 2 A general example of computing block 112 is provided, as described above, which can operate on scalar and / or vector instructions.

[0027] One or more FIFO elements 200 serve as input channels to provide input to the execution circuit 210, and one or more FIFO elements 220 serve as output channels, as described above. Execution is performed by the execution circuit 210 relative to one or more processor registers 230.

[0028] An instruction queue provides an example of an instruction storage device for providing program instructions for execution. The program instructions are provided in response to a trigger circuit 250, which, in response to a trigger state generated by executing a program instruction (e.g., a previously executed program instruction) and trigger conditions associated with the instructions stored in queue 240, controls queue 240 to provide program instructions for execution. The program instructions issued by queue 240 are decoded by decoding circuit 260 before being passed to execution circuit 210.

[0029] Exemplary memory block Figure 3 The general schematic representation of MT 114 in the figure and Figure 2 The general schematic representation of CT scans is basically the same, with the following exceptions: (a) The "storage" block or circuit 300 is connected to the execution circuit; and (b) An "array interface" block or circuit 310, including an interface to the on-chip network 150, is connected to the execution circuitry.

[0030] In addition, the operation of memory block 114 corresponds to the computation block operation discussed above. Note that MT uses trigger instructions like CT, and although the execution path may (in some examples) be simpler in MT than in CT because MT does not necessarily perform batch data processing, MT still retains sufficient functionality to perform address calculation, data substitution, and data transfer between memory block or circuit 300 and the rest of the array via array interface block or circuit 310.

[0031] Communication of data items between CT 112 and MT 114 of data processing element 110 is performed via the output channel of the data item transmission block and the input channel of the data item reception block.

[0032] Data Flow Diagram In the techniques discussed below, it may be useful to first identify the data flow graph (DFG) representing the operations within the application in order to expand the computation within the application in space.

[0033] Examples of this type of DFG are as follows: Figure 4 As shown schematically. The input channels (ich) are indicated along the top of the DFG. n The bottom of the DFG represents the output channel (och 0) and represents computational operations such as multiplication (x), addition (+), subtraction (-) and maximum / min functions (max / min), where the lines that schematically link the various operations represent the input operands and output destinations of the operations.

[0034] The data flow graph can then be partitioned and distributed across available hardware units. However, the actual DFG often exceeds available space resources, so some form of time slicing eventually occurs to map the DFG to hardware. However, in some current examples of space design, the extent of this time slicing may be limited relative to conventional architectures.

[0035] Within the spatial architecture, the overall speedup observed relative to conventional architectures derives from a hybrid of instruction-level parallelism (ILP), data-level parallelism (DLP), and task-level parallelism (TLP). Task-level parallelism, or the establishment of task pipelines (tasks connected via data flows), can be considered orthogonal to the orchestration level that incorporates ILP and / or DLP. Thus, for example, task A can be placed on one set of processing elements, while task B can be placed on another set (and connected between the two sets so that data produced by A can be consumed by B), and these two sets of processing elements can operate concurrently, with each set individually striving to fully utilize the ILP and / or DLP present in its portion of the DFG.

[0036] Vectorization (enabling functional units to operate on groups of data elements simultaneously) and tiling (dividing the dataset into fixed blocks distributed across a spatial structure) generally enable the extraction of DLP. However, even if the system improves the chances of extracting DLP and TLP as described above, there may be ILP insufficiency, a potential source of parallelism that is not yet adequately addressed in current trigger architectures. This embodiment proposes a way to efficiently instruct processing elements to operate on a set of operations in parallel in a manner that achieves a potentially better trade-off or balance between the computational intensity of each processing element and available memory or network bandwidth. In either of these embodiments, the processing circuitry may therefore include vector processing circuitry configured to execute two or more vector processing instructions in parallel, each vector processing instruction applying a corresponding processing operation to a corresponding vector of two or more data elements.

[0037] Overview of the proposed technology Examples of how the architectural extensions proposed in this disclosure can potentially extract additional parallelism will now be described.

[0038] This example involves an application that has been divided into multiple smaller parts running on multiple corresponding processing elements. Assume that a part of the application or kernel has... Figure 4 The data flow diagram is shown. An example of how this can be implemented in the triggered processing element will be given.

[0039] Note that from this perspective, assuming vectorization and tiling have already been performed, Figure 4 The operation shown can (where appropriate) process vector data from the input channel and can return the vector data to other processing elements or memory.

[0040] observe Figure 4 In a DFG, it can be noted that multiple operations can be executed in parallel. That is, nodes at the same "level" (vertical position as shown in the figure) in the DFG do not have any interdependence and can be executed simultaneously without data conflicts.

[0041] In the absence of the technology proposed in this disclosure, a previously proposed specific implementation of this data stream may be as follows: 1mul z1, ich0, ich1; set p = 1001: when p == 1000 2add z2, ich2, ich3; set p = 1010: when p == 1001 3mul z3, ich0, ich2; deq ich0, deq ich2; set p = 1011: when p ==1010 4sub z4, ich1, ich3; deq ich1, deq ich3; set p = 1100: when p ==1011 5max z5, z1, z2; set p = 1101: when p == 1100 6min z6, z3, z4; set p = 1110: when p == 1101 7sub och0, z5, z6; set p = 1111: when p == 1110 8sub r1, r1, #1; set p = 0001: when p == 1111 9ne p3, r1, #0; set p = z000: when p == 0001 10 Here, "mul" represents multiplication; "sub" represents subtraction; and "ne" represents the "not equal to" test, which in this case is an immediate value of zero.

[0042] The instructions in lines 1 through 7 represent operations corresponding to... Figure 4 The nodes in the DFG (labeled 1 to 7). Additionally, in lines 3 and 4, there are channel dequeue operations ("deq") used to remove data items from the header of the specified channel. This can happen once all relevant uses have been performed on the corresponding data.

[0043] Register r1 stores the special iteration count value updated on line 8 (decreasing by the immediate value 1), and the comparison instruction on line 9 is used to choose between the instruction that triggers the restart of the DFG state transition sequence on line 1 and entering some other state that may indicate that all relevant values ​​have been processed.

[0044] The use of "z" in line 9 indicates that this specific bit is set at runtime based on the comparison result. That is, if r1 != 0, the bit at position 3 will be set to 1, but if r1 == 0, the bit at position 3 will be set to 0. Therefore, if the comparison (ne) succeeds, the final predicate result will be 1000, and if the check fails, the final predicate result will be 0000.

[0045] The arrangements proposed in this disclosure can utilize arrangements in which a programmer or compiler specifies a "group" or "bundle" of one or more instructions that can be processed in parallel (these two terms are considered equivalent for the purposes of this specification). In such arrangements, compilation or other operations may involve generating program instructions for execution according to corresponding triggering conditions, the execution of which sets the next triggering condition; dividing or bundling the program instructions into multiple groups of program instructions, at least some groups containing more than one program instruction, wherein the program instructions within a given group do not depend on the result of another program instruction in that given group; and generating input triggering conditions and output triggering states for each group; the input triggering condition being a condition that, when satisfied, enables the execution of the program instructions in that group, and the output triggering condition being a condition generated in response to the completion of the execution of all program instructions in that group.

[0046] That is, a bundle of instructions can be specified using the following format: *<predicates written upon completion of bundle> when<inputtrigger conditions> <instruction list> … * / / bundle-terminating asterisk In other words, instead of a trigger condition associated with the initiation of a single corresponding instruction, and that single instruction generating a trigger state in response to its execution, in the proposed arrangement, the trigger circuitry controls queue 240 to provide the instruction bundle for execution in response to a trigger state generated by executing a bundle of instructions, and in response to a trigger condition associated with a given bundle. In other words, predicate generation is performed bundle-by-bundle, and predicate testing for trigger conditions is also performed bundle-by-bundle; therefore, trigger conditions are associated with bundles rather than individual instructions.

[0047] Note that a bundle may contain only one instruction, but in many cases a bundle may contain more than one instruction, and in any case, the arrangement of this disclosure allows for bundle-by-bundle trigger condition testing and trigger state generation.

[0048] Therefore, applying this approach to the code above (and assuming the circuitry used can execute up to, for example, four instructions in parallel) generates the following program code. Note that software pipelining is employed in this code, and there is now a preamble section (lines 1 through 10) for aligning operations in time. Similar instruction-bundling programs can also be generated by expanding the previous code and grouping the operations within the expanded body; however, such expansion often leads to code "bloat" (a term used to describe the undesirable increase in the total number of program instructions performing a particular set of tasks), and is best used in scenarios where instruction space is not a critical resource.

[0049] 1* set p = 1010 : when p == 0010 2mul z1, ich0, ich1 3add z2, ich2, ich3 4mul z3, ich0, ich2; deq ich0, deq ich2 5sub z4, ich1, ich3; deq ich1, deq ich3 6* 7* set p = 1000 : when p == 1010 8max z5, z1, z2 9min z6, z3, z4 10* 11 12* set p = 1100 : when p == 1000 13mul z1, ich0, ich1 14add z2, ich2, ich3 15mul z3, ich0, ich2; deq ich0, deq ich2 16sub z4, ich1, ich3; deq ich1, deq ich3 17* 18* set p = 1101 : when p == 1100 19max z5, z1, z2 20min z6, z3, z4 21sub och0, z5, z6 22sub r1, r1, #1 twenty three* 24ne p3, r1, #0; set p = z000: when p == 1101 This code and Figure 4 The following operation bundles are defined for comparison with the DFG: • Figure 4 The operations are shown as 1, 2, 3, and 4; these are defined by the bundles shown in rows 1 through 6 of the list; the bundle executes when p == 0010, and in response to its execution, it sets p = 1010; • Figure 4 The operations shown in the middle are 5 and 6; these are defined by the bundles shown in rows 7 through 10 of the list; the bundle is executed when p == 1010, and in response to its execution, it sets p = 1000; As described above, these two bundles form what is called the prologue before the main loop. Executing the bundles on lines 1-6 and 7-10 provides the initial values ​​for z5 and z6, namely z5' and z6'. Subsequently, executing the bundles on lines 12-17 and 18-23 produces new values ​​for z5 and z6, namely z5'' and z6'', while consuming the old values: z5' and z6' (see the operation on line 21). This process is then repeated (the loop from line 24 back to line 12): that is, the operation on line 21 always consumes the previously produced values ​​of z5 and z6, while the bundles (lines 18-23) produce new values ​​for z5 and z6 for future iterations. The prologue needs to obtain the first pair of z5 and z6 values ​​at the beginning of the sequence.

[0050] Therefore, the main loop includes the following bundles: • Figure 4 The operations are shown as 1, 2, 3, and 4; these are defined by the bundle shown in rows 12 through 17 of the list; the bundle executes when p == 1000, and in response to its execution, it sets p = 1100; • Figure 4 The operations shown in the middle are 5 and 6; these are defined by the bundles shown in rows 7 through 10 of the list; the bundle is executed when p == 1100, and in response to its execution, it sets p = 1101; • The above loop continuation operation is represented by the single instruction bundle on line 23, which executes when p==1101 and sets p=z000.

[0051] Then, if r1 != 0, the loop branch returns to line 12, when p=1000. On the other hand, if r1 == 0, the check fails, and the code will trigger the processing... Figure 4 The instructions / bundle are the input predicate 0000 (not shown in this list) for further operations outside the DFG shown.

[0052] A side effect of the bundled triggering method shown above is that it can help reduce the number of active predicate bits or state space that a program must traverse, thereby enabling potential hardware improvements. Multiple instructions can utilize a single trigger condition, potentially improving the scalability of instruction selection logic.

[0053] Furthermore, instruction bundles achieve concurrency without traditional rename operations, dependency checks, or real-time operand availability tracking units, which are common in conventional processors and can lead to inefficiencies due to the additional complexity they introduce.

[0054] Note that all channel dequeue (or actually enqueue) operations are deferred until all instructions in the bundle have been completed. Therefore, the dequeue operations specified on lines 4, 5, 15, and 16 will not be executed until the entire corresponding bundle has been completed. In other words, compiling the code may include generating one or more operations, for one or more input channels that provide input data for the execution of the group, to dequeue the input data from one or more input channels after the program instructions for that group have been executed.

[0055] The exemplary circuit described below ensures that instructions are executed in a truly concurrent manner, so that no writes to intermediate register variables are seen until the end of the bundle. Therefore, for example, writes to vector registers z5 and z6 in lines 19 and 20 respectively will not occur until after the bundle terminates, and thus will not be seen by the "sub" operation in line 21. Multiple writes to the same destination vector register or channel within the bundle can lead to nondeterministic behavior and ideally should be detected by the compiler. Otherwise, some implementations may produce exceptions, while others may provide system registers that indicate such a failure has occurred (and can be used for debugging purposes).

[0056] All instructions within a bundle share the same triggering condition, so depending on the machine's current state, they either all proceed or none proceed. Thus, for example, if there is no data on input channel 3 (ich3), the "add" on line 14 and the "sub" on line 16 naturally cannot execute, but because they are bundled with the "mul" operation on line 13 and another "mul" operation on line 15, these operations will stall even if the data they operate on might actually be available. While this indirect synchronization of readers across multiple channels has some advantages, it can become costly for large bundles due to the increased likelihood of stalling. Therefore, some compiler implementations are operable to artificially reduce the bundle size from the bundle size specified in the code in order to reap some of the benefits of bundling while limiting the frequency of stalling. In some examples, the bundle can be limited to the degree of parallelism provided by the circuitry used to execute the instructions, for example, bundling up to four instructions in some of the examples given below.

[0057] While multiple execution pipelines or paths within a triggering microarchitecture capable of executing bundled instructions can operate concurrently, such pipelines may not be symmetrical. Therefore, in some implementations, a compiler or other similar tool may be operational to verify that the mixing of instructions within each bundle is supported by the underlying hardware. If some execution "slots" or paths will only accept a limited number of instructions, then the instructions may also need to be reordered (relocated) within the bundle to match the available hardware. Furthermore, if certain concurrent combinations of operations are not supported, the bundle may need to be broken down by the compiler, or the triggering instruction hardware may invoke a sorting unit that may be able to time-slice the operations within the bundle at runtime. In fact, this may also occur when the number of instructions in a bundle exceeds the maximum supported execution (parallel) width. It may also be the case that even if the bundle width matches the execution width, in some implementations, not all instructions in the bundle may be able to execute concurrently due to register access constraints, thus some form of sorting may be unavoidable.

[0058] State transition instructions, such as comparisons (which are written to the predicate register), are allowed within the bundle, but multiple writes to the same predicate register may lead to unpredictable behavior. Additionally, the predicate set indicator for the entire bundle will have a high-impedance indicator in the relevant bit position (such as the position shown in line 24), allowing that bit to be set by the result of one or more comparisons within the bundle.

[0059] In other words, if there is only one comparison in the bundle, you can use an example like the following: 1* set p = z101 : when p == 1111 2sub z1, z2, z3 3mul z7, z6, z8 4ne p3, r1, #0 5sub z0, z1, z6 6* Here, the transformation in bit 3, which is usually associated with a single instruction, is now associated with the entire bundle; and the predicate bit "3" will only be updated when the bundle is complete.

[0060] If there are more comparison operations within the bundle, it should be ensured that updates do not conflict; in other words, updates will preferably be applied to different predicate positions. For example: 1* set p = z10z : when p == 1111 2sub z1, z2, z3 3ne p0, r2, #0 4ne p3, r1, #0 5sub z0, z1, z6 6* One aspect worth considering is the fact that bundle granularity may not be constant throughout the program, and in some programs it may even vary in a highly irregular manner. Some instances of this irregularity can be observed by examining programs with the aforementioned bundled trigger instructions, as these programs have bundles of sizes 1, 2, and 4. Therefore, the hardware implementation of arranging bundles in the instruction memory where they appear in the program may suffer from inefficiency or underutilization of certain memory regions. In this regard, refer to... Figure 5 It provides illustrative examples of bundles of different sizes (represented by the first shade 500) and corresponding underutilized or wasted memory areas in each case, represented by the second shade 510.

[0061] Assuming each triggered instruction contains multiplexed state transition operations, these do not necessarily need to be placed sequentially in instruction memory, but can be freely rearranged. As a result, an exemplary implementation is proposed. Figure 6 The organization of the instruction memory is shown to enable potentially more efficient storage of bundled instructions. Figure 6 An exemplary implementation of a processing element in a space-triggered architecture that supports instruction bundling is shown.

[0062] Figure 6 The arrangement (and in fact) Figure 7 or Figure 8 The arrangement of these blocks can represent aspects of memory partitioning described above (different from memory devices and array interfaces) and / or computational partitioning, or in other words, Figure 1 The circuitry at a node of an array of such processors or circuits. The compilation operation may involve routing a set of program instructions to a single processor within an array of such processors or circuits.

[0063] That is, in Figure 6 In this context, bundles of similar size are grouped together in instruction queues (or more generally, instruction storage devices) of corresponding different widths, where different bundle sizes are placed in separate memory modules so that they can collectively have a larger size than the specified bundles. Figure 5 This demonstrates the achievement of higher storage density.

[0064] The instruction output flip-flop 610, which receives the signal from the trigger circuit 615, is extended (relative to the reference). Figure 2 Those described are incorporated into a "path" number or other indication to indicate the size of the bundle to be triggered next, thereby simplifying the retrieval of the relevant bundle. The "path" number is also provided to the multiplexer 620 so that program instructions provided by the relevant queues of the instruction storage device 600 are routed for decoding and execution.

[0065] The actual size of the queues in instruction store 600 can depend on a mix of bundle sizes in the parsed program. Routing circuitry 625 operates under the control of signals or data provided, for example, by the compiler, to route instructions to appropriate queues in instruction store 600 for queuing, thereby routing a set of program instructions to an instruction queue selected from a plurality of instruction queues configured to selectively provide that set of program instructions for parallel execution. Note that the current arrangement of bundles and the provision of queues in instruction store 600 provides the possibility that a particular bundle may include one instruction, but also explicitly provides the possibility of multiple instruction bundles. In cases where a bundle includes more than one instruction, the instruction store is configured to provide more than one instruction (such as 2, 3, or 4 instructions) for parallel execution. Note that, under the control of the compiler, a bundle of 1 or 2 instructions can be routed by routing circuitry 625 to 4 instruction queues, depending on the storage requirements of other bundles in that processing level.

[0066] It is not required to provide a queue to hold the entire bundle, but in the exemplary arrangement, the bundle can be compiled into a queue no larger than the maximum width provided by the circuit, as described below.

[0067] The queue may have a depth of one or more bundles, but in an exemplary implementation, the queue has a depth of at least two bundles, such that when the queue provides bundles for execution, another bundle has already been queued and is ready to become the new head of the queue.

[0068] Note that in a potentially more efficient implementation, storing the bit pattern corresponding to the previously decoded instruction in a front-end memory area (which can then be accessed in parallel, rather than copying the instruction decoding hardware unit multiple times) is... Figure 6 The multiple instruction decoding units 630 shown may not exist. Additionally, in some embodiments, both approaches may be present, and a special storage area containing previously decoded bundles (obtained a priori during the compilation phase or when decoding earlier instances of bundled instructions) may be used in some instances to reduce front-end power requirements or pipeline depth by skipping the decoding phase.

[0069] Trigger circuit 615 is used to evaluate the current state of the processing element (possibly using data and channel occupancy information from the result bus and / or accessing the predicate memory (not shown), as described above), determine which bundle triggering conditions have been met, select the bundle to be triggered from the instruction memory, and control multiplexer 620 to route the selected bundle.

[0070] Execution is performed relative to the values ​​stored in register file 635 and input channel 640, which are routed to execution circuitry 645 by schematic multiplexer 650. Execution results are presented on result bus 655, from which they can be routed to output channel 660, back to register file 635, and / or trigger circuitry 615.

[0071] therefore, Figure 6 An example is provided in which the instruction storage device 600 includes at least two instruction queues, each instruction queue configured to provide a set of program instructions for execution. The instruction queues include a first instruction queue configured to provide a set of up to n program instructions for parallel execution and a second instruction queue configured to provide a set of up to m program instructions for parallel execution, where m is not equal to n. For example, in... Figure 6 In the example, m and n can be considered as any of the values ​​1, 2, and 4.

[0072] In this example, trigger circuit 615 responds to a trigger state generated by executing program instructions and to a trigger condition associated with a given instruction queue in at least two instruction queues of instruction storage device 600, to control 610 to provide queued program instructions for execution in the given instruction queue.

[0073] The arrangement also shows routing circuitry 625, configured to route a set of program instructions to a selected instruction queue in the instruction queue; and multiple instruction decoding units 630 and execution circuitry 645 to execute multiple instructions in parallel (in Figure 6 In the example, there are four program instructions, which is greater than or equal to the maximum number of program instructions that can be provided in parallel by any one of the instruction queues in the instruction queue of the instruction storage device 600 (again, four in this example). In other embodiments, for example, the number could be seven, such that bundles from each queue can be executed in parallel.

[0074] therefore, Figure 6 (and in fact) Figure 7 or Figure 8 The circuitry provides an example including: an instruction decoding unit 630; an execution circuit 645 configured to execute program instructions according to a corresponding trigger condition matching the current trigger state, and to set a next trigger state in response to the execution of the program instructions; the processing circuitry including: an instruction storage device 600 configured to selectively provide a set of two or more program instructions for parallel execution; and a trigger circuit 615 configured to control the instruction storage device to provide program instructions (e.g., program instructions from a given set of program instructions) for execution in response to a trigger state generated by executing a set of program instructions and in response to a trigger condition associated with a given set of program instructions.

[0075] Register file considerations Figure 6 A general-purpose or monolithic register file 635 is provided. Therefore, although this arrangement provides... Figure 6 The multiple execution paths are represented by the instruction decoding unit 630 and the execution circuit 645, but Figure 6 The arrangement provides a set of processor registers (i.e., a set of processor registers) shared by program instructions executed by any execution path in the execution path, for executing program instructions within a set of program instructions. This set of processor registers is accessible during the execution of program instructions.

[0076] However, this arrangement presents challenges in practical design because the register file 635 can have a large number of read and write ports: for example, 12 read ports and 4 write ports in one implementation. This potentially prohibitive cost arises because each execution slot should ideally be able to access up to 3 source operands simultaneously, and the bandwidth of the data paths at the exit function unit and the supply forwarding path, as well as at the back end of the register write circuitry, needs to be sufficiently high to avoid introducing stagnation. Several potential solutions exist.

[0077] In some exemplary implementations, operations such as the multiply-accumulate operation "mla" requiring three source operands can be limited to a small number of pipelines (execution paths), and other pipelines may only support register file access to one or two source operands. This approach reduces the total port count but may potentially compromise flexibility and performance. Therefore, in this example, at least one execution path is configured to execute program instructions with up to a first number of operands, and at least another execution path is configured to execute program instructions with up to a second number of operands, which are different from the first number. For example, the first and second numbers of operands could be 2 and 3, respectively.

[0078] Partition register file Now refer to Figure 7 Another implementation using a partitioned register file is described here. Figure 6 The common features of the configurations are given the same reference numerals and will not be described in detail again.

[0079] Figure 7 The arrangement provides at least two sets of processor registers (in Figure 7 The arrangement is shown as "Reg Bank n" 700, where n = 0, 1, 2 or 3), a set of processor registers for each of the execution paths, which are accessible during the execution of program instructions through the execution path; the arrangement also provides communication circuitry 710 for transferring data between the set of processor registers.

[0080] In this implementation, during the compilation phase, the register allocator can be restricted so that all instructions sharing the same slot or execution path have a common portion of the register file (memory bank n) between them, but explicit "register moving" is required to transfer information between memory banks using the inter-memory communication circuit 710. In this implementation, lines 12 through 23 of the previously shown code can be rewritten as follows: 12* set p = 1100 : when p == 1000 13mul z1_0, ich0, ich1 14add z2_1, ich2, ich3 15mul z3_2, ich0, ich2; deq ich0, deq ich2 16sub z4_3, ich1, ich3; deq ich1, deq ich3 17* 18* set p = 1101 : when p == 1100 19[ mov z2_0, z2_1; mov z3_3, z3_2; mov z5_2, z5_0; mov z6_2, z6_3 ] 20max z5_0, z1_0, z2_0 21sub r1_1, r1_1, #1 22sub och0, z5_2, z6_2 23min z6_3, z3_3, z4_3 twenty four* As can be seen, the instructions within a bundle have been "reordered" to reduce the number of data movement operations between memory banks. In the register notation used here, the suffixes "_0", "_1", "_2", and "_3" identify the corresponding register memory bank containing that register. The explicit move operations required to support instruction bundling are shown in line 19.

[0081] exist Figure 7 In this example, there are four input channels 640, which are not stored like a register file. This is because the number of input channels is typically much smaller than the main register file and they are "read-only," so this may be an acceptable trade-off. Additionally, data sent to the four output channels is never read back, so storage can be avoided in some implementations. However, in other examples, the input channels may be stored in the same way as a register file.

[0082] Note that return path 720 allows the execution result of a specific execution path to be written back to the register memory associated with that execution path without requiring additional operations using the inter-memory communication circuit 710.

[0083] In another implementation using a partitioned register file, such as Figure 8 As shown, another example of a register access scheme provides a bundled trigger instruction set architecture that reduces the number of read ports required for the register file while allowing parallel access through multiple slots or execution paths.

[0084] Again, with Figure 6 or Figure 7 The same features are referred to by the same reference numerals and will not be described in further detail.

[0085] However, with Figure 7 The solutions are different, in Figure 8 In this approach, no explicit move operations are required to maintain consistency between slots or execution paths. In this scheme, each slot has a small local register file called the slot register buffer (SRB0..3) 800, which holds a copy of the operands retrieved from the main register file 810 (shared across all paths) or written by previous data processing operations performed by that execution path (note that there is a return path 820 for data produced by a given execution path).

[0086] There are many possible techniques for managing the inflow or outflow of information into such a structure, and one approach is described below. By keeping each SRB 800 small relative to the main register file 810 and limiting the number of read ports each has, it is possible to handle the concurrency opportunities of the bundle while keeping it within a reasonable power envelope.

[0087] The Register Buffer Management Unit (RBMU) 830 is responsible for moving data between the main register file 810 and each SRB 800. Whenever a slot attempts to read a register value from its corresponding SRB 800, it consults the corresponding small local structure called the Register Index Translation Table (RITT) 840, and if a valid entry is found, it uses the corresponding index stored in the RITT 840 to retrieve the actual value from the SRB 800. In some implementations, the RITT 840 may be implemented using latches. The indirectness of the RITT structure is to ensure that the SRB 800 can be compact and fully associative, but without introducing a large number of expensive comparators in potentially critical paths. If no valid entry is found, a valid entry can be obtained by directly accessing another SRB 800 (i.e., for another path). If no other SRB has a valid entry, the register read value is obtained from the main register file 810. The newly retrieved value is placed in the SRB 800 of the requesting slot. An entry is also created in the corresponding RITT 840, where the valid bit is set to true. As can be expected, at the start of a program that includes bundled instructions, many read values ​​must be obtained directly from the main register file 810. These accesses may initially cause latency due to the limited number of read ports available for accessing the main register file 810. However, as the program progresses further and begins iterating over certain bundled trigger instructions, the SRB 800 may provide more access than the main register file, potentially improving parallelism.

[0088] The RBMU 830 broadcasts any updates to a specific register to all SRB800s that have a copy of that register. This broadcasting scheme is efficient because only one function unit is allowed to write to each destination register within the bundle. A "modify" bit is set at the corresponding location to ensure that the relevant entry in the SRB 800 is written to the main register file if it is later evicted. Such evicting occurs due to capacity issues when a new value is about to be added to the SRB, and to make the process efficient, an access counter can be used to perform usage tracking. Low-usage entries can be evicted. If there is currently no matching entry in any SRB for the register being written to, the value is written to the main register file.

[0089] In conventional processors, the aforementioned description of multi-level register storage structures would be unacceptable because these structures would introduce additional latency when encountering speculation failures or exceptions. Making the architectural register state visible could only be achieved by potentially exhausting all SRBs, which could be an expensive and time-consuming operation. However, the proposed structure is considered not only acceptable but also advantageous in this use case because the primary purpose of the bundled trigger instruction architecture is flexible multi-domain space acceleration. In this use case, there are fewer requirements for general objectives that reflect those applicable to conventional processors, such as rich speculation, accurate exception handling, and fast exception entry capabilities.

[0090] exist Figure 8 Within the module, there exists a hardware structure called the Input Channel Buffer Management Unit (ICBMU) 850, which operates similarly to the RBMU and can transfer input data from channels to a small storage area called the Slot Channel Buffer (SCB0..3) 860. However, unlike the fully associative SRBs, each SCB can be directly mapped because the number of input channels is much smaller relative to the main register file. Additionally, each SCB may require fewer ports compared to the SRBs, as instructions to read up to three channels simultaneously are rare. Furthermore, the input channels are "read-only," so the ICBMU does not need to have as many coherent functions as the RBMU. Its key purpose is to listen for "dequeue" and "channel read" events, and whenever a dequeue operation occurs at the end of the bundle, new data at the head of the corresponding channel is propagated to all slots recently read from that channel. No evicting is required because the SCBs are a directly mapped structure.

[0091] Information from the execution unit to the output channel does not need to pass through any special management unit because there are no critical events requiring synchronization between the data transmitted in the backend and the output channel. Furthermore, two premises—that only one writer is allowed per channel within the bundle and that the functional units of the triggered processing elements never read data back from these channels—further simplify the construction of the output path required to support the bundle.

[0092] therefore, Figure 8 A set of main register files 810 shared by program instructions executed in any execution path is shown; buffer circuitry 800 for each execution path to store copies of data held in one or more processor registers in the processor registers; and control circuitry 830, 840 for controlling data copying between the set of processor registers and the buffer circuitry. As described above, in some examples, the execution result of any execution path can be directly written back to the buffer circuitry 800 associated with that execution path.

[0093] Processing array When implemented using any of the circuits according to the exemplary embodiments of this disclosure, Figure 1 The arrangement provides an example of a processing array, which includes: an array of such circuits; and a switch 140 and an on-chip network 150 for transferring data between the circuits in the array.

[0094] Compiler Examples Now refer to Figure 9 and Figure 10 An exemplary arrangement illustrating a compiler implementation scheme is described here. Figure 9 This schematically illustrates what can be used, for example, according to reference below. Figure 12 The method described therein performs compiler operations to produce a data processing apparatus 900 with bundled program code as described above. It should be noted that any of the circuits previously described can be used to perform compiler operations, but in at least some examples, a general-purpose data processing apparatus such as apparatus 900 may be used.

[0095] The device 900 includes one or more processing elements or a central processing unit (CPU) 910, random access memory 920, a non-volatile storage device 930 such as flash memory, optical disk or magnetic disk, read-only memory (examples of a machine-readable non-transitory storage medium that can provide or store computer software for performing the compiler operations described herein), a graphical user interface 940 such as a display, keyboard, pointing controls, etc., and one or more other interfaces 950 such as a network interface, all interconnected via a bus structure 960. In operation, program instructions for performing compiler or other functions are read from the non-volatile storage device 930 and executed by the CPU 910 in cooperation with the random access memory 920.

[0096] Figure 10 The illustration schematically depicts a compilation operation, where source code 1000 is compiled by compilation operation 1010, for example, using reference... Figure 12 The process described is used to compile and generate executable program instructions 1020.

[0097] Method Overview Based on the overview of the technologies discussed above, Figure 11 This is a schematic flowchart illustrating a method (which may be implemented, for example, by the circuit described above), the method comprising: Execute the program instruction (at step 1100) according to the corresponding trigger condition that matches the current trigger state, and set the next trigger state in response to the execution of the program instruction; A set of two or more program instructions is provided (at step 1110) by the instruction storage device for parallel execution; and In response to a trigger state generated by executing program instructions and in response to a trigger condition associated with a given set of program instructions, the instruction storage device is controlled (at step 1120) to provide program instructions from the given set of program instructions for execution.

[0098] Through a further overview of the above technologies Figure 12 This is a schematic flowchart illustrating a computer-implemented method, which includes: Based on the corresponding triggering conditions, program instructions are generated (at step 1200) for execution, and the execution of the program instructions sets the next triggering condition; The program instructions are divided (at step 1210) into multiple groups of program instructions, at least some groups containing more than one program instruction, wherein the program instructions within a given group do not depend on the result of another program instruction in that given group; and For each group, an input trigger condition and an output trigger state are generated (at step 1220); the input trigger condition is a condition that enables the execution of the program instructions of the group when it is met, and the output trigger condition is a condition generated in response to the completion of the execution of all program instructions in the group.

[0099] In the exemplary arrangement, each of steps 1200, 1210, and 1220 can be implemented by a computer, such as operating under the control of computer software. Figure 9 The device (computer software can also be stored by non-volatile storage device 930).

[0100] Simulated implementation plan Figure 13 A specific implementation of a simulator that can be used is illustrated. While the previously described embodiments implement the invention in terms of means and methods for operating specific processing hardware supporting the technologies involved, it is also possible to provide an instruction execution environment according to the embodiments described herein, which is implemented using a computer program. Such computer programs are generally referred to as simulators, in part because they provide a software-based implementation of a hardware architecture. Types of simulator computer programs include emulators, virtual machines, models, and binary converters, including dynamic binary converters. Typically, a simulator implementation can run on a host processor 1330 that supports the simulator program 1310, which optionally runs a host operating system 1320. In some arrangements, multiple emulation layers may exist between the hardware and the provided instruction execution environment and / or multiple different instruction execution environments provided on the same host processor. Historically, powerful processors were required to provide simulator implementations that execute at a reasonable speed, but this approach may be reasonable in certain situations, such as when it is desirable to run code native to another processor for compatibility or reuse reasons. For example, a simulator implementation may provide additional functionality to the instruction execution environment that is not supported by the host processor hardware, or provide an instruction execution environment that is typically associated with a different hardware architecture. The following reference [2] provides an overview of the simulation.

[0101] With respect to embodiments previously described with reference to specific hardware constructions or features, in simulated embodiments, equivalent functionality may be provided by suitable software constructions or features. For example, a particular circuit system may be implemented as computer program logic in a simulated embodiment. Similarly, memory hardware such as registers or cache memory may be implemented as software data structures in a simulated embodiment. One or more of the hardware elements referenced in the previously described embodiments are present in an arrangement on host hardware (e.g., host processor 1330), and where appropriate, some simulated embodiments may utilize the host hardware.

[0102] The simulator program 1310 may be stored on a computer-readable storage medium (which may be a non-transitory medium) and provides a program interface (instruction execution environment) to the target code 1300 (which may include an application program, operating system, and management program), the program interface being identical to the interface of the hardware architecture modeled by the simulator program 1310. Therefore, the program instructions of the target code 1300 include instructions for providing processing program logic configured to execute program instructions according to a corresponding trigger condition matching the current trigger state and to set the next trigger state in response to the execution of the program instructions; the processing program logic includes: instruction storage program logic configured to selectively provide a set of two or more program instructions for parallel execution; and triggering program logic that controls the instruction storage program logic to provide program instructions for the above execution in response to a trigger state generated by executing program instructions and in response to trigger conditions associated with a given set of program instructions. The program instructions of the target code can be executed from within the instruction execution environment using the simulator program 1310, enabling a host processor 1330, which does not actually possess the hardware features of the aforementioned device, to simulate these features.

[0103] Therefore, an exemplary embodiment may provide a virtual machine computer program including instructions for controlling a host data processing apparatus to provide an instruction execution environment including process logic configured to execute program instructions according to a corresponding trigger condition matching a current trigger state and to set a next trigger state in response to the execution of program instructions; and processing circuitry including: instruction storage program logic configured to selectively provide a set of two or more program instructions for parallel execution; and triggering program logic configured to control the instruction storage program logic to provide program instructions for execution in response to a trigger state generated by executing program instructions and a trigger condition associated with a given set of program instructions.

[0104] Overview In this application, the phrase "configured as..." is used to mean that the elements of the device have a configuration capable of performing the defined operations. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operations, or a processor or other processing device may be programmed to perform the function. "Configured as" does not mean that the elements of the device need to be changed in any way to provide the defined operations.

[0105] While exemplary embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments, and various changes, additions, and modifications can be made therein by those skilled in the art without departing from the scope and spirit of the invention as defined in the appended claims. For example, features of dependent claims may be combined with features of independent claims in various ways without departing from the scope of the invention.

[0106] References : [1]A. Parashar et al., "Efficient Spatial Processing Element Controlvia Triggered Instructions," in IEEE Micro, vol. 34, no. 3, pp. 120-137, May-June 2014, doi: 10.1109 / MM.2014.14.

[0107] [2] R. Bedichek, "Some Efficient Architecture Simulation Techniques", in Winter 1990 USENIX Conference, Pages 53 - 63.< / operation>

Claims

1. A circuit comprising: The processing circuit is configured to execute program instructions according to a corresponding trigger condition that matches the current trigger state, and to set the next trigger state in response to the execution of the program instructions. The processing circuit includes: An instruction storage device configured to selectively provide a set of two or more program instructions for parallel execution; and A trigger circuit, in response to a trigger state generated by executing program instructions and a trigger condition associated with a given set of program instructions, controls the instruction storage device to provide program instructions from the given set of program instructions for execution. The instruction storage device includes at least two instruction queues, each instruction queue being configured to provide a set of program instructions for execution. The instruction queues include a first instruction queue and a second instruction queue. The first instruction queue is configured to provide a set of up to n program instructions for parallel execution, and the second instruction queue is configured to provide a set of up to m program instructions for parallel execution, where m is not equal to n.

2. The circuit of claim 1, wherein the triggering circuit controls the given instruction queue to provide queued program instructions for execution in response to a trigger state generated by executing program instructions and in response to a trigger condition associated with a given instruction queue of the at least two instruction queues.

3. The circuit of claim 1 or claim 2, further comprising a routing circuit configured to route a set of program instructions to a selected instruction queue in the instruction queue.

4. The circuit according to claim 1 or claim 2, comprising multiple execution paths for executing multiple program instructions in parallel, the number of said multiple program instructions being greater than or equal to the maximum number of program instructions provided in parallel by any one of said instruction queues.

5. The circuit of claim 4, comprising a set of processor registers shared by the execution of program instructions within a set of program instructions, the set of processor registers being accessible during the execution of the program instructions.

6. The circuit according to claim 4, comprising: At least two sets of processor registers, one set for each execution path in the execution path, wherein the set of processor registers for a given execution path is accessible during the execution of program instructions by the execution path; and A communication circuit for transmitting data between the respective groups of processor registers.

7. The circuit according to claim 4, comprising: A set of processor registers shared by program instructions executed in any execution path within the execution path; A buffer circuit for each execution path, the buffer circuit being used to store a copy of the data held by one or more processor registers in the processor registers; and A control circuit for controlling data copying between the set of processor registers and the buffer circuit.

8. The circuit of claim 4, wherein at least one of the execution paths is configured to execute program instructions having up to a first number of operands, and at least another execution path is configured to execute program instructions having up to a second number of operands, the first number and the second number being different.

9. The circuit of claim 1, wherein the processing circuit includes a vector processing circuit configured to execute two or more vector processing instructions in parallel, each vector processing instruction applying a corresponding processing operation to a corresponding vector of two or more data elements.

10. A processing array, comprising: An array of circuits according to any one of claims 1 to 9; and A data communication circuit for transmitting data between circuits in the array.

11. A processing method, comprising: The program instruction is executed according to the corresponding trigger condition that matches the current trigger state, and the next trigger state is set in response to the execution of the program instruction. A set of two or more program instructions is provided by an instruction storage device for parallel execution; as well as In response to a trigger state generated by executing program instructions and in response to a trigger condition associated with a given set of program instructions, the instruction storage device is controlled to provide program instructions from the given set of program instructions for execution. The instruction storage device includes at least two instruction queues, each instruction queue being configured to provide a set of program instructions for execution. The instruction queues include a first instruction queue and a second instruction queue. The first instruction queue is configured to provide a set of up to n program instructions for parallel execution, and the second instruction queue is configured to provide a set of up to m program instructions for parallel execution, where m is not equal to n.

12. A computer-implemented method, the method comprising: According to the corresponding triggering conditions, program instructions are generated in the instruction storage device for execution, and the execution of the program instructions sets the next triggering conditions; The program instructions are divided into multiple groups of program instructions, at least some groups contain more than one program instruction, wherein the program instructions in a given group do not depend on the result of another program instruction in the given group, the instruction storage device includes at least two instruction queues, the instruction queues include a first instruction queue and a second instruction queue, the first instruction queue is configured to provide a group of up to n program instructions for parallel execution, and the second instruction queue is configured to provide a group of up to m program instructions for parallel execution, where m is not equal to n; as well as Generate input trigger conditions and output trigger states for each group; The input trigger condition is a condition that enables the execution of the program instructions of the group when it is met, and the output trigger condition is a condition generated in response to the completion of the execution of all program instructions in the group.

13. The method of claim 12, further comprising, for one or more input channels providing input data for execution of the group, generating one or more operations to dequeue the input data from the one or more input channels after execution of the program instructions of the group.

14. The method of claim 12 or claim 13, comprising routing a set of program instructions to a single processor of a processor array.

15. The method of claim 12 or claim 13, further comprising routing a set of program instructions to an instruction queue selected from a plurality of instruction queues, the instruction queues being configured to provide the set of program instructions for parallel execution.

16. A compiler comprising computer program code that, when executed by a computer, causes the computer to perform the method according to any one of claims 12 to 15.

17. A non-transitory machine-readable storage medium storing the compiler according to claim 16.

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