Driving method of display panel, display driving circuit and display device

Abstract

A display panel driving method, a display driving circuit and a display device, the display panel driving method comprising: in a data refresh stage of at least one display frame in a plurality of continuous display frames, loading a gate opening voltage to a gate line in the display panel, and loading a data voltage of a to-be-displayed image to each data line, so that each sub-pixel inputs a corresponding data voltage (S100); in a blank time stage of the at least one display frame, loading a gate closing voltage to the gate line in the display panel, and loading a compensation voltage to each data line (S200); when the data voltage in the sub-pixel connected with the data line is greater than a common electrode voltage, the compensation voltage loaded on the data line is less than the data voltage in the sub-pixel connected with the data line; and / or when the data voltage in the sub-pixel connected with the data line is less than the common electrode voltage, the compensation voltage loaded on the data line is greater than the data voltage in the sub-pixel connected with the data line.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a driving method for a display panel, a display driving circuit, and a display device. Background Technology

[0002] Displays such as Liquid Crystal Displays (LCDs) and Organic Light-Emitting Diodes (OLEDs) typically include multiple pixels. Each pixel may include a red subpixel, a green subpixel, and a blue subpixel. By controlling the display data corresponding to each subpixel, the display brightness of each subpixel is controlled, thereby mixing the desired colors to display a color image. Summary of the Invention

[0003] The display panel driving method provided in this disclosure operates in multiple consecutive display frames, each display frame including a data refresh phase and a blank time phase;

[0004] The driving method for the display panel includes:

[0005] During the data refresh phase of at least one of a series of display frames, a gate enable voltage is applied to the gate lines in the display panel, and a data voltage of the image to be displayed is applied to each data line so that each sub-pixel receives a corresponding data voltage.

[0006] During the blank time phase of at least one of the display frames, a gate shutdown voltage is applied to the gate lines in the display panel, and a compensation voltage is applied to each of the data lines.

[0007] Wherein, when the data voltage in the sub-pixel connected by the data line is greater than the common electrode voltage, the compensation voltage applied on the data line is less than the data voltage in the sub-pixel connected by the data line;

[0008] And / or, when the data voltage in the sub-pixel connected by the data line is less than the common electrode voltage, the compensation voltage applied on the data line is greater than the data voltage in the sub-pixel connected by the data line.

[0009] In some examples, the compensation voltage is fully applied during a blank time phase of at least one of the display frames.

[0010] In some examples, the display panel employs a column inversion or frame inversion method; the compensation voltage includes a first sub-compensation voltage;

[0011] For each of the data lines, the polarity of the first sub-compensation voltage applied to the data line is opposite to the polarity of the sub-pixel to which the data line is connected.

[0012] In some examples, the display frames in which the compensation voltage is applied to each of the data lines during the blank time phase include a first display frame and a second display frame;

[0013] The first display frame corresponds to a first refresh rate, and the second display frame corresponds to a second refresh rate; and the first refresh rate is greater than the second refresh rate;

[0014] The duration of the blank time phase in the first display frame is shorter than the duration of the blank time phase in the second display frame.

[0015] In some examples, the display frame in which the compensation voltage is applied to each of the data lines during the blank time phase is defined as a setting display frame; in two adjacent setting display frames, for the same data line, there is a first difference between the first sub-compensation voltage applied to the data line in the previous setting display frame and the common electrode voltage, and a second difference between the first sub-compensation voltage applied to the data line and the common electrode voltage in the next setting display frame;

[0016] The absolute value of the first difference is equal to the absolute value of the second difference.

[0017] In some examples, the compensation voltage also includes a transition compensation voltage that occurs before the first sub-compensation voltage;

[0018] For each of the data lines, the polarity of the transition compensation voltage applied to the data line is the same as the polarity of the sub-pixel to which the data line is connected.

[0019] In some examples, the display panel employs a column inversion or frame inversion method; the compensation voltage includes a second sub-compensation voltage;

[0020] For each of the data lines, the polarity of the second sub-compensation voltage applied on the data line is the same as the polarity of the data voltage in the sub-pixel connected to the data line.

[0021] In some examples, the display frame in which the compensation voltage is applied to each of the data lines during the blank time phase is defined as the set display frame;

[0022] A portion of the consecutive display frames are the designated display frames;

[0023] Of the multiple consecutive display frames, the display frames other than the set display frames are non-set display frames;

[0024] The non-defined display frames include:

[0025] During the data refresh phase, a gate enable voltage is applied to the gate lines in the display panel, and a data voltage of the image to be displayed is applied to the data lines so that each sub-pixel inputs the corresponding data voltage.

[0026] During the blank time period, a gate shutdown voltage is applied to the gate lines in the display panel, and each of the data lines is floated.

[0027] In some examples, there is at least one non-configured display frame between two adjacent configured display frames.

[0028] In some examples, the number of non-defined display frames is the same between every two adjacent defined display frames.

[0029] In some examples, the grayscale corresponding to the compensation voltage applied to each of the data lines is the same.

[0030] In some examples, for each of the data lines, the gray level corresponding to the compensation voltage applied on the data line is the same as the gray level corresponding to a data voltage in a sub-pixel connected to the data line.

[0031] In some examples, the grayscale corresponding to the compensation voltage is determined using the following formula;

[0032] VS11 = (VA12 + VA12) / 2;

[0033] Wherein, VS11 represents the gray level corresponding to the compensation voltage, VA11 represents the maximum gray level in a display frame selected from the multiple consecutive display frames, VA12 represents the minimum gray level in the display frame selected from the multiple consecutive display frames, and VA11+VA12 is an even number.

[0034] In some examples, the grayscale corresponding to the compensation voltage is determined using the following formula;

[0035] VS21 = (VA21 + VA22 + 1) / 2;

[0036] Wherein, VS21 represents the gray level corresponding to the compensation voltage, VA21 represents the maximum gray level in a display frame selected from the multiple consecutive display frames, VA22 represents the minimum gray level in the display frame selected from the multiple consecutive display frames, and VA21+VA22 is an odd number.

[0037] In some examples, applying a compensation voltage to each of the data lines includes:

[0038] During the blank time phase of the set display frame, a display frame is selected from the plurality of display frames, and for each data line, the voltage of the gray level corresponding to the data voltage of a row of sub-pixels in the display panel is loaded onto the data line of the selected display frame.

[0039] In some examples, applying a compensation voltage to each of the data lines includes:

[0040] During the blank time phase of the set display frame, a display frame is selected from the plurality of display frames, and for each data line, the data voltage of the last row of sub-pixels in the display panel corresponding to the gray level of the selected display frame is loaded onto the data line.

[0041] In some examples, applying a compensation voltage to each of the data lines includes:

[0042] During the blank time phase of the set display frame, a display frame is selected from the plurality of display frames, and for each data line, the voltage of the gray level corresponding to the data voltage on the selected display frame is sequentially loaded onto the data line.

[0043] In some examples, the display frame selected from the plurality of display frames is one of the previous display frame adjacent to the set display frame and the set display frame.

[0044] The display driving circuit provided in this embodiment allows the display panel to operate in multiple consecutive display frames, each display frame including a data refresh phase and a blank time phase;

[0045] The display driving circuit is configured as follows:

[0046] During the data refresh phase of at least one of a series of display frames, a gate enable voltage is applied to the gate lines in the display panel, and a data voltage of the image to be displayed is applied to each data line so that each sub-pixel receives a corresponding data voltage.

[0047] During the blank time phase of at least one of the display frames, a gate shutdown voltage is applied to the gate lines in the display panel, and a compensation voltage is applied to each of the data lines.

[0048] Wherein, when the data voltage in the sub-pixel connected by the data line is greater than the common electrode voltage, the compensation voltage applied on the data line is less than the data voltage in the sub-pixel connected by the data line;

[0049] When the data voltage in the sub-pixel connected by the data line is less than the common electrode voltage, the compensation voltage applied on the data line is greater than the data voltage in the sub-pixel connected by the data line.

[0050] The display device provided in this disclosure includes a display panel and a timing controller; the display panel includes multiple gate lines, multiple data lines, a source driving circuit, and a gate driving circuit; wherein the source driving circuit is coupled to the multiple data lines; and the gate driving circuit is coupled to the multiple gate lines.

[0051] The timing controller is coupled to the source drive circuit and the gate drive circuit;

[0052] The timing controller is configured to input a first gate drive signal to the gate drive circuit and a first source drive signal to the source drive circuit during a data refresh phase of at least one of a plurality of consecutive display frames; and to input a second gate drive signal to the gate drive circuit and a second source drive signal to the source drive circuit during a blank time phase of at least one of the display frames.

[0053] The gate driving circuit is configured to apply a gate enable voltage to the gate lines in the display panel according to the received first gate driving signal; and to apply a gate disable voltage to the gate lines in the display panel according to the received second gate driving signal.

[0054] The source drive circuit is configured to apply a data voltage of the image to be displayed to each data line according to the first source drive signal received, so that each sub-pixel inputs a corresponding data voltage; and to apply a compensation voltage to each of the data lines according to the second source drive signal received. Attached Figure Description

[0055] Figure 1a This is a schematic diagram of the structure of the display panel in an embodiment of this disclosure;

[0056] Figure 1b This is a schematic diagram of the common electrode voltage and data voltage in an embodiment of this disclosure;

[0057] Figure 2 This is a signal timing diagram from a relevant disclosed embodiment;

[0058] Figure 3 This is a flowchart of the driving method for the display panel in the embodiments of this disclosure;

[0059] Figure 4a These are some schematic diagrams illustrating the polarity of each sub-pixel in the display panel corresponding to the previous display frame in two adjacent display frames in this embodiment of the present disclosure;

[0060] Figure 4b These are some schematic diagrams illustrating the polarity of each sub-pixel in the display panel corresponding to the next display frame in two adjacent display frames in this embodiment of the present disclosure;

[0061] Figure 4c This is another schematic diagram showing the polarity of each sub-pixel in the display panel corresponding to the previous display frame in two adjacent display frames in this embodiment of the present disclosure;

[0062] Figure 4d This is another schematic diagram showing the polarity of each sub-pixel in the display panel corresponding to the next display frame in two adjacent display frames in this embodiment of the present disclosure;

[0063] Figure 5 These are some signal timing diagrams from embodiments of this disclosure;

[0064] Figure 6 Here are some other signal timing diagrams in the embodiments of this disclosure;

[0065] Figure 7 These are some more signal timing diagrams in the embodiments of this disclosure;

[0066] Figure 8 These are some more signal timing diagrams in the embodiments of this disclosure;

[0067] Figure 9 These are some more signal timing diagrams in the embodiments of this disclosure;

[0068] Figure 10 These are some more signal timing diagrams in the embodiments of this disclosure;

[0069] Figure 11 These are some more signal timing diagrams in the embodiments of this disclosure;

[0070] Figure 12 These are some more signal timing diagrams in the embodiments of this disclosure;

[0071] Figure 13 These are some structural schematic diagrams of the display device in the embodiments of this disclosure. Detailed Implementation

[0072] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0073] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0074] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0075] Current monitors typically operate at a frequency of 60Hz, meaning the screen refreshes 60 times per second, resulting in a smooth, dynamic visual experience. However, in some applications, to conserve power, the monitor needs to reduce its frequency, for example, from 60Hz to 30Hz. In other scenarios, such as playing high-frequency games, the monitor's frequency needs to be increased, for example, from 60Hz to 90Hz or 120Hz, to achieve even smoother visuals. Therefore, to suit different scenarios, monitors need to adjust their display frequency, i.e., perform dynamic frame rate display.

[0076] See Figure 1a The display may include multiple pixels arranged in an array, multiple grid lines (e.g., GA1, GA2, GA3, GA4), and multiple data lines (e.g., DA1, DA2, DA3). Each pixel includes multiple sub-pixels. For example, a pixel may include red, green, and blue sub-pixels, allowing for color mixing to achieve a color display. Alternatively, a pixel may include red, green, blue, and white sub-pixels, also allowing for color mixing. Of course, in practical applications, the emission color of the sub-pixels within a pixel can be designed and determined according to the actual application environment, and is not limited here.

[0077] See Figure 1a and Figure 2Each sub-pixel includes a transistor 01 and a pixel electrode 02. One row of sub-pixels corresponds to one gate line, and one column of sub-pixels corresponds to one data line. The gate of transistor 01 is electrically connected to the corresponding gate line, the source of transistor 01 is electrically connected to the corresponding data line, and the drain of transistor 01 is electrically connected to the pixel electrode 02. It should be noted that the pixel array structure of this invention can also be a dual-gate structure, that is, two gate lines are set between two adjacent rows of pixels. This arrangement can reduce the number of data lines by half, meaning that some data lines between adjacent columns of pixels are included, while others are not. The specific pixel arrangement structure and the arrangement of data lines and scan lines are not limited. Furthermore, a display frame F0 of the display can include a data refresh phase TS and a blanking time phase TB. During the data refresh phase TS, signal ga1 is applied to gate line GA1, signal ga2 to gate line GA2, signal ga3 to gate line GA3, and signal ga4 to gate line GA4. When a gate enable voltage (e.g., the voltage corresponding to a high level) appears in signals ga1 to ga4, the corresponding transistor 010 can be turned on. Furthermore, when a gate enable voltage appears in signal ga1, all transistors 01 in the first row of sub-pixels can be turned on, applying a corresponding data voltage da1 to data line DA1, a corresponding data voltage da2 to data line DA2, and a corresponding data voltage da3 to data line DA3, so that the pixel electrode 02 in the first row of sub-pixels receives the corresponding data voltage. When a gate enable voltage appears in signal ga2, all transistors 01 in the second row of sub-pixels can be turned on, applying a corresponding data voltage da1 to data line DA1, a corresponding data voltage da2 to data line DA2, and a corresponding data voltage da3 to data line DA3, so that the pixel electrode 02 in the second row of sub-pixels receives the corresponding data voltage. When the gate turn-on voltage appears in signal ga3, all transistors 01 in the third row of sub-pixels can be turned on, applying a corresponding data voltage da1 to data line DA1, a corresponding data voltage da2 to data line DA2, and a corresponding data voltage da3 to data line DA3, so that the pixel electrode 02 in the third row of sub-pixels receives the corresponding data voltage. When the gate turn-on voltage appears in signal ga4, all transistors 01 in the fourth row of sub-pixels can be turned on, applying a corresponding data voltage da1 to data line DA1, a corresponding data voltage da2 to data line DA2, and a corresponding data voltage da3 to data line DA3, so that the pixel electrode 02 in the fourth row of sub-pixels receives the corresponding data voltage. The remaining rows follow the same principle and will not be elaborated further here.

[0078] See Figure 1a and Figure 2During the Blanking Time (TB) phase, signals ga1 to ga4 are all at a low level, and transistor 01 in each sub-pixel is in the off state. Furthermore, data lines DA1 to DA3 can be unloaded and are all in a floating state.

[0079] When the display frequency of a monitor changes from a high frequency to a low frequency, if the monitor displays the same image, the brightness of the image displayed at the low frequency will be higher than that displayed at the high frequency. This is because the charging rate during the data refresh phase at the low frequency is higher than that at the high frequency. Although there is leakage current in the transistors of the sub-pixels during the blanking time phase, in this case, the leakage current accounts for a smaller proportion compared to the charging rate. To maintain stable brightness when the monitor switches between different frequencies, avoid display abnormalities caused by frequency switching, improve display quality, and enhance the viewing experience, this disclosure provides a driving method for a display panel that can improve the problem of increased display brightness when the display frequency changes from a high frequency to a low frequency, maintain stable brightness, and improve display quality and viewing experience.

[0080] In the display panel driving method provided in this disclosure embodiment, the display panel operates in multiple consecutive display frames, each display frame including a data refresh phase and a blank time phase. By applying a gate-on voltage to the gate lines in the display panel and applying a data voltage of the image to be displayed to each data line during the data refresh phase of at least one of the multiple consecutive display frames, each sub-pixel receives a corresponding data voltage, thereby achieving the display of one display frame. Furthermore, during the blank time phase of at least one display frame, a gate-off voltage is applied to the gate lines in the display panel and a compensation voltage is applied to each data line. This can improve the problem of increased brightness in the low-frequency display compared to the high-frequency display when the display frequency switches from high to low, maintaining stable brightness and improving display quality and viewing experience.

[0081] In this embodiment of the disclosure, the display frame in which a compensation voltage is applied to the data line during the blank time phase is defined as the set display frame. The driving method for the display panel provided in this embodiment of the disclosure, such as... Figure 3 As shown, it may include the following steps:

[0082] S100: During the data refresh phase of the set display frame, a gate turn-on voltage is applied to the gate lines in the display panel, and a data voltage of the image to be displayed is applied to each data line so that each sub-pixel inputs the corresponding data voltage.

[0083] S200. During the blank time period of the set display frame, a gate shutdown voltage is applied to the gate lines in the display panel, and a compensation voltage is applied to each data line.

[0084] It should be noted that the display panel in this embodiment can be a liquid crystal display panel. In this embodiment, a set display frame is designed within a series of consecutive display frames. This set display frame includes a data refresh phase and a blank time phase. During the data refresh phase, a gate enable voltage is applied to the gate lines in the display panel, and the data voltage of the image to be displayed is applied to each data line, so that each sub-pixel inputs the corresponding data voltage, thereby realizing the display of one display frame. During the blank time phase, a gate disable voltage is applied to the gate lines in the display panel to control the transistors in each sub-pixel to be in the off state. Furthermore, a compensation voltage is applied to each data line. When the data voltage in the sub-pixel connected to the data line is greater than the common electrode voltage, the compensation voltage applied to the data line is less than the data voltage in the sub-pixel connected to the data line. Figure 1a and Figure 1b As shown, Vda1-1 to Vda1-4 represent the data voltages in the first to fourth rows of sub-pixels in the first column of sub-pixels, respectively. Vdc1 represents the compensation voltage applied to the data line DA1 connected to the first column of sub-pixels. If Vda1-1 to Vda1-4 are all greater than the common electrode voltage Vcom, and Vdc1 is less than Vda1-1 to Vda1-4, due to leakage current in the transistors within the sub-pixels, the leakage current flows from the sub-pixel to the data line DA1, thereby reducing the voltages of Vda1-1 to Vda1-4. For example, Vda1-1 is reduced to Vda1-1'. This reduces the voltage difference ΔV1 between Vda1-1 and Vcom to ΔV1'. Since the brightness of a sub-pixel is related to the voltage difference between the data voltage and the common electrode voltage within the sub-pixel, reducing the voltage difference reduces the brightness of the sub-pixel; therefore, the brightness of the first column of sub-pixels can be reduced.

[0085] Furthermore, when the data voltage in the sub-pixel connected by the data line is lower than the common electrode voltage, the compensation voltage applied to the data line is greater than the data voltage in the sub-pixel connected by the data line. Combined with... Figure 1a and Figure 1bAs shown, Vda2-1 to Vda2-4 represent the data voltages in the first to fourth rows of sub-pixels in the second column of sub-pixels, respectively. Vdc2 represents the compensation voltage applied to the data line DA2 connected to the second column of sub-pixels. If Vda2-1 to Vda2-4 are all less than the common electrode voltage Vcom, and Vdc2 is greater than Vda1-1 to Vda1-4, due to leakage current in the transistors within the sub-pixels, the leakage current flows from the data line DA2 to the sub-pixels, thereby increasing the voltages of Vda1-1 to Vda1-4. For example, Vda2-1 increases to Vda2-1'. This reduces the voltage difference ΔV2 between Vda2-1 and Vcom to ΔV2'. Since the brightness of a sub-pixel is related to the voltage difference between the data voltage in the sub-pixel and the common electrode voltage, a decrease in the voltage difference reduces the brightness of the sub-pixel; therefore, the brightness of the second column of sub-pixels can be reduced.

[0086] The same principle applies to the rest, thus reducing the brightness of sub-pixels. In this way, when the display frequency changes from high to low, by applying a compensation voltage to the data lines, the brightness of the display at the low frequency can be reduced, thereby keeping the brightness of the display at both high and low frequencies as stable as possible, improving display quality and viewing experience.

[0087] It should be noted that the display panel in this embodiment can be a liquid crystal display panel. Exemplarily, when the data voltage in the pixel electrode of a sub-pixel is greater than the common electrode voltage, the polarity of the sub-pixel can be positive. When the data voltage in the pixel electrode of a sub-pixel is less than the common electrode voltage, the polarity of the sub-pixel can be negative. For example, in practical applications, the common electrode voltage on the common electrode can be 8V. Taking a sub-pixel as an example, if a voltage of 8V to 12V is applied to the pixel electrode of the sub-pixel, the liquid crystal molecules at that sub-pixel can be made positive. For a grayscale level of 0 to 255, when a 12V voltage is applied to the pixel electrode, the sub-pixel corresponds to a brightness of +255 grayscale. If a voltage of 4V to 8V is applied to the pixel electrode of the sub-pixel, the liquid crystal molecules at that sub-pixel can be made negative. For a grayscale level of 0 to 255, when a 4V voltage is applied to the pixel electrode, the sub-pixel corresponds to a brightness of -255 grayscale.

[0088] To achieve better display effects, column inversion or frame inversion methods are often used to control liquid crystal molecules, improving their display performance. In practical applications, the inversion of liquid crystal molecules is driven by an electric field, causing their polarity to reverse. In this embodiment of the disclosure, to improve the performance of the liquid crystal, the display panel can employ a column inversion method. For example, Figure 4a and Figure 4b This illustrates the polarity of subpixels in two adjacent display frames when the display panel uses a column-reversed method. Among them, Figure 4aThis illustrates the polarity of each sub-pixel in the display panel corresponding to the previous display frame in two adjacent display frames. Figure 4b This diagram illustrates the polarity of each sub-pixel in the display panel corresponding to the next display frame in two adjacent display frames. "+" indicates a positive polarity, and "-" indicates a negative polarity. For example, positive and negative sub-pixel columns alternate. Furthermore, for the same sub-pixel column, if it was positive in the previous display frame, it will be negative in the next display frame. Conversely, if it was negative in the previous display frame, it will be positive in the next display frame.

[0089] In this embodiment of the disclosure, in order to improve the performance of the liquid crystal while reducing power consumption, the display panel can employ a frame inversion method. For example, Figure 4c and Figure 4d This illustrates the polarity of subpixels in two adjacent display frames when the display panel uses a frame inversion method. Among them, Figure 4c This illustrates the polarity of each sub-pixel in the display panel corresponding to the previous display frame in two adjacent display frames. Figure 4d This illustrates the polarity of each sub-pixel in the display panel corresponding to the next display frame in two adjacent display frames. "+" indicates a positive polarity, and "-" indicates a negative polarity. For example, in the previous display frame, all sub-pixel columns were positive. In the next display frame, all sub-pixel columns are negative.

[0090] The following explanation uses the example of a display panel using a column reversal method.

[0091] In this embodiment of the disclosure, the compensation voltage may include a first sub-compensation voltage, and for each data line, the polarity of the first sub-compensation voltage applied to the data line is opposite to the polarity of the sub-pixel to which the data line is connected. For example, as Figure 4aAs shown, the first sub-pixel column corresponds to positive polarity. Therefore, during the idle time phase, the first sub-compensation voltage applied to the data line corresponding to the first sub-pixel column has a negative polarity; for example, a voltage selected from 4V to 8V can be applied to this data line. The second sub-pixel column corresponds to negative polarity. Therefore, during the idle time phase, the first sub-compensation voltage applied to the data line corresponding to the second sub-pixel column has a positive polarity; for example, a voltage selected from 8V to 12V can be applied to this data line. The third sub-pixel column corresponds to positive polarity. Therefore, during the idle time phase, the first sub-compensation voltage applied to the data line corresponding to the third sub-pixel column has a negative polarity; for example, a voltage selected from 4V to 8V can be applied to this data line. The fourth sub-pixel column corresponds to negative polarity. Therefore, during the idle time phase, the first sub-compensation voltage applied to the data line corresponding to the fourth sub-pixel column has a positive polarity; for example, a voltage selected from 8V to 12V can be applied to this data line.

[0092] For example, such as Figure 4b As shown, the first sub-pixel column corresponds to negative polarity. Therefore, during the idle time phase, the first sub-compensation voltage applied to the data line corresponding to the first sub-pixel column has a positive polarity; for example, a voltage selected from 8V to 12V can be applied to this data line. The second sub-pixel column corresponds to positive polarity, so during the idle time phase, the first sub-compensation voltage applied to the data line corresponding to the second sub-pixel column has a negative polarity; for example, a voltage selected from 4V to 8V can be applied to this data line. The third sub-pixel column corresponds to negative polarity, so during the idle time phase, the first sub-compensation voltage applied to the data line corresponding to the third sub-pixel column has a positive polarity; for example, a voltage selected from 8V to 12V can be applied to this data line. The fourth sub-pixel column corresponds to positive polarity, so during the idle time phase, the first sub-compensation voltage applied to the data line corresponding to the fourth sub-pixel column has a negative polarity; for example, a voltage selected from 4V to 8V can be applied to this data line.

[0093] In this embodiment of the disclosure, in two adjacent setting display frames, for the same data line, there is a first difference between the first sub-compensation voltage and the common electrode voltage applied to the data line in the previous setting display frame, and a second difference between the first sub-compensation voltage and the common electrode voltage applied to the data line in the next setting display frame. The absolute value of the first difference can be made equal to the absolute value of the second difference. For example, as... Figure 5As shown, in display frame F1, there is a first difference ΔVdc1 between the first sub-compensation voltage Vdc11-1 applied to the data line and the common electrode voltage Vcom. In display frame F2, there is a second difference ΔVdc2 between the first sub-compensation voltage Vdc11-2 applied to the data line and the common electrode voltage Vcom. |ΔVdc1|=|ΔVdc2|, which reduces the computational load for determining the first sub-compensation voltage and reduces power consumption.

[0094] In embodiments of this disclosure, the compensation voltage can be fully applied during the blank time phase of at least one display frame. For example, such as Figure 5 As shown, the first sub-compensation voltage can be applied to each data line throughout the entire blank time phase TB in the F1 display frame. The first sub-compensation voltage is also applied to each data line throughout the entire blank time phase TB in the F2 display frame.

[0095] In this embodiment, each of a plurality of consecutive display frames can be set as a set display frame. Specifically, during the data refresh phase of each of the plurality of consecutive display frames, a gate enable voltage is applied to the gate lines in the display panel, and a data voltage of the image to be displayed is applied to each data line, so that each sub-pixel inputs a corresponding data voltage. Furthermore, during the blank time phase of each of the plurality of consecutive display frames, a gate disable voltage is applied to the gate lines in the display panel, and a first sub-compensation voltage is applied to each data line. This allows for compensation for each display frame, thereby maintaining stable brightness.

[0096] In this embodiment, the grayscale corresponding to the compensation voltage applied to each data line can be the same. This reduces the computational burden in determining the grayscale of each compensation voltage, thus lowering power consumption. For example, the grayscale corresponding to the first sub-compensation voltage applied to each data line can be the same. This reduces the computational burden in determining the first sub-compensation voltage in different display frames, further reducing power consumption. For instance, the grayscale corresponding to the first sub-compensation voltage applied to each data line is grayscale 127. Figure 4aAs shown, the first sub-pixel column corresponds to positive polarity. Therefore, the first sub-compensation voltage applied to the data line corresponding to the first sub-pixel column has a negative polarity, and a voltage corresponding to 127 gray levels is selected from 4V to 8V and applied to this data line. The second sub-pixel column corresponds to negative polarity. Therefore, the first sub-compensation voltage applied to the data line corresponding to the second sub-pixel column has a positive polarity, and a voltage corresponding to 127 gray levels is selected from 8V to 12V and applied to this data line. The third sub-pixel column corresponds to positive polarity. Therefore, the first sub-compensation voltage applied to the data line corresponding to the third sub-pixel column has a negative polarity, and a voltage corresponding to 127 gray levels is selected from 4V to 8V and applied to this data line. The fourth sub-pixel column corresponds to negative polarity. Therefore, the compensation voltage applied to the data line corresponding to the fourth sub-pixel column has a positive polarity, and a voltage corresponding to 127 gray levels is selected from 8V to 12V and applied to this data line.

[0097] like Figure 4b As shown, the first sub-pixel column corresponds to negative polarity. Therefore, the first sub-compensation voltage applied to the data line corresponding to the first sub-pixel column can be of positive polarity, and a voltage corresponding to 127 gray levels can be selected from 8V to 12V and applied to this data line. The second sub-pixel column corresponds to positive polarity. Therefore, the first sub-compensation voltage applied to the data line corresponding to the second sub-pixel column can be of negative polarity, and a voltage corresponding to 127 gray levels can be selected from 4V to 8V and applied to this data line. The third sub-pixel column corresponds to negative polarity. Therefore, the first sub-compensation voltage applied to the data line corresponding to the third sub-pixel column can be of positive polarity, and a voltage corresponding to 127 gray levels can be selected from 8V to 12V and applied to this data line. The fourth sub-pixel column corresponds to positive polarity. Therefore, the first sub-compensation voltage applied to the data line corresponding to the fourth sub-pixel column can be of negative polarity, and a voltage corresponding to 127 gray levels can be selected from 4V to 8V and applied to this data line.

[0098] In this embodiment, the compensation voltage can be any gray level. For example, the first sub-compensation voltage can be any gray level. For instance, the gray level corresponding to the first sub-compensation voltage applied to each data line can be selected from gray levels 0 to 255, such as gray level 127. Alternatively, it could be gray level 200. Here, "any gray level" refers to applying the same gray level voltage to the sub-pixels of the display panel that require compensation. This compensation method is simple, requires no additional compensation modules or operations, and saves power. In practical applications, the gray level can be selected according to the needs of the actual application, and is not limited here.

[0099] In the embodiments of the present disclosure, for each data line, the gray level corresponding to the compensation voltage loaded on the data line is the same as the gray level corresponding to one of the data voltages in the sub-pixels connected to the data line. For example, for each data line, the gray level corresponding to the first sub-compensation voltage loaded on the data line is the same as the gray level corresponding to one of the data voltages in the sub-pixels connected to the data line. For example, the gray level corresponding to the first sub-compensation voltage loaded on the data line corresponding to the first sub-pixel column may be the same as the gray level corresponding to the data voltage in the first row of sub-pixels in the first sub-pixel column. Or the gray level corresponding to the first sub-compensation voltage loaded on the data line corresponding to the first sub-pixel column may be the same as the gray level corresponding to the data voltage in the first row of sub-pixels in the second sub-pixel column. Or the gray level corresponding to the first sub-compensation voltage loaded on the data line corresponding to the first sub-pixel column may be the same as the gray level corresponding to the data voltage in the last row of sub-pixels in the first sub-pixel column.

[0100] In the embodiments of the present disclosure, during the blank time period of the display frame, the first compensation voltage may also be partially loaded. For example, it can be made such that the blank time period has at least one compensation stage, and the first sub-compensation voltage is loaded on the data line during the compensation stage. Exemplarily, as Figure 6 shown, the blank time period of the display frame may have one compensation stage BC. Or, the blank time period of the display frame may have multiple compensation stages, for example, including 3 compensation stages. Of course, in practical applications, the number of compensation stages that the blank time period of the display frame may have can be set and determined according to the actual application requirements, and is not limited herein.

[0101] In the embodiments of the present disclosure, when the blank time period of the display frame has multiple compensation stages, the time interval between every two adjacent compensation stages is the same. This can uniformly load the compensation voltage on the data line during the blank time period.

[0102] In the embodiments of the present disclosure, the duration of the compensation stage satisfies the relationship: 0 < tc < 1 / 2tb; where tc represents the duration of the compensation stage, and tb represents the duration of the blank time period. This can make only a part of the time in the blank time period be used as the compensation stage, thereby avoiding the voltage loaded on the data line flowing back into the sub-pixels due to the leakage of the application transistor and affecting the brightness of the sub-pixels.

[0103] In the embodiments of the present disclosure, the boundary of the compensation stage may coincide with the boundary of the data refresh stage. Or, the boundary of the compensation stage and the boundary of the data refresh stage may be separated by a certain time interval.

[0104] Next, in combination with Figure 1a and Figures 4a to 5The driving method for a display panel provided in this embodiment will be described. Each of a plurality of consecutive display frames is a set display frame. Figure 4a Corresponding display frame F1, Figure 4b The corresponding display frame is F2. Furthermore, display frames F1 and F2 are two adjacent display frames in a series of consecutive display frames.

[0105] Within display frame F1, during the data refresh phase TS, when a gate enable voltage appears on signal ga1, all transistors 01 in the first row of sub-pixels can be turned on, applying a corresponding data voltage da1 to data line DA1, a corresponding data voltage da2 to data line DA2, and a corresponding data voltage da3 to data line DA3, so that the pixel electrodes 02 in the first row of sub-pixels input the corresponding data voltage. When a gate enable voltage appears on signal ga2, all transistors 01 in the second row of sub-pixels can be turned on, applying a corresponding data voltage da1 to data line DA1, a corresponding data voltage da2 to data line DA2, and a corresponding data voltage da3 to data line DA3, so that the pixel electrodes 02 in the second row of sub-pixels input the corresponding data voltage. When a gate enable voltage appears on signal ga3, all transistors 01 in the third row of sub-pixels can be turned on, applying a corresponding data voltage da1 to data line DA1, a corresponding data voltage da2 to data line DA2, and a corresponding data voltage da3 to data line DA3, so that the pixel electrodes 02 in the third row of sub-pixels input the corresponding data voltage. When the gate turn-on voltage appears in signal ga4, transistor 01 in the fourth row of sub-pixels can be turned on, applying a corresponding data voltage da1 to data line DA1, a corresponding data voltage da2 to data line DA2, and a corresponding data voltage da3 to data line DA3, so that the pixel electrode 02 in the fourth row of sub-pixels receives the corresponding data voltage. The remaining rows follow the same principle, which will not be elaborated here.

[0106] During the blank time phase TB, a gate shutdown voltage is simultaneously applied to the gate lines in the display panel to control the transistor O1 in each sub-pixel to be in the off state. A voltage corresponding to 127 gray levels is selected from 4V to 8V as the first sub-compensation voltage for the corresponding negative polarity and applied to the data line corresponding to the first sub-pixel column. A voltage corresponding to 127 gray levels is selected from 8V to 12V as the first sub-compensation voltage for the corresponding positive polarity and applied to the data line corresponding to the second sub-pixel column. A voltage corresponding to 127 gray levels is selected from 4V to 8V as the first sub-compensation voltage for the corresponding negative polarity and applied to the data line corresponding to the third sub-pixel column. A voltage corresponding to 127 gray levels is selected from 8V to 12V as the first sub-compensation voltage for the corresponding positive polarity and applied to the data line corresponding to the fourth sub-pixel column.

[0107] Within display frame F2, during the data refresh phase TS, when a gate enable voltage appears on signal ga1, all transistors 01 in the first row of sub-pixels can be turned on, applying a corresponding data voltage da1 to data line DA1, a corresponding data voltage da2 to data line DA2, and a corresponding data voltage da3 to data line DA3, so that the pixel electrodes 02 in the first row of sub-pixels input the corresponding data voltage. When a gate enable voltage appears on signal ga2, all transistors 01 in the second row of sub-pixels can be turned on, applying a corresponding data voltage da1 to data line DA1, a corresponding data voltage da2 to data line DA2, and a corresponding data voltage da3 to data line DA3, so that the pixel electrodes 02 in the second row of sub-pixels input the corresponding data voltage. When a gate enable voltage appears on signal ga3, all transistors 01 in the third row of sub-pixels can be turned on, applying a corresponding data voltage da1 to data line DA1, a corresponding data voltage da2 to data line DA2, and a corresponding data voltage da3 to data line DA3, so that the pixel electrodes 02 in the third row of sub-pixels input the corresponding data voltage. When the gate turn-on voltage appears in signal ga4, transistor 01 in the fourth row of sub-pixels can be turned on, applying a corresponding data voltage da1 to data line DA1, a corresponding data voltage da2 to data line DA2, and a corresponding data voltage da3 to data line DA3, so that the pixel electrode 02 in the fourth row of sub-pixels receives the corresponding data voltage. The remaining rows follow the same principle, which will not be elaborated here.

[0108] During the blank time phase TB, a gate shutdown voltage is simultaneously applied to the gate lines in the display panel to control the transistor O1 in each sub-pixel to be in the off state. A voltage corresponding to 127 gray levels is selected from 8V to 12V as the first sub-compensation voltage for the corresponding positive polarity and applied to the data line corresponding to the first sub-pixel column. A voltage corresponding to 127 gray levels is selected from 4V to 8V as the first sub-compensation voltage for the corresponding negative polarity and applied to the data line corresponding to the second sub-pixel column. A voltage corresponding to 127 gray levels is selected from 8V to 12V as the first sub-compensation voltage for the corresponding positive polarity and applied to the data line corresponding to the third sub-pixel column. A voltage corresponding to 127 gray levels is selected from 4V to 8V as the first sub-compensation voltage for the corresponding negative polarity and applied to the data line corresponding to the fourth sub-pixel column.

[0109] The same applies to the other display frames, which will not be elaborated upon here.

[0110] This disclosure provides other driving methods for display panels, which are variations of the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0111] In this embodiment, the compensation voltage may further include a transition compensation voltage that occurs before the first sub-compensation voltage. Furthermore, when the data voltage in the sub-pixel connected to the data line is greater than the common electrode voltage, the transition compensation voltage applied to the data line is less than the data voltage in the sub-pixel connected to the data line. And, when the data voltage in the sub-pixel connected to the data line is less than the common electrode voltage, the transition compensation voltage applied to the data line is greater than the data voltage in the sub-pixel connected to the data line.

[0112] In this embodiment of the disclosure, for each data line, the polarity of the transition compensation voltage applied to the data line is the same as the polarity of the sub-pixel connected to the data line. For example, combined with Figure 4a and Figure 7 As shown, in display frame F1, the first sub-pixel column in the data refresh phase TS corresponds to positive polarity. Therefore, during the blank time phase, TB can first apply a transition compensation voltage Vdc21-1 corresponding to the positive polarity to the data line corresponding to the first sub-pixel column. For example, a voltage selected from 8V to 12V can be applied to this data line. Then, a first sub-compensation voltage Vdc11-1 corresponding to the negative polarity can be applied to this data line. For example, a voltage selected from 4V to 8V can be applied to this data line. Similarly, in the data refresh phase TS, the second sub-pixel column corresponds to negative polarity. Therefore, during the blank time phase, TB can first apply a transition compensation voltage corresponding to the negative polarity to the data line corresponding to the second sub-pixel column. For example, a voltage selected from 4V to 8V can be applied to this data line. Then, a first sub-compensation voltage corresponding to the positive polarity can be applied to this data line. For example, a voltage selected from 8V to 12V can be applied to this data line. The transition compensation voltage and first sub-compensation voltage applied to the data lines corresponding to the third sub-pixel column are in the same manner as those applied to the data lines corresponding to the first sub-pixel column, and will not be described further here. The transition compensation voltage and first sub-compensation voltage applied to the data lines corresponding to the fourth sub-pixel column are in the same manner as those applied to the data lines corresponding to the second sub-pixel column, and will not be described further here.

[0113] For example, combining Figure 4a and Figure 7As shown, in display frame F2, the first sub-pixel column in the data refresh phase TS corresponds to negative polarity. Therefore, during the blank time phase, TB can first apply a transition compensation voltage Vdc21-2 of negative polarity to the data line corresponding to the first sub-pixel column. For example, a voltage selected from 4V to 8V can be applied to this data line. Then, a first sub-compensation voltage Vdc11-2 of positive polarity is applied to the data line corresponding to the first sub-pixel column. For example, a voltage selected from 8V to 12V can be applied to this data line. Similarly, in the data refresh phase TS, the second sub-pixel column corresponds to positive polarity. Therefore, during the blank time phase, TB can first apply a transition compensation voltage of positive polarity to the data line corresponding to the second sub-pixel column. For example, a voltage selected from 8V to 12V can be applied to this data line. Then, a first sub-compensation voltage of negative polarity is applied to the data line corresponding to the second sub-pixel column. For example, a voltage selected from 4V to 8V can be applied to this data line. The transition compensation voltage and first sub-compensation voltage applied to the data lines corresponding to the third sub-pixel column are in the same manner as those applied to the data lines corresponding to the first sub-pixel column, and will not be described further here. The transition compensation voltage and first sub-compensation voltage applied to the data lines corresponding to the fourth sub-pixel column are in the same manner as those applied to the data lines corresponding to the second sub-pixel column, and will not be described further here.

[0114] This disclosure provides further driving methods for display panels, which are variations of the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0115] In this embodiment of the disclosure, the gray level corresponding to the compensation voltage can also be determined using the following formula;

[0116] VS11 = (VA12 + VA12) / 2;

[0117] Wherein, VS11 represents the gray level corresponding to the compensation voltage, VA11 represents the maximum gray level in a display frame selected from multiple consecutive display frames, VA12 represents the minimum gray level in a display frame selected from multiple consecutive display frames, and VA11+VA12 is an even number.

[0118] For example, VS11 can represent the gray level corresponding to the first sub-voltage in the compensation voltage, so the gray level of the first sub-compensation voltage can be determined by VS11 = (VA12 + VA12) / 2.

[0119] In this embodiment of the disclosure, the display frame selected from a plurality of display frames can be the previous display frame adjacent to the set display frame. For example, such as Figure 5 As shown, when VA11+VA12 is an even number, VS11 can represent the gray level corresponding to the first sub-compensation voltage in display frame F2, VA11 can represent the maximum gray level corresponding to the data voltage in the input sub-pixel in display frame F1, and VA12 can represent the minimum gray level corresponding to the data voltage in the input sub-pixel in display frame F1.

[0120] In this embodiment of the disclosure, the display frame selected from a plurality of display frames can be a set display frame. For example, such as Figure 5 As shown, when VA11+VA12 is even, VS11 can represent the gray level corresponding to the first sub-compensation voltage in display frame F1, VA11 can represent the maximum gray level corresponding to the data voltage in the input sub-pixel in display frame F1, and VA12 can represent the minimum gray level corresponding to the data voltage in the input sub-pixel in display frame F1.

[0121] It should be noted that the remaining working process of the display panel driving method corresponding to this embodiment is basically the same as the remaining working process of the display panel driving method in the above embodiments, and will not be described in detail here.

[0122] This disclosure provides further driving methods for display panels, which are variations of the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0123] In this embodiment of the disclosure, the gray level corresponding to the compensation voltage can also be determined using the following formula;

[0124] VS21 = (VA21 + VA22 + 1) / 2;

[0125] Wherein, VS21 represents the gray level corresponding to the compensation voltage, VA21 represents the maximum gray level in a display frame selected from multiple consecutive display frames, VA22 represents the minimum gray level in a display frame selected from multiple consecutive display frames, and VA21+VA22 is an odd number.

[0126] For example, VS21 can represent the gray level corresponding to the first sub-voltage in the compensation voltage, so the gray level of the first sub-compensation voltage can be determined by VS21 = (VA21 + VA22 + 1) / 2.

[0127] In this embodiment of the disclosure, the display frame selected from a plurality of display frames can be the previous display frame adjacent to the set display frame. For example, such as Figure 5As shown, when VA21+VA22 is odd, VS21 can represent the gray level corresponding to the first sub-compensation voltage in display frame F2, VA21 can represent the maximum gray level corresponding to the data voltage in the input sub-pixel in display frame F1, and VA22 can represent the minimum gray level corresponding to the data voltage in the input sub-pixel in display frame F1.

[0128] In this embodiment of the disclosure, the display frame selected from a plurality of display frames can be a set display frame. For example, such as Figure 5 As shown, when VA21+VA22 is odd, VS21 can represent the gray level corresponding to the first sub-compensation voltage in display frame F1, VA21 can represent the maximum gray level corresponding to the data voltage in the input sub-pixel in display frame F1, and VA12 can represent the minimum gray level corresponding to the data voltage in the input sub-pixel in display frame F1.

[0129] It should be noted that the remaining working process of the display panel driving method corresponding to this embodiment is basically the same as the remaining working process of the display panel driving method in the above embodiments, and will not be described in detail here.

[0130] This disclosure provides further driving methods for display panels, which are variations of the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0131] In this embodiment of the disclosure, applying a compensation voltage to each data line may include: during the blank time phase of a set display frame, selecting one display frame from multiple display frames, and for each data line, applying the grayscale voltage corresponding to the data voltage of a row of sub-pixels in the display panel of the selected display frame to that data line.

[0132] In this embodiment of the disclosure, the display frame selected from a plurality of display frames may be the previous display frame adjacent to the set display frame.

[0133] In this embodiment of the disclosure, the display frame selected from a plurality of display frames may be a set display frame.

[0134] In this embodiment, applying a compensation voltage to each data line may include: during a blank time period of a set display frame, selecting one display frame from multiple display frames, and for each data line, applying the grayscale voltage corresponding to the data voltage of the first row of sub-pixels in the display panel of the selected display frame as the first sub-compensation voltage. For example, taking a display panel with four rows of sub-pixels as an example (of course, in actual applications, the number of sub-pixel rows of the display panel is not limited to four; it can be determined according to actual conditions and is not limited here), combined with... Figures 4a to 5In display frame F2, the grayscale corresponding to the data voltage of the first row of sub-pixels in the first sub-pixel column of display frame F1 is selected as the grayscale corresponding to the first sub-compensation voltage input to the data line electrically connected to the first sub-pixel column. For example, if the data voltage of the first row of sub-pixels in the first sub-pixel column of display frame F1 corresponds to grayscale 120, then during the blank time phase in display frame F2, a voltage corresponding to grayscale 120 is applied to the data line electrically connected to the first sub-pixel column as the first sub-compensation voltage, and the polarity of this grayscale 120 voltage is opposite to the polarity corresponding to the first sub-pixel column in display frame F2. If the data voltage of the first row of sub-pixels in the second sub-pixel column of display frame F1 corresponds to grayscale 220, then during the blank time phase in display frame F2, a voltage corresponding to grayscale 220 is applied to the data line electrically connected to the second sub-pixel column as the first sub-compensation voltage, and the polarity of this grayscale 220 voltage is opposite to the polarity corresponding to the second sub-pixel column in display frame F2. The method for applying the first sub-compensation voltage to the data lines corresponding to the third sub-pixel column is the same as that for the data lines corresponding to the first sub-pixel column. The method for applying the first sub-compensation voltage to the data lines corresponding to the fourth sub-pixel column is the same as that for the data lines corresponding to the second sub-pixel column, and will not be described in detail here.

[0135] In this embodiment, applying compensation voltage to each data line may include: during a blank time period of a set display frame, selecting one display frame from multiple display frames, and for each data line, applying the grayscale voltage corresponding to the data voltage of the middle row of sub-pixels in the display panel of the selected display frame as the first sub-compensation voltage. For example, taking a display panel with four rows of sub-pixels as an example (of course, in actual applications, the number of sub-pixel rows of the display panel is not limited to four; it can be determined according to actual conditions and is not limited here), combined with... Figures 4a to 5In display frame F2, the grayscale corresponding to the data voltage input of the third row sub-pixel in display frame F1 is selected as the grayscale corresponding to the first sub-compensation voltage input to the data line electrically connected to that sub-pixel. For example, if the data voltage input of the third row, first column sub-pixel in display frame F1 corresponds to grayscale 120, then during the blank time phase in display frame F2, a voltage corresponding to grayscale 120 is applied to the data line electrically connected to the first column sub-pixel as the first sub-compensation voltage, and the polarity of this grayscale 120 voltage is opposite to the polarity corresponding to the third row, first column sub-pixel in display frame F2. If the data voltage input of the third row, second column sub-pixel in display frame F1 corresponds to grayscale 220, then during the blank time phase in display frame F2, a voltage corresponding to grayscale 220 is applied to the data line electrically connected to the second column sub-pixel as the first sub-compensation voltage, and the polarity of this grayscale 220 voltage is opposite to the polarity corresponding to the third row, second column sub-pixel in display frame F2. If the data voltage input to the third row, third column sub-pixel in display frame F1 corresponds to 150 gray levels, then during the blank time phase in display frame F2, a voltage corresponding to 150 gray levels is applied to the data line electrically connected to the third column sub-pixel as the first sub-compensation voltage, and the polarity of this 150 gray level voltage is the same as the polarity corresponding to the third row, third column sub-pixel in display frame F2. If the data voltage input to the third row, fourth column sub-pixel in display frame F1 corresponds to 60 gray levels, then during the blank time phase in display frame F2, a voltage corresponding to 60 gray levels is applied to the data line electrically connected to the fourth column sub-pixel as the first sub-compensation voltage, and the polarity of this 60 gray level voltage is opposite to the polarity corresponding to the third row, fourth column sub-pixel in display frame F2.

[0136] In this embodiment, applying compensation voltage to each data line may include: during a blank time period of a set display frame, selecting one display frame from multiple display frames, and for each data line, applying the grayscale voltage corresponding to the data voltage of the last row of sub-pixels in the display panel of the selected display frame as the first sub-compensation voltage. For example, taking a display panel with four rows of sub-pixels as an example (of course, in actual applications, the number of sub-pixel rows of the display panel is not limited to four; it can be determined according to actual conditions and is not limited here), combined with... Figures 4a to 5In display frame F2, the grayscale corresponding to the data voltage input of the fourth row sub-pixel in display frame F1 is selected as the grayscale corresponding to the compensation voltage input of the data line electrically connected to that sub-pixel. For example, if the data voltage input of the fourth row, first column sub-pixel in display frame F1 corresponds to grayscale 120, then during the blank time phase in display frame F2, a voltage corresponding to grayscale 120 is applied to the data line electrically connected to the first column sub-pixel as the first sub-compensation voltage, and the polarity of this grayscale 120 voltage is the same as the polarity corresponding to the fourth row, first column sub-pixel in display frame F2. If the data voltage input of the fourth row, second column sub-pixel in display frame F1 corresponds to grayscale 220, then during the blank time phase in display frame F2, a voltage corresponding to grayscale 220 is applied to the data line electrically connected to the second column sub-pixel as the first sub-compensation voltage, and the polarity of this grayscale 220 voltage is the same as the polarity corresponding to the fourth row, second column sub-pixel in display frame F2. If the data voltage input to the fourth row, third column sub-pixel in display frame F1 corresponds to 150 gray levels, then during the blank time phase in display frame F2, a voltage corresponding to 150 gray levels is applied to the data line electrically connected to the third column sub-pixel as the first sub-compensation voltage, and the polarity of this 150 gray level voltage is the same as the polarity of the corresponding fourth row, third column sub-pixel in display frame F2. If the data voltage input to the fourth row, fourth column sub-pixel in display frame F1 corresponds to 60 gray levels, then during the blank time phase in display frame F2, a voltage corresponding to 60 gray levels is applied to the data line electrically connected to the fourth column sub-pixel as the first sub-compensation voltage, and the polarity of this 60 gray level voltage is the same as the polarity of the corresponding fourth row, fourth column sub-pixel in display frame F2.

[0137] It should be noted that the remaining working process of the display panel driving method corresponding to this embodiment is basically the same as the remaining working process of the display panel driving method in the above embodiments, and will not be described in detail here.

[0138] This disclosure provides further driving methods for display panels, which are variations of the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0139] In this embodiment of the disclosure, applying compensation voltage to each data line may include: during a blank time period of a set display frame, selecting one display frame from multiple display frames, and sequentially applying the grayscale voltage corresponding to the data voltage on the input data line of the selected display frame to each data line. This allows for more diverse selection of compensation voltages and more precise compensation.

[0140] In this embodiment of the disclosure, the display frame selected from multiple display frames can be the previous display frame adjacent to the set display frame. For example, taking a display panel with four rows of sub-pixels as an example (of course, in actual applications, the number of sub-pixel rows of a display panel is not limited to four; it can be determined according to actual conditions and is not limited here), combined with... Figures 4a to 8 In display frame F2, the grayscale corresponding to the data voltage input of the first to fourth rows of sub-pixels in display frame F1 is selected as the grayscale corresponding to the compensation voltage input of the data line electrically connected to that sub-pixel. For example, if the data voltage input of the first row and first column of sub-pixels in display frame F1 corresponds to grayscale 120, the data voltage input of the first row and first column of sub-pixels in display frame F1 corresponds to grayscale 150, the data voltage input of the first row and first column of sub-pixels in display frame F1 corresponds to grayscale 60, and the data voltage input of the first row and first column of sub-pixels in display frame F2 corresponds to grayscale 220, then in the compensation stage of display frame F2, the first sub-compensation voltage corresponding to grayscale 120, grayscale 150, grayscale 60, and grayscale 220 is sequentially input to the data line electrically connected to the first column of sub-pixels. Furthermore, the polarity of the first sub-compensation voltage input to the data line electrically connected to the first column of sub-pixels in display frame F2 is opposite to the polarity of the data voltage input to the first column of sub-pixels in display frame F2, for example, both are positive polarities.

[0141] In display frame F1, the data voltage input to the first row, second column sub-pixel corresponds to gray level 127; the data voltage input to the second row, second column sub-pixel corresponds to gray level 159; the data voltage input to the third row, second column sub-pixel corresponds to gray level 160; and the data voltage input to the fourth row, second column sub-pixel corresponds to gray level 68. Then, in the compensation stage of display frame F2, the data lines electrically connected to the second column sub-pixels are sequentially input with the first sub-compensation voltage corresponding to gray level 127, gray level 159, gray level 160, and gray level 68. Furthermore, the polarity of the first sub-compensation voltage input to the data lines electrically connected to the second column sub-pixels in display frame F2 is opposite to the polarity of the data voltage input to the second column sub-pixels in display frame F2; for example, both are negative polarities.

[0142] In display frame F1, the data voltage input to the first row and third column of the sub-pixels corresponds to grayscale 140, the data voltage input to the second row and third column of the sub-pixels corresponds to grayscale 130, the data voltage input to the third row and third column of the sub-pixels corresponds to grayscale 40, and the data voltage input to the fourth row and third column of the sub-pixels corresponds to grayscale 175. Then, in the compensation stage of display frame F2, the data lines electrically connected to the third column of the sub-pixels are sequentially input with the first sub-compensation voltage corresponding to grayscale 140, the first sub-compensation voltage corresponding to grayscale 130, the first sub-compensation voltage corresponding to grayscale 40, and the first sub-compensation voltage corresponding to grayscale 175. Furthermore, the polarity of the first sub-compensation voltage input to the data lines electrically connected to the third column of the sub-pixels in display frame F2 is opposite to the polarity of the data voltage input to the third column of the sub-pixels in display frame F2; for example, both are positive polarity.

[0143] In display frame F1, the data voltage input to the first row, fourth column sub-pixel corresponds to gray level 177; the data voltage input to the second row, fourth column sub-pixel corresponds to gray level 129; the data voltage input to the third row, fourth column sub-pixel corresponds to gray level 80; and the data voltage input to the fourth row, fourth column sub-pixel corresponds to gray level 198. Then, in the compensation stage of display frame F2, the data lines electrically connected to the fourth column sub-pixel are sequentially input with the first sub-compensation voltage corresponding to gray level 177, gray level 129, gray level 80, and gray level 198. Furthermore, the polarity of the first sub-compensation voltage input to the data lines electrically connected to the fourth column sub-pixel in display frame F2 is opposite to the polarity of the data voltage input to the fourth column sub-pixel in display frame F2; for example, both are negative polarities.

[0144] In this embodiment of the disclosure, the display frame selected from multiple display frames can be a set display frame. For example, taking a display panel with four rows of subpixels as an example (of course, in actual applications, the number of subpixel rows on the display panel is not limited to four; it can be determined according to actual conditions, and is not limited here), combined with... Figures 4a to 8In display frame F2, the grayscale corresponding to the data voltage input of the sub-pixels in the first to fourth rows of display frame F2 is selected as the grayscale corresponding to the first sub-compensation voltage input to the data line electrically connected to that sub-pixel. For example, if the data voltage input of the first column of the first row of display frame F2 corresponds to grayscale 120, the data voltage input of the first column of the second row of display frame F2 corresponds to grayscale 150, the data voltage input of the first column of the third row of display frame F2 corresponds to grayscale 60, and the data voltage input of the first column of the fourth row of display frame F2 corresponds to grayscale 220, then in the compensation stage of display frame F2, the first sub-compensation voltage corresponding to grayscale 120, grayscale 150, grayscale 60, and grayscale 220 is sequentially input to the data line electrically connected to the first column of sub-pixels. Furthermore, the polarity of the first sub-compensation voltage input to the data line electrically connected to the first column of sub-pixels in display frame F2 is opposite to the polarity of the data voltage input to the first column of sub-pixels in display frame F2, for example, both are positive polarities.

[0145] In display frame F2, the data voltage input to the first row, second column sub-pixel corresponds to gray level 127; the data voltage input to the second row, second column sub-pixel corresponds to gray level 159; the data voltage input to the third row, second column sub-pixel corresponds to gray level 160; and the data voltage input to the fourth row, second column sub-pixel corresponds to gray level 68. During the compensation phase in display frame F2, the data lines electrically connected to the second column sub-pixels are sequentially input with the first sub-compensation voltage corresponding to gray level 127, gray level 159, gray level 160, and gray level 68. Furthermore, the polarity of the first sub-compensation voltage input to the data lines electrically connected to the second column sub-pixels in display frame F2 is opposite to the polarity of the data voltage input to the second column sub-pixels in display frame F2; for example, both are negative polarities.

[0146] In display frame F2, the data voltage input to the first row and third column sub-pixels corresponds to grayscale 140, the data voltage input to the second row and third column sub-pixels corresponds to grayscale 130, the data voltage input to the third row and third column sub-pixels corresponds to grayscale 40, and the data voltage input to the fourth row and third column sub-pixels corresponds to grayscale 175. During the compensation phase in display frame F2, the data lines electrically connected to the third column sub-pixels are sequentially input with the first sub-compensation voltage corresponding to grayscale 140, grayscale 130, grayscale 40, and grayscale 175. Furthermore, the polarity of the first sub-compensation voltage input to the data lines electrically connected to the third column sub-pixels in display frame F2 is opposite to the polarity of the data voltage input to the third column sub-pixels in display frame F2; for example, both are positive polarity.

[0147] In display frame F2, the data voltage input to the first row, fourth column sub-pixel corresponds to gray level 177; the data voltage input to the second row, fourth column sub-pixel corresponds to gray level 129; the data voltage input to the third row, fourth column sub-pixel corresponds to gray level 80; and the data voltage input to the fourth row, fourth column sub-pixel corresponds to gray level 198. During the compensation phase in display frame F2, the data lines electrically connected to the fourth column sub-pixel are sequentially input with the first sub-compensation voltage corresponding to gray level 177, gray level 129, gray level 80, and gray level 198. Furthermore, the polarity of the first sub-compensation voltage input to the data lines electrically connected to the fourth column sub-pixel in display frame F2 is opposite to the polarity of the data voltage input to the fourth column sub-pixel in display frame F2; for example, both are negative polarities.

[0148] This disclosure provides further driving methods for display panels, which are variations of the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0149] In this embodiment of the disclosure, a portion of the consecutive display frames are designated display frames. Furthermore, among the consecutive display frames, the display frames other than the designated display frames are non-designated display frames. That is, a portion of the consecutive display frames are designated display frames, and the remaining portion are non-designated display frames.

[0150] In this embodiment of the disclosure, the non-set display frame includes:

[0151] During the data refresh phase, gate enable voltages are applied to the gate lines in the display panel in a time-division manner, and the data voltage of the image to be displayed is applied to each data line when the gate enable voltage is applied to each gate line, so that each sub-pixel inputs the corresponding data voltage.

[0152] During the blanking period, a gate shutdown voltage is simultaneously applied to the gate lines in the display panel, and each data line is floated.

[0153] It should be noted that "floating" of each data line during the blank time period can mean that no voltage is applied to each data line.

[0154] In other words, the data refresh process in non-set display frames is basically the same as that in set display frames. However, no compensation phase is set during the blank time phase in non-set display frames.

[0155] In embodiments of this disclosure, at least one non-setting display frame may exist between two adjacent set display frames. For example, one non-setting display frame may exist between two adjacent set display frames. Two non-setting display frames may also exist between two adjacent set display frames. Three non-setting display frames may also exist between two adjacent set display frames. For example, Figure 9 As shown, display frames F1, F3, and F5 are the set display frames, while display frames F2 and F4 are the non-set display frames.

[0156] In embodiments of this disclosure, the number of non-defined display frames between any two adjacent defined display frames can be the same. For example, there can be one non-defined display frame between any two adjacent defined display frames. Alternatively, there can be two non-defined display frames between any two adjacent defined display frames. Or, there can be three non-defined display frames between any two adjacent defined display frames. For example, Figure 6 As shown, display frames F1, F3, and F5 are the set display frames, while display frames F2 and F4 are the non-set display frames.

[0157] This disclosure provides further driving methods for display panels, which are variations of the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0158] In this embodiment of the disclosure, the compensation voltage may include a second sub-compensation voltage; for each data line, the polarity of the second sub-compensation voltage applied on the data line is the same as the polarity of the sub-pixel connected to the data line. For example, as Figure 4a and Figure 10 As shown, the first sub-pixel column corresponds to positive polarity. Therefore, the second sub-compensation voltage Vdc31-1 applied to the data line corresponding to the first sub-pixel column can also be positive polarity, for example, a voltage selected from 8V to 12V can be applied to this data line. The second sub-pixel column corresponds to negative polarity. Therefore, the second sub-compensation voltage applied to the data line corresponding to the second sub-pixel column can also be negative polarity, for example, a voltage selected from 4V to 8V can be applied to this data line. The third sub-pixel column corresponds to positive polarity. Therefore, the second sub-compensation voltage applied to the data line corresponding to the third sub-pixel column can also be positive polarity, for example, a voltage selected from 8V to 12V can be applied to this data line. The fourth sub-pixel column corresponds to negative polarity. Therefore, the second sub-compensation voltage applied to the data line corresponding to the fourth sub-pixel column can also be negative polarity, for example, a voltage selected from 4V to 8V can be applied to this data line.

[0159] like Figure 4b and Figure 10As shown, the first sub-pixel column corresponds to negative polarity. Therefore, the second sub-compensation voltage Vdc31-2 applied to the data line corresponding to the first sub-pixel column can also be negative polarity, for example, a voltage selected from 4V to 8V can be applied to this data line. The second sub-pixel column corresponds to positive polarity. Therefore, the second sub-compensation voltage applied to the data line corresponding to the second sub-pixel column can also be positive polarity, for example, a voltage selected from 8V to 12V can be applied to this data line. The third sub-pixel column corresponds to negative polarity. Therefore, the second sub-compensation voltage applied to the data line corresponding to the third sub-pixel column can also be negative polarity, for example, a voltage selected from 4V to 8V can be applied to this data line. The fourth sub-pixel column corresponds to positive polarity. Therefore, the second sub-compensation voltage applied to the data line corresponding to the fourth sub-pixel column can also be positive polarity, for example, a voltage selected from 8V to 12V can be applied to this data line.

[0160] This disclosure provides further driving methods for display panels, which are variations of the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0161] In the embodiments disclosed herein, such as Figure 11 As shown, when the display frequency switches from a higher frequency H1 (e.g., 120Hz) to a lower frequency H2 (e.g., 60Hz, 30Hz, 48Hz), the driving method in this embodiment can be used to drive the display panel only when the display uses the lower frequency H2. For example, if the duration of the blank time phase TB of display frames F1 to F5 is shorter than the duration of the blank time phase TB of display frames F6 to F10, display frames F1 to F5 can be used as the first frame, and display frames F6 to F10 can be used as the second frame. When the display refreshes at 120Hz, the data lines are floating during the blank time phase TB of display frames F1 to F5. When the display switches from 120Hz to 48Hz and refreshes at a display frequency of 48Hz, a gate shutdown voltage is applied to the gate lines in the display panel and a compensation voltage is applied to each data line during the blank time phase TB of each display frame (e.g., display frames F6 to F10). This addresses the issue of increased brightness in low-frequency displays compared to high-frequency displays, maintaining stable brightness and improving display quality and viewing experience.

[0162] In the embodiments of this disclosure, the display can also employ various display frequencies, such as... Figure 12As shown, the display panel is driven by the driving method described in this embodiment at both higher frequencies H1 and lower frequencies H2. For example, the duration of the blank time phase TB of display frames F1 to F5 is shorter than the duration of the blank time phase TB of display frames F6 to F10. Display frames F1 to F5 can be used as the first frame, and display frames F6 to F10 can be used as the second frame. When the display refreshes at a display frequency of 120Hz, during the blank time phase of each display frame (e.g., display frames F1 to F5), a gate shutdown voltage is applied to the gate lines in the display panel, and a compensation voltage is applied to each data line. That is, display frames F1 to F5 are all refreshed at a display frequency of 120Hz, and a compensation voltage is applied to each data line. When the monitor switches from 120Hz to 48Hz and refreshes at a 48Hz display frequency, during the blank time phase of each display frame (e.g., display frames F6-F10), a gate shutdown voltage is applied to the gate lines in the display panel, and a compensation voltage is applied to each data line. That is, display frames F6-F10 all refresh at a 48Hz display frequency, and a compensation voltage is applied to each data line. In this way, when refreshing at different display frequencies, a compensation voltage can be applied to the data lines during the blank time phase, thus eliminating the need for additional compensation based on display frequency. This invention allows for unified compensation across different display frequencies, making TCON timing easier to adjust, simplifying TCON timing design, and reducing power consumption. It's important to note that in this case, the display anomalies that occur when switching from a low-frequency refresh rate to a high-frequency refresh rate are caused by leakage during the blank time phase and insufficient charging at the high refresh rate. Currently, displays tend towards higher refresh rates, such as 144Hz and 240Hz. Higher refresh rates result in lower charging rates, leading to reduced display panel brightness. When insufficient charging at high refresh rates becomes dominant, the display brightness at high refresh rates is lower than at low refresh rates. This causes brightness differences and display anomalies when switching refresh rates. To simplify TCON timing adjustment and design, this invention applies a compensation voltage with the opposite polarity to the data signal at both high and low frequencies. Since the blank time phase at high refresh rates is shorter than that at low refresh rates, even with increased compensation voltage, the display anomaly can still be resolved. Of course, this solution could also apply compensation voltage only to the display frames at low refresh rates, while maintaining a blank time phase at high refresh rates, for example, only applying a 0 grayscale voltage during this phase. In this case, the brightness at the refresh rate can be reduced to match the brightness at the high refresh rate, thus achieving good display uniformity.

[0163] This disclosure provides further driving methods for display panels, which are variations of the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0164] When the data voltage in the sub-pixel connected by the data line is greater than the common electrode voltage, the compensation voltage applied to the data line can also be greater than the data voltage in the sub-pixel connected by the data line. Conversely, when the data voltage in the sub-pixel connected by the data line is less than the common electrode voltage, the compensation voltage applied to the data line can also be less than the data voltage in the sub-pixel connected by the data line. This reduces the voltage difference between the source and drain of the transistor in the sub-pixel during the blanking time, thus reducing transistor leakage. This allows the input data voltage in the sub-pixel to remain stable when the display is continuously operating at a low frequency, thereby preventing a decrease in display brightness when the display is continuously operating at a low frequency.

[0165] This disclosure also provides a display driving circuit, wherein the display panel operates on multiple consecutive display frames, each display frame including a data refresh phase and a blank time phase; and the display driving circuit is configured to:

[0166] During the data refresh phase of at least one of a series of display frames, a gate turn-on voltage is applied to the gate lines in the display panel, and a data voltage of the image to be displayed is applied to each data line so that each sub-pixel inputs the corresponding data voltage.

[0167] During the blank time phase of at least one display frame, a gate shutdown voltage is applied to the gate lines in the display panel, and a compensation voltage is applied to each data line; wherein, when the data voltage in the sub-pixel connected to the data line is greater than the common electrode voltage, the compensation voltage applied to the data line is less than the data voltage in the sub-pixel connected to the data line; and when the data voltage in the sub-pixel connected to the data line is less than the common electrode voltage, the compensation voltage applied to the data line is greater than the data voltage in the sub-pixel connected to the data line.

[0168] It should be noted that the working principle and specific implementation method of the display driving circuit are the same as those of the driving method of the display panel in the above embodiments. Therefore, the working method of the display driving circuit can be implemented by referring to the specific implementation method of the driving method of the display panel in the above embodiments, and will not be repeated here.

[0169] This disclosure also provides a display device, such as... Figure 13 As shown, the device includes a display panel 100 and a timing controller (TCON) 200. The display panel 100 includes multiple gate lines GA1 to GA5, multiple data lines DA1 to DA6, a source drive circuit 110, and a gate drive circuit 120. The source drive circuit 110 is coupled to the multiple data lines DA1 to DA6, and the gate drive circuit 120 is coupled to the multiple gate lines GA1 to GA5.

[0170] In the embodiments disclosed herein, such as Figure 13 As shown, the timing controller 200 is coupled to the source drive circuit 110 and the gate drive circuit 120, respectively.

[0171] The timing controller 200 is configured to input a first gate drive signal to the gate drive circuit 120 and a first source drive signal to the source drive circuit 110 during the data refresh phase of at least one of a plurality of consecutive display frames. The gate drive circuit 120 is configured to apply a gate turn-on voltage to the gate lines GA1 to GA5 in the display panel 100 based on the received first gate drive signal. The source drive circuit 110 is configured to apply the data voltage of the image to be displayed to each data line DA1 to DA6 based on the received first source drive signal, thereby realizing the display of one display frame.

[0172] The timing controller 200 is configured to input a second gate drive signal to the gate drive circuit 120 and a second source drive signal to the source drive circuit 110 during a blank time phase of at least one display frame. The gate drive circuit 120 is configured to apply a gate turn-off voltage to the gate lines GA1 to GA5 in the display panel according to the received second gate drive signal. The source drive circuit 110 is configured to apply a compensation voltage to each data line DA1 to DA6 according to the received second source drive signal. Specifically, when the data voltage in the sub-pixel connected to the data line is greater than the common electrode voltage, the compensation voltage applied to the data line is less than the data voltage in the sub-pixel connected to the data line; conversely, when the data voltage in the sub-pixel connected to the data line is less than the common electrode voltage, the compensation voltage applied to the data line is greater than the data voltage in the sub-pixel connected to the data line. This improves the problem of increased display brightness when the display frequency changes from high to low frequency, maintaining stable brightness and improving display quality and viewing experience.

[0173] It should be noted that the working principle and specific implementation method of this display device are the same as those of the driving method of the display panel in the above embodiments. Therefore, the working method of this display device can be implemented by referring to the specific implementation method of the driving method of the display panel in the above embodiments, and will not be repeated here.

[0174] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0175] The display panel driving method, display driving circuit, and display device provided in this disclosure achieve the display of one display frame by time-divisionally applying gate-on voltages to the gate lines in the display panel during the data refresh phase of a set display frame in multiple consecutive display frames, and applying the data voltage of the image to be displayed to each data line when the gate-on voltage is applied to each gate line, so that each sub-pixel inputs the corresponding data voltage. Furthermore, during the blank time phase of the set display frame, gate-off voltages are simultaneously applied to the gate lines in the display panel, and compensation voltages are applied to each data line. This reduces the voltage difference between the source and drain of the transistor during the blank time phase, thereby reducing sub-pixel leakage and improving display quality and viewing experience.

[0176] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0177] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0178] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0179] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0180] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0181] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A driving method for a display panel, the display panel operating in a series of consecutive display frames, each display frame including a data refresh phase and a blank time phase; The display frame in which compensation voltage is applied to each data line during the blank time period is defined as the set display frame; A portion of the consecutive display frames are the designated display frames; The driving method for the display panel for the set display frame includes: During the data refresh phase of at least one of the set display frames in a series of set display frames, a gate turn-on voltage is applied to the gate lines in the display panel, and a data voltage of the image to be displayed is applied to each data line so that each sub-pixel inputs a corresponding data voltage. During the blank time phase of at least one of the set display frames, a gate shutdown voltage is applied to the gate lines in the display panel, and a compensation voltage is applied to each of the data lines. Wherein, when the data voltage in the sub-pixel connected by the data line is greater than the common electrode voltage, the compensation voltage applied on the data line is less than the data voltage in the sub-pixel connected by the data line; And / or, when the data voltage in the sub-pixel connected by the data line is less than the common electrode voltage, the compensation voltage applied on the data line is greater than the data voltage in the sub-pixel connected by the data line; The display panel employs either column inversion or frame inversion; the compensation voltage includes a first sub-compensation voltage; for each data line, in the set display frame, the polarity of the first sub-compensation voltage applied to the data line is opposite to the polarity of the data voltage in the sub-pixel connected to the data line; or, the compensation voltage includes a second sub-compensation voltage; for each data line, in the set display frame, the polarity of the second sub-compensation voltage applied to the data line is the same as the polarity of the data voltage in the sub-pixel connected to the data line. Of the multiple consecutive display frames, the display frames other than the set display frames are non-set display frames; The driving method for the display panel in relation to the non-set display frame includes: During the data refresh phase, a gate enable voltage is applied to the gate lines in the display panel, and a data voltage of the image to be displayed is applied to the data lines so that each sub-pixel inputs the corresponding data voltage. During the blank time period, a gate shutdown voltage is applied to the gate lines in the display panel, and each of the data lines is floated.

2. The driving method for the display panel as described in claim 1, wherein, The compensation voltage is fully applied during the blank time phase of at least one of the set display frames.

3. The driving method for the display panel as described in claim 2, wherein, The display frame in which the compensation voltage is applied to each of the data lines during the blank time period includes a first display frame and a second display frame. The first display frame corresponds to a first refresh rate, and the second display frame corresponds to a second refresh rate; and the first refresh rate is greater than the second refresh rate; The duration of the blank time phase in the first display frame is shorter than the duration of the blank time phase in the second display frame.

4. The driving method for the display panel as described in claim 2, wherein, The display frame in which the compensation voltage is applied to each of the data lines during the blank time period is defined as a setting display frame; in two adjacent setting display frames, for the same data line, there is a first difference between the first sub-compensation voltage applied to the data line and the common electrode voltage in the previous setting display frame, and a second difference between the first sub-compensation voltage applied to the data line and the common electrode voltage in the next setting display frame; The absolute value of the first difference is equal to the absolute value of the second difference.

5. The driving method for a display panel as described in claim 2, wherein, The compensation voltage also includes a transition compensation voltage that occurs before the first sub-compensation voltage; For each of the data lines, the polarity of the transition compensation voltage applied to the data line is the same as the polarity of the sub-pixel to which the data line is connected.

6. The driving method for a display panel as described in claim 5, wherein, There is at least one non-set display frame between two adjacent set display frames.

7. The driving method for a display panel as described in claim 6, wherein, The number of non-defined display frames is the same between any two adjacent defined display frames.

8. The driving method for a display panel as described in any one of claims 1-4, wherein, The grayscale corresponding to the compensation voltage applied to each of the data lines is the same.

9. The driving method for a display panel as described in claim 8, wherein, For each of the data lines, the gray level corresponding to the compensation voltage applied on the data line is the same as the gray level corresponding to a data voltage in a sub-pixel connected to the data line.

10. The driving method for a display panel as described in claim 9, wherein, The gray level corresponding to the compensation voltage is determined using the following formula; VS11 = (VA12 + VA12) / 2; Wherein, VS11 represents the gray level corresponding to the compensation voltage, VA11 represents the maximum gray level in a display frame selected from the multiple consecutive display frames, VA12 represents the minimum gray level in the display frame selected from the multiple consecutive display frames, and VA11+VA12 is an even number.

11. The driving method for a display panel as described in claim 9, wherein, The gray level corresponding to the compensation voltage is determined using the following formula; VS21 = (VA21 + VA22 + 1) / 2; Wherein, VS21 represents the gray level corresponding to the compensation voltage, VA21 represents the maximum gray level in a display frame selected from the multiple consecutive display frames, VA22 represents the minimum gray level in the display frame selected from the multiple consecutive display frames, and VA21+VA22 is an odd number.

12. The driving method for a display panel as described in claim 4, wherein, The process of applying a compensation voltage to each of the data lines includes: During the blank time phase of the set display frame, a display frame is selected from the plurality of display frames, and for each data line, the voltage of the gray level corresponding to the data voltage of a row of sub-pixels in the display panel is loaded onto the data line of the selected display frame.

13. The driving method for a display panel as described in claim 12, wherein, The process of applying a compensation voltage to each of the data lines includes: During the blank time phase of the set display frame, a display frame is selected from the plurality of display frames, and for each data line, the data voltage of the last row of sub-pixels in the display panel corresponding to the gray level of the selected display frame is loaded onto the data line.

14. The driving method for a display panel as described in claim 4, wherein, The process of applying a compensation voltage to each of the data lines includes: During the blank time phase of the set display frame, a display frame is selected from the plurality of display frames, and for each data line, the voltage of the gray level corresponding to the data voltage on the selected display frame is sequentially loaded onto the data line.

15. The driving method for a display panel as described in any one of claims 11-14, wherein, The display frame selected from the plurality of display frames is one of the previous display frame adjacent to the set display frame and the set display frame.

16. A display driving circuit for performing a driving method for a display panel as described in any one of claims 1-15, the display panel operating in a plurality of consecutive display frames, each display frame including a data refresh phase and a blank time phase; The display frame in which compensation voltage is applied to each data line during the blank time period is defined as the set display frame; A portion of the consecutive display frames are the designated display frames; The display driving circuit is configured to, for the specified display frame: During the data refresh phase of at least one of the set display frames in a series of set display frames, a gate turn-on voltage is applied to the gate lines in the display panel, and a data voltage of the image to be displayed is applied to each data line so that each sub-pixel inputs a corresponding data voltage. During the blank time phase of at least one of the set display frames, a gate shutdown voltage is applied to the gate lines in the display panel, and a compensation voltage is applied to each of the data lines. Wherein, when the data voltage in the sub-pixel connected by the data line is greater than the common electrode voltage, the compensation voltage applied on the data line is less than the data voltage in the sub-pixel connected by the data line; When the data voltage in the sub-pixel connected by the data line is less than the common electrode voltage, the compensation voltage applied on the data line is greater than the data voltage in the sub-pixel connected by the data line. The display panel employs either column inversion or frame inversion; the compensation voltage includes a first sub-compensation voltage; for each data line, in the set display frame, the polarity of the first sub-compensation voltage applied to the data line is opposite to the polarity of the data voltage in the sub-pixel connected to the data line; or, the compensation voltage includes a second sub-compensation voltage; for each data line, in the set display frame, the polarity of the second sub-compensation voltage applied to the data line is the same as the polarity of the data voltage in the sub-pixel connected to the data line. Of the multiple consecutive display frames, the display frames other than the set display frames are non-set display frames; For the non-set display frame, the display driving circuit is configured as follows: During the data refresh phase, a gate enable voltage is applied to the gate lines in the display panel, and a data voltage of the image to be displayed is applied to the data lines so that each sub-pixel inputs the corresponding data voltage. During the blank time period, a gate shutdown voltage is applied to the gate lines in the display panel, and each of the data lines is floated.

17. A display device, comprising a display panel as described in claim 16 and a timing controller; the display panel comprising a plurality of gate lines, a plurality of data lines, a source driving circuit, and a gate driving circuit; wherein, The source drive circuit is coupled to the plurality of data lines; the gate drive circuit is coupled to the plurality of gate lines; The timing controller is coupled to the source drive circuit and the gate drive circuit; The timing controller is configured to input a first gate drive signal to the gate drive circuit and a first source drive signal to the source drive circuit during the data refresh phase of at least one of a plurality of consecutive set display frames. And during the blank time phase of at least one of the display frames, a second gate drive signal is input to the gate drive circuit and a second source drive signal is input to the source drive circuit. The gate driving circuit is configured to apply a gate enable voltage to the gate lines in the display panel according to the received first gate driving signal; and to apply a gate disable voltage to the gate lines in the display panel according to the received second gate driving signal. The source drive circuit is configured to apply a data voltage of the image to be displayed to each data line according to the first source drive signal received, so that each sub-pixel inputs a corresponding data voltage; and to apply a compensation voltage to each of the data lines according to the second source drive signal received.

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