Dac layout routing method and system

Abstract

The application discloses a DAC layout wiring method and system, and the method comprises the following steps: determining DAC layout design parameters, including the number, device type and expected layout shape of each of resistance R, logic gate NAND and switch tube Tg; based on the type size of the device, a group of resistances RX, logic gates NAND <x>and the switch tube Tg <x>fabricated as a standard cell; resistance RX, logic gate NAND are performed within the standard cell <x>and the switch tube Tg <x>Connection and optimization; the standard unit is copied and arranged according to the expected layout shape, the DAC layout optimization layout and optimization are completed. The whole layout signal line is less and short, simple, clear and beautiful, and a large number of repeated connection work can be avoided, and the work efficiency is improved.< / x> < / x> < / x> < / x>

Description

Technical Field

[0001] This invention belongs to the field of DAC layout design technology, and relates to DAC layout and routing methods and systems. Background Technology

[0002] A digital-to-analog converter, also known as a D / A converter or simply DAC, is a device that converts digital signals into analog signals. Typically, an N-bit DAC requires 2... N One resistor and 2 N Each gating switch, taking a 6-bit DAC as an example, such as Figure 2 As shown, a 6-bit DAC requires 64 resistors and 64 gating switches. Its gating switch circuit structure consists of AND logic gates NAND<0:63> and switching transistors Tg<0:63>. Tg is connected to both the NAND gates and the resistors. <x>With NAND <x>The connections between RX and DAC are identical. Therefore, as the number of DAC bits increases, the number of resistors, NAND flash units, and Tg units increases exponentially, as does the number of signal lines. This makes the layout and routing of resistors, NAND flash units, and Tg units particularly important.

[0003] Conventional layout and routing methods for resistors, NAND flash memory, and Tg are as follows: Figure 3 As shown, NAND<0:63> are arranged in a rectangle in sequence, Tg<0:63> are arranged in a rectangle in sequence, and resistors R0 to R63 are arranged in a rectangle in sequence. Dashed line 1 represents Tg. <0> With NAND <0> The schematic diagram shows the connection path between R0 and R1, with dashed line 2 representing Tg. <15> With NAND <15> The diagram illustrates the connection path between R15 and T15. Because the layout area of ​​each NAND, Tg, and resistor is different, it's difficult to create an aesthetically pleasing layout by simply combining the three rectangles formed by the resistor, NAND, and Tg. Connecting Tg to both NAND and resistor requires 64 traces each, totaling 128 traces, wasting layout area and resulting in long signal path paths with high resistance. In this layout and routing method, each group of Tg, NAND, and resistor needs to be manually connected individually, leading to excessive repetitive work. As the DAC bit width increases, this layout and routing method wastes a significant amount of time.

[0004] Because DACs have high matching requirements, the order of signal lines connected using this layout and routing method is unpredictable. If any signal line is connected incorrectly, the LVS (Layout versus schematic) error will not directly point to the location of the error, so the LVS verification process will consume a lot of time. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a DAC layout and routing method and system that reduces the number and length of signal lines in the entire layout, making it simple, clear, and aesthetically pleasing, avoiding a large amount of repetitive wiring work, and improving work efficiency.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] The DAC layout and routing method is as follows: First, a set of resistors RX and logic gates NAND are arranged... <x>and switching transistor Tg <x>The standard cells are fabricated and then copied and arranged according to the expected layout shape to complete the DAC layout and routing.

[0008] The present invention further includes the following preferred embodiments:

[0009] Preferably, the method specifically includes the following steps:

[0010] Step 1: Determine the DAC layout design parameters, including the expected layout shape, the number and type of resistors R, logic gates NAND, and switching transistors Tg;

[0011] Step 2: Based on the device type and size, connect a set of resistors RX and logic gates NAND. <x>and switching transistor Tg <x>To be manufactured as a standard unit;

[0012] Step 3: Perform resistor RX and logic gate NAND within the standard cell. <x>and switching transistor Tg <x>Connections and optimizations;

[0013] Step 4: Copy and arrange the standard cells according to the expected layout shape to complete the DAC layout optimization and routing.

[0014] Preferably, in the DAC layout described in step 1, the number of resistors R, logic gates NAND, and switching transistors Tg are all equal, each being n.

[0015] Preferably, n is 64.

[0016] Preferably, in the DAC layout described in step 1, each group of resistors RX and logic gates NAND... <x>and switching transistor Tg <x>The lines connecting them are the same, and X ranges from 0 to n-1.

[0017] Preferably, in step 2, the maximum device width among the resistor R, the logic gate NAND, and the switching transistor Tg is first determined according to the device type;

[0018] Next, a set of resistors RX and logic gate NAND are connected. <x>and switching transistor Tg <x>A standard unit is made according to the maximum device width.

[0019] Preferably, in step 3, within the standard cell, the resistor RX and the logic gate NAND... <x>and switching transistor Tg <x>The three are placed in corresponding positions.

[0020] Preferably, in step 3, within the standard cell, the resistor RX and the logic gate NAND... <x>and switching transistor Tg <x>By connecting the wires on its own device, without occupying additional traces, the signal line connection length is minimized.

[0021] The DAC layout and routing system of the present invention is used to implement the above-described DAC layout and routing method.

[0022] The beneficial effects of this invention are compared with those of the prior art:

[0023] 1. This invention first fabricates a standard cell, and then completes the Tg process within the standard cell. <x>With NAND <x>The connection between RX and Tg completes the layout optimization of the standard cell. <x>With NAND <x>The layout positions of the three devices (RX, RX, and RX) correspond one-to-one, and the connections between them are handled on their own devices, without requiring additional traces, and the signal line connection length is minimized.

[0024] 2. After the standard cells are prepared, the standard cells are copied according to the desired layout shape of the layout to complete all Tg. <x>With NAND <x>Optimizing the connections and layout between RX and other components can achieve better matching results and ensure the correctness of the layout connections. Attached Figure Description

[0025] Figure 1 This is a flowchart of the DAC layout and routing method of the present invention;

[0026] Figure 2 This is a schematic diagram of a 6-bit DAC system architecture;

[0027] Figure 3 This is a schematic diagram of a conventional layout and routing method for resistors, NAND flash memory, and Tg.

[0028] Figure 4 This is a schematic diagram of the layout and routing method of the resistor, NAND and Tg of the present invention. Detailed Implementation

[0029] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention.

[0030] like Figure 1 As shown, Embodiment 1 of the present invention provides a DAC layout and routing method. In a preferred but non-limiting embodiment of the present invention, the method is as follows: First, a set of resistors RX and logic gates NAND are connected... <x>and switching transistor Tg <x>The standard cells are fabricated and then copied and arranged according to the expected layout shape to complete the DAC layout and routing.

[0031] More preferably, the method specifically includes the following steps:

[0032] Step 1: Determine the DAC layout design parameters, including the expected layout shape, the number and type of resistors R, logic gates NAND, and switching transistors Tg;

[0033] More preferably, in the DAC layout, the number of resistors R, NAND gates, and switches Tg is equal, each being n. Furthermore, each group of resistors Rx and NAND gates... <x>and switching transistor Tg <x>The lines connecting them are the same, and X ranges from 0 to n-1.

[0034] Step 2: Based on the device dimensions, connect a set of resistors RX and logic gates NAND. <x>and switching transistor Tg <x>To be manufactured as a standard unit;

[0035] More preferably, the maximum device width among the resistor R, the logic gate NAND, and the switching transistor Tg is first determined according to the model.

[0036] Next, a set of resistors RX and logic gate NAND are connected. <x>and switching transistor Tg <x>A standard unit is made according to the maximum device width.

[0037] Step 3: Perform resistor RX and logic gate NAND within the standard cell. <x>and switching transistor Tg <x>Connections and optimizations;

[0038] More preferably, within the standard cell, the resistor RX and the logic gate NAND... <x>and switching transistor Tg <x>The three components are placed in a one-to-one correspondence. The resistor RX and the logic gate NAND are also positioned correctly. <x>and switching transistor Tg <x>By connecting the wires on its own device, without occupying additional traces, the signal line connection length is minimized.

[0039] Step 4: Copy and arrange the standard cells according to the expected layout shape to obtain n sets of standard cells, and complete the connection and layout routing and optimization between Tg<0:n-1> and NAND<0:n-1> and R0~Rn-1.

[0040] The DAC layout and routing system of the present invention is used to implement the above-described DAC layout and routing method.

[0041] like Figure 4 As shown, taking n=64 as an example, the embodiment of the present invention will be described in detail below:

[0042] Because Tg <x>With NAND <x>The wiring between NAND and RX is the same, so NAND... <0> Tg <0> R0 is grouped together, and a standard unit, standcell1, is made using the widest device as the standard width. Figure 4 middle dashed box;

[0043] Complete Tg in standard cell 1. <x>With NAND <x>The connection between RX and RX also involves layout optimization. Since the three of them are placed in a one-to-one correspondence, the connection between them can be handled on their own devices without occupying additional traces, and the signal line connection length is minimized.

[0044] After creating the standard cell (standcell1), the standard cell is copied according to the expected layout shape. Standcell1 is copied to form standcell2, and standcell2 is copied to form standcell4, followed by standcell8, standcell16, standcell32, and standcell64. This completes the connection and layout optimization between Tg<0:63>, NAND<0:63>, and R0 to R63.

[0045] Because DACs have high matching requirements, they are no longer arranged in the traditional order. This layout and routing method can array standard cells (standcell1) in the desired matching order to achieve a higher matching effect and ensure the correctness of the layout wiring.

[0046] The entire layout has fewer and shorter signal lines, making it simple, clear, and aesthetically pleasing. This method avoids a lot of repetitive wiring work and improves work efficiency.

[0047] The beneficial effects of this invention are compared with those of the prior art:

[0048] 1. This invention first fabricates a standard cell, and then completes the Tg process within the standard cell. <x>With NAND <x>The connection between RX and Tg completes the layout optimization of the standard cell. <x>With NAND <x>The layout positions of the three components (RX, RX, and RX) correspond one-to-one, and the connections between them are handled on their own components, without requiring additional traces, and the signal line connection length is minimized.

[0049] 2. After the standard cells are prepared, the standard cells are copied according to the desired layout shape of the layout to complete all Tg. <x>With NAND <x>Optimizing the connections and layout between RX and other components can achieve better matching results and ensure the correctness of the layout connections.

[0050] The applicant of this invention has provided a detailed description of the embodiments of the invention in conjunction with the accompanying drawings. However, those skilled in the art should understand that the above embodiments are merely preferred embodiments of the invention. The detailed description is only intended to help readers better understand the spirit of the invention and is not intended to limit the scope of protection of the invention. On the contrary, any improvements or modifications made based on the inventive spirit of the invention should fall within the scope of protection of the invention.< / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x>

Claims

1. A DAC layout and routing method, characterized in that: The method is as follows: First, connect a set of resistors RX and logic gates NAND. <x>and switching transistor Tg <x> The process involves creating standard cells, then replicating and arranging these standard cells according to the expected layout shape to complete the DAC layout and routing. The method specifically includes the following steps:< / x> < / x> Step 1: Determine the DAC layout design parameters, including the expected layout shape, the quantity and type of resistors R, NAND gates, and switching transistors Tg; in the DAC layout, each group of resistors RX, NAND gates, and switching transistors Tg... <x>and switching transistor Tg <x> The lines connecting them are the same, and X ranges from 0 to n-1;< / x> < / x> Step 2: Based on the device type and size, connect a set of resistors RX and logic gates NAND. <x>and switching transistor Tg <x> To manufacture as a standard unit;< / x> < / x> Step 3: Perform resistor RX and logic gate NAND within the standard cell. <x>and switching transistor Tg <x>Wiring and optimization; within the standard cell, resistors RX and logic gates NAND... <x>and switching transistor Tg <x>The three are placed in corresponding positions; within the standard cell, resistors RX and logic gates NAND are... <x>and switching transistor Tg <x> By connecting the wires on its own device, without occupying additional traces, the signal line connection length is minimized.< / x> < / x> < / x> < / x> < / x> < / x> Step 4: Copy and arrange the standard cells according to the expected layout shape to complete the DAC layout optimization and routing.

2. The DAC layout and routing method according to claim 1, characterized in that: In the DAC layout described in step 1, the number of resistors R, logic gates NAND, and switching transistors Tg are all equal, each consisting of n units.

3. The DAC layout and routing method according to claim 2, characterized in that: The value of n is 64.

4. The DAC layout and routing method according to claim 1, characterized in that: In step 2, the maximum device width among resistor R, logic gate NAND, and switching transistor Tg is first determined according to the device type; Next, a set of resistors RX and logic gate NAND are connected. <x>and switching transistor Tg <x> A standard unit is made according to the maximum device width.< / x> < / x> 5. A DAC layout and routing system, characterized in that: The system is used to implement the DAC layout and routing method according to any one of claims 1-4.

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