Memory system and method of determining optimal read voltage for semiconductor memory

Abstract

This disclosure relates to memory systems and methods for determining optimal read voltages for semiconductor memories. Embodiments provide memory systems with improved reliability and methods for determining optimal read voltages for semiconductor memories. A memory system includes first and second memory cells and a controller configured to write data having a first value into the first memory cell and data having a second value into the second memory cell, determine a first voltage by performing a tracking process, and read data from the memory cells using the first voltage. During the tracking process, the controller performs multiple read operations to determine a first distribution of the memory cells, estimates a second distribution of the first memory cells based on the first distribution, calculates a third distribution of the second memory cells based on the difference between the first and second distributions, and determines a voltage within the third voltage range as the first voltage based on the second and third distributions.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Japanese Patent Application No. 2022-043988, filed on March 18, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments described herein generally relate to memory systems and methods for determining the optimal read voltage for a semiconductor memory. Background Technology

[0004] Memory systems, including memory devices capable of storing data in a non-volatile manner and controllers that control such memory devices, are known. Summary of the Invention

[0005] The embodiments provide a memory system with improved reliability and a method for determining the optimal read voltage of a semiconductor memory.

[0006] Generally, according to one embodiment, a memory system according to the embodiment includes a semiconductor memory and a controller. The semiconductor memory includes a plurality of memory cells, each memory cell being configured to store data having at least one of a first value and a second value according to its threshold voltage, the first value corresponding to the threshold voltage being included in a first voltage range, and the second value corresponding to the threshold voltage being included in a second voltage range. The controller is configured to write data having the first value into each of a plurality of first memory cells, write data having the second value into each of a plurality of second memory cells, determine the first voltage by performing a tracking process on the plurality of memory cells, and read data from the plurality of memory cells using the first voltage during a read process following the tracking process. The controller is configured to perform multiple read operations using multiple read voltages within a third voltage range, the third voltage range including a portion of a first voltage range and a portion of a second voltage range, to determine a first distribution of the plurality of memory primitives, estimate a second distribution of the plurality of first memory primitives within the third voltage range based on the first distribution, calculate a third distribution of the plurality of second memory primitives within the third voltage range based on the difference between the first distribution and the second distribution, and determine a voltage within the third voltage range as the first voltage based on the second distribution and the third distribution. Attached Figure Description

[0007] Figure 1This is a block diagram illustrating a configuration example of an information processing system including a memory system and a host device according to an embodiment.

[0008] Figure 2 This is a diagram illustrating the functional components arranged in the controller according to an embodiment.

[0009] Figure 3 This is a block diagram illustrating an example configuration of a NAND memory according to an embodiment.

[0010] Figure 4 This is a circuit diagram illustrating an example configuration of blocks in a memory cell array of a NAND memory according to an embodiment.

[0011] Figure 5 This is a diagram illustrating the threshold voltage distribution of the memory cell transistors of a NAND memory according to an embodiment.

[0012] Figure 6A and Figure 6B This is a diagram illustrating a shift read operation performed in a memory system according to an embodiment.

[0013] Figure 7 This is a flowchart illustrating the overall operation of a memory system according to an embodiment.

[0014] Figure 8 This is a flowchart illustrating the threshold voltage tracking process performed in a memory system according to an embodiment.

[0015] Figure 9 This is a diagram illustrating a summary of the calculation process of a detected histogram performed in a memory system according to an embodiment.

[0016] Figure 10 This is a flowchart illustrating the process of calculating a detection histogram performed in a memory system according to an embodiment.

[0017] Figure 11 This is a diagram illustrating the generation of labels using read data in a memory system according to an embodiment.

[0018] Figure 12 This is a diagram illustrating an example of a case where, according to an embodiment, read data from a memory primitive transistor undergoes multiple changes during a cyclic process.

[0019] Figure 13 This is a graph showing a detection histogram calculated by a computational process performed in a memory system according to an embodiment.

[0020] Figure 14This is a flowchart illustrating the overall process of detecting a voltage range in a memory system according to an embodiment.

[0021] Figure 15 This is a flowchart illustrating the detection process for determining a temporary marker range for voltage in a memory system according to an embodiment.

[0022] Figure 16 This is a diagram illustrating the range of temporary markers determined by the voltage detected in the memory system according to an embodiment.

[0023] Figure 17 This is a flowchart illustrating another process for detecting a temporary marker range for voltage determination performed in a memory system according to an embodiment.

[0024] Figure 18 This is a diagram illustrating the range of temporary markers determined by the voltage detected in the memory system according to an embodiment.

[0025] Figure 19 This is a flowchart illustrating the overall process of estimating a first histogram in a memory system according to an embodiment.

[0026] Figure 20 This is a schematic diagram of the estimation process of a histogram within a first range performed in a memory system according to an embodiment.

[0027] Figure 21 This is a flowchart illustrating the process of estimating a histogram within a first range in a memory system according to an embodiment.

[0028] Figure 22 This is a schematic diagram of the estimation process of a histogram within a second range performed in a memory system according to an embodiment.

[0029] Figure 23 This is a schematic diagram illustrating the calculation process of the second histogram and the determination process of the optimal read voltage performed in the memory system according to an embodiment.

[0030] Figure 24 This is a flowchart illustrating the calculation process of the second histogram and the determination process of the optimal read voltage performed in a memory system according to an embodiment.

[0031] Figure 25 This is a flowchart illustrating the detection process of determining the range of temporary markers based on the voltage performed in the memory system according to the first variation.

[0032] Figure 26 This is a flowchart illustrating the detection process of determining the range of temporary markers based on the voltage performed in the memory system according to the first variation.

[0033] Figure 27 This is a flowchart illustrating the overall process of estimating the first histogram in a memory system according to the first variant.

[0034] Figure 28 It is a schematic diagram of the estimation process of a histogram in the third range executed in the memory system according to the first variation.

[0035] Figure 29 This is a flowchart illustrating the estimation process of a histogram within a third range performed in a memory system according to the first variation.

[0036] Figure 30 It is a schematic diagram of the estimation process of a histogram in the fourth range executed in the memory system according to the first variation.

[0037] Figure 31 This is a flowchart illustrating the calculation process of the second histogram and the determination process of the optimal read voltage performed in the memory system according to the first variation.

[0038] Figure 32 This is a flowchart illustrating the threshold voltage tracking process performed in a memory system according to the second variation.

[0039] Figure 33A and Figure 33B This is a schematic diagram illustrating the determination of whether to determine the optimal read voltage in a memory system according to the second variation.

[0040] Figure 34 This is a flowchart illustrating the threshold voltage tracking process performed in a memory system according to the third variation.

[0041] Figure 35 This is a flowchart illustrating the determination of whether to determine the optimal read voltage in a memory system according to the third variation.

[0042] Figure 36A and Figure 36B This is a schematic diagram illustrating the determination of whether to determine the optimal read voltage in a memory system according to the third variation.

[0043] Figure 37A and Figure 37B This is a schematic diagram illustrating the determination of whether to determine the optimal read voltage in a memory system according to the third variation.

[0044] Figure 38 This is a flowchart illustrating the determination of whether to determine the optimal read voltage in a memory system according to the fourth variation.

[0045] Figure 39 This is a graph showing the variation of the detection histogram values ​​caused by noise in a memory system according to the fourth variation.

[0046] Figure 40 This is a flowchart illustrating the threshold voltage tracking process performed in a memory system according to the fifth variation.

[0047] Figures 41A to 41C This is a diagram illustrating the determination of whether to determine the optimal read voltage in a memory system according to the fifth variation.

[0048] Figure 42 This is a flowchart illustrating the overall operation of the memory system according to the sixth variant.

[0049] Figure 43 This is a diagram illustrating an example of the trend of the shape of the threshold voltage distribution in a memory system according to the sixth variation. Detailed Implementation

[0050] In the following description, embodiments will be described with reference to the accompanying drawings. Furthermore, in the following description, the same reference numerals denote components having substantially the same function and configuration. When it is necessary to distinguish components with the same configuration, different characters or numbers may be added to the end of the same reference numerals.

[0051] 1. Example

[0052] 1.1 Configuration

[0053] 1.1.1 Memory System

[0054] Reference Figure 1 Describe a configuration example for the memory system. Figure 1 This is a block diagram illustrating a configuration example of an information processing system including a host device and a memory system according to an embodiment.

[0055] The memory system 1 includes a controller 10 and a memory device 20.

[0056] Memory system 1 is, for example, a solid-state drive (SSD) or The memory system 1 communicates with, for example, an external host device 2. The memory system 1 stores data for the host device 2. Furthermore, the memory system 1 reads data for the host device 2.

[0057] Controller 10 may be configured with integrated circuits, such as a system-on-a-chip (SoC). Controller 10 receives commands from host device 2. The function of each component of controller 10 may be implemented by dedicated hardware, a processor executing programs (e.g., firmware), or a combination thereof. Controller 10 controls memory device 20 based on the received commands. Specifically, controller 10 writes data to be written to memory device 20 based on write commands received from host device 2. Furthermore, controller 10 sends data read from memory device 20 based on read commands received from host device 2 to host device 2.

[0058] Memory device 20 is, for example, a semiconductor memory. Memory device 20 is, for example, a NAND flash memory. Hereinafter, memory device 20 will be referred to as NAND memory 20. NAND memory 20 includes a plurality of memory element transistors. NAND memory 20 stores data in a non-volatile manner. NAND memory 20 is connected to controller 10 via a NAND bus.

[0059] The NAND bus sends and receives various signals according to the NAND interface standard via separate signal lines. These signals include, for example, IO<7:0>, / CE, CLE, ALE, / WE, / RE, and / RB. The / CE signal is the chip enable signal. The / CE signal is used to enable NAND memory 20. The CLE signal is the command latch enable signal. When the CLE signal is high (H), it notifies NAND memory 20 that the IO<7:0> signals sent to NAND memory 20 are commands. The ALE signal is the address latch enable signal. When the ALE signal is high (H), it notifies NAND memory 20 that the IO<7:0> signals sent to NAND memory 20 are addresses. The / WE signal is the write enable signal. The / WE signal instructs NAND memory 20 to take in IO<7:0>. The / RE signal is the read enable signal. The / RE signal instructs NAND memory 20 to output IO<7:0>. The / RB signal is the ready / busy signal. The / RB signal indicates whether the NAND memory 20 is in a ready state (able to receive commands from the outside) or a busy state (unable to receive commands from the outside).

[0060] Signal IO<7:0> is, for example, an 8-bit wide signal. Signal IO<7:0> is sent and received between controller 10 and NAND memory 20. Signal IO<7:0> includes address, command, and data. Commands are signals used to control NAND memory 20. Data includes read and write data.

[0061] 1.1.2 Controller

[0062] The controller 10 includes a processor (CPU: Central Processing Unit) 11, an embedded memory 12, a buffer memory 13, a host I / F (e.g., host interface circuitry) 14, a NAND I / F (e.g., NAND interface circuitry) 15, and an error checking and correction (ECC) circuitry 16.

[0063] The processor 11 controls the overall operation of the controller 10. For example, the processor 11 issues commands to instruct the NAND memory 20 to perform various operations, including write operations, read operations, and erase operations.

[0064] Embedded memory 12 is, for example, a semiconductor memory such as static random access memory (SRAM). Embedded memory 12 serves as the working area of ​​processor 11. Embedded memory 12 stores firmware for managing NAND memory 20, various management tables including multiple compressed data tables, etc.

[0065] The buffer memory 13 is, for example, a semiconductor memory such as dynamic random access memory (DRAM). The buffer memory 13 temporarily stores write data received from the host device 2, read data received by the controller 10 from the NAND memory 20, etc. Note that the buffer memory 13 may be located outside the controller 10.

[0066] The host interface circuit 14 is connected to the host device 2 via a host bus. The host bus is, for example, a bus operating according to various standards, including PCIe (PCI... (Fast interconnection of peripheral components)), UFS (Universal Flash Memory) Interfaces include SAS (Serial Attached SCSI (Small Computer System) interface), SATA (Serial ATA (Advanced Technology Accessory)), and NVMe (NVM). (Non-volatile fast memory). The host interface circuit 14 is responsible for communication between the controller 10 and the host device 2. The host interface circuit 14, for example, sends commands and data received from the host device 2 to each of the processor 11 and the buffer memory 13.

[0067] NAND interface circuit 15 is connected to NAND memory 20 via a NAND bus. The NAND bus may be a bus operating according to, for example, the ToggleNAND (Toggle DDR) standard or the Open NAND Flash Interface (ONFI) standard. NAND interface circuit 15 is responsible for communication with NAND memory 20. NAND interface circuit 15 sends commands, addresses, and write data to NAND memory 20 according to instructions from processor 11. Furthermore, NAND interface circuit 15 receives read data from NAND memory 20.

[0068] ECC circuit 16 performs error checking and correction processes on the data stored in NAND memory 20. More specifically, ECC circuit 16 generates error correction codes during data writing and adds them to the data being written. Error correction codes can be, for example, hard-decision decoding codes such as Bose-Chaudhuri-Hocquenghem (BCH) codes, Reed-Solomon (RS) codes, or soft-decision decoding codes such as low-density parity-check (LDPC) codes. Furthermore, during data reading, ECC circuit 16 decodes the error correction codes and detects the presence of error bits. When an error bit is detected, ECC circuit 16 corrects the error by specifying the location of the error bit.

[0069] 1.1.3 Functional Components of the Controller

[0070] Reference Figure 2 Examples of functional components of the controller 10 according to an embodiment are described. Figure 2 This is a diagram illustrating the functional components of the controller according to an embodiment.

[0071] The processor 11 includes various functional units, such as a tracking control unit 101, a read control unit 102, a marker generation unit 103, and a histogram calculation unit 104. The buffer memory 13 includes a read data memory unit 131. Note that the controller 10 can implement the various functional units, such as the tracking control unit 101, the read control unit 102, the marker generation unit 103, and the histogram calculation unit 104, as dedicated hardware.

[0072] The tracking control unit 101 controls the threshold voltage tracking process, described later, and estimates the optimal read voltage based on a histogram. The histogram is a distribution of the number of memory cell transistors (the number of on-cells) whose threshold voltages belong to multiple voltage ranges. More specifically, the tracking control unit 101 controls the read control unit 102 and the tag generation unit 103 to generate tags assigned to each memory cell transistor. Tags are identifiers used to distinguish the voltage ranges that include the threshold voltage of each memory cell transistor. Furthermore, the tracking control unit 101 determines the optimal read voltage by using the number of on-cells corresponding to the tags.

[0073] The read control unit 102 issues read commands to the NAND memory 20 to perform read operations. For example, when generating a tag, the read control unit 102 issues multiple read commands to search for a voltage range that includes the threshold voltage of each memory cell transistor.

[0074] The read data memory unit 131 stores data read from the memory cell transistors through read operations performed on the NAND memory 20. Furthermore, the read data memory unit 131 stores the tags assigned to each memory cell transistor.

[0075] The tag generation unit 103 uses the data stored in the read data memory unit 131 to generate tags to be assigned to each memory primitive transistor.

[0076] The histogram calculation unit 104 calculates the number of memory base transistors assigned the same label based on the label of each memory base transistor stored in the read data memory unit 131. Then, the histogram calculation unit 104 calculates a histogram representing the distribution of the number of conducting base transistors corresponding to each label.

[0077] 1.1.4 NAND Memory Configuration

[0078] Next, we will refer to Figure 3 A configuration example of NAND memory 20 according to an embodiment is described. Figure 3 This is a block diagram illustrating an example configuration of a NAND memory according to an embodiment.

[0079] The NAND memory 20 includes a memory cell array 21, an input / output circuit 22, a logic control circuit 23, a register 24, a sequencer 25, a voltage generation circuit 26, a row decoder module 27, and a sense amplifier module 28.

[0080] The memory primitive array 21 includes multiple blocks BLK (BLK0, BLK1, ...). Each block BLK is a set of multiple memory primitive transistors capable of storing data in a non-volatile manner and, for example, used as a data erasure unit. Furthermore, multiple bit lines and multiple word lines are provided in the memory primitive array 21. One memory primitive transistor is associated with, for example, one bit line and one word line.

[0081] Input / output circuit 22 sends and receives signals IO<7:0> from controller 10. Input / output circuit 22 sends commands and addresses in signals IO<7:0> to register 24. Input / output circuit 22 sends and receives write data and read data to / from sense amplifier module 28.

[0082] The logic control circuit 23 receives signals / CE, CLE, ALE, / WE, and / RE from the controller 10. Additionally, the logic control circuit 23 sends signal / RB to the controller 10.

[0083] Register 24 stores commands and addresses. Register 24 sends addresses to the line decoder module 27 and the sense amplifier module 28, and sends commands to the sequencer 25.

[0084] Sequencer 25 receives commands and controls the entire NAND memory 20 according to the sequence of the received commands.

[0085] The voltage generation circuit 26 generates the voltage required for operations such as writing, reading, and erasing data based on instructions from the sequencer 25. The voltage generation circuit 26 provides the generated voltage to the memory primitive array 21, the row decoder module 27, and the sense amplifier module 28.

[0086] The row decoder module 27 receives the row address from the address in register 24 and selects block BLK based on the row address. In addition, the voltage from the voltage generation circuit 26 is sent to the selected block BLK through the row decoder module 27.

[0087] During a data read operation, the sense amplifier module 28 senses the data read from the memory primitive transistors to the bit lines and sends the sensed data to the input / output circuit 22. During a data write operation, the sense amplifier module 28 sends the write data to the memory primitive transistors via the bit lines. Furthermore, the sense amplifier module 28 receives the column address from the register 24 and outputs the column data based on the column address.

[0088] 1.1.5 Configuration of Memory Cell Array

[0089] Next, we will refer to Figure 4The configuration of each block BLK in the memory primitive array 21 of the NAND memory 20 according to an embodiment is described. Figure 4 This is a circuit diagram illustrating an example configuration of blocks in a memory cell array of a NAND memory according to an embodiment.

[0090] A block BLK may consist of four string units SU (SU0, SU1, SU2, and SU3). Each string unit SU contains multiple NAND strings NS.

[0091] Each NAND string NS includes, for example, eight memory primitive transistors MT (MT0 to MT7), a select transistor STD, and a select transistor STS. Note that the number of memory primitive transistors MT in each NAND string NS is not limited to eight. Each memory primitive transistor MT includes a stacked gate, which includes a control gate and a charge storage layer. The individual memory primitive transistors MT are connected in series between the select transistors STD and STS. Note that in the following description, the term "connection" also includes the case where another conductive element is inserted.

[0092] Within a given block BLK, the gates of the select transistors STD for serial cells SU0 to SU3 are connected to select gate lines SGD0 to SGD3, respectively. Furthermore, the gates of the select transistors STS for all serial cells SU in the block BLK are shared by the select gate line SGS. The control gates of the memory primitive transistors MT0 to MT7 in the same BLK are connected to word lines WL0 to WL7, respectively. That is, word lines WL for the same address are shared by all serial cells SU in the same BLK, and select gate lines SGS are shared by all serial cells SU in the same BLK. Simultaneously, a select gate line SGD is connected to only one of the serial cells SU in the same BLK.

[0093] Furthermore, in the matrix of NAND strings NS arranged in the memory primitive array 21, the other end of the selection transistor STD of the NAND string NS in the same row is connected to any one of the p bit lines BL (BL0 to BL(p-1)). The number p is a natural number. In addition, the bit lines BL are connected to the NAND strings NS in the same column across multiple blocks BLK.

[0094] In addition, the other end of the select transistor STS is connected to the source line CELSRC. The source line CELSRC is connected to multiple NAND strings NS across multiple block BLKs.

[0095] As described above, for example, data is erased collectively for memory transistors MT within the same block BLK. In contrast, data can be read and written collectively for multiple memory transistors MT that share a word line WL in any string cell SU connected to any block BLK. Such a group of memory transistors MT sharing a word line WL in a string cell SU will be referred to, for example, a primitive cell CU. That is, a primitive cell CU is a group of memory transistors MT that collectively perform write or read operations. A primitive cell CU corresponds to, for example, a memory region or a group of multiple memory regions. A write or read operation of a primitive cell CU is performed against one of the memory regions. A unit of such a memory region will be called a "page".

[0096] 1.1.6 Threshold distribution of memory element transistors

[0097] Reference Figure 5 The threshold voltage distribution of the memory primitive transistor MT of the NAND memory 20 according to an embodiment is described. Figure 5 This is a diagram illustrating the threshold voltage distribution of the memory cell transistors of a NAND memory according to an embodiment. Figure 5 An example of the threshold voltage distribution of the memory primitive transistor MT in the NAND memory 20 according to an embodiment is shown. Figure 5 In the threshold voltage distribution shown, the vertical axis corresponds to the number of memory cell transistors MT, and the horizontal axis corresponds to the threshold voltage of the memory cell transistors MT.

[0098] like Figure 5 As shown, in the NAND memory 20 according to an embodiment, for example, eight threshold voltage distributions are formed by the threshold voltages of a plurality of memory primitive transistors MT. Hereinafter, these eight threshold voltage distributions will be referred to as the “S0” state, “S1” state, “S2” state, “S3” state, “S4” state, “S5” state, “S6” state, and “S7” state arranged in ascending order of threshold voltage.

[0099] The “S0” state corresponds to, for example, the data erasure state. The threshold voltage of the memory primitive transistor MT included in the “S0” state is lower than voltage R1.

[0100] States “S1” through “S7” correspond to states where charge is injected into the charge storage layer of the memory transistor MT. The threshold voltage of the memory transistor MT in state “S1” is equal to or higher than voltage R1 and lower than voltage R2 (R2 > R1). The threshold voltage of the memory transistor MT in state “S2” is equal to or higher than voltage R2 and lower than voltage R3 (R3 > R2). The threshold voltage of the memory transistor MT in state “S3” is equal to or higher than voltage R3 and lower than voltage R4 (R4 > R3). The threshold voltage of the memory transistor MT in state “S4” is equal to or higher than voltage R4 and lower than voltage R5 (R5 > R4). The threshold voltage of the memory transistor MT in state “S5” is equal to or higher than voltage R5 and lower than voltage R6 (R6 > R5). The threshold voltage of the memory transistor MT in state “S6” is equal to or higher than voltage R6 and lower than voltage R7 (R7 > R6). The threshold voltage of the memory base transistor MT, including the state “S7”, is equal to or higher than voltage R7 and lower than voltage VREAD (VREAD > R7). Voltage VREAD is the voltage used to turn on the memory base transistor MT when applied to the control gate, regardless of whether the threshold voltage of the memory base transistor MT is in any of the states from “S0” to “S7”.

[0101] When a voltage is applied to the control gate of the memory transistor MT, the memory transistor MT turns on if it has a threshold voltage lower than the applied voltage. When a voltage is applied to the control gate, the memory transistor MT turns off if it has a threshold voltage equal to or higher than the applied voltage.

[0102] Different 3-bit data are assigned to the eight threshold voltage distributions of the aforementioned memory primitive transistor MT. Examples of the data assigned to the threshold voltage distributions are shown below. The data assigned to each state is represented in the order of "high bit, middle bit, and low bit" associated with the corresponding state.

[0103] "S0" state: "1, 1, 1" data

[0104] "S1" status: "1, 1, 0" data

[0105] "S2" status: "1, 0, 0" data

[0106] "S3" status: 0, 0, 0 data

[0107] "S4" status: "0, 1, 0" data

[0108] "S5" status: "0, 1, 1" data

[0109] "S6" status: "0, 0, 1" data

[0110] "S7" status: "1, 0, 1" data

[0111] In the above data allocation, the page containing the least significant byte (low page data) is determined by reading operations using voltages R1 and R5 respectively. The page containing the middle byte (middle page data) is determined by reading operations using voltages R2, R4, and R6 respectively. The page containing the most significant byte (high page data) is determined by reading operations using voltages R3 and R7 respectively.

[0112] 1.2 Operation

[0113] The operation of the memory system 1 according to an embodiment will be described. Note that, in the description of the memory system 1 according to the embodiment, for the sake of simplicity, the case in which a read operation is performed using any of the read voltages R1 to R7 is used as an example.

[0114] 1.2.1 Shift read operation

[0115] First, refer to Figure 6A and Figure 6B This describes a shift read operation performed in memory system 1 according to an embodiment. Figure 6A and Figure 6B This is a diagram illustrating a shift read operation performed in a memory system according to an embodiment. For example, a shift read operation is performed when data cannot be read correctly at the default read voltage.

[0116] like Figure 6A As shown, immediately following the write operation, the threshold voltage distribution of state "S(m-1)" (where m represents an integer greater than or equal to 1 and less than or equal to 7) is separated from the threshold voltage distribution of state "Sm". Therefore, the controller 10 sets the read voltage Rm to the default read voltage Rmdef between the threshold voltage distributions of states "S(m-1)" and "Sm", thereby enabling correct data reading.

[0117] However, due to factors such as interference, the threshold voltage of the memory primitive transistor MT may fluctuate. As a result, the width of the threshold voltage distribution for each state may widen, or the mode (i.e., the most frequently occurring value) of the threshold voltage distribution for each state may change. Consequently, as... Figure 6B As shown, adjacent distributions may overlap. When adjacent distributions overlap, the data read from the memory primitive transistor MT during a read operation at the read voltage Rmdef differs from the data read during a write operation (corresponding to...). Figure 6B(The diagonal portion of the text). More specifically, in the threshold voltage distribution of state "S(m-1)", data of the memory cell transistor MT having a threshold voltage equal to or higher than the read voltage Rmdef becomes an error bit. Furthermore, in the threshold voltage distribution of state "Sm", read data of the memory cell transistor MT having a threshold voltage lower than the read voltage Rmdef becomes an error bit. Moreover, when the number of error bits exceeds the correctable error bit number of the ECC circuit 16, the data cannot be corrected.

[0118] When the number of error bits (i.e., the number of bit errors) is relatively large, the controller 10 will reduce the voltage of the number of error bits (e.g., Figure 6B The read voltage Rmopt is set to the new read voltage Rm. For example, the read voltage Rmopt is higher than the read voltage Rmdef.

[0119] Therefore, a shift read operation is a read operation performed by setting the voltage obtained by shifting the default read voltage Rmdef by a specific voltage to the read voltage Rm.

[0120] 1.2.2 Overall Operation

[0121] Next, the overall operation of the memory system 1 according to the embodiment, including the threshold voltage tracking process, will be described.

[0122] To minimize the number of error bits, it is desirable to perform the shift read operation at the optimal read voltage Rmopt, where Figure 6B The area of ​​the diagonal portion becomes the minimum. In the following description, "opt" will be appended to the end of the optimal read voltage for each state.

[0123] In the following text, the threshold voltage tracking process will be described as one of the operations used to search for the optimal read voltage Rmopt (R1opt to R7opt) together with the overall operation including the threshold voltage tracking process.

[0124] 1.2.2.1 Overall Operation Process

[0125] Reference Figure 7 The flowchart describes the overall operation, including the threshold voltage tracking process, performed in memory system 1 according to an embodiment. Figure 7 This is a flowchart illustrating the overall operation flow of a memory system according to an embodiment.

[0126] When the number of error bits detected in a read operation performed using the default read voltage Rmdef exceeds the number of error-correctable bits, controller 10 performs a shift read operation (ST1) using a read voltage Rmasm shifted from the default read voltage Rmdef. Read control unit 102 issues a read command to perform a read operation in NAND memory 20 using read voltage Rmasm. NAND memory 20 performs the read operation based on the read command. Figure 7 (The shift read operation in ST1) and sends the read data to the controller 10. In the following description, "asm" is appended to the end of the read voltage for each state relative to the read voltage for the shift read operation used for ST1.

[0127] ECC circuit 16 performs error detection and error correction procedures. Additionally, controller 10 determines whether error correction was successful (ST2). If error correction is successful (ST2; Yes), controller 10 acquires the successful error correction status and terminates the operation. If error correction is unsuccessful (ST2; No), the process proceeds to ST3.

[0128] Controller 10 performs a threshold voltage tracking process to determine a new read voltage Rm(ST3) that reduces the number of erroneous bits. The details of the threshold voltage tracking process will be described later.

[0129] The controller 10 performs a shift read operation (ST4) using the determined new read voltage Rm. The read control unit 102 issues a read command to perform a shift read operation in the NAND memory 20 using the new read voltage Rm. The NAND memory 20 performs the shift read operation based on the read command and sends the read data to the controller 10.

[0130] ECC circuit 16 performs error detection and error correction procedures. Then, controller 10 determines whether error correction was successful (ST5). When error correction is successful (ST5; Yes), controller 10 acquires the error correction success status and terminates the operation. When error correction is unsuccessful (ST5; No), the process proceeds to ST6.

[0131] If it is determined that error correction is unsuccessful (ST5; No), controller 10 executes other retry procedures (ST6).

[0132] The entire operation concludes with the steps described above.

[0133] 1.2.2.2 Threshold Voltage Tracking Process

[0134] Reference Figure 8 The flow of the threshold voltage tracking process (ST3) performed in memory system 1 according to an embodiment is described. Figure 8This is a flowchart illustrating the threshold voltage tracking process performed in a memory system according to an embodiment.

[0135] Controller 10 calculates the detection histogram h in the valley region of the threshold voltage distribution for states “S(m-1)” and “Sm”. d (ST11). In the following text, the ST11 process is also referred to as the calculation process for the detection histogram. Here, the valley region is the voltage range centered on the read voltage Rmasm. Detection histogram h d This is a histogram (e.g., a distribution chart) showing the number of memory cell transistors MT (the number of conducting cells) whose threshold voltages belong to each of multiple voltage ranges included in the valley region. As mentioned above, each voltage range is identified by a marker. The details of the calculation process for detecting the histogram will be described later.

[0136] The tracking control unit 101 uses the detection bar chart h d This involves detecting the range of markers to be used when determining the optimal reading voltage Rmopt (hereinafter referred to as the voltage-determined marker range) (ST12). The process of ST12 will also be referred to below as the voltage-determined marker range detection process. Details of the voltage-determined marker range detection process will be described later.

[0137] The tracking control unit 101 estimates a histogram (here referred to as the first histogram) corresponding to one of states "S(m-1)" and "Sm" (ST13). The process of ST13 will be referred to below as the estimation process of the first histogram. Here, the histogram corresponding to each state is a histogram configured with memory transistors MT belonging to the state immediately following the write operation (i.e., memory transistors MT programmed to have a threshold voltage corresponding to that state). Furthermore, in the following description, the memory transistors MT belonging to each state immediately following the write operation will be simply referred to as the memory transistors MT belonging to that state.

[0138] like Figure 6B As shown, some memory transistors MT belonging to state "S(m-1)" among multiple memory transistors MT have a threshold voltage higher than the default read voltage Rmdef due to interference, etc. In this embodiment, the tracking control unit 101 detects the low voltage side range within the detection mark range determined by the relevant voltage in the histogram h. d Perform a fitting operation to estimate the histogram h corresponding to state “S(m-1)”. (m-1). The details of the fitting will be described later. Here, the low-voltage side range is the range on the side that includes the minimum voltage in the voltage range corresponding to the voltage-determined mark range. In addition, in the following description, the range that is adjacent to the low-voltage side range and includes the maximum voltage in the voltage range corresponding to the voltage-determined mark range will be referred to as the high-voltage side range.

[0139] Here, the ratio of A to B is referred to as the overlap value in the threshold voltage. A is the number of memory cell transistors MT belonging to the state “S(m - 1)” and having a specific threshold voltage, and B is the number of memory cell transistors MT belonging to the state “Sm” and having the same specific threshold voltage. Note that the overlap value does not exceed 1. That is, when A ≥ B, the overlap value is B / A. When A < B, the overlap value is A / B. In the case of A = B, the overlap value becomes the maximum value. In addition, the average value of the overlap values within a specific threshold voltage range is referred to as the overlap of the corresponding threshold voltage distributions of the states “Sm” and “S(m - 1)”. In addition, in the following description, the overlap of the corresponding threshold voltage distributions of the states “Sm” and “S(m - 1)” will also be simply referred to as the overlap of the threshold voltage distributions.

[0140] In this embodiment, it is assumed that the overlap of the threshold voltage distribution in the low-voltage side range is less than the overlap of the threshold voltage distribution in the high-voltage side range. In this embodiment, the first histogram is histogram h (m-1) .

[0141] Return reference Figure 8 , based on the estimated histogram h (m-1) and the detected histogram h d , the tracking control unit 101 calculates a histogram corresponding to the other state in the states “S(m - 1)” and “Sm” (referred to as the second histogram here) (ST14). Hereinafter, the process of ST14 is also referred to as the calculation process of the second histogram. In this embodiment, the tracking control unit 101 calculates the histogram h m corresponding to the state “Sm”. That is, the second histogram in this embodiment is histogram h m .

[0142] In addition, the tracking control unit 101 determines the optimal read voltage Rmopt as the new read voltage Rm by using the histograms h (m-1) and h m (ST15). Hereinafter, the process of ST15 is also referred to as the determination process of the optimal read voltage.

[0143] Through the above operations, the threshold voltage tracking process is ended.

[0144] 1.2.2.2.1 Calculation process of the detected histogram

[0145] Reference will be made to Figure 9 describe an overview of the calculation process (ST11) of the detection histogram performed in the memory system 1 according to an embodiment. Figure 9 FIG. is a diagram showing an overview of the calculation process of the detection histogram performed in the memory system according to an embodiment.

[0146] In the calculation process of the detection histogram, the controller 10 calculates a threshold voltage distribution (indicated by the Figure 9 dashed line in ) corresponding to the number of conduction elements of the threshold voltage distribution where the respective threshold voltage distributions of the states “S(m−1)” and “Sm” overlap.

[0147] Specifically, the tracking control unit 101 sets a voltage range (referred to as the voltage range for the calculation of the detection histogram) that is higher than the voltage Rm_(N + 1) (< Rmasm) and equal to or lower than the voltage Rm_1 (> Rmasm) and centered on the read voltage Rmasm used in the shift read operation ST1 to be a voltage range that sufficiently includes the valley region between the two states. “N” is a positive integer. The voltage range for the calculation of the detection histogram is, for example, wider than the voltage range corresponding to the mark range determined by the voltage.

[0148] The tracking control unit 101 divides the voltage range for the calculation of the detection histogram into N consecutive voltage ranges, each having a voltage range ΔR. That is, the tracking control unit 101 divides the voltage range for the calculation of the detection histogram into N voltage ranges, including a range higher than the voltage Rm_(N + 1) and equal to or lower than the voltage Rm_N, a range higher than the voltage Rm_N and equal to or lower than the voltage Rm_(N - 1),..., a range higher than the voltage Rm_3 and equal to or lower than the voltage Rm_2, and a range higher than the voltage Rm_2 and equal to or lower than the voltage Rm_1. Here, Rm_N = Rm_(N + 1)+ΔR, Rm_(N - 1)=Rm_N + ΔR, Rm_2 = Rm_3+ΔR, Rm_1 = Rm_2+ΔR.

[0149] The controller 10 performs multiple shift read operations with the respective voltages Rm_(N + 1), Rm_N,..., Rm_2, and Rm_1. In addition, the mark generation unit 103 detects which of the (N + 2) voltage ranges the threshold voltage of each memory cell transistor MT belongs to based on the data read through the multiple shift read operations, that is, within one of the N voltage ranges, within the voltage range equal to or lower than the voltage Rm_(N + 1), and within the voltage range higher than the voltage Rm_1. In addition, the mark generation unit 103 generates a mark for each memory cell transistor MT based on the detection result.

[0150] The histogram calculation unit 104 calculates the number of conducting primitives in each of the (N+2) voltage ranges based on the generated markers of each memory primitive transistor MT.

[0151] The calculation process for detecting the histogram will be described in more detail below.

[0152] (Flowchart of the calculation process for detecting bar charts)

[0153] Reference Figure 10 The flowchart describes the process of calculating the detection histogram performed in memory system 1 according to an embodiment. Figure 10 This is a flowchart illustrating the process of calculating a detection histogram performed in a memory system according to an embodiment.

[0154] In ST21, the tracking control unit 101 sets the variable “n” to 1 (n = 1). Here, “n” is an integer greater than or equal to 1 and less than or equal to (N+1), and is a variable used in the loop process during the calculation of the detection histogram.

[0155] Controller 10 performs a shift read operation (ST22) using the read voltage Rm_n. Read control unit 102 issues a read command to perform a shift read operation in NAND memory 20 using the read voltage Rm_n. NAND memory 20 performs the shift read operation based on the read command and sends 1 bit of read data from each memory cell transistor MT to controller 10. Controller 10 stores the read data in, for example, embedded memory 12.

[0156] The tracking control unit 101 determines whether the variable "n" is greater than or equal to 5 and less than (N+1) (ST23). When the variable "n" is determined to be greater than or equal to 5 and less than (N+1) (ST23; Yes), the process proceeds to ST24. When the variable "n" is determined to be greater than or equal to (N+1) or less than 5 (ST23; No), the process proceeds to ST25.

[0157] The tag generation unit 103 performs data compression (ST24) based on the read data during multiple (5 or more) shift read operations performed using a read voltage greater than or equal to Rm_1 and less than or equal to Rm_n. Note that the ST24 process is optional, so the tag generation unit 103 may not perform the ST24 process.

[0158] The tracking control unit 101 determines whether the variable "n" is (N+1) (ST25). When the variable "n" is determined to be (N+1) (ST25; Yes), the process proceeds to ST27. When the variable "n" is determined to be less than (N+1) (ST25; No), the process proceeds to ST26.

[0159] The tracking control unit 101 increments the variable “n” (ST26), and the process proceeds to ST22. As described above, the controller 10 repeats the process from ST22 to ST26 until the tracking control unit 101 determines that the variable “n” is (N+1) (ST25; Yes).

[0160] The tag generation unit 103 generates a tag (ST27) corresponding to each memory primitive transistor MT based on the (N+1) bit read data of each memory primitive transistor MT obtained through the cyclic process of ST22 to ST26. The details of tag generation will be described later.

[0161] The histogram calculation unit 104 calculates the detection histogram h using the generated markers. d (ST28). The detection histogram h will be described later. d Details of the calculation results.

[0162] By performing the above operations, the detection of the histogram h is completed. d The calculation process.

[0163] Furthermore, the tag generation unit 103 can perform multiple data compression processes (ST24) on the data in each loop process from ST22 to ST26, compressing the (N+1) bits of read data obtained through (N+1) read operations into 5-bit wide data. The tag generation unit 103 compresses the (N+1) bits of read data into 5-bit wide data by using, for example, (N-4) compressed data tables stored in the embedded memory 12. The (N-4) compressed data tables correspond to the fifth loop process (n=5) to the Nth loop process (n=N), respectively. Each compressed data table is a table that associates the 5-bit wide data in the loop process with the corresponding 4-bit wide compressed data.

[0164] More specifically, in the fifth loop, the tag generation unit 103 compresses the read data (5-bit wide data) from the first to fifth loops into 4-bit wide data using a compression data table corresponding to the fifth loop. Similarly, in the nth loop, the tag generation unit 103 compresses the 4-bit wide data compressed in the (n-1)th loop and the read data from the nth loop into 4-bit wide data using a compression data table corresponding to the nth loop. Note that the tag generation unit 103 does not perform the data compression process in the final (N+1)th loop (n = (N+1)). That is, in the (N+1)th loop, the tag generation unit 103 obtains 5-bit wide data from the 4-bit wide data compressed in the Nth loop and the read data from the (N+1)th loop.

[0165] By compressing data sequentially based on a cyclic process, the tag generation unit 103 can compress (N+1) bits of read data into 5 bits of wide data. More specifically, the tag generation unit 103 compresses N bits of read data into 4 bits of wide data and adds this 4 bits of wide data to the read data in the last (N+1)th cyclic process (n = (N+1)), thereby turning (N+1) bits of read data into 5 bits of wide data.

[0166] (Calculation of bar chart)

[0167] Reference Figure 11 A more detailed description of the calculation of the detection histogram h d The generation of the tags used in (ST27). Figure 11 This is a diagram showing the generation of markers used to read data in a memory system according to an embodiment.

[0168] exist Figure 11 In the table shown, each row lists the read data that can be read from the memory base transistor MT during the corresponding loop process. The corresponding read data for the first loop process, the second loop process, ..., the Nth loop process, and the (N+1)th loop process are arranged in this order along the row direction. Furthermore, in each column, read data for memory base transistor MTs having threshold voltages included within the voltage range corresponding to the same column are arranged. Read data for memory base transistor MTs having threshold voltages included in the voltage range equal to or below voltage Rm_(N+1), the voltage range above voltage Rm_(N+1) and equal to or below voltage Rm_N, ..., the voltage range above voltage Rm_2 and equal to or below voltage Rm_1, and the voltage range above voltage Rm_1 are arranged in this order along the column direction.

[0169] During the first cycle, when the threshold voltage of the memory primitive transistor MT is equal to or lower than the voltage Rm_1, the read data (Rm_1) becomes the data "1"; when the threshold voltage of the memory primitive transistor MT is higher than the voltage Rm_1, the read data (Rm_1) becomes the data "0".

[0170] Furthermore, during the second cycle, when the threshold voltage of the memory primitive transistor MT is equal to or lower than the voltage Rm_2, the read data (Rm_2) becomes the data "1", and when the threshold voltage of the memory primitive transistor MT is higher than the voltage Rm_2, the read data (Rm_2) becomes the data "0".

[0171] Similarly, in the nth loop, when the threshold voltage of the memory transistor MT is equal to or lower than the voltage Rm_n, the read data (Rm_n) becomes the data "1", and when the threshold voltage of the memory transistor MT is higher than the voltage Rm_n, the read data (Rm_n) becomes the data "0". In the (n+1)th loop, when the threshold voltage of the memory transistor MT is equal to or lower than the voltage (Rm_(n+1)), the read data (Rm_(n+1)) becomes the data "1", and when the threshold voltage of the memory transistor MT is higher than the voltage (Rm_(n+1)), the read data (Rm_(n+1)) becomes the data "0".

[0172] As described above, within the voltage range (Rm_(N+1) to Rm_1) calculated for the detection histogram, when the threshold voltage of the memory transistor MT is higher than voltage Rm_(n+1) and equal to or lower than voltage Rm_n, the read data becomes data "1" in the first to the nth cycle, and becomes data "0" in the (n+1)th to the (N+1)th cycle. Therefore, when the threshold voltage of the memory transistor MT is within the voltage range calculated for the detection histogram, it is detected that the read data that became data "1" in the previous cycle changes to data "0" in a specific cycle within the (N+1)th cycle.

[0173] Furthermore, when the threshold voltage of the memory primitive transistor MT is equal to or lower than the voltage Rm_(N+1), the read data becomes the data "1" in all loops.

[0174] Furthermore, when the threshold voltage of the memory primitive transistor MT is higher than the voltage Rm_1, the read data becomes the data "0" in all loops.

[0175] In summary, the tag generation unit 103 can detect, based on read data (Rm_1) to read data (Rm_(N+1)), which voltage range of (N+2) voltage ranges the threshold voltage of the memory primitive transistor MT falls within. The tag generation unit 103 generates a tag corresponding to the detected voltage range as a tag for the memory primitive transistor MT. The tags corresponding to the (N+2) voltage ranges will be described later.

[0176] Furthermore, when the threshold voltage of the memory element transistor MT is within the voltage range calculated by the detection histogram, the read data from each memory element transistor MT obtained through the cyclic process from ST22 to ST26 may exhibit several variations (e.g. Figure 12 As shown, the changes from data "1" to data "0", and from data "0" to data "1", are caused by... Figure 12The noise is caused by the read operation in the example shown. Figure 12 This is a diagram illustrating an example of a situation where read data from a memory primitive transistor MT, according to an embodiment, exhibits multiple changes during a cyclic process.

[0177] In this scenario, the tag generation unit 103 estimates the actual change in the read data based on, for example, the loop number (n1+1) where the read data initially represented data "0" and the loop number (n2+1) where the read data last changed from data "1" to data "0". Here, n1 is an integer greater than or equal to 1 and less than or equal to (N-2). n2 is an integer greater than or equal to 3 and less than or equal to N. More specifically, for example, the tag generation unit 103 estimates that the read data is data "1" during the first loop to the n3rd loop and data "0" during the (n3+1)th loop to the (N+1)th loop. Here, n3 is the largest integer less than or equal to the sum of n1 and n2 (i.e., (n1+n2) / 2). As a result, the tag generation unit 103 detects that the threshold voltage of the memory primitive transistor MT is higher than voltage Rm_(n3+1) and equal to or lower than voltage Rm_n3.

[0178] Based on the range of threshold voltages of each memory primitive transistor MT detected as described above, the histogram calculation unit 104 calculates the values ​​respectively compared with... Figure 13 The bar chart (detection bar chart) shows the number of conducting elements corresponding to multiple markers across (N+2) voltage ranges. d . Figure 13 This is a graph illustrating a detection histogram generated by a computational process performed in a memory system according to an embodiment.

[0179] Please note that in Figure 13 In the following description, the flag corresponding to the memory transistor MT whose threshold voltage is equal to or lower than voltage Rm_(N+1) is set to 0, the flag corresponding to the memory transistor MT whose threshold voltage is higher than voltage Rm_(n+1) and equal to or lower than voltage Rm_n is set to ((N+1)-n), and the flag corresponding to the memory transistor MT whose threshold voltage is higher than voltage Rm_1 is set to (N+1). That is, the flag "i" (i is an integer greater than or equal to 0 and less than or equal to (N+1)) is set such that the voltage range corresponding to the threshold voltage of the flag "i" becomes a high voltage range as the flag "i" increases.

[0180] Furthermore, in the following description, “(i)” is appended to the end of the value (and function value) of the conduction primitive number in the label “i”. For example, the value of the conduction primitive number in the label “i” is called the conduction primitive number h. d (i).

[0181] exist Figure 13 The detection bar chart h shown d In the example, the number of conducting primitives marked "0" is h. d (0). That is, the number of memory primitive transistors MT whose threshold voltage is equal to or lower than voltage Rm_(N+1) is h. d (0). The number of conducting primitives marked "1" is h. d (1). That is, the number of memory primitive transistors MT whose threshold voltage is higher than voltage Rm_(N+1) and equal to or lower than voltage Rm_N is h. d (1). The number of conducting primitives in marker "2" is h. d (2). That is, the number of memory primitive transistors MT whose threshold voltage is higher than voltage Rm_N and equal to or lower than voltage Rm_(N-1) is h. d (2). The number of conducting elements in the "N" label is h. d (N). That is, the number of memory primitive transistors MT whose threshold voltage is higher than voltage Rm_2 and equal to or lower than voltage Rm_1 is h. d (N). The number of conducting primitives in the label "(N+1)" is h. d (N+1). That is, the number of memory primitive transistors MT whose threshold voltage is higher than voltage Rm_1 is h. d (N+1).

[0182] 1.2.2.2.2 Detection of the marked range determined by voltage

[0183] Reference Figure 14 The overall flow of the detection process (ST12) for determining the mark range of voltage performed in memory system 1 according to an embodiment is described. Figure 14 This is a flowchart illustrating the overall process of detecting a voltage range in a memory system according to an embodiment.

[0184] During the detection process of the voltage-determined mark range, the controller 10 determines the maximum mark imax and the minimum mark imin that are included within the voltage-determined mark range.

[0185] During the detection of the voltage-determined marker range, controller 10 first detects a temporary marker range based on the optimal read voltage Rmopt to be determined. Furthermore, when the temporary marker range is wide enough to execute processes ST13 to ST15, controller 10 sets the temporary marker range as the voltage-determined marker range. Conversely, when the temporary marker range is too narrow to execute processes ST13 to ST15, controller 10 sets a marker range wider than the temporary marker range as the voltage-determined marker range. The overall flow of the voltage-determined marker range detection process will be described in more detail below.

[0186] The tracking control unit 101 determines whether the optimal read voltage to be determined is the read voltage R1opt (ST31). When it is determined that the optimal read voltage to be determined is the read voltage R1opt (ST31; Yes), the process proceeds to ST32. When it is determined that the optimal read voltage to be determined is between voltages R2opt and R7opt (ST31; No), the process proceeds to ST33.

[0187] The tracking control unit 101 detects a temporary mark range (ST32) for the voltage of the read voltage R1opt. Here, the temporary mark range for the voltage of the read voltage R1opt is a temporarily detected mark range for the voltage of the read voltage R1opt. In the following text, the process of ST32 is referred to as the detection process of the temporary mark range for the voltage of the read voltage R1opt. Then, the process proceeds to ST34. Details of the detection process of the temporary mark range for the voltage of the read voltage R1opt will be described later.

[0188] The tracking control unit 101 detects a temporary mark range (ST33) determined by the voltage readings from R2opt to R7opt. Here, the temporary mark range determined by the voltage readings from R2opt to R7opt is the mark range determined by the temporarily detected voltage readings from R2opt to R7opt. In the following text, the process of ST33 is referred to as the detection process of the temporary mark range determined by the voltage readings from R2opt to R7opt. Then, the process proceeds to ST34.

[0189] The tracking control unit 101 determines whether the difference (imax-imin) between the largest mark imax and the smallest mark imin within the voltage-determined temporary mark range is greater than or equal to Lmin, where Lmin is a predetermined lower limit (ST34) of the voltage-determined mark range. When it is determined that the difference (imax-imin) is greater than or equal to the lower limit Lmin (ST34; yes), the process proceeds to ST40. When it is determined that the difference (imax-imin) is less than the lower limit Lmin (ST34; no), i.e., when the voltage-determined temporary mark range is too narrow, the process proceeds to ST35. The lower limit Lmin, for example, corresponds to the number of marks required to perform processes ST13 to ST15.

[0190] When the difference (imax-imin) is less than the lower limit Lmin (ST34; No), the tracking control unit 101 determines whether the maximum marker imax is N (ST35). When the maximum marker imax is determined to be N (ST35; Yes), that is, when the maximum voltage corresponding to the temporary marker range determined by the voltage is equal to the maximum voltage of the calculated voltage range of the detection histogram, the process proceeds to ST38. When the maximum marker imax is determined not to be N (ST35; No), the process proceeds to ST36.

[0191] The tracking control unit 101 determines whether the minimum marker imin is 1 (ST36). When it is determined that the minimum marker imin is 1 (ST36; Yes), that is, when the minimum voltage corresponding to the temporary marker range determined by the voltage is equal to the minimum voltage of the voltage range calculated by the detection histogram, the process proceeds to ST39. When it is determined that the minimum marker imin is not 1 (ST36; No), the process proceeds to ST37.

[0192] The tracking control unit 101 determines the number of conducting elements h. d Is (imax) greater than the number of conducting primitives h? d (imin)(ST37). When the number of conducting primitives h is determined. d (imax) is greater than the number of conducting elements h d When (imin) (ST37; Yes), that is, when the number of conducting elements corresponding to the largest mark in the temporary mark range determined by the voltage is greater than the number of conducting elements corresponding to the smallest mark in the temporary mark range determined by the voltage, the process proceeds to ST38. When the number of conducting elements h is determined... d (imax) is less than or equal to the number of conducting primitives h d When (imin) (ST37; no), the process proceeds to ST39.

[0193] In ST38, the tracking control unit 101 decrements the minimum mark imin (imin = imin-1), and the process proceeds to ST34. That is, when the maximum voltage corresponding to the temporary mark range determined by the voltage is equal to the maximum voltage of the voltage range calculated by the detection histogram (ST35; Yes), the tracking control unit 101 decrements the minimum mark imin to expand the temporary mark range determined by the voltage. Furthermore, when the maximum voltage and minimum voltage corresponding to the temporary mark range determined by the voltage are not equal to the maximum voltage and minimum voltage of the voltage range calculated by the detection histogram (ST35; No, and ST36; No), and when the number of conducting elements corresponding to the maximum mark of the temporary mark range determined by the voltage is greater than the number of conducting elements corresponding to the minimum mark of the temporary mark range determined by the voltage (ST37; Yes), the tracking control unit 101 decrements the minimum mark imin to expand the temporary mark range determined by the voltage.

[0194] In ST39, the tracking control unit 101 increments the maximum mark imax (imax = imax + 1), and the process proceeds to ST34. That is, when the maximum voltage corresponding to the voltage-determined temporary mark range is not equal to the maximum voltage of the voltage range calculated by the detection histogram (ST35; yes), and when the minimum voltage corresponding to the voltage-determined temporary mark range is equal to the minimum voltage of the voltage range calculated by the detection histogram (ST36; yes), the tracking control unit 101 increments the maximum value imax to expand the voltage-determined temporary mark range. That is, the tracking control unit 101 expands the mark range corresponding to the smaller of the number of conducting elements corresponding to the maximum mark and the minimum mark, respectively, to expand the voltage-determined temporary mark range (ST37, ST38, and ST39).

[0195] As described above, the tracking control unit 101 repeats ST34 to ST39 until it is determined in ST34 that the difference (imax-imin) is greater than or equal to the lower limit value Lmin. That is, the tracking control unit 101 expands the temporary mark range for voltage determination until it is determined that the mark range for voltage determination has a width greater than or equal to the lower limit value Lmin.

[0196] When the difference (imax-imin) is greater than or equal to the predetermined lower limit Lmin of the voltage-determined mark range (ST34; no), the tracking control unit 101 determines the maximum mark imx and the minimum mark imin within the voltage-determined mark range (ST40).

[0197] This concludes the detection process for the voltage-defined marking range.

[0198] (Detection process of determining the temporary mark range by reading the voltage R1opt)

[0199] Reference Figure 15 Describe the process (ST32) of detecting the temporary mark range for voltage determination of the read voltage R1opt. Figure 15 It is a flowchart showing the process of detecting the temporary mark range for voltage determination of the read voltage R1opt executed in the memory system according to an embodiment.

[0200] In the process of detecting the temporary mark range for voltage determination of the read voltage R1opt, the controller 10 detects the temporary mark range for voltage determination such that the number of conductive elements h d (i) is less than a predetermined reference value, and the proportion of the memory cell transistors MT belonging to the state "S1" among the memory cell transistors MT having a threshold voltage within the voltage range corresponding to the temporary mark range for voltage determination does not become too high. Through this process, the controller 10 temporarily detects the mark range for voltage determination to be used when determining the optimal read voltage R1opt.

[0201] The tracking control unit 101 detects the mark "i" that satisfies the first condition (ST41). In the first case, the cumulative value c of the number of conductive elements in the histogram h d is detected. d (i) is less than the sum of the constant C10 and the constant C11 (c d (i) < C10 + C11). Here, the cumulative value c of the number of conductive elements in the histogram h d is detected. d (i) is the sum of the number of conductive elements h d (0) to h d (i). In addition, the constant C10 is the expected value of the number of memory cell transistors MT included in one state. In addition, the constant C11 is an adjustment value for detecting the mark range for voltage determination of the read voltage R1opt. Through the process of ST41, the tracking control unit 101 detects the range of the mark "i" such that the proportion of the memory cell transistors MT belonging to the state "S1" among the memory cell transistors MT having a threshold voltage within the voltage range corresponding to the temporary mark range for voltage determination does not become too high.

[0202] The tracking control unit 101 detects the mark "i" that satisfies the second condition (ST42). Under the second condition, the number of conductive elements h d (i) is less than the constant H10 (h d (i) < H10). The constant H10 is the reference value of the number of conductive elements h d (i) for detecting the mark range for voltage determination of the read voltage R1opt.

[0203] The tracking control unit 101 detects the largest marker imax and the smallest marker imin (ST43) among the markers "i" that satisfy the first and second conditions.

[0204] The tracking control unit 101 determines whether the difference (imax-imin) is greater than the upper limit value Lmax of the voltage-determined marked range (ST44). When it is determined that the difference (imax-imin) is greater than the upper limit value Lmax (ST44; Yes), the process proceeds to ST45. When it is determined that the difference (imax-imin) is less than or equal to the upper limit value Lmax (ST44; No), the tracking control unit 101 terminates the detection process of reading the voltage R1opt of the voltage-determined temporary marked range.

[0205] The tracking control unit 101 sets the marker imax to the value obtained by adding the upper limit value Lmax to the marker imin (ST45). That is, when the difference (imax-imin) is greater than the upper limit value Lmax (ST44; Yes), the tracking control unit 101 adjusts the maximum marker imax so that the difference (imax-imin) becomes equal to the upper limit value Lmax.

[0206] As mentioned above, such as Figure 16 As shown, the temporary mark range is determined by detecting the reading voltage R1opt. Figure 16 This is a diagram showing the range of temporary markers determined by the voltage of the read voltage R1opt detected in the memory system according to an embodiment.

[0207] exist Figure 16 The detection bar chart h shown d In the example, the number of conducting primitives marked "0" is h. d (0). The number of conducting primitives marked "1" is h. d (1). The number of conducting elements in the label “M1” is h. d (M1). The number of conducting elements in the label “(M1+1)” is h. d (M1+1). Number of conducting elements h d (0) to h d The sum of (M1) is less than the constant C10 + C11. The number of conducting elements h d (0) to h d The sum of (M1+1) is greater than or equal to the constant C10+C11. That is, the first condition is satisfied for the markers 0 to M1.

[0208] Furthermore, the number of conducting elements in the "K1" label is h. d (K1). The number of conducting elements in the label “(K1+1)” is h. d (K1+1). The number of conducting elements in the label “(L1-1)” is h. d(L1-1). The number of conductive elements in the mark "L1" is h d (L1). All the number of conductive elements h d (K1) to h d (L1) is less than the constant H10. That is, all the marks K1 to L1 satisfy the second condition. In addition, all the marks K1 to L1 satisfy the first condition and the second condition. Therefore, the tracking control unit 101 detects the range of the marks K1 to L1 as the temporary mark range determined by the reading voltage R1opt.

[0209] (Detection process of the temporary mark range determined by the reading voltages R2opt to R7opt)

[0210] Take the reference Figure 17 Describe the process flow of the detection process (ST33) of the temporary mark range determined by the reading voltages R2opt to R7opt. Figure 17 It is a flowchart showing the process flow of the detection process of the temporary mark range determined by the reading voltages R2opt to R7opt executed in the memory system according to the embodiment. Hereinafter, the case of detecting the temporary mark range determined by the reading voltage Rmopt (that is, any one of R2opt to R7opt) will be described.

[0211] In the detection process of the temporary mark range determined by the reading voltages R2opt to R7opt, the tracking control unit 101 detects the number of conductive elements h d (i) is less than a predetermined reference value and the cumulative value c of the number of conductive elements d (i) is included in the voltage-determined temporary mark range within a predetermined range. Through this process, the tracking control unit 101 temporarily detects the voltage-determined mark range to be used when determining the optimal reading voltages R2opt to R7opt.

[0212] The tracking control unit 101 detects the mark "i" that satisfies the third condition (ST51). Under the third condition, the cumulative value c of the number of conductive elements in the histogram h d is detected d (i) is greater than the value obtained by subtracting the constant C21 from the product (C10 × m) of the constant C10 and the number of states "m", and less than the value obtained by adding the constant C22 to the product (C10 × m) (C10 × m - C21 < c d (i) < C10 × m + C22). The constants C21 and C22 are adjustment values for detecting the voltage-determined mark range of the reading voltages R2opt to R7opt. Through this process, the tracking control unit 101 detects the range of the mark "i" in which the cumulative value c of the number of conductive elements d (i) is included in a predetermined range.

[0213] The tracking control unit 101 detects the tag "i" that satisfies the fourth condition (ST52). Under the fourth condition, the number of conduction elements h d (i) is less than the constant H20 (h d (i) < H20). The constant H20 is the reference value of the number of conduction elements h d (i) for detecting the tag range determined by the read voltage R2opt to R7opt.

[0214] The tracking control unit 101 detects the maximum tag imax and the minimum tag imin among the tags "i" that satisfy the third condition and the fourth condition (ST53).

[0215] The tracking control unit 101 determines whether the difference (imax - imin) is greater than the upper limit value Lmax of the tag range determined by the voltage (ST54). When it is determined that the difference (imax - imin) is greater than the upper limit value Lmax (ST54; YES), the process proceeds to ST55. When it is determined that the difference (imax - imin) is less than or equal to the upper limit value Lmax (ST54; NO), the tracking control unit 101 ends the detection process of the temporary tag range determined by the read voltage R2opt to R7opt.

[0216] The tracking control unit 101 sets the tag imax to the value obtained by adding the upper limit value Lmax to the tag imin (ST55). That is, when the difference (imax - imin) is greater than the upper limit value Lmax (ST54; YES), the tracking control unit 101 adjusts the maximum tag imax so that the difference (imax - imin) is equal to the upper limit value Lmax.

[0217] As described above, the temporary tag range determined by the read voltage R2opt to R7opt is detected as Figure 18 shown. Figure 18 is a diagram showing the temporary tag range determined by the read voltage R2opt to R7opt detected in the memory system according to the embodiment.

[0218] In Figure 18 the example of the detection histogram h d shown, the number of conduction elements in the tag "0" is h d (0). The number of conduction elements in the tag "1" is h d (1). The number of conduction elements in the tag "(Q - 1)" is h d (Q - 1). The number of conduction elements in the tag "Q" is h d (Q). The number of conduction elements in the tag "M2" is h d (M2). The number of conduction elements in the tag "(M2 + 1)" is hd (M2+1). Number of conducting elements h d (0) to h d The sum of (M2) is greater than the constant (C10×m-C21) and less than the constant (C10×m+C22). Number of conducting elements h d (0) to h d The sum of (M2+1) is greater than or equal to the constant (C10×m+C22). Number of conducting elements h d (0) to h d The sum of (Q) is greater than the constant (C10×m-C21) and less than the constant (C10×m+C22). Number of conducting elements h d (0) to h d The sum of (Q-1) is less than or equal to the constant (C10×m-C21). That is, marking Q to M2 satisfies the third condition.

[0219] Furthermore, the number of conducting elements in the "K2" label is h. d (K2). The number of conducting elements in the label “(K2+1)” is h. d (K2+1). The number of conducting elements in the label “(L2-1)” is h. d (L2-1). The number of conducting primitives in the "L2" label is h. d (L2). The total number of conducting primitives h d (K2) to h d (L2) is less than the constant H20. That is, all markers K2 to L2 satisfy the fourth condition. In addition, all markers K2 to L2 satisfy the third and fourth conditions. Therefore, the tracking control unit 101 detects the range of markers K2 to L2 as a temporary marker range determined by the voltages R2opt to R7opt.

[0220] 1.2.2.2.3 Estimation process of the first bar chart

[0221] Reference Figure 19 Description of a first histogram (h) executed in memory system 1 according to an embodiment. (m-1) The overall process of estimating (ST13). Figure 19 This is a flowchart illustrating the overall process of estimating a first histogram in a memory system according to an embodiment.

[0222] Controller 10 detects a first and a second range (ST61) within a voltage-determined range of markers using the maximum marker *imax* and the minimum marker *imin* determined in ST40, and a constant L0 determined experimentally (e.g., L0 = 6; a larger L0 provides better accuracy for estimating the distribution, but at the cost of consuming a larger memory area). Furthermore, L0 is an integer greater than 0 and less than (imax - imin). The first range is the range of markers corresponding to the low-voltage side range, within which fitting is performed in ST13. The first range is greater than or equal to marker *imin* and less than or equal to (imin + L0 - 1). The second range is the range of markers corresponding to the high-voltage side range, which is adjacent to the low-voltage side range and includes markers corresponding to the optimal read voltage *Rmopt*. The second range is greater than or equal to marker *imin + L0 - 1* and less than or equal to marker *imax*.

[0223] The tracking control unit 101 estimates the histogram h1 within the first range. (m-1) (ST62). The tracking control unit 101 assumes that the overlap of the threshold voltage distribution is smaller in the low-voltage side range. The tracking control unit 101 bases its analysis on the detection histogram h within the first range. d Estimate the histogram h1 within the first range (m-1) The bar chart h1 will be described later. (m-1) Details of the estimate.

[0224] The tracking control unit 101 uses the estimated histogram h1 (m-1) To estimate the histogram h2 within the second range (m-1) (ST63). The bar chart h2 will be described later. (m-1) Details of the estimate.

[0225] The tracking control unit 101 will make the estimated histogram h1 (m-1) And the estimated histogram h2 (m-1) The resulting bar chart, obtained by adding the two bars, is set as the first bar chart h. (m-1) (ST64).

[0226] Through the above operations, the first histogram h within the marked range of the final voltage determination is completed. (m-1) The estimation process.

[0227] (Estimation process of the bar chart within the first range)

[0228] Reference Figure 20 Detailed description of the bar chart h1 within the first range (m-1) A summary of the estimation process (ST62). Figure 20 This is a schematic diagram of the estimation process of a histogram within a first range performed in a memory system according to an embodiment.

[0229] The tracking control unit 101 detects the distribution function H by performing a fit using the least squares method. Lkbest This function is used to detect histogram h. d The number of conducting elements h d (i) (in Figure 20 The bar chart h1 within the first range (represented by "○") (m-1) The number of conducting elements h1 (m-1) (i) (in Figure 20 (In Chinese, "Δ" is used to represent this).

[0230] In addition, the tracking control unit 101 is based on the obtained distribution function H Lkbest Estimate the histogram h1 within the first range. (m-1) The number of conducting elements h1 (m-1) (i).

[0231] The histogram h1 within the first range will be described in more detail below. (m-1) The estimation process.

[0232] Tracking control unit 101 is prepared to reproduce the number of conducting elements h1 (m-1) (i) F1 candidate distribution functions H LK (that is, H) L1 To H LF1 Here, F1 is an integer greater than 1. Additionally, "k" is an integer greater than or equal to 1 and less than or equal to F1. The candidate distribution function H in this embodiment... Lk It is represented by the following formula (1).

[0233] [Formula 1]

[0234] H Lk =a L ×V Lk (1)

[0235] The value a in formula (1) L It is a constant. The function V in formula (1) Lk It is represented by the following formula (2).

[0236] [Formula 2]

[0237]

[0238] In formula (2) and the description below, the label i1 (>0) is equal to (-i + imin + L0) (i.e., i1 = -i + imin + L0). The label i2 is an integer greater than or equal to 1 and less than or equal to L0. The value “ρ” is a constant. Furthermore, the above formulas (1) and (2) are distribution functions generated by using the probability density function of the Laplace distribution.

[0239] Tracking control unit 101 detects candidate distribution function H Lk In the candidate distribution function H Lk In the first range, the detection histogram h d With candidate distribution function H Lk The squared error between SE Lk (i.e., SE) L1 to SE LF1 ) becomes the F1 candidate distribution function H Lk The minimum value among them. Here, the squared error SE in the first range. Lk The number of conducting elements h d (i) and the value H of the candidate distribution function in label i1 corresponding to label i. Lk The sum of squares of the differences between (i1). Squared error SE Lk It is a function that depends on "k", and is represented by the following formula (3).

[0240] [Formula 3]

[0241]

[0242] The value C in formula (3) L This is expressed by the following formula (4). That is, C L The value is obtained by using the number of conduction primitives h. d (i) The calculated constants do not depend on the distribution function H. Lk In addition, the value C L It is a constant set to satisfy formula (5).

[0243] [Formula 4]

[0244]

[0245] [Formula 5]

[0246]

[0247] The function e in formula (3) Lk It is a function represented by the following formula (6), and depends on the function V. Lk .

[0248] [Formula 6]

[0249]

[0250] From the above, the tracking control unit 101 searches for the squared error SE. Lk The value of the function e Lk The distribution function H that becomes the maximum value Lk To detect the squared error SE within the first range. Lk The distribution function H that becomes the minimum value Lk The tracking control unit 101 will correspond to the searched distribution function H. Lk The "k" is set to kbest.

[0251] In addition, the tracking control unit 101 is based on the searched distribution function H Lkbest Estimate the number of conducting elements h1 in the first range (m-1) (i).

[0252] (Flowchart of the estimation process for the bar chart within the first range)

[0253] Reference Figure 21 Detailed description of the bar chart h1 within the first range (m-1) The estimation process (ST62) flow. Figure 21 This is a flowchart illustrating the process of estimating a histogram within a first range in a memory system according to an embodiment.

[0254] In ST71, the tracking control unit 101 sets the variable k to 1 and sets the evaluation value e of the squared error. Lbest The value is set to 0 (k=1, e Lbest =0).

[0255] Tracking control unit 101 calculates the detection histogram h d With candidate distribution function H Lk The value of the squared error between them, e Lk (ST72).

[0256] The tracking control unit 101 determines the calculated value e Lk Is it greater than the evaluation value e? Lbest (ST73). When the calculated value e is determined Lk Greater than the evaluation value e Lbest At time (ST73; yes), the process proceeds to ST74. When the calculated value e is determined... Lk Less than or equal to the evaluation value e Lbest At time (ST73; no), the process proceeds to ST75.

[0257] In ST74, the tracking control unit 101 will evaluate the value e. Lbest The value is set to the calculated value e. Lk (eLbest =e Lk Set kbest as the variable "k" (kbest = k).

[0258] In ST75, the tracking control unit 101 increments the variable k (k = k + 1), and the process proceeds to ST76.

[0259] The tracking control unit 101 determines whether the variable "k" is greater than F1, which is a candidate number (ST76). When the variable "k" is determined to be greater than F1, which is a candidate number (ST76; yes), the process proceeds to ST77. When the variable "k" is determined to be less than or equal to F1, which is a candidate number (ST76; no), the process proceeds to ST72. As described above, the tracking control unit 101 repeats ST72 to ST76 until the variable "k" is determined to be greater than F1, which is a candidate number, in ST76. As a result, the tracking control unit 101 calculates the squared error SE therein. Lk It becomes the minimum value and the value e Lk The variable "k" that becomes the maximum value is set to kbest.

[0260] In ST77, the tracking control unit 101 uses the candidate distribution function H corresponding to kbest. Lkbest To estimate the number of conducting elements h1 in the first range (m-1) (i). More specifically, the tracking control unit 101 estimates the distribution function value H. Lkbest (i) h1, which is the number of conducting primitives in the first range (m-1) (i).

[0261] As described above, the histogram h1 within the first range (m-1) The estimation process is now complete.

[0262] (Estimation process of the bar chart within the second range)

[0263] Reference Figure 22 Detailed description of the bar chart h2 within the second range (m-1) The estimation process (ST63). Figure 22 This is a schematic diagram of the estimation process of a histogram within a second range performed in a memory system according to an embodiment.

[0264] histogram h2 in the second range (m-1) During the estimation process, the tracking control unit 101 uses a function represented by the following formula (7) (by... Figure 22 (And as indicated by "a function based on the estimation results of the first range" in the following description) Estimate the number of conducting primitives h2 in the second range. (m-1) (i) (in Figure 22In the formula (7), the number of conducting elements h1 in the first range is used (represented by "Δ"). (m-1) (imin+L0-1).

[0265] [Formula 7]

[0266] h2 (m-1) (i)=h1 (m-1) (imin+L0-1)×B LKbest (i-(imin+L0-1)) (7)

[0267] The value B in formula (7) Lkbest It is determined to correspond to the distribution function H Lkbest The constant.

[0268] 1.2.2.2.4 Calculation process of the second bar chart and determination process of the optimal reading voltage

[0269] Reference Figure 23 Describe the second bar chart (bar chart h) m A summary of the calculation process (ST14) and the determination process (ST15) of the optimal reading voltage Rmopt. Figure 23 This is a schematic diagram illustrating the calculation process of the second histogram and the determination process of the optimal read voltage performed in the memory system according to an embodiment.

[0270] In the bar chart h m In the calculation process (ST14), the tracking control unit 101 calculates based on the number of conduction primitives h in the detection histogram. d (i) (in Figure 23 The number of conduction elements h (represented by "○" in the diagram) and the estimated number of conduction elements h in the first histogram. (m-1) (i) (in Figure 23 (Used as "Δ"), calculate the number of conducting elements h in the second histogram within the marked range determined by the voltage. m (i) (in Figure 23 (Used as "◇" in Chinese).

[0271] In the process of determining the optimal read voltage Rmopt (ST15), the tracking control unit 101 uses the estimated first histogram h (m-1) and the calculated second histogram h m The tracking control unit 101 calculates the marker imopt corresponding to the intersection of the threshold voltage distribution of state "Sm" and the threshold voltage distribution of state "S(m-1)". Furthermore, the tracking control unit 101 determines the optimal read voltage Rmopt based on the calculated marker imopt.

[0272] (Flowchart of the calculation process for the second bar chart and the determination process for the optimal reading voltage)

[0273] Reference Figure 24 Description of a second histogram (h) executed in memory system 1 according to an embodiment. m The process of calculating the optimal reading voltage Rmopt and determining the optimal reading voltage are described. Figure 24 This is a flowchart illustrating the calculation process of the second histogram and the determination process of the optimal read voltage performed in a memory system according to an embodiment.

[0274] In ST81, the tracking control unit 101 sets the marker "i" to imin (i = imin).

[0275] The tracking control unit 101 determines whether the marker "i" is greater than the marker "imax" (ST82). When it is determined that the marker "i" is greater than the marker "imax" (ST82; Yes), the process proceeds to ST87. When it is determined that the marker "i" is less than or equal to the marker "imax" (ST82; No), the process proceeds to ST83.

[0276] The tracking control unit 101 determines the number of conducting elements h. d (i) Whether it is greater than the number of conducting primitives h (m-1) (i)(ST83). When the number of conducting primitives h is determined... d (i) Greater than the number of conducting primitives h (m-1) (i) When (ST83; yes), the process proceeds to ST84. When the number of conducting primitives h is determined... d (i) Less than or equal to the number of conducting primitives h (m-1) (i) When (ST83; no), the process proceeds to ST85.

[0277] When the number of conducting primitives h d (i) Greater than the number of conducting primitives h (m-1) (i) When (ST83; yes), the tracking control unit 101 will transmit the signal from the number of conducting elements h d (i) Subtract the number of conducting primitives h (m-1) (i) The obtained value is set to the number of conduction primitives h. m (i)(ST84). That is, when detecting histogram h d The number of conducting elements h d (i) The number of conducting elements h is greater than the estimated number in the first histogram. (m-1) (i) When this occurs, the tracking control unit 101 treats the difference as a histogram h. m The number of conducting elements h m (i). Then, the process proceeds to ST86.

[0278] When the number of conducting primitives h d (i) Less than or equal to the number of conducting primitives h (m-1)(i) When (ST83; no), the tracking control unit 101 will turn on the number of basic elements h. m (i) Set to 0 (ST85). That is, when detecting histogram h d The number of conducting elements h d (i) The number of conducting elements h is less than or equal to the estimated number of elements in the first histogram. (m-1) (i) When the tracking control unit 101 moves the bar chart h m The number of conducting elements h m (i) is considered 0. Then, the process proceeds to ST86.

[0279] The tracking control unit 101 increments the marker "i" (ST86), and the process proceeds to ST82. As described above, the tracking control unit 101 repeats ST82 to ST86 until it is determined that the marker "i" is greater than the marker imax (ST82; Yes). That is, for the marker "i" that is greater than or equal to imin and less than or equal to imax, the number of conduction primitives h is calculated through the process from ST83 to ST85. m (i). As a result, the tracking control unit 101, based on the detection histogram h... d and bar chart h (m-1) Calculate the histogram h within the marked range determined by the voltage. m (ST14).

[0280] The tracking control unit 101 calculates the number of conducting elements h. (m-1) (i) Greater than the number of conducting primitives h m (i)(that is, h) (m-1) (i)>h m The largest of the tags “i” in (i) is used as the tag imopt(ST87).

[0281] The tracking control unit 101 determines the optimal read voltage Rmopt (ST88) based on the calculated mark imopt. More specifically, for example, the tracking control unit 101 sets the center voltage of the read voltage range corresponding to the mark imopt, i.e., (Rm_(N-imopt+2)+Rm_(N-imopt+1)) / 2, as the voltage Rmopt.

[0282] As described above, the tracking control unit 101 performs the determination process (ST15) of the optimal read voltages R1opt to R7opt for the read voltages R1 to R7 respectively via ST87 and ST88.

[0283] 1.3 Effects of the Implementation Examples

[0284] According to the embodiments, the reliability of the memory system 1 can be enhanced. The effects of the embodiments will be described below.

[0285] In the memory system 1 according to an embodiment, the controller 10 determines the optimal read voltage Rmopt by performing a threshold voltage tracking process on a plurality of memory primitive transistors MT. When the optimal read voltage Rmopt is determined, the controller 10 calculates a detection histogram h corresponding to the valleys of the corresponding threshold voltage distributions of states "Sm" and "S(m-1)". d Controller 10 uses the calculated detection histogram h d The fitting is used to estimate the histogram h1 within the first range. (m-1) The controller 10 estimates the number of active elements h1 based on the histogram within the first range. (m-1) (imin+L0-1), estimate the histogram h2 within the second range. (m-1) Controller 10 is based on bar chart h1 (m-1) and bar chart h2 (m-1) Estimate the first bar chart h (m-1) Controller 10 is based on the detected histogram h. d And the first bar chart h (m-1) The difference is used to calculate h in the second bar chart. m Controller 10 is based on the first histogram h. (m-1) Second bar chart h m The optimal read voltage Rmopt is determined. As a result, when the optimal read voltage Rmopt is determined, the controller 10 can reduce the difference between the read voltage and the optimal read voltage Rmopt caused by the overlap of threshold voltage distributions. Consequently, the memory system 1 can prevent an increase in the number of error bits. Therefore, the memory system 1 according to the embodiment can enhance its reliability.

[0286] <Comparative Example 1>

[0287] As a method for reducing the number of error bits in a memory system according to Comparative Example 1, for example, a method is used where the voltage adjacent to the voltage that minimizes the number of conducting elements in the valley region of the threshold voltage distribution (the minimum voltage) is set as the new read voltage. However, for example, when the threshold voltage distribution of state "S(m-1)" is asymmetrically extended on the high voltage side, the overlap of the threshold voltage distribution increases on the state "Sm" side in the valley region of the threshold voltage distribution. As a result, the difference between the optimal read voltage and the minimum voltage increases. Therefore, even if the minimum voltage is used as the read voltage, it may be difficult to reduce the number of error bits.

[0288] <Comparative Example 2>

[0289] Regarding the memory system according to Comparative Example 2, as a method for reducing the number of error bits when the difference between the optimal read voltage and the minimum voltage increases, a method is used to determine the read voltage by utilizing the slope of the valley region based on the detection histogram. More specifically, the controller of the memory system according to Comparative Example 2 determines the new read voltage based on the intersection of the slope of the high-voltage side portion of the valley region based on the detection histogram and the slope of the low-voltage side portion of the valley region based on the detection histogram. Furthermore, the controller of the memory system according to Comparative Example 2 determines the voltage at which any slope becomes a value near the minimum value in the valley region of the detection histogram as the new read voltage. However, when the overlap of the threshold voltage distribution is large, even with this method, the difference between the determined new read voltage and the optimal read voltage may increase. As a result, even with this method, it may be difficult to reduce the number of error bits.

[0290] According to an embodiment, the controller 10 uses a detection histogram h of the voltage range. d To estimate the first histogram h of state "S(m-1)" within the marked range of voltage determination (m-1) Furthermore, the controller 10 is based on the detection histogram h. d And the estimated first histogram h (m-1) Calculate the second histogram h of state "Sm". m As a result, controller 10, based on the estimated first histogram h... (m-1) and the calculated second histogram h m The controller 10 determines the optimal read voltage Rmopt. Therefore, the controller 10 can reduce the difference between the read voltage and the optimal read voltage Rmopt caused by the overlap of the threshold voltage distribution.

[0291] 2. Variations

[0292] The embodiments can have various variations.

[0293] The memory system according to a modified example will be described below. Note that since the configuration of the memory system according to the modified example is substantially the same as that of the memory system according to the embodiment, its description will be omitted. The differences between the operation of the memory system according to the modified example and the operation of the memory system according to the embodiment will be emphasized below. The memory system according to the modified example achieves the same effects as the embodiment.

[0294] 2.1 First Variation Example

[0295] In this embodiment, the tracking control unit 101 estimates the histogram h of state “S(m-1)” during the estimation process (ST13) of the first histogram. (m-1)However, this disclosure is not limited thereto. The tracking control unit 101 can estimate the histogram h of state “Sm” based on the shape of the threshold voltage distribution during the estimation process of the first histogram (ST13). m .

[0296] The operation of memory system 1 will be described below when the overlap of the threshold voltage distributions of the corresponding states "Sm" and "S(m-1)" increases in the low-voltage side range compared to the high-voltage side range due to the expansion of the threshold voltage distribution of state "Sm" in the low-voltage side range.

[0297] (Detection process for a voltage-defined marking range)

[0298] According to the first variation, the tracking control unit 101 detects a marker range corresponding to the high-voltage side voltage range in the voltage-determined marker range detection process (ST12). Furthermore, the tracking control unit 101 detects a marker range corresponding to the low-voltage side range, which is adjacent to the high-voltage side range and includes a marker corresponding to the optimal read voltage Rmopt. The voltage-determined marker range detection process (ST12) according to the first variation is substantially equivalent to the voltage-determined marker range detection process (ST12) according to the embodiment, except for the detection process (ST32) for a temporary marker range determined by the optimal read voltage R1opt and the detection process (ST33) for a temporary marker range determined by the optimal read voltage R2opt to R7opt. Hereinafter, the detection process (ST32) for a temporary marker range determined by the optimal read voltage R1opt and the detection process (ST33) for a temporary marker range determined by the optimal read voltage R2opt to R7opt will be mainly described, and other descriptions will be omitted. Furthermore, as described above, in the modified example, it is assumed that the overlap of the threshold voltage distribution is larger in the low-voltage side range compared to the high-voltage side range. Note that in the following description of the first modified example, the range corresponding to the high-voltage side range will also be referred to as the third range. Furthermore, the range corresponding to the low-voltage side range will also be referred to as the fourth range.

[0299] (Detection process of determining the temporary mark range by reading the voltage R1opt)

[0300] Reference Figure 25 The flow chart describes the detection process (ST32) for determining the temporary mark range of the read voltage R1opt. Figure 25 This is a flowchart illustrating the detection process of determining the range of a temporary marker based on the voltage of the read voltage R1opt performed in the memory system according to the first variant.

[0301] Since ST91 to ST94 in the first variation are substantially the same as ST41 to ST44 in the embodiment, their description will be omitted. ST95 in the first variation will be described below.

[0302] The tracking control unit 101 sets the marker imin to the value obtained by subtracting the upper limit value Lmax from the marker imax (ST95). That is, when the difference (imax-imin) is greater than the upper limit value Lmax (ST94; yes), the tracking control unit 101 adjusts the minimum marker imin so that the difference (imax-imin) is equal to the upper limit value Lmax.

[0303] As described above, the temporary mark range is determined by detecting the voltage of the read voltage R1opt.

[0304] (Detection process of determining the temporary mark range by reading the voltage from R2opt to R7opt)

[0305] Reference Figure 26 The flow chart describes the detection process (ST33) for determining the temporary mark range of the voltage reading from R2opt to R7opt. Figure 26 This is a flowchart illustrating the process of detecting the temporary mark range determined by the read voltages R2opt to R7opt in a memory system according to a first variation. The following will describe the detection of the temporary mark range determined by the read voltages Rmopt (R2opt to R7opt).

[0306] Since ST101 to ST104 in the first variation are substantially the same as ST51 to ST54 in the embodiment, their description will be omitted. ST105 in the first variation will be described below.

[0307] The tracking control unit 101 sets the marker imin to the value obtained by subtracting the upper limit value Lmax from the marker imax (ST105). That is, when the difference (imax-imin) is greater than the upper limit value Lmax (ST104; yes), the tracking control unit 101 adjusts the minimum marker imin so that the difference (imax-imin) is equal to the upper limit value Lmax.

[0308] As described above, the temporary mark range is determined by detecting and reading the voltages from R2opt to R7opt.

[0309] (Estimation process for the first bar chart)

[0310] According to the tracking control unit 101 of the first variant, the histogram h is estimated during the estimation process of the first histogram. m(ST13). That is, the first histogram in the first variation is histogram h. m .

[0311] Furthermore, according to the tracking control unit 101 of the first variant example, during the calculation process of the second histogram, the estimated histogram h is used as a basis. m and detection bar chart h d Calculate the histogram h (m-1) (ST14). That is, the second histogram in the first variation is histogram h. (m-1) .

[0312] 2.1.1 Estimation process of the first bar chart

[0313] Reference Figure 27 Describes the first histogram (h) executed in memory system 1 according to the first variant example. m The overall process of estimating (ST13). Figure 27 This is a flowchart illustrating the overall process of estimating the first histogram in a memory system according to the first variant.

[0314] The controller 10 detects a third and fourth range (ST111) within a voltage-determined range of markers using the maximum marker *imax* and the minimum marker *imin* determined in ST40, along with a constant L0. The third range corresponds to the range of markers within the high-voltage side range, where fitting is performed in ST13 of the first variant. The third range is greater than or equal to the marker *imin* and less than or equal to *imax*. The fourth range corresponds to the range of markers within the low-voltage side range, which is adjacent to the high-voltage side range and includes markers corresponding to the optimal read voltage *Rmopt*. The fourth range is greater than or equal to the marker *imin* and less than the marker *imin* and *imin*.

[0315] The tracking control unit 101 estimates the histogram h3 within the third range. m (ST112). The tracking control unit 101 assumes that the overlap of the threshold voltage distribution is smaller in the high-voltage side range. The tracking control unit 101 bases its analysis on the detection histogram h in the third range. d Estimate the histogram h3 within the third range. m The bar chart h3 will be described later. m Details of the estimate.

[0316] The tracking control unit 101 uses the estimated histogram h3 m To estimate the histogram h4 in the fourth range m (ST113). The bar chart h4 will be described later. m Details of the estimate.

[0317] The tracking control unit 101 will make the estimated histogram h3 m The histogram obtained by adding the estimated histogram h4m to the first histogram h is set as the first histogram h. m (ST114).

[0318] Through the above operations, the first histogram h within the marked range of the final voltage determination is completed. m The estimation process.

[0319] 2.1.2 Estimation process of the bar chart within the third range

[0320] Reference Figure 28 Detailed description of the bar chart h3 within the third range m A summary of the estimation process (ST112). Figure 28 It is a schematic diagram of the estimation process of a histogram in the third range executed in the memory system according to the first variation.

[0321] The tracking control unit 101 performs fitting using the least squares method to detect the distribution function H. Rjbest The distribution function H Rjbest Now detect the histogram h d The number of conducting elements h d (i) (in Figure 28 The bar chart h3 within the third range (represented by "○") m The number of conducting elements h3 m (i) (in Figure 28 (In Chinese, "Δ" is used to represent this).

[0322] Then, the tracking control unit 101, based on the acquired distribution function H Rjbest Estimate the histogram h3 within the third range. m The number of conducting elements h3 m (i).

[0323] The bar chart h3 within the third range will be described in more detail below. m The estimation process.

[0324] Tracking control unit 101 is prepared to reproduce the number of conducting elements h3 m (i) F2 candidate distribution functions H Rj (that is, H) R1 To H RF2 Here, F2 is an integer greater than 1. Additionally, "j" is an integer greater than or equal to 1 and less than or equal to F2. The candidate distribution function H in the first variation is... Rj It is represented by the following formula (8).

[0325] [Formula 8]

[0326] H Rj =a R ×V Rj (8)

[0327] The value a in formula (8) R It is a constant. The function V in formula (8) Rj It is represented by the following formula (9).

[0328] [Formula 9]

[0329]

[0330] In formula (9) and the description below, the label i3 (>0) is equal to (i-imax+L0) (i.e., i3=i-imax+L0). The label i4 is an integer greater than or equal to 1 and less than or equal to L0. The value “ρ” is a constant. Furthermore, the above formulas (8) and (9) are distribution functions generated by using the probability density function of the Laplace distribution.

[0331] Tracking control unit 101 detects candidate distribution function H Rj In the candidate distribution function H Rj In the middle, the detection bar chart h in the third range d and candidate distribution function H Rj The squared error between SE Rj (i.e., SE) R1 to SE RF2 The distribution functions H are transformed into F2 candidate distribution functions. Rj The minimum value in the range. Here, the squared error SE in the third range. Rj The number of conducting elements h d (i) and the value H of the candidate distribution function in label i3 corresponding to label i. Rj The sum of squares of the differences between (i3). Squared error SE Rj It is a function that depends on "j", and is represented by the following formula (10).

[0332] [Formula 10]

[0333]

[0334] The value C in formula (10) R This is expressed by the following formula (11). That is, the value C R It is achieved by using the number of conduction primitives h d (i) The calculated constants do not depend on the distribution function H. Rj In addition, the value C R It is a constant set to satisfy formula (12).

[0335] [Formula 11]

[0336]

[0337] [Formula 12]

[0338]

[0339] The function e in formula (10) Rj It is a function represented by the following formula (13), and depends on the function V. Rj .

[0340] [Formula 13]

[0341]

[0342] From the above, the tracking control unit 101 searches for the squared error SE. Rj The value of the function e Rj The distribution function H that becomes the maximum value Rj To detect the squared error SE in the third range. Rj The distribution function H that becomes the minimum value Rj The tracking control unit 101 will correspond to the searched distribution function H. Rj The "j" is set to jbest.

[0343] Then, the tracking control unit 101, based on the searched distribution function H... Rjbest Estimate the number of conducting elements h3 in the third range. m (i).

[0344] 2.1.2.1 Flowchart of the estimation process for the bar chart within the third range

[0345] Reference Figure 29 Description of the bar chart h3 within the third range m The estimation process (ST112) flow. Figure 29 This is a flowchart illustrating the estimation process of a histogram within a third range performed in a memory system according to the first variation.

[0346] In ST121, the tracking control unit 101 sets the variable "j" to 1 and sets the evaluation value e of the squared error. Rbest The value is set to 0 (j = 1, and e) Rbest =0).

[0347] Tracking control unit 101 calculates the detection histogram h d With candidate distribution function H Rj The value of the squared error between them, e Rj (ST122).

[0348] The tracking control unit 101 determines the calculated value e Rj Is it greater than the evaluation value e? Rbest (ST123). When the calculated value e is determined. Rj Greater than the evaluation value e Rbest At time (ST123; yes), the process proceeds to ST124. When the calculated value e is determined... Rj Less than or equal to the evaluation value e Rbest At (ST123; No), the process proceeds to ST125.

[0349] In ST124, the tracking control unit 101 will evaluate the value e. Rbest The value is set to the calculated value e. Rj (e Rbest =e Rj ), and set jbest as the variable "j" (jbest=j).

[0350] In ST125, the tracking control unit 101 increments the variable j (j = j + 1), and the process proceeds to ST126.

[0351] The tracking control unit 101 determines whether variable "j" is greater than F2, which is a candidate number (ST126). When it is determined that variable "j" is greater than F2, which is a candidate number (ST126; yes), the process proceeds to ST127. When it is determined that variable "j" is less than or equal to F2, which is a candidate number (ST126; no), the process proceeds to ST122. As described above, the tracking control unit 101 repeats ST122 to ST126 until it is determined in ST126 that variable "j" is greater than F2, which is a candidate number. As a result, the tracking control unit 101 calculates the squared error SE therein. Rj It becomes the minimum value and the value e Rj The variable "j" that becomes the maximum value is set to jbest.

[0352] In ST127, the tracking control unit 101 uses the candidate distribution function H corresponding to jbest. Rjbest To estimate the number of conducting elements h3 in the third range m (i). More specifically, the tracking control unit 101 will distribute the distribution function value H Rjbest (i) The estimated number of conducting primitives h3 within the third range m (i).

[0353] As mentioned above, the bar chart h3 in the third range m The estimation is now complete.

[0354] 2.1.3 Estimation process of the bar chart within the fourth range

[0355] Reference Figure 30 Detailed description of the bar chart h4 within the fourth range m The estimation process (ST113). Figure 30 It is a schematic diagram of the estimation process of a histogram in the fourth range executed in the memory system according to the first variation.

[0356] The bar chart h4 in the fourth range m During the estimation process, the tracking control unit 101 uses a function represented by the following formula (14) (by... Figure 30 (and the "function based on the estimation results of the third range" in the following description) estimates the number of conducting primitives h4 in the fourth range. m (i) (in Figure 30 In the formula (14), the number of conducting elements h3 in the third range is used (represented by "Δ"). m (imax-(L0-1)).

[0357] [Formula 14]

[0358] h4 m (i)=h3 m (imax-L0+1)×B Rjbest ((imax-L0+1)-i) (14)

[0359] The value B in formula (14) Rjbest It is determined to correspond to the distribution function H Rjbest The constant.

[0360] 2.1.4 Calculation process of the second bar chart and determination process of the optimal reading voltage

[0361] Reference Figure 31 Describing the second histogram (h) executed in the memory system 1 according to the first variant example. (m-1) The process of calculating the optimal reading voltage Rmopt and determining the optimal reading voltage are described. Figure 31 This is a flowchart illustrating the calculation process of the second histogram and the determination process of the optimal read voltage performed in the memory system according to the first variation.

[0362] In ST131, the tracking control unit 101 sets the marker "i" to imin (i = imin).

[0363] The tracking control unit 101 determines whether the marker "i" is greater than the marker "imax" (ST132). When it is determined that the marker "i" is greater than the marker "imax" (ST132; Yes), the process proceeds to ST137. When it is determined that the marker "i" is less than or equal to the marker "imax" (ST132; No), the process proceeds to ST133.

[0364] The tracking control unit 101 determines the number of conducting elements h. d (i) Whether it is greater than or equal to the number of conducting primitives h m (i)(ST133). When the number of conducting primitives h is determined. d (i) Greater than or equal to the number of conducting primitives h m (i) When (ST133; yes), the process proceeds to ST134. When the number of conducting primitives h is determined... d (i) Less than the number of conducting primitives h m (i) When (ST133; no), the process proceeds to ST135.

[0365] When the number of conducting primitives h d (i) Greater than or equal to the number of conducting primitives h m (i) When (ST133; yes), the tracking control unit 101 will reduce the number of conducting elements h d (i) Subtract the number of conducting primitives h m (i) The obtained value is set to the number of conduction primitives h. (m-1) (i)(ST134). That is, when detecting histogram h d The number of conducting elements h d (i) The estimated number of conducting elements h in the first histogram is greater than or equal to that in the first histogram. m (i) When this occurs, the tracking control unit 101 treats the difference as a histogram h. (m-1) The number of conducting elements h (m-1) (i). Then, the process proceeds to ST136.

[0366] When the number of conducting primitives h d (i) Less than the number of conducting primitives h m (i) When (ST133; no), the tracking control unit 101 will turn on the number of basic elements h. (m-1) (i) Set to 0 (ST135). That is, when detecting histogram h d The number of conducting elements h d (i) The number of conducting elements h is less than the estimated number in the first histogram. m (i) When the tracking control unit 101 moves the bar chart h (m-1) The number of conducting elements h (m-1) (i) is considered 0. Then, the process proceeds to ST136.

[0367] ST136 to ST138 are essentially the same as ST86 to ST88 in the embodiments.

[0368] Through the above operations, the optimal read voltage Rmopt was determined.

[0369] According to the memory system 1 of the first variant, even if the overlap of the threshold voltage distribution increases in the low-voltage side portion of the valley region of the threshold voltage distribution of states "S(m-1)" and "Sm" due to the expansion of the threshold voltage distribution of state "Sm" on the low-voltage side, the optimal read voltage Rmopt can be determined.

[0370] 2.2 Second Variation

[0371] In one embodiment, the tracking control unit 101 determines the optimal read voltage R1opt during threshold voltage tracking. However, this disclosure is not limited thereto. When the corresponding threshold voltage distributions of states "S0" and "S1" overlap significantly, it is not possible to detect the histogram h by fitting. d To estimate the histogram h with high accuracy (m-1) (or bar chart h) m In this case, controller 10 cannot be based on the histogram h. (m-1) (or bar chart h) m The optimal read voltage R1opt is determined by estimating the value of the voltage. More specifically, the tracking control unit 101 can perform a process to determine whether the optimal read voltage R1opt has been determined.

[0372] In the following description, the differences between the operation performed in the memory system 1 according to the second variation and the operation in the memory system 1 according to the embodiment will be emphasized.

[0373] 2.2.1 Threshold Voltage Tracking Process

[0374] Reference Figure 32 The flowchart describes the threshold voltage tracking process performed in memory system 1 according to the second variation. Figure 32 This is a flowchart illustrating the threshold voltage tracking process performed in a memory system according to the second variation.

[0375] Controller 10 determines whether to determine the optimal read voltage R1opt (ST141). When controller 10 determines that the optimal read voltage R1opt will be determined (ST141; Yes), the process proceeds to ST143. When controller 10 determines that the optimal read voltage R1opt will not be determined (ST141; No), the process proceeds to ST142. Controller 10 determines whether to determine the optimal read voltage R1opt based on whether a voltage determination marker range (including a range in which the corresponding threshold voltage distributions of states "S0" and "S1" overlap less) can be detected. Details regarding the determination of whether to determine the optimal read voltage R1opt will be described later.

[0376] The tracking control unit 101, for example, determines the read voltage R1asm as the new read voltage R1 (ST142).

[0377] ST143 to ST147 are the same as ST11 to ST15 according to the embodiment.

[0378] As described above, in the memory system 1 according to the second variation, a new read voltage R1 is determined when the optimal read voltage R1opt is determined and when the optimal read voltage R1opt is not determined.

[0379] 2.2.2 Determination of whether to determine the optimal reading voltage R1opt

[0380] Next, we will refer to Figure 33A and Figure 33B Describe the determination of whether to determine the optimal read voltage R1opt (ST141). Figure 33A and Figure 33B This is a schematic diagram illustrating the determination of whether to determine the optimal read voltage in a memory system according to the second variation.

[0381] like Figure 33A As shown, when c is the number of memory primitive transistors MT Rmin Less than the reference value c Th At that time, the overlap of the corresponding threshold voltage distributions for states "S0" and "S1" within the low-voltage side range may be small (in Figure 33A In the example shown, it is almost zero. Here, the number c of memory primitive transistors MT is... Rmin This refers to the number of memory primitive transistors MT that have a threshold voltage equal to or lower than the minimum read voltage Rmin that can be used to perform a read operation. In the following text, the minimum read voltage Rmin that can be used to perform a read operation will also be referred to as the lower limit voltage Rmin. The number of memory primitive transistors MT, c Rmin This refers to the number of memory primitive transistors MT that become active when a read operation is performed using the lower limit voltage Rmin. Also, as... Figure 33B As shown, when the number of memory primitive transistors MT c Rmini Greater than or equal to the reference value c Th At this time, the overlap of the corresponding threshold voltage distributions for states "S0" and "S1" within the low-voltage side range may be significant. The threshold voltage distribution is related to the number of memory primitive transistors (MTs), c. Rmin (like Figure 33A and Figure 33B The relationship between the two (as shown) can be demonstrated, for example, through the performance evaluation of the NAND memory 20.

[0382] The tracking control unit 101 compares the number of memory primitive transistors MT c Rmin and reference value c Th .like Figure 33AAs shown, when the number of memory primitive transistors MT c Rmin Less than the reference value c Th At that time, the tracking control unit 101 determines the optimal read voltage R1opt. For example... Figure 33B As shown, when the number of memory primitive transistors MT c Rmin Greater than or equal to the reference value c Th At that time, the tracking control unit 101 determines that the optimal read voltage R1opt will be uncertain.

[0383] <Comparative Example 3>

[0384] like Figure 33B As shown, when the number of memory primitive transistors MT c Rmin Greater than or equal to the reference value c Th In this case, the overlap of the corresponding threshold voltage distributions within the low-voltage side range may be significant. That is, the voltage range in which the controller performs fitting when determining the optimal read voltage R1opt becomes a voltage range in which the threshold voltage distributions overlap significantly. Even in this case, the controller of the memory system according to Comparative Example 3 attempts to determine the optimal read voltage R1opt. However, in this case, the controller cannot properly perform the fitting of the detection histogram. As a result, the difference between the new read voltage determined by fitting and the true optimal read voltage becomes greater than the difference between the read voltage R1asm and the true optimal read voltage. Therefore, the number of error bits may increase.

[0385] According to the second variation, when the lower limit voltage Rmin approaches the valley position of the threshold voltage distribution of states "S0" and "S1", the tracking control unit 101 sets the read voltage R1asm as the new read voltage Rm, instead of determining the optimal read voltage R1opt. As a result, the memory system 1 according to the second variation can prevent an increase in the number of error bits, which is caused by a detection histogram h based on a voltage range where the threshold voltage distribution overlaps significantly. d This is due to the determination of the optimal read voltage R1opt.

[0386] Please note that during threshold voltage tracking, controller 10 can determine the optimal read voltages R2opt to R7opt for each read voltage R2 to R7 through an operation similar to that in the embodiment.

[0387] 2.3 Third variation example

[0388] In the second variation, the tracking control unit 101 sets the threshold voltage to the number c of memory primitive transistors MT that are less than or equal to the lower limit voltage Rmin. Rmin Compared with reference value c ThThe comparison is performed to determine whether the optimal read voltage R1opt is determined. However, this disclosure is not limited thereto. The tracking control unit 101 can base its analysis on the detection histogram h. d The shape of the voltage R1opt is used to determine whether the optimal read voltage is determined.

[0389] In the following text, the differences between the operations performed in memory system 1 according to the third variation and the operations of memory system according to the second variation will be described in detail.

[0390] 2.3.1 Threshold Voltage Tracking Process

[0391] Reference Figure 34 The flowchart describes the threshold voltage tracking process performed in memory system 1 according to the third variation. Figure 34 This is a flowchart illustrating the threshold voltage tracking process performed in a memory system according to the third variation.

[0392] In a manner similar to ST11 and ST12 of the operation of the memory system according to the embodiment, the tracking control unit 101 performs the calculation of the detection histogram (ST151) and the detection process of the voltage determination mark range (ST152).

[0393] Then, the tracking control unit 101 determines whether the optimal read voltage R1opt is determined (ST153). When the tracking control unit 101 determines that the optimal read voltage R1opt will be determined (ST153; Yes), the process proceeds to ST155. When the tracking control unit 101 determines that the optimal read voltage R1opt will not be determined (ST153; No), the process proceeds to ST154. The tracking control unit 101 bases its analysis on the detection histogram h within the first range. d The shape of the voltage R1opt is used to determine whether the optimal read voltage R1opt is determined. Details regarding the determination of whether the optimal read voltage R1opt is determined will be described later.

[0394] ST154 to ST157 are the same as ST142 and ST145 to ST147 according to the second variation, respectively.

[0395] 2.3.2 Determination of whether to determine the optimal reading voltage

[0396] Reference Figure 35 , Figure 36A and Figure 36B The process of determining whether to determine the optimal read voltage R1opt is performed in memory system 1 according to the third variation (ST153). Figure 35 This is a flowchart illustrating the determination of whether to determine the optimal read voltage in a memory system according to the third variation. Figure 36A and Figure 36BThis is a schematic diagram illustrating the determination of whether to determine the optimal read voltage in a memory system according to the third variation.

[0397] In determining whether to determine the optimal read voltage, the tracking control unit 101 determines the number of conducting elements h. d (i) Whether it monotonically decreases as the marker "i" in the first range increases. When the number of conducting primitives h is determined... d (i) When the marker “i” in the first range decreases monotonically as it increases, the tracking control unit 101 determines that the overlap of the corresponding threshold voltage distributions of states “S0” and “S1” in the low-voltage side range is small (in Figure 36A In the example shown, it is almost zero, such as Figure 36A As shown. Then, the tracking control unit 101 determines the estimated optimal read voltage R1opt. Simultaneously, when the number of conducting elements h is determined... d (i) When the value of the marker "i" in the first range does not decrease monotonically with the increase of the marker "i", the tracking control unit 101 determines that the corresponding threshold voltage distributions of states "S0" and "S1" overlap significantly in the low-voltage side range, such as... Figure 36B As shown. Then, the tracking control unit 101 determines that the optimal read voltage R1opt is not estimated.

[0398] refer to Figure 35 In ST161, the tracking control unit 101 sets the marker "i" to imin (i = imin).

[0399] The tracking control unit 101 determines whether the marker "i" is equal to (imin+L0-1) (ST162). When it is determined that the marker "i" is equal to (imin+L0-1) (ST162; Yes), the process proceeds to ST165. When it is determined that the marker "i" is less than (imin+L0-1) (ST162; No), the process proceeds to ST163.

[0400] The tracking control unit 101 calculates the number of conducting elements h. d (i+1) minus the number of conducting primitives h d (i) and the difference Δh obtained d (i)(ST163).

[0401] The tracking control unit 101 increments the marker “i” (ST164), and the process proceeds to ST162. As described above, the tracking control unit 101 repeats ST162 to ST164 until it is determined that the marker “i” is equal to (imin+L0-1) (ST162; Yes).

[0402] The tracking control unit 101 calculates the evaluation value N based on the results of the cyclic process from ST162 to ST164. cnEvaluation value N cn It is used to indicate the number of conduction elements h d (i) Whether the value monotonically decreases as the marker "i" increases. Evaluation value N cn When the difference Δh d (imin), Δh d (imin+1), ..., Δh d (imin+L0-2), Δh d When (imin+L0-1) are arranged in this order, the difference Δh d (i) The maximum value among the number of consecutive negative values. The tracking control unit 101 bases its decision on the evaluation value N. cn Is it greater than or equal to the reference value N? cTh Determine the number of conducting primitives h d (i) Whether it decreases monotonically as the mark “i” in the first range increases.

[0403] That is, the tracking control unit 101 is based on the evaluation value N cn Determine whether the optimal read voltage R1opt (ST165) has been determined. When the evaluation value N is determined... cn Greater than or equal to the reference value N cTh At time (ST165; yes), the tracking control unit 101 determines that the optimal read voltage R1opt will be determined because the number of conducting elements h d (i) It decreases monotonically as the marker "i" increases, and the process proceeds to ST155. When the evaluation value N is determined... cn Less than the reference value N cTh When (ST165; No), the tracking control unit 101 determines that the optimal read voltage R1opt will be uncertain because the number of conducting elements h d (i) does not decrease monotonically with the increment of the marker “i”, and the process proceeds to ST154.

[0404] As described above, determine whether to determine the optimal read voltage R1opt.

[0405] Reference Figure 37A and Figure 37B Further description of the determination of whether to determine the optimal read voltage R1opt. Figure 37A and Figure 37B This is a schematic diagram illustrating the determination of whether to determine the optimal read voltage in a memory system according to the third variation.

[0406] like Figure 37A As shown, when the evaluation value N cn Greater than or equal to the reference value N within the first range cTh When (for example, when the number of conducting elements h) d(i) When the reading voltage decreases monotonically as the reading voltage increases, the tracking control unit 101 determines that the optimal reading voltage R1opt will be determined because the overlap of the threshold voltage distribution in the low voltage side range is small.

[0407] exist Figure 37A In the example shown, the difference Δh d (imin), Δh d (imin+1), ..., Δh d (imin+L0-2), Δh d (imin+L0-1) are all negative. That is, the evaluation value N cn Let L0 be the evaluation value. cn (Here, L0) is greater than or equal to the reference value N. cTh At that time, the tracking control unit 101 determines the optimal read voltage R1opt.

[0408] At the same time, such as Figure 37B As shown, when the evaluation value N in the first range cn Less than the reference value N cTh When (e.g., when the detection histogram in the first range has a downward convex shape), the tracking control unit 101 determines that the optimal read voltage R1opt will be uncertain because the threshold voltage distributions in the low voltage side range overlap significantly.

[0409] exist Figure 37B In the example shown, the difference Δh d (imin) and Δh d (imin+1) is negative. Simultaneously, the difference Δh d (imin+2), Δh d (imin+3), ..., Δh d (imin+L0-2) and Δh d (imin+L0-1) are all positive. That is, the evaluation value N cn The value is 2. When the evaluation value N cn (Here, 2) is less than the reference value N. cTh At that time, the tracking control unit 101 determines that the optimal read voltage R1opt will be uncertain.

[0410] As described above, the memory system 1 according to the third variation can prevent the increase of error bits, just like in the second variation.

[0411] 2.4 Fourth Variation Example

[0412] In the third variation, the tracking control unit 101 is based on the difference Δh within the first range. d (i) The maximum value among the consecutive negative values ​​(evaluation value N) cnThe system determines whether to determine the optimal read voltage R1opt. However, this disclosure is not limited thereto. The tracking control unit 101 can base its determination on a negative difference value Δh within a first range. d The number of (i) determines whether the optimal read voltage R1opt is determined.

[0413] In the following description, the differences between the operation performed in memory system 1 according to the fourth variation and the operation of memory system according to the third variation will be emphasized.

[0414] Reference Figure 38 The description pertains to the determination of whether to determine the optimal read voltage R1opt, performed in memory system 1 according to the fourth variation. Figure 38 This is a flowchart illustrating the determination of whether to determine the optimal read voltage in a memory system according to the fourth variation.

[0415] In determining whether to determine the optimal read voltage R1opt, the tracking control unit 101 determines the number of conducting elements h. d (i) Whether it tends to decrease as the number of markers "i" in the first range increases. When the number of conducting primitives h d (i) When the value tends to decrease as the mark "i" in the first range increases, the tracking control unit 101 estimates the optimal read voltage R1opt. When the number of conducting elements h... d (i) When the reading voltage R1asm does not tend to decrease as the mark “i” in the first range increases, the tracking control unit 101 sets the reading voltage R1asm to the reading voltage R1.

[0416] ST171 to ST174 are the same as ST161 to ST164 respectively.

[0417] The tracking control unit 101 calculates the evaluation value N based on the results of the cyclic process from ST172 to ST174. n Evaluation value N n It is used to indicate the number of conduction elements h d (i) Whether the value monotonically decreases as the marker "i" increases. Evaluation value N n The difference Δh is calculated during the cycle from ST172 to ST174. d (i) The negative difference Δh d The number of (i). The tracking control unit 101 is based on the evaluation value N. n Is it greater than or equal to a certain value N? nTh (0 <N nTh ≤L0), determine the number of conducting primitives h d (i) Whether it decreases monotonically as the mark “i” in the first range increases.

[0418] That is, the tracking control unit 101 is based on the evaluation value N n Determine whether the optimal read voltage R1opt (ST175) has been determined. When the evaluation value N n Greater than or equal to a definite value N nTh At time (ST175; yes), the tracking control unit 101 determines that the optimal read voltage R1opt will be determined because the number of conducting elements h d (i) It decreases monotonically as the marker "i" increases, and the process proceeds to ST155. When the evaluation value N... n Less than a certain value N nTh When (ST175; No), the tracking control unit 101 determines that the optimal read voltage R1opt will be uncertain because the number of conducting elements h d (i) does not decrease monotonically with the increment of the marker “i”, and the process proceeds to ST154.

[0419] Figure 39 This indicates the number of conduction primitives h in the detection histogram. d (i) The graph changes due to noise. Figure 39 In the example shown, the number of conducting primitives h d (imin) is greater than the number of conducting primitives h d (imin+1). Number of conducting primitives h d (imin+1) is less than the number of conducting primitives h d (imin+2). Number of conducting primitives h d (imin+2) is greater than the number of conducting primitives h. d (imin+3). Therefore, the number of conducting primitives h d (i) Due to, for example, noise.

[0420] According to the memory system 1 of the fourth variation, even if the number of conducting primitives h d (i) Changes, the tracking control unit 101 can also be based on the evaluation value N. n To determine whether the low-voltage side range is the range in which the threshold voltage distribution has less overlap.

[0421] Thus, as in the second and third modifications, in the memory system 1 according to the fourth modification, even if the histogram h is detected... d Variations due to noise can also prevent an increase in the number of error bits.

[0422] 2.5 Fifth Variation

[0423] In the above embodiments, the tracking control unit 101 determines optimal read voltages R1opt to R7opt for each of the read voltages R1 to R7. However, this disclosure is not limited thereto. The tracking control unit 101 may determine whether to determine an optimal read voltage Rmopt for each of the read voltages R1 to R7.

[0424] In the following description, the differences between the operation performed in memory system 1 according to the fifth variation and the operation of memory system according to the embodiment will be emphasized.

[0425] Reference Figure 40 The flowchart describes the threshold voltage tracking process performed in memory system 1 according to the fifth variation. Figure 40 This is a flowchart illustrating the threshold voltage tracking process performed in a memory system according to the fifth variation.

[0426] The number c of memory primitive transistors MT when its threshold voltage is equal to or lower than the read voltage Rmasm. Rmasm When included within a predetermined range, the tracking control unit 101 determines that the read voltage Rmasm is approximately equal to the optimal read voltage Rmopt. Then, the tracking control unit 101 determines that the optimal read voltage Rmopt will be uncertain. Furthermore, when the number c of memory primitive transistors MT... Rmasm If the reading voltage Rmasm is not included in the predetermined range, the tracking control unit 101 determines that the reading voltage Rmopt and the optimal reading voltage Rmopt are different values. Then, the tracking control unit 101 determines that the optimal reading voltage Rmopt will be determined.

[0427] The tracking control unit 101 calculates the number c of memory primitive transistors MT. Rmasm (ST181). The number c of memory primitive transistors MT. Rmasm It is the number of memory primitive transistors MT that become on when a read operation is performed at the read voltage Rmasm.

[0428] The tracking control unit 101 is based on the number c of memory primitive transistors MT. Rmasm Determine whether the optimal read voltage Rmopt (ST182) has been determined. The tracking control unit 101 determines the number c of memory primitive transistors MT. Rmasm Is it less than or equal to the value (C10×m-C31) or greater than or equal to the value (C10×m+C32)? Here, constants C31 and C32 are adjustment values ​​used to determine whether the optimal read voltage Rmopt is determined by fitting. Constants C31 and C32 have positive values.

[0429] When c Rmasm Less than or equal to the value (C10×m-C31) or c RmasmWhen the value is greater than or equal to (C10×m+C32), the tracking control unit 101 determines that the optimal read voltage Rmopt will be determined (ST182; Yes). The process proceeds to ST184.

[0430] When the number of memory primitive transistors MT c Rmasm When the value is greater than (C10×m-C31) and less than (C10×m+C32), the tracking control unit 101 determines that the optimal read voltage Rmopt is uncertain (ST182; No). For example, the tracking control unit 101 determines the read voltage Rmasm as the new read voltage Rm (ST183).

[0431] As described above, the tracking control unit 101 is based on the number c of memory primitive transistors MT. Rmasm Determine whether the read voltage Rmasm and the optimal read voltage Rmopt are approximately equal to each other within the range of (C10×m-C31) and (C10×m+C32).

[0432] ST184 to ST188 are the same as ST11 to ST15, respectively.

[0433] The threshold voltage tracking process according to the fifth variation is then completed through the above operations.

[0434] Reference Figures 41A to 41C The determination of whether to determine the optimal read voltage Rmopt is described in more detail (ST182). Figures 41A to 41C This is a diagram illustrating the determination of whether to determine the optimal read voltage in a memory system according to the fifth variation.

[0435] like Figure 41A As shown, for example, when the read voltage Rmasm is less than the optimal read voltage Rmopt, the number c of memory primitive transistors MT Rmasm The threshold voltage becomes less than or equal to the reference value (C10×m-C31). In this case, due to the expansion of the threshold voltage distribution of state "S(m-1)" on the high-voltage side, the overlap of the threshold voltage distribution within the high-voltage side range becomes greater than the overlap of the threshold voltage distribution within the low-voltage side range. In this case, the tracking control unit 101 determines that the optimal read voltage Rmopt will be determined.

[0436] In addition, such as Figure 41B As shown, for example, when the read voltage Rmasm is greater than the optimal read voltage Rmopt, the number c of memory primitive transistors MT RmasmThe threshold voltage distribution becomes greater than or equal to the reference value (C10×m+C32). In this case, due to the expansion of the threshold voltage distribution of state "Sm" on the low-voltage side, the overlap of the threshold voltage distribution within the low-voltage side range becomes greater than the overlap of the threshold voltage distribution within the high-voltage side range. In this case, the tracking control unit 101 determines that the optimal read voltage Rmopt will be determined.

[0437] In addition, such as Figure 41C As shown, for example, when the read voltage Rmasm equals the optimal read voltage Rmopt, the number c of memory primitive transistors MT Rmasm The value becomes greater than the reference value (C10×m-C31) and less than the reference value (C10×m+C32). In this case, the corresponding threshold voltage distributions of states "S(m-1)" and "Sm" can be symmetrical to each other, and sufficient reading voltage accuracy can be obtained by setting the reading voltage Rmasm to the reading voltage Rm. In this case, the tracking control unit 101 determines that the optimal reading voltage Rmopt will be uncertain.

[0438] Figures 41A to 41C The threshold voltage distribution shown is related to the number c of memory primitive transistors MT. Rmasm The relationship can be demonstrated, for example, through the evaluation of the characteristics of NAND memory 20.

[0439] According to the fifth variation, when determining each new read voltage R1 to R7, the tracking control unit 101 bases its calculations on the number c of the memory primitive transistors MT. Rmasm The system determines whether to set the optimal read voltage Rmopt to the new read voltage Rm, or whether to set the read voltage Rmasm to the new read voltage Rm. Therefore, in the memory system 1 according to the fifth variation, when sufficient accuracy is obtained by setting the read voltage Rmasm to the new read voltage Rm, the time period used to determine the optimal read voltage Rmopt can be shortened.

[0440] 2.6 Sixth Variation

[0441] In the fifth variation described above, the tracking control unit 101 determines whether to determine the optimal read voltages R1opt to R7opt when determining new read voltages R1 to R7, respectively. However, this disclosure is not limited thereto. The tracking control unit 101 may detect the read voltage Rm, which is the target for determination of the optimal read voltage Rmopt, before the threshold voltage tracking process, based on, for example, the trend of the shape of the threshold voltage distribution in each of states "S0" to "S7".

[0442] 2.6.1 Overall Operation

[0443] Reference Figure 42The flow describes the overall operation, including the threshold voltage tracking process, performed in memory system 1 according to the sixth variation. Figure 42 This is a flowchart illustrating the overall operation flow of the memory system according to the sixth variant.

[0444] The tracking control unit 101 detects the read voltage Rm (process target read voltage), which is the target of the process (ST193) for determining the optimal read voltage Rmopt among read voltages R1 to R7. In the following text, the ST193 process is also referred to as the process target read voltage detection process. The tracking control unit 101 is based on... Figure 6B The diagonal portion represents the overlapping shape of the threshold voltage distributions of states "S(m-1)" and "Sm", which is the target read voltage Rm during the detection process. Details of the detection process for the target read voltage will be described later.

[0445] The tracking control unit 101 performs a threshold voltage tracking process (ST194) only for the process target read voltage Rm. This threshold voltage tracking process is the same as the threshold voltage tracking process (ST3) according to the embodiment. Therefore, the tracking control unit 101 determines the optimal read voltage Rmopt as the new read voltage Rm for the process target read voltage Rm. Simultaneously, the tracking control unit 101 determines the read voltage Rmasm as the new read voltage Rm for read voltages that are not the process target.

[0446] ST191, ST192, ST195 to ST197 are the same as ST1, ST2, ST4 to ST6 according to the embodiment.

[0447] 2.6.2 Detection process of target reading voltage

[0448] Reference Figure 43 Describe the detection process of the target read voltage (ST193). Figure 43 This is a diagram illustrating an example of the trend in the shape of the threshold voltage distribution for each of states “S0” to “S7”. Figure 43 The threshold voltage distribution of each of the states “S0” to “S7” is shown after a write operation, which widens due to factors such as interference.

[0449] The tracking control unit 101 performs a process to detect the target reading voltage based on the trend of the shape of the threshold voltage distribution in each of states “S0” to “S7”.

[0450] like Figure 43As shown, the threshold voltage distributions of the corresponding low-voltage sides (S0 to S3) in states "S0" to "S7" tend to extend further on the high-voltage side than on the low-voltage side. On the other hand, the threshold voltage distributions of the corresponding high-voltage sides (S4 to S7) in states "S0" to "S7" tend to widen symmetrically compared to the threshold voltage distributions of states "S0" to "S3". Through these trends in threshold voltage distribution, the overlap of threshold voltage distributions between states "S0" and "S1", between states "S1" and "S2", between states "S2" and "S3", and between states "S3" and "S4" is asymmetrical. Furthermore, the overlap of threshold voltage distributions between states "S4" and "S5", between states "S5" and "S6", and between states "S6" and "S7" is further symmetrical.

[0451] The tracking control unit 101 determines whether each of the overlaps in the threshold voltage distributions of states "S0" and "S1" and the overlaps in the threshold voltage distributions of states "S6" and "S7" is asymmetrical. When the overlaps in the threshold voltage distributions of states "S(m-1)" and "Sm" are asymmetrical, the tracking control unit 101 determines that the optimal read voltage Rmopt and the read voltage Rmasm are different. Furthermore, the tracking control unit 101 detects the read voltage corresponding to the overlap of the threshold voltage distributions determined to be asymmetrical. Figure 43 The reading voltages R1 to R4 in the process are used as the process target reading voltage Rm. Furthermore, when the threshold voltage distributions of states "S(m-1)" and "Sm" overlap symmetrically, the tracking control unit 101 determines that the optimal reading voltage Rmopt and the reading voltage Rmasm are approximately equal to each other. Additionally, the tracking control unit 101 detects the reading voltage corresponding to the overlap of the determined symmetrical threshold voltage distributions (Rmopt and Rmasm). Figure 43 The reading voltages R5 to R7 in the process are used as the reading voltage Rm, which is not the process target.

[0452] Furthermore, the tracking control unit 101, for example, before the detection process (ST193) of the process target read voltage, uses a ratio to calculate the detection histogram h. d For a wider voltage range ΔR, a histogram is calculated including the valley regions of the threshold voltage distribution corresponding to the read voltages R1 to R7, respectively. The tracking control unit 101 determines, for example, whether the overlap of the threshold voltage distributions is asymmetrical based on the shape of the calculated histogram.

[0453] In the memory system 1 according to the sixth modification, the tracking control unit 101 detects a read voltage Rm before the threshold voltage tracking process to determine the optimal read voltage Rmopt among the read voltages R1 to R7. Thus, in the memory system 1 according to the sixth modification, during the threshold voltage tracking process, the time period for determining whether the optimal read voltage Rmopt is determined for each of the read voltages R1 to R7 can be shortened.

[0454] 3. Miscellaneous

[0455] In the above embodiments and modifications, any one of the read voltages R1 to R7 is used to perform the read operation. However, the present disclosure is not limited thereto. The controller 10 may perform the read operation using multiple voltages (e.g., voltages R1 and R5 corresponding to low page data). When performing the read operation using the voltages R1 to R5, the controller 10 sets the voltage range for histogram calculation detection to a range higher than the voltage R1_(N + 1) (<R1asm) and equal to or lower than the voltage R1_1 (>R1asm) based on the voltage R1asm, and a range higher than the voltage R5_(N + 1) (R1_1 < R5_(N + 1) < R5asm) and equal to or lower than the voltage R5_1 (>R5asm) based on the voltage R5asm. That is, the memory system 1 performs multiple shifted read operations using two read voltages R1_n and R5_n. In addition, the controller 10 may include split reads for determining whether the threshold voltage of each memory cell transistor MT is included in the range equal to or lower than the voltage R1_1 and whether the threshold voltage of each memory cell transistor MT is included in the range equal to or higher than the voltage R5_(N + 1) when calculating the detection histogram. The read voltage for the split read is higher than the voltage R1_1 and lower than the voltage R5_(N + 1). The read voltage for the split read is, for example, the default read voltage R3def.

[0456] In addition, in each of the embodiment and the first modification, the fitting of the first range is performed for all the read voltages R1 to R7, and the fitting of the third range is performed for all the read voltages R1 to R7. However, the present disclosure is not limited thereto. For example, for each read voltage Rm among the read voltages R1 to R7, the optimal read voltage Rmopt may be determined by performing the fitting of the first range, and the optimal read voltage Rmopt may be determined by performing the fitting of the third range.

[0457] Although certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of this disclosure. In fact, the novel embodiments described herein may be embodied in many other forms; furthermore, various omissions, substitutions, and changes may be made to the form of the embodiments described herein without departing from the spirit of this disclosure. The appended claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of this disclosure.

[0458] 1. Memory System

[0459] 2. Main unit

[0460] 10 Controllers

[0461] 11 processors

[0462] 12 Embedded Memory

[0463] 13 Buffer memory

[0464] 14. Host I / F

[0465] 15 NAND I / F

[0466] 16 ECC Circuit

[0467] 20 Memory devices

[0468] 21. Memory cell array

[0469] 22 Input / Output Circuits

[0470] 23 Logic Control Circuit

[0471] 24 registers

[0472] 25 Sequencer

[0473] 26 Voltage Generation Circuit

[0474] 27-line decoder module

[0475] 28 Sensing Amplifier Module

[0476] 101 Tracking Control Unit

[0477] 102 Read control unit

[0478] 103 Marker Generation Unit

[0479] 104 Bar Chart Calculation Unit

[0480] 131 Read Data Memory Unit

Claims

1. A memory system, comprising: A semiconductor memory includes a plurality of memory cells, each memory cell being configured to store data having at least one of a first value and a second value according to its threshold voltage, the first value corresponding to the threshold voltage being included in a first voltage range and the second value corresponding to the threshold voltage being included in a second voltage range. as well as The controller is configured as The data having the first value is written into each of the plurality of first memory cells. The data having the second value is written into each of the plurality of second memory cells. By performing a tracking process on the plurality of memory cells, the first voltage is determined, and During the read process following the tracking process, data is read from the plurality of memory cells using the first voltage. The controller is configured to, during the tracking process, Multiple read operations are performed using multiple read voltages within a third voltage range, which includes a portion of the first voltage range and a portion of the second voltage range, to determine a first distribution of the plurality of memory cells. Based on the first distribution, a second distribution of the plurality of first memory primitives within the third voltage range is estimated. Based on the difference between the first distribution and the second distribution, a third distribution of the plurality of second memory primitives within the third voltage range is calculated, and Based on the second distribution and the third distribution, the voltage within the third voltage range is determined as the first voltage.

2. The memory system of claim 1, wherein, The controller is configured to Based on the first distribution included in the fourth voltage range within the third voltage range, the fourth distribution is estimated. Based on the fourth distribution, estimate a fifth distribution within a fifth voltage range that is included in the third voltage range but different from the fourth voltage range, and The second distribution is estimated based on the fourth and fifth distributions.

3. The memory system of claim 2, wherein, The controller is configured to estimate the fourth distribution by performing curve fitting on the first distribution within the fourth voltage range.

4. The memory system of claim 3, wherein, The controller is configured to determine a first function by performing a least-squares method for the curve fitting, and to estimate the fourth distribution based on the first function.

5. The memory system of claim 4, wherein, The controller is configured to estimate the fifth distribution based on voltage values ​​included in the fourth voltage range and constants determined to correspond to the first function.

6. The memory system of claim 2, wherein, The first voltage range includes voltages lower than the second voltage range, and The fourth voltage range includes voltages lower than the fifth voltage range.

7. The memory system of claim 2, wherein, The first voltage range includes voltages higher than the second voltage range, and The fourth voltage range includes voltages that are higher than the fifth voltage range.

8. The memory system of claim 1, wherein, The controller is configured to perform a determination process to determine whether to determine the first voltage.

9. The memory system of claim 8, wherein, The controller is configured to, during the determination process: Calculate the first number of conducting primitives, which is the number of third memory primitives that become conducting when a read process is performed on the plurality of memory primitives using a third voltage included in the first voltage range or the second voltage range. Determine whether to determine the first voltage based on the first number of conducting elements.

10. The memory system of claim 9, wherein The third voltage is the minimum read voltage used to perform the read process on the plurality of memory cells, and The controller determines that the first voltage will be determined when the number of the first conducting primitives is less than the first threshold, and determines that the first voltage will not be determined when the number of the first conducting primitives is equal to or greater than the first threshold.

11. The memory system according to claim 8, wherein, The controller is configured to, during the determination process: Based on the shape of the second distribution within a sixth voltage range included in the third voltage range, determine whether the second distribution exhibits a decreasing trend with increasing read voltage, and When the second distribution within the sixth voltage range shows a decreasing trend as the read voltage increases, the first voltage is determined.

12. The memory system of claim 8, wherein, The controller is configured to, during the determination process: Determine whether the maximum number of times the second distribution, included in the sixth voltage range within the third voltage range, continuously decreases with increasing read voltage is equal to or greater than a first determined value, and When the maximum number of times is equal to or greater than the first determined value, the first voltage will be determined.

13. The memory system of claim 8, wherein, The controller is configured to, during the determination process: Determine whether the total number of times the second distribution, included in the sixth voltage range within the third voltage range, decreases with increasing read voltage is equal to or greater than a second determined value, and When the total number of times is equal to or greater than the second determined value, the first voltage will be determined.

14. The memory system of claim 8, wherein, The controller is configured to, during the determination process: Determine whether the overlap between the second and third distributions is asymmetrical with respect to the read voltage, and When the overlap between the second distribution and the third distribution is asymmetrical with respect to the read voltage, it is determined that the first voltage will be determined.

15. A method for determining an optimal read voltage for a semiconductor memory, the semiconductor memory comprising a plurality of memory cells, each memory cell configured to store data having at least one of a first value and a second value according to its threshold voltage, the first value corresponding to the threshold voltage included in a first voltage range, the second value corresponding to the threshold voltage included in a second voltage range, the method comprising: Perform a first write operation to write data having the first value into each of the plurality of first memory cells; Perform a second write operation to write data having the second value into each of the plurality of second memory cells; as well as The optimal read voltage is determined by performing a tracking process on the plurality of memory cells. The tracking process includes: Multiple read operations are performed using multiple read voltages within a third voltage range, which includes a portion of the first voltage range and a portion of the second voltage range, to determine a first distribution of the plurality of memory cells. Based on the first distribution, a second distribution of the plurality of first memory primitives within the third voltage range is estimated. Based on the difference between the first distribution and the second distribution, a third distribution of the plurality of second memory cells within the third voltage range is calculated; and Based on the second distribution and the third distribution, the voltage within the third voltage range is determined as the optimal reading voltage.

16. The method of claim 15, wherein, The tracking process also includes: Based on the first distribution included in the fourth voltage range within the third voltage range, the fourth distribution is estimated. Based on the fourth distribution, estimate a fifth distribution within a fifth voltage range that is included in the third voltage range but different from the fourth voltage range, and The second distribution is estimated based on the fourth and fifth distributions.

17. The method of claim 16, wherein, The fourth distribution is estimated by performing curve fitting on the first distribution within the fourth voltage range.

18. The method according to claim 17, wherein, The fourth distribution is estimated based on a first function determined by performing a least-squares method for the curve fitting.

19. The method of claim 16, wherein, The first voltage range includes voltages lower than the second voltage range, and The fourth voltage range includes voltages lower than the fifth voltage range.

20. The method of claim 16, wherein, The first voltage range includes voltages higher than the second voltage range, and The fourth voltage range includes voltages that are higher than the fifth voltage range.

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