Memory and method of reading memory

Abstract

The present application provides a memory including a selected memory cell block and a first sense amplifier. The selected memory cell block and the first sense amplifier are coupled to a first common bit line. The first sense amplifier is configured to: in a leakage current detection mode, detect a leakage current of the selected memory cell block on the first common bit line to generate leakage current information; and in a data read mode, provide a reference signal based on the leakage current information, and generate read data by comparing a read signal on the first common bit line with the reference signal, wherein the leakage current detection mode occurs before the data read mode.

Description

Technical Field

[0001] This invention relates to a memory and a method for reading the memory, and more particularly to a memory capable of compensating for leakage current and a method for reading the memory. Background Technology

[0002] In flash memory, the erasure process of a storage cell can be paused for various reasons, resulting in incomplete erasure. This can cause leakage current to occur in unselected storage cells during read operations, such as... Figure 1 This is a schematic diagram of a known memory read operation. Memory cell MC2 is a memory cell that has not yet been erased. When memory 100 performs a read operation on the common bit line GBL, and memory cell MC1 is selected while memory cell MC2 is not selected, memory cells MC1 and MC2 will respectively provide read current IC and leakage current IL. Therefore, the sensing operation for reading data based on the total current value on the common bit line GBL may be erroneous due to interference from the leakage current IL, leading to incorrect read data. Summary of the Invention

[0003] According to an embodiment of the present invention, the memory includes a selected memory cell block and a first sensing amplification device. Both the selected memory cell block and the first sensing amplification device are coupled to a first common bit line. The first sensing amplification device is used to: in a leakage current sensing mode, sense the leakage current of the selected memory cell block on the first common bit line to generate leakage current information; and in a read data mode, provide a reference signal based on the leakage current information, and generate read data by comparing a read signal on the first common bit line with the reference signal, wherein the leakage current sensing mode occurs before the read data mode.

[0004] According to an embodiment of the present invention, a memory read method includes: providing a first sensing amplification device to be coupled to a first common bit line; in a leakage current sensing mode, causing the first sensing amplification device to sense leakage current of a selected memory cell block on the first common bit line to generate leakage current information; in a read data mode, causing the first sensing amplification device to provide a reference signal based on the leakage current information, and generating read data by comparing a read signal on the first common bit line with the reference signal, wherein the leakage current sensing mode occurs before the read data mode.

[0005] Based on the above, before performing a read operation, the memory of the present invention can first perform a leakage current sensing operation on the shared bit line to obtain leakage current information. Furthermore, during the data read operation, compensation is performed based on the leakage current information to obtain accurate read data. Attached Figure Description

[0006] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0007] Figure 1 A schematic diagram of a known memory read operation;

[0008] Figure 2 This is a schematic diagram of a memory according to an embodiment of the present invention;

[0009] Figure 3 This is a schematic diagram illustrating an embodiment of the memory according to another embodiment of the present invention;

[0010] Figure 4 This is a flowchart illustrating the process of obtaining leakage current information in a memory according to an embodiment of the present invention.

[0011] Figure 5 This is a timing diagram of the memory read operation according to an embodiment of the present invention.

[0012] Figure 6A as well as Figure 6B This is a schematic diagram illustrating multiple implementations of the leakage current sensing mode of the memory according to an embodiment of the present invention;

[0013] Figure 7A as well as Figure 7B This is a schematic diagram illustrating multiple implementations of the data reading mode of the memory according to an embodiment of the present invention;

[0014] Figure 8 This is a flowchart illustrating the memory read operation according to an embodiment of the present invention.

[0015] Explanation of icon numbers

[0016] 200, 300, 601, 602, 701, 702: Memory;

[0017] 210, 310, SMC: Select the storage cell block;

[0018] 220, 320, 721: Sensing amplification devices;

[0019] 311~31n: Divisions;

[0020] 321: Proportional controller;

[0021] 322, SA~SA': Sensing amplifier;

[0022] 611, 612: Memory cell array;

[0023] 621, 622: Proportional controllers;

[0024] CR: Comparison results;

[0025] DOUT: Read data;

[0026] GBL: Common Baseline;

[0027] IE~IE': Input end;

[0028] IL: Leakage current;

[0029] ILD: Leakage current information;

[0030] IR: Current reference signal;

[0031] ISET: Set signal;

[0032] ITH: Critical signal;

[0033] MC1, MC2, MC1~MCn+i-1: storage units;

[0034] RS: Read signal;

[0035] S410~S450, S511~S532, S810~S830: Steps;

[0036] VR: Voltage reference signal;

[0037] WL[0]~WL[n+i-1]: Character lines. Detailed Implementation

[0038] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0039] Please refer to Figure 2 , Figure 2 This is a schematic diagram of a memory according to an embodiment of the present invention. The memory 200 includes a selected memory cell block 210 and a sensing amplification device 220. The selected memory cell block 210 has a plurality of memory cells and is commonly coupled to a common bit line GBL. The sensing amplification device 220 is coupled to the selected memory cell block 210 via the common bit line GBL. In this embodiment, when one or more memory cells in the selected memory cell block 210 are selected to perform a read operation, the sensing amplification device 220 can sense the leakage current of the selected memory cell block 210 on the common bit line GBL in a leakage current sensing mode to generate leakage current information. Then, in a read data mode, the sensing amplification device 220 can provide a reference signal based on the leakage current information and generate read data DOUT by comparing the read signal RS on the common bit line GBL with the reference signal.

[0040] In this embodiment, the leakage current sensing mode can occur before the data read mode. Furthermore, in the leakage current sensing mode, the multiple character line signals received by multiple memory cells corresponding to the common bit line GBL are all disabled. That is, in the leakage current sensing mode, all memory cells in the selected memory cell block 210 are in a non-accessible state. At this time, the sensing amplification device 220 can receive the leakage current IL generated on the common bit line GBL and generate leakage current information.

[0041] Furthermore, the sensing amplification device 220 can receive a setting signal ISET and adjust the setting signal ISET according to a setting ratio to generate a leakage current replication signal. The sensing amplification device 220 compares the leakage current replication signal with the leakage current IL on the common bit line GBL to generate a comparison result. If the initial value of the comparison result is a first logic level, the sensing amplification device 220 can perform the setting ratio adjustment operation while the comparison result remains at the first logic level, and perform the next comparison operation between the leakage current replication signal and the leakage current IL. Once the comparison result changes from the first logic level to the second logic level, the sensing amplification device 220 can record the current leakage current replication signal to generate leakage current information.

[0042] Incidentally, in other embodiments, the sensing amplification device 220 may also record the current set ratio to generate leakage current information.

[0043] In this embodiment, the setting signal ISET can be assumed to be a signal with a relatively high value. Under this condition, the sensing amplification device 220 can gradually decrease the setting ratio to compare the leakage current replication signal with the leakage current IL. In the initial stage, the leakage current replication signal can be greater than the leakage current IL, and the comparison result is at the first logic level. As the setting ratio decreases, the leakage current replication signal can be adjusted to be less than or equal to the leakage current IL, and the sensing amplification device 220 can generate a comparison result at the second logic level. At this time, the leakage current replication signal is closest to the leakage current IL.

[0044] Alternatively, the setting signal ISET can be set to a relatively low value by default. Under this condition, the sensing amplification device 220 can gradually increase the set ratio to compare the leakage current replication signal with the leakage current IL. In the initial stage, the leakage current replication signal can be less than the leakage current IL, and the comparison result is at the first logic level. As the set ratio increases, the leakage current replication signal can be adjusted to be greater than or equal to the leakage current IL, and the sensing amplification device 220 can generate a comparison result at the second logic level. At this time, the leakage current replication signal can also be the state closest to the leakage current IL.

[0045] Furthermore, the first logic level mentioned above can be logic 1 or logic 0, and the second logic level mentioned above can be logic 0 or 1, which are complementary to the first logic level, without any fixed restrictions.

[0046] After the leakage current sensing mode is completed, the memory 100 can enter the read data mode. In the read data mode, a selected character line in the selected memory cell block 210 can be enabled, while at least one of the remaining unselected character lines is disabled. At this time, the selected memory cell in the selected memory cell block 210 can provide a read signal RS on the common bit line GBL.

[0047] On the other hand, in the data readout mode, the sensing amplification device 220 can generate a reference signal based on leakage current information. Furthermore, the sensing amplification device 220 can compare the readout signal RS with the reference signal and generate readout data DOUT. As can be seen from the above description, since the reference signal generated by the sensing amplification device 220 in this embodiment of the invention is generated after compensation based on leakage current information, the readout data DOUT generated by the sensing amplification device 220 can be free from interference from leakage current generated by the memory cells in the selected memory cell block 210. This effectively improves the accuracy of the readout data DOUT.

[0048] Please refer to the following: Figure 3 , Figure 3 This is a schematic diagram illustrating an embodiment of the memory according to another embodiment of the present invention. The memory 300 includes a selected memory cell block 310 and a sensing amplification device 320. The selected memory cell block 310 can be divided into multiple sectors 311 to 31n. The multiple sectors 311 to 31n of the selected memory cell block 310 share the same shared bit line GBL. The selected memory cell block 310 has multiple memory cells MC1 to MCn+i-1. The memory cells MC1 to MCn+i-1 are respectively coupled to character lines WL[0] to WL[n+i-1]. The source terminals of the memory cells MC1 to MCn+i-1 are also commonly coupled to the ground voltage GND.

[0049] The sensing amplification device 320 includes a proportional controller 321 and a sensing amplifier 322. The sensing amplifier 322 has a first input terminal coupled to a common bit line GBL and a second input terminal coupled to the proportional controller 321. The proportional controller 321 receives a setting signal ISET and adjusts the setting signal ISET according to a set ratio to generate a leakage current replication signal. The proportional controller 321 can also adjust the aforementioned set ratio based on the comparison result CR generated by the sensing amplifier 322.

[0050] In the leakage current sensing mode, the character lines WL[0] to WL[n+i-1] are all disabled. The sensing amplifier 320 compares the leakage current copy signal provided by the proportional controller 321 with the leakage current IL on the common character line GBL. The proportional controller 321 gradually adjusts the value of the set ratio based on the comparison result CR generated by the sensing amplifier 322, thereby obtaining leakage current information.

[0051] The implementation details regarding the method for obtaining leakage current information are as described above. Figure 1 The examples have been described in detail and will not be repeated here.

[0052] On the other hand, in the data read mode, one of the selected character lines WL[0] to WL[n+i-1] is enabled (the remaining unselected character lines are disabled). The selected memory cell can provide a read signal RS to the common character line GBL based on the stored data and the leakage current IL. At the same time, the sensing amplifier 320 can generate a reference signal based on the leakage current information obtained in the leakage current sensing mode, and the sensing amplifier 322 compares the read signal RS with the reference signal to generate read data DOUT.

[0053] Note that since the reference signal is generated based on leakage current information, the leakage current IL portion of the read signal RS can be eliminated when the sense amplifier 322 compares the read signal RS with the reference signal. In this way, the sense amplifier 322 can generate correct readout data DOUT.

[0054] Please refer to the following: Figure 4 , Figure 4 This is a flowchart illustrating the operation of obtaining leakage current information in a memory according to an embodiment of the present invention. In the leakage current sensing mode, in step S410, the value of the setting signal can be set during wafer testing through a test procedure trimming mechanism. The setting signal can be set to a signal with a relatively large value. In this embodiment, the setting signal can be a current signal. Regarding the test procedure trimming mechanism, it can be implemented by blowing (or not blowing) an electronic fuse, or by utilizing test procedure trimming techniques well-known to those skilled in the art; there are no particular limitations.

[0055] In step S420, the setting ratio is adjusted. In this embodiment, the setting signal can be set to a signal with a relatively large value, and the setting ratio can be a value equal to 1. Using the setting signal and the setting value, the sensing amplification device in this embodiment can generate a leakage current replication signal and compare it with the leakage current on the common bit line, generating a comparison result in step S430.

[0056] In step S440, it is determined whether the comparison result is equal to the initial value (e.g., logic 0). If the result is yes, step S420 is re-executed to further reduce the set ratio. If the result is no, the set ratio can be recorded to obtain leakage current information (step S450).

[0057] Incidentally, step S410 in this embodiment can also be adjusted to a relatively small setting signal through the test process adjustment mechanism. In this way, the setting ratio in step S420 can be adjusted to a value less than 1. And after the judgment result in step S440 is yes, step S420 can further increase the setting ratio.

[0058] Please refer to the following: Figure 5 , Figure 5 This is a timing diagram of the read operation of the memory according to an embodiment of the present invention. First, for the common bit line GBL of the first selected memory cell block, the steps of read data sensing S511 and data buffering S512 are executed sequentially. The corresponding character line signal WL can be enabled (pulled up to a high voltage), and a voltage value corresponding to the read data is generated on the corresponding common bit line GBL. Next, for the common bit line GBL' of the second selected memory cell block, the steps of leakage current sensing S521, read data sensing S522, and data buffering S523 are executed sequentially. During the leakage current sensing S521 step, the corresponding character line signal WL is disabled. During the read data sensing S522 step, the voltage on the character line signal WL is pulled up and enabled. Correspondingly, the common bit line GBL does not operate and is at a low voltage, while the common bit line GBL' generates a voltage change corresponding to the leakage current sensing S521 step and the read data sensing S522 step.

[0059] It is worth mentioning that while the leakage current sensing S521, read data sensing S522, and data buffering S523 steps are executed sequentially, the data read from the first selected memory cell block can be transmitted via the data sequence output S513 step. The data sequence output S513 step and the leakage current sensing S521, read data sensing S522, and data buffering S523 steps can be executed synchronously. The total time required for the data sequence output S513 step is exactly enough to execute all the actions of the leakage current sensing S521, read data sensing S522, and data buffering S523 steps. In other words, the leakage current sensing S521 step does not require extra time to execute, effectively maintaining the memory's data read rate.

[0060] Next, for the common bit line GBL'' of the third selected memory cell block, steps such as leakage current sensing S531 and read data sensing S532 are executed sequentially. Simultaneously, data sequence output S524 is executed to transmit the read data obtained from the second selected memory cell block. The read operation for the third selected memory cell block is similar to the read operation for the third selected memory cell block, and will not be described in detail here.

[0061] In this embodiment, it can be seen that by operating in the leakage current sensing mode, the leakage current phenomenon can be effectively compensated without increasing the memory read time, so as to ensure the correctness of the read data.

[0062] Please refer to Figure 6A as well as Figure 6B , Figure 6A as well as Figure 6B This is a schematic diagram illustrating multiple embodiments of the leakage current sensing mode of the memory according to an embodiment of the present invention. Figure 6A In this embodiment, the memory 601 includes a memory cell array 611. The memory cell array 611 has multiple memory cell blocks, and multiple sensing amplifiers SA~SA' are configured corresponding to the multiple memory cell blocks. The sensing amplifiers SA~SA' are respectively coupled to common bit lines GBL~GBL'. In this embodiment, a leakage current replication signal is generated by multiplying a set ratio with a set signal ISET using a proportional controller 621. The leakage current replication signal is a current signal, and multiple mirrored leakage current replication signals can be generated by the mirroring action of a current mirror circuit and transmitted to the multiple sensing amplifiers SA~SA'. In this way, by comparing the results of the multiple sensing amplifiers SA~SA' and by gradually adjusting the set ratio with the proportional controller 621, the leakage current information of the multiple memory cell blocks corresponding to the common bit lines GBL~GBL' can be calculated one by one, quickly completing the leakage current sensing action.

[0063] exist Figure 6B In this embodiment, the memory 602 includes a memory cell array 612. The memory cell array 612 has multiple memory cell blocks, and multiple sensing amplifiers SA~SA' are configured corresponding to the multiple memory cell blocks. The sensing amplifiers SA~SA' are respectively coupled to common bit lines GBL~GBL'. In this embodiment, a leakage current replication signal is generated by multiplying a set ratio by a set signal ISET using a proportional controller 622. The leakage current replication signal can be a voltage signal, which is transmitted to the multiple sensing amplifiers SA~SA' via transmission lines. In this way, by comparing the results of the multiple sensing amplifiers SA~SA' and by gradually adjusting the set ratio with the proportional controller 621, the leakage current information of the multiple memory cell blocks corresponding to the common bit lines GBL~GBL' can be calculated one by one, quickly completing the leakage current sensing operation.

[0064] Please refer to Figure 7A as well as Figure 7B , Figure 7A as well as Figure 7B This is a schematic diagram illustrating multiple embodiments of the data reading mode of the memory according to an embodiment of the present invention. Figure 7A In this embodiment, memory 701 includes a selected memory cell block 711 and a sensing amplifier 721. In read data mode, the memory cell SMC is the selected memory cell, and a read signal RS is transmitted on the common bit line GBL. One end of the sensing amplifier SA receives the read signal RS, and the other end receives a reference signal combining a threshold signal ITH and leakage current information ILD. In this embodiment, the read signal RS, the threshold signal ITH, and the leakage current information ILD are all current signals. The leakage current information ILD can be used to offset the error in the read signal RS caused by leakage current, effectively improving the accuracy of the read data DOUT.

[0065] exist Figure 7B In this embodiment, memory 702 includes a memory cell array 712 and multiple sense amplifiers SA~SA'. The memory cell array 712 has multiple memory cell blocks, each coupled to multiple common bit lines GBL~GBL'. In read data mode, sense amplifiers SA~SA' receive read signals generated by the common bit lines GBL~GBL' respectively, and also receive a common reference signal. In this embodiment, the reference signal can be a current reference signal IR or a voltage reference signal VR.

[0066] When the reference signal is a current reference signal IR, a current mirror circuit can be set on the input terminals IE~IE' of the sensing amplifiers SA~SA'. Each current mirror circuit at the input terminals IE~IE' can have a different mirror ratio, with multiple mirror ratios equivalent to multiple weight values, each corresponding to multiple leakage current information on the common bit lines GBL~GBL'. The leakage current information can be generated in the leakage current sensing mode.

[0067] When the reference signal is a voltage reference signal IR, an adjustable input impedance device can be provided on the input terminals IE~IE' of the sensing amplifiers SA~SA', such as an adjustable load or adjusting the size of the transistors on the input terminals IE~IE' of the sensing amplifiers SA~SA'. This provides multiple weighted values ​​corresponding to multiple leakage current information on the common bit lines GBL~GBL'. The leakage current information can also be generated in leakage current sensing mode.

[0068] Please refer to the following: Figure 8 , Figure 8This is a flowchart of a memory read operation according to an embodiment of the present invention. In step S810, a first sensing amplification device is provided and coupled to a first common bit line. In step S820, in leakage current sensing mode, the first sensing amplification device senses the leakage current of the selected memory cell block on the first common bit line to generate leakage current information. Next, in step S830, in read data mode, the first sensing amplification device provides a reference signal based on the leakage current information, and read data is generated by comparing the read signal on the first common bit line with the reference signal.

[0069] The implementation details of the above steps have been described in detail in the foregoing embodiments, and will not be repeated here.

[0070] In summary, the memory of the present invention senses leakage current information on the common bit line through a leakage current sensing mode during the read operation, and compensates for leakage current based on the leakage current information during the data read mode, effectively ensuring the accuracy of the read data.

[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory, comprising: Select the memory cell block and couple it to the first common bit line; as well as A first sensing amplification device, coupled to the first common bit line, is used to: In the leakage current sensing mode, the leakage current of the selected memory cell block on the first common bit line is sensed to generate leakage current information; In read data mode, a reference signal is provided based on the leakage current information, and read data is generated by comparing the read signal on the first common bit line with the reference signal. The leakage current sensing mode occurs before the data reading mode. The first sensing amplification device includes: A first sensing amplifier has a first input terminal coupled to the first common bit line; as well as A proportional controller, coupled to the second input terminal of the sensing amplifier, receives a setting signal and adjusts the setting signal according to a set ratio to generate a leakage current replication signal. In the leakage current sensing mode, the first sensing amplifier compares the leakage current on the first common bit line with the leakage current copy signal to generate a comparison result, and the proportional controller adjusts the set ratio based on the comparison result. When the comparison result changes from the first logic level to the second logic level, the leakage current replication signal is equal to the leakage current information.

2. The memory according to claim 1, wherein in the leakage current sensing mode, all character lines corresponding to the selected memory cell block are disabled.

3. The memory according to claim 2, wherein in the read data mode, one of the selected character lines of the plurality of character lines is enabled, and at least one unselected character line of the plurality of character lines is disabled.

4. The memory according to claim 1, wherein the setting signal, the leakage current copy signal, and the reference signal are all current signals.

5. The memory according to claim 4, further comprising: The second sensing amplifier is coupled to the second common bit line; as well as A current mirror, coupled between the first sensing amplifier and the second sensing amplifier, mirrors the leakage current replica signal in the leakage current sensing mode to generate a mirrored leakage current replica signal transmitted to the second sensing amplifier.

6. The memory according to claim 1, further comprising: A current mirror, disposed at the input terminal of the first sensing amplifier, in the data reading mode, mirrors the set signal according to the leakage current information to generate the reference signal, wherein the leakage current information is a current signal.

7. The memory of claim 1, wherein the reference signal is a voltage signal, and in the data read mode, the sensing amplifier adjusts the impedance at its input to generate the reference signal based on the leakage current information.

8. The memory of claim 1, wherein in the data read mode, the sensing amplification device combines the leakage current information with a default threshold signal to generate the reference signal.

9. A method for reading from a memory, comprising: A first sensing amplification device is provided to be coupled to a first common bit line; In the leakage current sensing mode, the first sensing amplification device senses the leakage current of the selected memory cell block on the first common bit line to generate leakage current information. as well as In the data readout mode, the first sensing amplification device provides a reference signal based on the leakage current information, and readout data is generated by comparing the readout signal on the first common bit line with the reference signal. The leakage current sensing mode occurs before the data reading mode. The steps for generating the leakage current information include: Couple the first input terminal of the first sensing amplifier to the first common bit line; A proportional controller is provided to couple to the second input of the sense amplifier; The proportional controller receives a setting signal and adjusts the setting signal according to the setting ratio to generate a leakage current replication signal. In the leakage current sensing mode, the first sensing amplifier compares the leakage current on the first common bit line with the leakage current replica signal to generate a comparison result, and the proportional controller adjusts the set ratio based on the comparison result; and When the comparison result changes from the first logic level to the second logic level, the leakage current copy signal is made equal to the leakage current information.

10. The method for reading the memory according to claim 9, further comprising: In the leakage current sensing mode, all character lines corresponding to the selected memory cell block are disabled.

11. The method for reading the memory according to claim 10, further comprising: In the data reading mode, one of the selected character lines of the plurality of character lines is enabled, and at least one unselected character line of the plurality of character lines is disabled.

12. The memory reading method according to claim 9, wherein the setting signal, the leakage current copy signal, and the reference signal are all current signals.

13. The memory reading method according to claim 12, further comprising: The current mirror is coupled between the first sensing amplifier and the second sensing amplifier; as well as The current mirror generates a mirror reference signal that is transmitted to the second sensing amplifier based on the mirror ratio and the leakage current information.

14. The memory read method according to claim 9, wherein the first sensing amplifier converts the leakage current on the first common bit line into a first voltage signal, and the reference signal is a second voltage signal.

15. The method for reading a memory according to claim 14, further comprising: In the data readout mode, the impedance at the input of the first sensing amplifier is adjusted to generate the reference signal based on the leakage current information.

16. The method for reading the memory according to claim 9, further comprising: In the data reading mode, the reference signal is generated by combining the leakage current information with the default critical signal.

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