Display device

Abstract

A display apparatus includes a substrate including a first display area having a first width, a second display area having a second width smaller than the first width, a surrounding area located around the first display area and the second display area, and a dummy area located in the surrounding area; first pixels located in the first display area; second pixels located in the second display area; first control lines connected to the first pixels and extending in the first display area; second control lines connected to the second pixels and extending in the second display area; and a dummy line connected to the second control lines and located in the dummy area, wherein the second control lines are located at a first conductive layer on a first insulating layer, and the dummy line is located at a second conductive layer on a second insulating layer on the first conductive layer.

Description

[0001] This application is a divisional application of the invention filed on November 29, 2017, with application number 201711225931.1 and titled "Display Device".

[0002] Cross-references to related applications

[0003] This application claims priority and benefit to Korean Patent Application No. 10-2016-0160814, filed with the Korean Intellectual Property Office on November 29, 2016, the entire disclosure of which is incorporated herein by reference. Technical Field

[0004] One aspect of this disclosure relates to a display device. Background Technology

[0005] The display device includes an active region for displaying an image. The active region includes multiple pixels for emitting light with a brightness corresponding to the input data and multiple lines for transmitting drive signals to the pixels.

[0006] Recently, with the increasing demand for display devices of various shapes, the shape of the active area has been implemented in various ways. Therefore, even within the active area, the line length can be different for each area. If the line lengths are different, the lines have different load values. Consequently, brightness deviations may occur between pixels at different locations within the active area, and these brightness deviations can cause image quality degradation. Summary of the Invention

[0007] An aspect of the embodiments of this disclosure relates to a display device having a structure that is protected from electrostatic discharge (ESD) while displaying an image with uniform image quality.

[0008] According to one aspect of this disclosure, a display device is provided, comprising: a substrate, including a first display area having a first width in a first direction, a second display area having a second width in the first direction less than the first width, a surrounding area surrounding the first display area and the second display area, and a dummy area located in the surrounding area; a first pixel located in the first display area; a second pixel located in the second display area; a first control line connected to the first pixel, the first control line extending in the first display area along a first direction; a second control line connected to the second pixel, the second control line extending in the second display area along the first direction; and a dummy line connected to the second control line, the dummy line located in the dummy area, wherein the second control line is located at a first conductive layer on a first insulating layer, the first insulating layer being located on the substrate, and the dummy line is located at a second conductive layer on a second insulating layer, the second insulating layer being located on the first conductive layer.

[0009] In some embodiments, the display device further includes a conductive bridge connecting the second control line and the dummy line.

[0010] In some embodiments, the conductive bridge is located on one side of the second display area.

[0011] In some embodiments, the conductive bridge is located on one side of the dummy region.

[0012] In some embodiments, the second pixel is connected to multiple second control lines to which different signals are applied, and multiple dummy lines connected to different second control lines among the multiple second control lines are in the dummy region.

[0013] In some embodiments, the second control line and the corresponding dummy line among the plurality of second control lines and the plurality of dummy lines are connected to each other through one of the first conductive bridges located on one side of the second display area, and another second control line and another dummy line corresponding to the other second control line among the plurality of second control lines and the plurality of dummy lines are connected to each other through one of the second conductive bridges located on one side of the dummy area.

[0014] In some embodiments, the dummy line among the plurality of dummy lines connected to the first conductive bridge located on one side of the second display area and the dummy line among the plurality of dummy lines connected to the second conductive bridge located on one side of the dummy area are arranged alternately in the dummy area.

[0015] In some embodiments, the display device further includes a power line located in the surrounding area, the power line at least partially overlapping the dummy line.

[0016] In some embodiments, the power line includes: an active pattern located between a substrate and a first insulating layer; and a main bus located at a third conductive layer on a third insulating layer, the third insulating layer being located on a second conductive layer, the main bus being connected to the active pattern through a contact opening.

[0017] In some embodiments, the thickness of the third insulating layer is greater than the thickness of the first insulating layer and the thickness of the second insulating layer.

[0018] In some embodiments, the thickness of the third insulating layer is equal to or greater than the sum of the thickness of the first insulating layer and the thickness of the second insulating layer.

[0019] In some embodiments, the power line includes: a plurality of active patterns located between a substrate and a first insulating layer, the plurality of active patterns extending in a direction intersecting with a dummy line; a main bus located at a third conductive layer on a third insulating layer, the third insulating layer being located on a second conductive layer, the main bus overlapping the active patterns; and a plurality of contact openings located at the edge of the dummy region, the plurality of contact openings facilitating electrical connection between the active patterns and the main bus.

[0020] In some embodiments, the second pixel includes at least one transistor connected to the second control line.

[0021] In some embodiments, the transistor includes: an active pattern located between a substrate and a first insulating layer; a source electrode and a drain electrode connected to the active pattern; and a gate electrode located on a first conductive layer and overlapping the active pattern, the first conductive layer being located on the first insulating layer, and the gate electrode being connected to a second control line.

[0022] In some embodiments, the gate electrode is integrally connected to the second control line.

[0023] In some embodiments, the second pixel includes at least one capacitor, the capacitor including a first electrode located at a first conductive layer and a second electrode located at a second conductive layer.

[0024] In some embodiments, the second control line includes at least one of the scan line, the light emission control line, and the initialization control line of the second pixel.

[0025] In some embodiments, the first pixel and the second pixel have the same structure.

[0026] In some embodiments, the surrounding area includes a first surrounding area surrounding at least one area in the first display area and a second surrounding area surrounding at least one area in the second display area, and the dummy area is located in the second surrounding area.

[0027] In some embodiments, the display device further includes: a third display area having a third width less than the first width in a first direction; a third pixel located in the third display area; a third control line connected to the third pixel, the third control line extending in the third display area along the first direction; and a dummy line connected to the third control line, the dummy line located in the dummy area.

[0028] In some embodiments, the second control line and the dummy line are formed of the same material. Attached Figure Description

[0029] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, these embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be exhaustive and comprehensive, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0030] In the accompanying drawings, dimensions may be exaggerated for clarity. Throughout the text, the same reference numerals refer to the same elements.

[0031] Figure 1 and Figure 2 The illustration shows a display device according to an embodiment of the present disclosure.

[0032] Figure 3 Illustration Figure 1 An embodiment of the display area and driver in the display device shown.

[0033] Figure 4 The illustration shows a first pixel according to an embodiment of the present disclosure.

[0034] Figure 5 Illustration Figure 4 The detailed structure of the first pixel embodiment shown is illustrated.

[0035] Figure 6 The diagram shows along Figure 5 The cross section intercepted by line I-I'.

[0036] Figure 7 The diagram shows along Figure 5 The cross section intercepted by line II-II'.

[0037] Figure 8 Illustration Figure 1 The detailed structure of the second pixel and the dummy region corresponding to region P1 shown in the embodiment.

[0038] Figure 9 The diagram shows the following: Figure 8 The cross section intercepted by line III-III'.

[0039] Figure 10 The diagram shows the following: Figure 8 The cross section intercepted by line IV-IV'.

[0040] Figure 11 Illustration Figure 1 The detailed structure of the second pixel and the dummy region corresponding to region P1 shown in the embodiment.

[0041] Figure 12 Illustration Figure 1 An embodiment of the detailed structure of the second pixel and the dummy region corresponding to region P1 is shown. Detailed Implementation

[0042] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, the present disclosure is not limited to the various embodiments, but may be implemented in different forms. These embodiments are provided for illustrative purposes and to enable those skilled in the art to fully understand the scope of the present disclosure.

[0043] In the following embodiments and figures, elements not directly related to this disclosure may be omitted from the figures, and the dimensional relationships between individual elements in the figures are illustrated for ease of understanding only and do not limit the actual scale. It should be noted that when giving reference numerals to elements in each figure, although the same reference numerals are shown in different figures, the same reference numerals refer to the same elements.

[0044] Figure 1 and Figure 2 The illustration shows a display device according to an embodiment of the present disclosure. Figure 2 yes Figure 1 The modifications are illustrated, and embodiments in which, for example, the shapes of the substrate and the active region are modified are shown.

[0045] refer to Figure 1 and Figure 2 The display device according to an embodiment of the present disclosure includes: a substrate SUB including a plurality of display areas PXA1, PXA2 and PXA3 (hereinafter referred to as "PXA"), a surrounding area PPA1, PPA2 and PPA3 (hereinafter referred to as "PPA"), and at least one dummy area DMP provided in at least some of the surrounding areas PPA; pixels PXL1, PXL2 and PXL3 (hereinafter referred to as "PXL") provided in the display areas PXA; and drivers SDV1, SDV2, SDV3, EDV1, EDV2, EDV3 and DDV and power lines ELVDD and ELVSS provided in the surrounding areas PPA on the substrate SUB.

[0046] In some embodiments, the substrate SUB may be a glass substrate or a plastic substrate; however, this disclosure is not limited thereto. For example, the substrate SUB may be a flexible substrate, including polyethersulfone (PES), polyacrylate (PA), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC), cellulose triacetate (TAC), cellulose acetate propionate (CAP), and / or the like. In some examples, the substrate SUB may be a rigid substrate, including a material selected from glass or tempered glass. In some examples, the substrate SUB may be a substrate made of a transparent material, i.e., a transmissive substrate; however, this disclosure is not limited thereto.

[0047] In some embodiments, the substrate SUB may include multiple regions, and at least two of the regions may have different areas. For example, the substrate SUB may include first to third regions A1, A2, and A3, and the first region A1 may have a different area than the second region A2 and the third region A3. The second region A2 and the third region A3 may have the same area or different areas. This embodiment illustrates a case where the substrate SUB is divided into three regions A1, A2, and A3; however, the number of regions on the substrate SUB is not limited to this.

[0048] Each of the first to third regions A1, A2, and A3 can have various suitable shapes. For example, each of the first to third regions A1, A2, and A3 can be provided in various suitable shapes, such as polygons with multiple linear sides, shapes with curved sides such as circles or ellipses, and shapes with both linear and curved sides such as semicircles or semi-ellipses. Additionally, at least one of the first to third regions A1, A2, and A3 can have inclined, stepped, or curved corner portions. For example, as... Figure 2 As shown, at least one corner portion of the first to third regions A1, A2 and A3 may have an inclined slope corner.

[0049] In some embodiments, the display areas PXA1, PXA2, PXA3, drivers SDV1, SDV2, SDV3, EDV1, EDV2, EDV3 and DDV, power lines ELVDD and ELVSS and / or dummy area DMP contained in the first to third regions A1, A2 and A3 may have shapes corresponding to the shapes of the first to third regions A1, A2 and A3. That is, the shapes of the first to third regions A1, A2 and A3 and the components provided in the first to third regions A1, A2 and A3 are not particularly limited, and can be varied and implemented in suitable forms.

[0050] In some embodiments, the first to third regions A1, A2, and A3 may include one or more display regions PXA1, PXA2, and PXA3, and surrounding regions PPA1, PPA2, and PPA3 (hereinafter referred to as "PPA") are arranged around the display regions PXA1, PXA2, and PXA3 to be adjacent to the display regions PXA1, PXA2, and PXA3, respectively. That is, the display device according to embodiments of the present disclosure may include multiple display regions PXA1, PXA2, and PXA3. Pixels PXL1, PXL2, and PXL3 are provided in the display regions PXA1, PXA2, and PXA3, and the display regions PXA1, PXA2, and PXA3 constitute the active region (screen region) for displaying an image.

[0051] In some embodiments, display areas PXA1, PXA2, and PXA3 may be arranged continuously to form a continuous screen. In some embodiments, at least two of display areas PXA1, PXA2, and PXA3 may be arranged discretely (e.g., spaced apart from each other) using one or more surrounding areas PPA placed between them to form separate screens.

[0052] The surrounding area PPA is the region where no image is displayed and where no pixel PXL is provided (e.g., a region where no pixel exists). Some of the following may be provided in the surrounding area PPA: drivers SDV1, SDV2, SDV3, EDV1, EDV2, EDV3, and DDV for driving the pixel PXL; power lines ELVDD and ELVSS for applying power to the pixel PXL; lines connecting the pixel PXL to the drivers SDV1, SDV2, SDV3, EDV1, EDV2, EDV3, and DDV; and / or dummy areas DMP. The surrounding area PPA corresponds to the bezel in the final display device, and the width of the bezel may be determined based on the width of the surrounding area PPA.

[0053] In some embodiments, among the first to third regions A1, A2, and A3, the first region A1 may have the largest area. The first region A1 may include a first display region PXA1 for displaying an image and a first surrounding region PPA1 surrounding at least a portion of the first display region PXA1.

[0054] In some embodiments, the first display area PXA1 may be provided in a shape corresponding to the shape of the first area A1. In embodiments of this disclosure, at least one area of ​​the first display area PXA1 may have a first width W1 in a first direction DR1. In some embodiments, the first display area PXA1 may have a first length L1 in a second direction DR2 intersecting the first direction DR1. For example, the first display area PXA1 may be implemented in a quadrilateral shape having a lateral length corresponding to the first width W1 and a longitudinal length corresponding to the first length L1. However, the shape and / or size of the first display area PXA1 are not limited thereto. For example, when at least one area of ​​the first display area PXA1 is implemented in a curved, inclined, or stepped shape, the first display area PXA1 may have a width that gradually increases or decreases in the corresponding area.

[0055] Multiple first pixels PXL1 are provided in the first display area PXA1. The first pixels PXL1 can be implemented in various suitable shapes, and exemplary structures of the first pixels PXL1 will be described later.

[0056] In some embodiments, a first surrounding region PPA1 may be provided at at least one side of the first display area PXA1. In embodiments of this disclosure, the first surrounding region PPA1 surrounds the outer periphery of the first display area PXA1 and may be provided in a portion other than the portions where the second area A2 and the third area A3, which will be described later, are arranged. That is, the first surrounding region PPA1 may be provided around the first display area PXA1 to surround at least a portion of the first display area PXA1.

[0057] In some embodiments, the first surrounding region PPA1 may include a lateral portion extending in a first direction DR1 and a longitudinal portion extending in a second direction DR2. The longitudinal portion of the first surrounding region PPA1 may be provided in pairs, spaced apart from each other along the first direction DR1, using the first display region PXA1 disposed therebetween. For example, the longitudinal portions of the first surrounding region PPA1 may be provided in pairs on the left and right sides (or opposite sides) of the first display region PXA1.

[0058] At least one driver (e.g., a first scan driver SDV1 and a first light emission control driver EDV1) for driving the first pixel PXL1 may be provided in the first surrounding region PPA1. Although in this embodiment, the first scan driver SDV1 and the first light emission control driver EDV1 are provided on the substrate SUB, this disclosure is not limited thereto. For example, at least one of the first scan driver SDV1 and the first light emission control driver EDV1 may be provided outside the substrate SUB for electrical connection to the first pixel PXL1 via pad units. Alternatively, depending on the structure of the first pixel PXL1, the first light emission control driver EDV1 may not be provided. Figure 1 and Figure 2 The diagram already illustrates that each of the first scan driver SDV1 and the first light emission control driver EDV1 is provided on only one side of the first display area PXA1; however, this disclosure is not limited thereto. For example, in another embodiment, the first scan driver SDV1 and the first light emission control driver EDV1 may be arranged on both sides of the first display area PXA1. In some embodiments, the first scan driver SDV1 and the first light emission control driver EDV1 may be arranged on different sides of the first display area PXA1, respectively.

[0059] In some embodiments, the first surrounding region PPA1 may have a shape symmetrical with respect to the first display region PXA1; however, this disclosure is not limited thereto. For example, the width W4 of the first surrounding region PPA1 arranged to the left of the first display region PXA1 may be different from the width W5 of the first surrounding region PPA1 arranged to the right of the first display region PXA1.

[0060] In some embodiments, the second region A2 may include a second display region PXA2 for displaying an image and a second surrounding region PPA2 disposed around the second display region PXA2 to surround at least a portion of the second display region PXA2.

[0061] In some embodiments, the second display area PXA2 may be provided in a shape corresponding to the shape of the second area A2. In embodiments of this disclosure, at least one area of ​​the second display area PXA2 may have a second width W2 in a first direction DR1. In some embodiments, the second display area PXA2 may have a second length L2 in a second direction DR2 intersecting the first direction DR1. For example, the second display area PXA2 may be implemented in a quadrilateral shape having a lateral length corresponding to the second width W2 and a longitudinal length corresponding to the second length L2. However, the shape and / or size of the second display area PXA2 are not limited thereto. For example, when at least one area of ​​the second display area PXA2 is implemented in a curved, inclined, or stepped shape, the second display area PXA2 may have a width that gradually increases or decreases in the corresponding area.

[0062] In some embodiments, the second width W2 of the second display area PXA2 may be smaller than the first width W1 of the first display area PXA1. In some embodiments, the second length L2 of the second display area PXA2 may be smaller than the first length L1 of the first display area PXA1. That is, in some embodiments, the second display area PXA2 may have a smaller area than the first display area PXA1.

[0063] In some embodiments, the second display area PXA2 is provided in a shape that protrudes from the first display area PXA1 and is continuously connected to the first display area PXA1. That is, one side of the second display area PXA2 may contact one side of the first display area PXA1.

[0064] A plurality of second pixels PXL2 are provided in the second display area PXA2. In some embodiments, each of the second pixels PXL2 may be configured to be substantially the same as each of the first pixels PXL1; however, this disclosure is not limited thereto.

[0065] In some embodiments, a second surrounding region PPA2 may be provided at least one side of the second display region PXA2. In embodiments of this disclosure, the second surrounding region PPA2 surrounds the second display region PXA2 and may not be provided at the portion connecting the first display region PXA1 and the second display region PXA2. That is, the second surrounding region PPA2 may be arranged around the second display region PXA2 to surround at least a portion of the second display region PXA2. In some embodiments, the second surrounding region PPA2 may include a lateral portion extending in a first direction DR1 and a longitudinal portion extending in a second direction DR2. The longitudinal portion of the second surrounding region PPA2 may be provided in pairs, spaced apart from each other in the first direction DR1, using the second display regions PXA2 disposed therebetween. For example, the longitudinal portions of the second surrounding region PPA2 may be provided in pairs on the left and right sides (or opposite sides) of the second display region PXA2.

[0066] At least one driver (e.g., a second scan driver SDV2 and a second light emission control driver EDV2) for driving the second pixel PXL2 may be provided in the second surrounding region PPA2. Although in this embodiment the second scan driver SDV2 and the second light emission control driver EDV2 are provided on the substrate SUB, this disclosure is not limited thereto. For example, at least one of the second scan driver SDV2 and the second light emission control driver EDV2 may be provided outside the substrate SUB for electrical connection to the second pixel PXL2 via pad units. Alternatively, depending on the structure of the second pixel PXL2, the second light emission control driver EDV2 may not be provided. Figure 1 and Figure 2 The diagram already illustrates that each of the second scan driver SDV2 and the second light emission control driver EDV2 is provided on only one side of the second display area PXA2; however, this disclosure is not limited thereto. For example, in another embodiment, the second scan driver SDV2 and the second light emission control driver EDV2 may be arranged on both sides of the second display area PXA2. In some embodiments, the second scan driver SDV2 and the second light emission control driver EDV2 may be arranged on different sides of the second display area PXA2, respectively.

[0067] In some embodiments, the third region A3 may include a third display region PXA3 for displaying an image and a third surrounding region PPA3 arranged around the third display region PXA3 to surround at least a portion of the third display region PXA3.

[0068] In some embodiments, the third display area PXA3 may be provided in a shape corresponding to the shape of the third area A3. In embodiments of this disclosure, at least one area of ​​the third display area PXA3 may have a third width W3 in the first direction DR1. In some embodiments, the third display area PXA3 may have a third length L3 in the second direction DR2 intersecting the first direction DR1. For example, the third display area PXA3 may be implemented in a quadrilateral shape having a lateral length corresponding to the third width W3 and a longitudinal length corresponding to the third length L3. However, the shape and / or size of the third display area PXA3 are not limited thereto. For example, when at least one area of ​​the third display area PXA3 is implemented in a curved, inclined, or stepped shape, the third display area PXA3 may have a width that gradually increases or decreases in the corresponding area.

[0069] In some embodiments, the third width W3 of the third display area PXA3 may be smaller than the first width W1 of the first display area PXA1. In some embodiments, the third length L3 of the third display area PXA3 may be smaller than the first length L1 of the first display area PXA1. That is, in some embodiments, the third display area PXA3 may have a smaller area than the first display area PXA1.

[0070] In some embodiments, the third width W3 of the third display area PXA3 may be equal to the second width W2 of the second display area PXA2; however, this disclosure is not limited thereto. In some embodiments, the third length L3 of the third display area PXA3 may be equal to the second length L2 of the second display area PXA2; however, this disclosure is not limited thereto. That is, in some embodiments, the third display area PXA3 may have the same area as the second display area PXA2; however, this disclosure is not limited thereto.

[0071] In some embodiments, a third display area PXA3 is provided in a shape that protrudes from the first display area PXA1 and is continuously connected to the first display area PXA1. That is, one side of the third display area PXA3 may contact one side of the first display area PXA1. In some embodiments, the third display area PXA3 may be arranged to be spaced apart from the second display area PXA2 by a set or predetermined distance. For example, the second display area PXA2 may be provided in a shape that protrudes from the upper left side of the first display area PXA1, and the third display area PXA3 may be provided in a shape that protrudes from the upper right side of the first display area PXA1, and the second display area PXA2 and the third display area PXA3 may be connected by an additional surrounding area APA located between the first to third display areas PXA1, PXA2 and PXA3.

[0072] A plurality of third pixels PXL3 are provided in a third display area PXA3. In some embodiments, each of the third pixels PXL3 may be configured to be substantially identical to each of the first pixels PXL1 and / or the second pixels PXL2; however, this disclosure is not limited thereto.

[0073] In some embodiments, a third surrounding region PPA3 may be provided at least one side of the third display region PXA3. In embodiments of this disclosure, the third surrounding region PPA3 surrounds the third display region PXA3 and may not be provided at the portion connecting the first display region PXA1 and the third display region PXA3. That is, the third surrounding region PPA3 may be arranged around the third display region PXA3 to surround at least a portion of the third display region PXA3. In some embodiments, the third surrounding region PPA3 may include a lateral portion extending in a first direction DR1 and a longitudinal portion extending in a second direction DR2. The longitudinal portion of the third surrounding region PPA3 may be provided in pairs, spaced apart from each other in the first direction DR1, using the third display regions PXA3 disposed therebetween. For example, the longitudinal portions of the third surrounding region PPA3 may be provided in pairs on the left and right sides (or opposite sides) of the third display region PXA3.

[0074] At least one driver (e.g., a third scan driver SDV3 and a third light emission control driver EDV3) for driving the third pixel PXL3 may be provided in the third surrounding region PPA3. Although in this embodiment, the third scan driver SDV3 and the third light emission control driver EDV3 are provided on the substrate SUB, this disclosure is not limited thereto. For example, at least one of the third scan driver SDV3 and the third light emission control driver EDV3 may be provided outside the substrate SUB for electrical connection to the third pixel PXL3 via pad units. Alternatively, depending on the structure of the third pixel PXL3, the third light emission control driver EDV3 may not be provided. Figure 1 and Figure 2 The diagram already illustrates that each of the third scan driver SDV3 and the third light emission control driver EDV3 is provided on only one side of the third display area PXA3; however, this disclosure is not limited thereto. For example, in another embodiment, the third scan driver SDV3 and the third light emission control driver EDV3 may be arranged on both sides of the third display area PXA3. In some embodiments, the third scan driver SDV3 and the third light emission control driver EDV3 may be arranged on different sides of the third display area PXA3, respectively.

[0075] In embodiments of this disclosure, the third region A3 may have a shape that is linearly symmetrical to the second region A2 about a vertical centerline, which extends along a second direction DR2 at the center point of the transverse portion of the first surrounding region PPA1 of the first region A1. In this case, the arrangement of components provided in the third region A3 may be substantially the same as the arrangement of components in the second region A2, except for some lines.

[0076] Therefore, the substrate SUB may have a shape in which the second region A2 and the third region A3 protrude in the first region A1 along the second direction DR2. Furthermore, since the second region A2 and the third region A3 are spaced apart from each other, the substrate SUB may have a shape recessed between the second region A2 and the third region A3. That is, the substrate SUB may have a groove between the second region A2 and the third region A3.

[0077] In embodiments of this disclosure, the longitudinal portion of the first surrounding region PPA1 may be connected to portions of the longitudinal portions of the second surrounding region PPA2 and the third surrounding region PPA3, respectively. For example, the left longitudinal portion of the first surrounding region PPA1 may be connected to the left longitudinal portion of the second surrounding region PPA2. In some embodiments, the left longitudinal portion of the first surrounding region PPA1 and the left longitudinal portion of the second surrounding region PPA2 may have the same width W4 (hereinafter referred to as the "fourth width"). Additionally, the right longitudinal portion of the first surrounding region PPA1 and the right longitudinal portion of the third surrounding region PPA3 may have the same width W5 (hereinafter referred to as the "fifth width"). In some embodiments, the fourth width W4 and the fifth width W5 may be different from each other. For example, the fourth width W4 may be smaller than the fifth width W5.

[0078] In embodiments of this disclosure, the substrate SUB may further include an additional surrounding region APA. The additional surrounding region APA may be provided adjacent to the first display region PXA1, the second surrounding region PPA2, and the third surrounding region PPA3. For example, the additional surrounding region APA may connect the second surrounding region PPA2 and the third surrounding region PPA3. For example, the additional surrounding region APA may connect the second surrounding region PPA2 and the third surrounding region PPA3 at the upper end of a region of the first display region PXA1.

[0079] In some embodiments, each of the pixels PXL provided in the display areas PXA (i.e., the first to third display areas PXA1, PXA2, and PXA3) on the substrate SUB may include a light-emitting display element. For example, each of the pixels PXL may include an organic light-emitting diode (OLED). However, this disclosure is not limited to organic light-emitting display devices in which OLEDs are used. That is, the pixel PXL may be implemented as a pixel of another type of display device.

[0080] In some embodiments, each of the pixels PXL may emit light having one of the colors red, green, and blue; however, this disclosure is not limited thereto. For example, each of the pixels PXL may emit light having one of the colors cyan, magenta, yellow, white, etc.

[0081] In some embodiments, the data driver DDV may be provided in the surrounding area PPA. For example, the data driver DDV may be provided in the first surrounding area PPA1. However, this disclosure is not limited thereto. For example, the data driver DDV may be provided outside the substrate SUB to be electrically connected to the first pixel PXL1, the second pixel PXL2, and / or the third pixel PXL3 via pad units.

[0082] In some embodiments, at least one power line may be further provided in the surrounding area PPA. For example, a first power line ELVDD and a second power line ELVSS for supplying a first power supply to the first display area PXA1, the second display area PXA2, and / or the third display area PXA3, respectively, may be arranged in the surrounding area PPA. Additionally, depending on the structure of the pixel PXL, one or more power lines may be further provided, such as an initialization power line for supplying a third power supply.

[0083] In some embodiments, one of the first power line ELVDD and the second power line ELVSS (e.g., the second power line ELVSS) may be arranged to correspond to one side of the first surrounding region PPA1, one side of the second surrounding region PPA2, and / or one side of the third surrounding region. For example, the second power line ELVSS may be arranged in the area where the data driver DDV of the first surrounding region PPA1 is arranged, such as at the lower end of the first display area PXA1. In some embodiments, the second power line ELVSS may extend along a first direction DR1 in the first surrounding region PPA1.

[0084] In some embodiments, the other of the first power line ELVDD and the second power line ELVSS (e.g., the first power line ELVDD) may be arranged in a surrounding area PPA other than the area where the second power line ELVSS is arranged. For example, the first power line ELVDD may be arranged to surround the first display area PXA1, the second display area PXA2, and the third display area PXA3. For example, the first power line ELVDD may have a shape extending along the left longitudinal portion of the first surrounding area PPA1, the second surrounding area PPA2, the additional surrounding area APA, the third surrounding area PPA3, and the right longitudinal portion of the first surrounding area PPA1.

[0085] In the above embodiments, it has been described as an example that the second power line ELVSS is arranged in the first surrounding area PPA1 corresponding to one side of the first display area PXA1, and the first power line ELVDD is arranged in other surrounding areas PPA; however, this disclosure is not limited thereto. For example, the first power line ELVDD and the second power line ELVSS may be arranged to surround the first display area PXA1, the second display area PXA2, and the third display area PXA3.

[0086] In some embodiments, the voltage applied through the first power line ELVDD may be higher than the voltage applied through the second power line ELVSS. For example, a high-potential pixel power supply may be applied through the first power line ELVDD, and a low-potential pixel power supply may be applied through the second power line ELVSS. However, the types of power supplies applied through the first power line ELVDD and / or the second power line ELVSS are not limited thereto.

[0087] Power lines ELVDD and ELVSS can be electrically connected between the pad unit and the first display area PXA1, the second display area PXA2, and / or the third display area PXA3. Therefore, power lines ELVDD and ELVSS can transmit set or predetermined power supplied from the outside to the first display area PXA1, the second display area PXA2, and / or the third display area PXA3.

[0088] In embodiments of this disclosure, the dummy region DMP may be located in a region of the surrounding region PPA. The dummy region DMP includes dummy lines that form parasitic capacitances to compensate for brightness differences between pixels PXL arranged in the display region PXA.

[0089] For example, a display device according to an embodiment of the present disclosure includes at least two display areas PXA with different widths. That is, in some embodiments, the number of first pixels PXL1, second pixels PXL2, and / or third pixels PXL3 arranged in a row of one of the first display areas PXA1, the second display area PXA2, and / or the third display area PXA3 may be different for each area.

[0090] For example, a row of a first display area PXA1 having a first width W1 may have a length corresponding to the first width W1, and a row of a second display area PXA2 having a second width W2 may have a length corresponding to the second width W2. Therefore, the second control lines (e.g., scan lines of the second display area PXA2) arranged on each row of the second display area PXA2 may have a shorter length than the first control lines (e.g., scan lines of the first display area PXA1) arranged on each row of the first display area PXA1. Furthermore, the number of second pixels PXL2 electrically connected to the control lines arranged on each row of the second display area PXA2 may be less than the number of first pixels PXL1 electrically connected to the control lines arranged on each row of the first display area PXA1. Therefore, the first control lines and the second control lines have different load values. Therefore, due to the brightness difference between the first pixels PXL1 and the second pixels PXL2, the image display may become uneven.

[0091] In some embodiments, even within the first display area PXA1, the second display area PXA2, and the third display area PXA3, the number of first pixels PXL1, second pixels PXL2, and / or third pixels PXL3 arranged in a row can be different. For example, when at least one region of each of the first display area PXA1, the second display area PXA2, and the third display area PXA3 has a tilted or curved shape, the length of the control line arranged in each row and / or the number of first pixels PXL1, second pixels PXL2, and / or third pixels PXL3 connected to the control line can be different, depending on the shape of the first display area PXA1, the second display area PXA2, and the third display area PXA3.

[0092] Therefore, in embodiments of this disclosure, a dummy region DMP is arranged in a surrounding region PPA, and dummy lines are formed in the dummy region DMP such that differences in the load values ​​between the lines are compensated. For example, the dummy region DMP is arranged in each of a second surrounding region PPA2 and a third surrounding region PPA3, and dummy lines connecting to the second surrounding region PPA2 and the third surrounding region PPA3 can be formed in the respective dummy region DMP. In some embodiments, the dummy lines can be designed such that the load values ​​of a first control line connected to a first pixel PXL1, a second control line connected to a second pixel PXL2, and a third control line connected to a third pixel PXL3 become similar (e.g., substantially the same). The dummy lines may overlap with at least one power line (e.g., a first power line ELVDD) to form parasitic capacitance. Therefore, differences in the load values ​​between the first pixel PXL1 and the second pixel PXL2 or the third pixel PXL3 can be compensated. Therefore, according to embodiments of this disclosure, the image quality of the image can be improved.

[0093] In other words, in the embodiments of this disclosure, since the dummy region DMP is provided or not provided in the surrounding region PPA corresponding to each display region PXA to compensate for the difference in load values ​​between each display region PXA, a structure with different parasitic capacitances can be provided. In the embodiments of this disclosure, the dummy region DMP may be arranged in each of the second surrounding region PPA2 and the third surrounding region PPA3; however, this disclosure is not limited thereto. The dummy region will be described in more detail later.

[0094] As described above, the dummy area DMP may overlap with at least one power line (e.g., the first power line ELVDD). However, in order to stably drive the display device, electrical stability (e.g., arising from insulation properties) must be ensured between the first power line ELVDD and the dummy line of the control line connected to the second display area PXA2 or the third display area PXA3. Therefore, in embodiments of this disclosure described later, a display device is provided that can prevent or reduce the occurrence rate of short circuits between the first power line ELVDD and the dummy lines (where ESD is relatively easily introduced) arranged in the second and third surrounding areas PPA2 and PPA3. Embodiments related thereto will be described in more detail later.

[0095] Figure 3 Illustration Figure 1 An embodiment of the display area and driver in the illustrated display device. For convenience, in Figure 3 In this context, ELVDD is used as the primary power source. Figure 1 The first power line ELVDD has the same reference numerals as the attached diagram, and ELVSS is used as the second power line. Figure 1The second power line, ELVSS, has the same reference numerals as in the attached diagram. Typically, in... Figure 3 In, with Figure 2 Components that are similar to or identical to each other are designated by the same reference numerals, and their detailed descriptions need not be repeated.

[0096] Below, we will refer to Figure 3 Combination Figure 1 and Figure 2 The display area and driver according to embodiments of the present disclosure will be described in more detail.

[0097] refer to Figures 1 to 3 The display device according to embodiments of the present disclosure may include pixels PXL, drivers SDV1, SDV2, SDV3, EDV1, EDV2, EDV3, DDV and TC, and wires.

[0098] In some embodiments, pixel PXL may include first to third pixels PXL1, PXL2, and PXL3, and drivers SDV1, SDV2, SDV3, EDV1, EDV2, EDV3, DDV, and TC may include first to third scan drivers SDV1, SDV2, and SDV3, first to third emission control drivers EDV1, EDV2, and EDV3, a data driver DDV, and a timing controller TC. Figure 3 For ease of description, the positions of the first to third scan drivers SDV1, SDV2, and SDV3, the first to third light emission control drivers EDV1, EDV2, and EDV3, the data driver DDV, and the timing controller TC are shown. When an actual display device is implemented, the first to third scan drivers SDV1, SDV2, and SDV3, the first to third light emission control drivers EDV1, EDV2, and EDV3, the data driver DDV, and the timing controller TC can be arranged in other suitable locations within the display device. For example, the data driver DDV has been illustrated as being arranged in an area closer to the second area A2 and the third area A3 than the first area A1; however, the position of the data driver DDV can be changed. For example, the data driver DDV can be arranged in an area adjacent to the first area A1.

[0099] The conductors transmit drive signals from drivers SDV1, SDV2, SDV3, EDV1, EDV2, EDV3, DDV, and TC to pixel PXL. The conductors may include scan lines S11 to S1n, S21, S22, S31, and S32, data lines D1 to Dm, light emission control lines E11 to E1n, E21, E22, E31, and E32, a first power line ELVDD, a second power line ELVSS, and an initialization power line.

[0100] In some embodiments, scan lines S11 to S1n, S21, S22, S31, and S32 may include first to third scan lines S11 to S1n, S21, S22, S31, and S32, and light emission control lines E11 to E1n, E21, E22, E31, and E32 may include first to third light emission control lines E11 to E1n, E21, E22, E31, and E32 respectively connected to first to third pixels PXL1, PXL2, and PXL3. Data lines D1 to Dm, as well as the first power line ELVDD and the second power line ELVSS, may be connected to the first to third pixels PXL1, PXL2, and PXL3.

[0101] A first pixel PXL1 is arranged in a first display area PXA1 and is connectable to first scan lines S11 to S1n, first light emission control lines E11 to E1n, and data lines D1 to Dm. When a scan signal is supplied from the first scan lines S11 to S1n, the first pixel PXL1 is supplied with data signals from the data lines D1 to Dm. Each of the first pixels PXL1 supplied with data signals can control (or influence) the amount of current flowing from the first power supply ELVDD to the second power supply ELVSS through the organic light-emitting diode OLED.

[0102] The second pixel PXL2 is arranged in the second display area PXA2 and is connectable to the second scan lines S21 and S22, the second light emission control lines E21 and E22, and the data lines D1 to D3. For convenience, although Figure 3 The illustration shows the second pixel PXL2 connected to two second scan lines S21 and S22, two second light-emitting control lines E21 and E22, and three data lines D1 to D3; however, the number and position of the second pixels PXL2 are not limited to this. When a scan signal is supplied from one of the second scan lines S21 and S22, each of the second pixels PXL2 is supplied with a data signal from one of the data lines D1 to D3. Each of the second pixels PXL2 supplied with a data signal can control (or influence) the amount of current flowing from the first power supply ELVDD to the second power supply ELVSS through the organic light-emitting diode OLED.

[0103] The third pixel PXL3 is arranged in the third display area PXA3 and can be connected to the third scan lines S31 and S32, the third light emission control lines E31 and E32, and the data lines Dm-2 to Dm. For convenience, although Figure 3The illustration shows the third pixel PXL3 connected to two third scan lines S31 and S32, two third light-emitting control lines E31 and E32, and three data lines Dm-2 to Dm, but the number and position of the third pixels PXL3 are not limited to this. When a scan signal is supplied from one of the third scan lines S31 and S32, each of the third pixels PXL3 is supplied with a data signal from one of the data lines Dm-2 to Dm. Each of the third pixels PXL3 supplied with a data signal can control (or influence) the amount of current flowing from the first power supply ELVDD to the second power supply ELVSS through the organic light-emitting diode OLED.

[0104] The first scan driver SDV1 can supply scan signals to the first scan lines S11 to S1n in response to the first gate control signal GCS1 from the timing controller TC. For example, the first scan driver SDV1 can supply scan signals to the first scan lines S11 to S1n sequentially. If scan signals are supplied to the first scan lines S11 to S1n sequentially, the first pixel PXL1 can be selected sequentially in horizontal row units.

[0105] The second scan driver SDV2 can supply scan signals to the second scan lines S21 and S22 in response to the second gate control signal GCS2 from the timing controller TC. For example, the second scan driver SDV2 can supply scan signals to the second scan lines S21 and S22 sequentially. If scan signals are supplied to the second scan lines S21 and S22 sequentially, the second pixel PXL2 can be selected sequentially in horizontal row units.

[0106] The third scan driver SDV3 can supply scan signals to the third scan lines S31 and S32 in response to the third gate control signal GCS3 from the timing controller TC. For example, the third scan driver SDV3 can supply scan signals to the third scan lines S31 and S32 sequentially. If scan signals are supplied to the third scan lines S31 and S32 sequentially, the third pixel PXL3 can be selected sequentially in horizontal row units.

[0107] The first light-emitting control driver EDV1 can supply light-emitting control signals to the first light-emitting control lines E11 to E1n in response to the fourth gate control signal GCS4. For example, the first light-emitting control driver EDV1 can sequentially supply light-emitting control signals to the first light-emitting control lines E11 to E1n. Here, the light-emitting control signals may have a wider width than the scan signals (e.g., the light-emitting control signals may be applied for a longer time period than the scan signals). For example, the light-emitting control signal supplied to the i-th (where i is a natural number) first light-emitting control line E1i may be supplied to overlap with the scan signals supplied to the (i-1)-th first scan line S1i-1 and the scan signals supplied to the i-th first scan line S1i by at least one time period. In some embodiments, the light-emitting control signal may be set to a gate cutoff voltage (e.g., a high voltage) such that the transistors contained in the pixel PXL may be turned off, and the scan signal may be set to a gate on voltage (e.g., a low voltage) such that the transistors contained in the pixel PXL may be turned on.

[0108] The second light emission control driver EDV2 can supply light emission control signals to the second light emission control lines E21 and E22 in response to the fifth gate control signal GCS5. For example, the second light emission control driver EDV2 can supply light emission control signals to the second light emission control lines E21 and E22 sequentially.

[0109] The third light emission control driver EDV3 can supply light emission control signals to the third light emission control lines E31 and E32 in response to the sixth gate control signal GCS6. For example, the third light emission control driver EDV3 can supply light emission control signals to the third light emission control lines E31 and E32 sequentially.

[0110] The data driver DDV can supply data signals to data lines D1 to Dm in response to the data control signal DCS. The data signals supplied to data lines D1 to Dm can be supplied to the pixel PXL selected by the scan signal.

[0111] The timing controller TC can supply the generated gate control signals GCS1 to GCS6 to the scan driver SDV and the light emission driver EDV based on the timing signals supplied from the outside. In addition, the timing controller TC can supply the data control signal DCS and image data to the data driver DDV.

[0112] The timing controller TC can be connected via wiring to the first to third scan drivers SDV1, SDV2, and SDV3, the first to third light emission control drivers EDV1, EDV2, and EDV3, and the data driver DDV in various suitable ways. The location of the timing controller TC is not particularly limited. For example, the timing controller TC can be mounted on a flexible printed circuit board to connect via the printed circuit board to the first to third scan drivers SDV1, SDV2, and SDV3, the first to third light emission control drivers EDV1, EDV2, and EDV3, and the data driver DDV. In some embodiments, the printed circuit board can be arranged in various suitable locations, such as one side of the substrate SUB and the back side of the substrate SUB.

[0113] A start pulse and a clock signal can be included in each of the gate control signals GCS1 to GCS6 output from the timing controller TC. The start pulse controls the timing of the supply of the first scan signal or the first light emission control signal. The clock signal can be used to shift the start pulse.

[0114] The source start pulse and clock signal can be included in the data control signal DCS output from the timing controller TC. The source start pulse controls the start time of data sampling. The clock signal can be used to control the sampling operation.

[0115] As described above, in the display device according to embodiments of the present disclosure, pixel PXL can be provided in regions A1, A2, and A3 with different areas. The lengths of scan lines S11 to S1n, S21, S22, S31, and S32, and light emission control lines E11 to E1n, E21, E22, E31, and E32 that provide signals to pixel PXL can be varied depending on regions A1, A2, and A3 (e.g., the areas of display regions PXA1, PXA2, and PXA3). For example, the first width W1 of the first display region PXA1 is longer than the second width W2 of the second display region PXA2. Therefore, when scan lines S11 to S1n, S21, S22, S31, and S32, and light emission control lines E11 to E1n, E21, E22, E31, and E32 extend along their width direction, the length of each of the first scan lines S11 to S1n and the first light emission control lines E11 to E1n is longer than the length of each of the second scan lines S21 and S22 and the second light emission control lines E21 and E22. Furthermore, each of the first scan lines S11 to S1n and the first light emission control lines E11 to E1n can connect to a greater number of pixels PXL than each of the second scan lines S21 and S22 and the second light emission control lines E21 and E22 connects to.

[0116] For the corresponding regions A1, A2, and A3, the length differences between scan lines S11 to S1n, S21, S22, S31, and S32, the length differences between light emission control lines E11 to E1n, E21, E22, E31, and E32, and / or the number of pixels PXL connected to them can cause differences in the load values ​​of scan lines S11 to S1n, S21, S22, S31, and S32, as well as differences in the load values ​​of light emission control lines E11 to E1n, E21, E22, E31, and E32. That is, the load value of the first scan lines S11 to S1n can be greater than the load value of the second scan lines S21 and S22. Furthermore, the load value of the first light emission control lines E11 to E1n can be greater than the load value of the second light emission control lines E21 and E22. This difference in load values ​​can cause a brightness difference (or deviation) between the first pixel PXL1 provided in the first display area PXA1 and the second pixel PXL2 provided in the second display area PXA2. In embodiments of this disclosure, the third pixel PXL3 provided in the third display area PXA3 can be provided in substantially the same form as the second pixel PXL2, therefore, a detailed description of the third pixel PXL3 need not be repeated.

[0117] Figure 4 The illustration shows a first pixel according to an embodiment of the present disclosure. For ease of description, Figure 4 The first pixel PXL1, which is connected to the m-th data line Dm and the i-th first scan line S1i, has been illustrated.

[0118] refer to Figure 3 and Figure 4 According to embodiments of the present disclosure, the first pixel PXL1 may include an organic light-emitting diode (OLED), a first transistor T1 to a seventh transistor T7, and a storage capacitor Cst.

[0119] The anode of the organic light-emitting diode (OLED) can be connected to the first transistor T1 via a sixth transistor T6, and the cathode of the OLED can be connected to a second power supply ELVSS. The OLED produces light with a set or predetermined brightness corresponding to the amount of current supplied from the first transistor T1. The voltage of the first power supply ELVDD can be set to be higher than the voltage of the second power supply ELVSS, allowing current to flow through the OLED.

[0120] A seventh transistor T7 can be connected between the initialization power supply Vint and the anode of the organic light-emitting diode (OLED). Additionally, the gate electrode of the seventh transistor T7 can be connected to the (i+1)th first scan line S1i+1. The seventh transistor T7 can be turned on when a scan signal is supplied to the (i+1)th first scan line S1i+1 to supply the voltage of the initialization power supply Vint to the anode of the OLED. Here, the voltage of the initialization power supply Vint can be set to a voltage lower than the data signal. That is, the voltage of the initialization power supply Vint can be set to not exceed the minimum voltage of the data signal. In this embodiment, the anode initialization control line connected to the gate electrode of the seventh transistor T7 is illustrated as the (i+1)th first scan line S1i+1; however, this disclosure is not limited thereto. For example, in another embodiment, the gate electrode of the seventh transistor T7 can be connected to the i-th first scan line S1i. In this case, when the scan signal is supplied to the i-th first scan line S1i, the voltage of the initialization power supply Vint can be supplied to the anode of the organic light-emitting diode OLED through the seventh transistor T7.

[0121] The sixth transistor T6 can be connected between the first transistor T1 and the organic light-emitting diode (OLED). Additionally, the gate electrode of the sixth transistor T6 can be connected to the i-th first light-emitting control line E1i. When a light-emitting control signal (e.g., a light-emitting control signal with a gate cutoff voltage (high-level voltage)) is supplied to the i-th first light-emitting control line E1i, the sixth transistor T6 can be turned off, and vice versa.

[0122] The fifth transistor T5 can be connected between the first power supply ELVDD and the first transistor T1. Additionally, the gate electrode of the fifth transistor T5 can be connected to the i-th first light-emitting control line E1i. When a light-emitting control signal is supplied to the i-th first light-emitting control line E1i, the fifth transistor T5 can be turned off, and vice versa.

[0123] The first electrode of the first transistor (driving transistor) T1 can be connected to the first power supply ELVDD via the fifth transistor T5, and the second electrode of the first transistor T1 can be connected to the anode of the organic light-emitting diode (OLED). Additionally, the gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 can control the amount of current flowing from the first power supply ELVDD to the second power supply ELVSS through the OLED in accordance with the voltage of the first node N1.

[0124] The third transistor T3 can be connected between the second electrode of the first transistor T1 and the first node N1. Additionally, the gate electrode of the third transistor T3 can be connected to the i-th first scan line S1i. When a scan signal is supplied to the i-th first scan line S1i, the third transistor T3 can be turned on, allowing the second electrode of the first transistor T1 and the first node N1 to be electrically connected to each other. Therefore, when the third transistor T3 is turned on, the first transistor T1 can be a diode connection.

[0125] A fourth transistor T4 can be connected between the first node N1 and the initialization power supply Vint. Additionally, the gate electrode of the fourth transistor T4 can be connected to the (i-1)th first scan line S1i-1. When a scan signal is supplied to the (i-1)th first scan line S1i-1, the fourth transistor T4 can be turned on to supply the voltage of the initialization power supply Vint to the first node N1. In this embodiment, the (i-1)th first scan line S1i-1 can be used as an initialization control line to initialize the gate node of the first transistor T1, i.e., the first node N1. However, this disclosure is not limited thereto. For example, in another embodiment, another control line, such as the (i-2)th first scan line S1i-2, can be used as an initialization control line to initialize the gate node of the first transistor T1.

[0126] The second transistor T2 can be connected to the m-th data line Dm (where m is a natural number) and the first electrode of the first transistor T1. Additionally, the gate electrode of the second transistor T2 can be connected to the i-th first scan line S1i. When a scan signal is supplied to the i-th first scan line S1i, the second transistor T2 can be turned on, allowing the m-th data line Dm and the first electrode of the first transistor T1 to be electrically connected to each other.

[0127] The storage capacitor Cst can be connected between the first power supply ELVDD and the first node N1. The storage capacitor Cst can store data signals and a voltage corresponding to the threshold voltage of the first transistor T1.

[0128] The structure of the first pixel PXL1 is not limited to Figure 4 The illustrated embodiment. For example, it will be apparent that pixel circuits with various suitable structures known in the art can be applied to the first pixel PXL1.

[0129] In non-limiting embodiments of this disclosure, each of the second pixel PXL2 and the third pixel PXL3 may be implemented having the same or substantially the same circuitry as the first pixel PXL1. Therefore, a detailed description of the structure of each of the second pixel PXL2 and the third pixel PXL3 need not be repeated.

[0130] Figure 5 Illustration Figure 4An embodiment showing the detailed structure of the first pixel. Specifically, Figure 5 Detailed illustrations Figure 4 A plan view of an embodiment of the layout of the first pixel. Figure 6 The diagram shows the following: Figure 5 The cross section intercepted by line I-I'. Figure 7 The diagram shows the following: Figure 5 The cross section intercepted by line II-II'.

[0131] Based on a first pixel PXL1 arranged in the i-th row and j-th column (where j is a natural number) in the first display area PXA1, Figures 5 to 7 The diagram illustrates three first scan lines S1i-1, S1i, and S1i+1 connected to the first pixel PXL1, a first light emission control line Eli, a power line PL, and a data line Dj. In other words, in embodiments of this disclosure, the first control line used to control the driving of the first pixel PXL1 may include multiple scan lines S1i-1, S1i, and S1i+1 connected to the first pixel PXL1 and the first light emission control line Eli.

[0132] Here, the first scan line S1i on the i-th row where the first pixel PXL1 is arranged can be the current scan line for supplying a scan signal to the first pixel PXL1 on the i-th row. Additionally, other first scan lines S1i-1 and S1i+1 connected to the first pixel PXL1 are used as initialization control lines for controlling initialization, and can be used as current scan lines in the first pixel PXL1 on adjacent rows (e.g., row (i-1) and row (i+1)). The first control lines S1i-1, S1i, S1i+1, and S1i extend along the first direction DR1 in the first display area PXA1 and can have a length corresponding to the first width W1.

[0133] exist Figures 5 to 7 For ease of description, the first scan line in row (i-1) is called "the (i-1)th first scan line S1i-1", the first scan line in row i is called "the ith first scan line S1i", the first scan line in row (i+1) is called "the (i+1)th first scan line S1i+1", the first light emission control line in row i is called "light emission control line E1i", the data line in column j is called "data line Dj", and the power line in column j (e.g., the power line in column j to which the first power supply ELVDD is applied) is called "power line PL".

[0134] Reference Figures 5 to 7 In combination with the above Figures 1 to 4 Embodiments of this disclosure are described. A display device according to an embodiment of this disclosure may include a substrate SUB, line units, and pixels PXL, for example, a first pixel PXL1.

[0135] The line unit supplies drive signals and / or power to each of the first pixels PXL1. In some embodiments, the line unit may include first scan lines S1i-1, S1i and S1i+1, data line Dj, light emission control line E1i, power line PL and initialization power line IPL.

[0136] The first scan lines S1i-1, S1i, and S1i+1 may extend along the first direction DR1 in the first display area PXA1. In some embodiments, the first scan lines S1i-1, S1i, and S1i+1 may include the (i-1)th first scan line S1i-1, the ith first scan line S1i, and the (i+1)th first scan line S1i+1 arranged sequentially along the second direction DR2 intersecting the first direction DR1. The first scan lines S1i-1, S1i, and S1i+1 may be applied with scan signals. For example, the (i-1)th first scan line S1i-1 may be applied with the (i-1)th first scan signal, the ith first scan line S1i may be applied with the ith first scan signal, and the (i+1)th first scan line S1i+1 may be applied with the (i+1)th first scan signal.

[0137] The light emission control line E1i may extend in the first display area PXA1 along the first direction DR1. The light emission control line E1i may be supplied with a light emission control signal.

[0138] Data line Dj can extend in the second direction DR2. That is, data line Dj can extend in the direction intersecting with the first control lines S1i-1, S1i, S1i+1, and E1i. Data signal can be applied to data line Dj.

[0139] The power line PL may extend along the second direction DR2; however, this disclosure is not limited thereto. The power line PL is arranged to be separated from the data line Dj and may be supplied with a first power supply ELVDD.

[0140] The initialization power line IPL may extend along the first direction DR1; however, this disclosure is not limited thereto. The initialization power line IPL may be applied with an initialization power supply Vint.

[0141] In some embodiments, each of the first pixels PXL1 may include first to seventh transistors T1 to T7, a storage capacitor Cst, and an organic light-emitting diode (OLED).

[0142] The first transistor T1 may include a first gate electrode GE1, a first active pattern ACT1, a first source electrode SE1, a first drain electrode DE1, and a first connection line CNL1. The first gate electrode GE1 may be connected to the third drain electrode DE3 of the third transistor T3 and the fourth drain electrode DE4 of the fourth transistor T4. In some embodiments, the first connection line CNL1 may be connected between the first gate electrode GE1 and the third drain electrode DE3 and the fourth drain electrode DE4. One end of the first connection line CNL1 may be connected to the first gate electrode GE1 through a first contact hole (e.g., a first contact opening) CH1, and the other end of the first connection line CNL1 may be connected to the third drain electrode DE3 and the fourth drain electrode DE4 through a second contact hole (e.g., a second contact opening) CH2.

[0143] In embodiments of this disclosure, the first active pattern ACT1, the first source electrode SE1, and the first drain electrode DE1 may be formed from an undoped or doped semiconductor layer. For example, the first source electrode SE1 and the first drain electrode DE1 may be formed from a doped semiconductor layer, and the active pattern ACT1 may be formed from an undoped semiconductor layer.

[0144] In some embodiments, the first active pattern ACT1 has a strip shape extending in a set or predetermined direction, and may have a shape with multiple bends along the extension direction. When viewed from a top view or plan view, the first active pattern ACT1 may overlap with the first gate electrode GE1. Since the first active pattern ACT1 is formed as elongated, the channel region of the first transistor T1 can be formed as elongated. Therefore, the driving range of the gate voltage applied to the first transistor T1 is widened. Therefore, the grayscale of the light emitted from the organic light-emitting diode OLED can be precisely controlled.

[0145] The first source electrode SE1 can be connected to one end of the first active pattern ACT1. The first source electrode SE1 can be connected to the second drain electrode DE2 of the second transistor T2 and the fifth drain electrode DE5 of the fifth transistor T5.

[0146] The first drain electrode DE1 can be connected to the other end of the first active pattern ACT1. The first drain electrode DE1 can be connected to the third source electrode SE3 of the third transistor T3 and the sixth source electrode SE6 of the sixth transistor T6.

[0147] The second transistor T2 may include a second gate electrode GE2, a second active pattern ACT2, a second source electrode SE2, and a second drain electrode DE2.

[0148] The second gate electrode GE2 can be connected to the i-th first scan line S1i. The second gate electrode GE2 can be provided as part of the i-th first scan line S1i, or it can be provided in a shape that protrudes from the i-th first scan line S1i.

[0149] In some embodiments, the second active pattern ACT2, the second source electrode SE2, and the second drain electrode DE2 may be formed from an undoped or doped semiconductor layer. For example, the second source electrode SE2 and the second drain electrode DE2 may be formed from a doped semiconductor layer, and the second active pattern ACT2 may be formed from an undoped semiconductor layer. The second active pattern ACT2 corresponds to the portion overlapping with the second gate electrode GE2. One end of the second source electrode SE2 may be connected to the second active pattern ACT2. The other end of the second source electrode SE2 may be connected to the data line Dj through a sixth contact hole (e.g., a sixth contact opening) CH6. One end of the second drain electrode DE2 may be connected to the second active pattern ACT2. The other end of the second drain electrode DE2 may be connected to the first source electrode SE1 of the first transistor T1 and the fifth drain electrode DE5 of the fifth transistor T5.

[0150] The third transistor T3 may be provided as a dual-gate structure to prevent or reduce leakage current. That is, the third transistor T3 may include a 3a transistor T3a and a 3b transistor T3b. The 3a transistor T3a may include a 3a gate electrode GE3a, a 3a active pattern ACT3a, a 3a source electrode SE3a, and a 3a drain electrode DE3a. The 3b transistor T3b may include a 3b gate electrode GE3b, a 3b active pattern ACT3b, a 3b source electrode SE3b, and a 3b drain electrode DE3b. Hereinafter, the 3a gate electrode GE3a and the 3b gate electrode GE3b are referred to as the third gate electrode GE3, the 3a active pattern ACT3a and the 3b active pattern ACT3b are referred to as the third active pattern ACT3, the 3a source electrode SE3a and the 3b source electrode SE3b are referred to as the third source electrode SE3, and the 3a drain electrode DE3a and the 3b drain electrode DE3b are referred to as the third drain electrode DE3.

[0151] The third gate electrode GE3 may be connected to the i-th first scan line S1i. The third gate electrode GE3 may be provided as part of the i-th first scan line S1i, or it may be provided in a shape that protrudes from the i-th first scan line S1i. For example, the 3a gate electrode GE3a may be provided in a shape that protrudes from the i-th first scan line S1i, and the 3b gate electrode GE3b may be provided as part of the i-th first scan line S1i.

[0152] The third active pattern ACT3, the third source electrode SE3, and the third drain electrode DE3 can be formed from an undoped or doped semiconductor layer. For example, the third source electrode SE3 and the third drain electrode DE3 can be formed from a doped semiconductor layer, and the third active pattern ACT3 can be formed from an undoped semiconductor layer. The third active pattern ACT3 corresponds to the portion overlapping with the third gate electrode GE3. One end of the third source electrode SE3 can be connected to the third active pattern ACT3. The other end of the third source electrode SE3 can be connected to the first drain electrode DE1 of the first transistor T1 and the sixth source electrode SE6 of the sixth transistor T6. One end of the third drain electrode DE3 can be connected to the third active pattern ACT3. The other end of the third drain electrode DE3 can be connected to the fourth drain electrode DE4 of the fourth transistor T4. Furthermore, the third drain electrode DE3 can be connected to the first gate electrode GE1 of the first transistor T1 through the first connection line CNL1, the second contact hole CH2, and the first contact hole CH1.

[0153] The fourth transistor T4 may be provided as a dual-gate structure to prevent or reduce leakage current. That is, the fourth transistor T4 may include a fourth transistor T4a and a fourth transistor T4b. The fourth transistor T4a may include a fourth gate electrode GE4a, a fourth active pattern ACT4a, a fourth source electrode SE4a, and a fourth drain electrode DE4a, and the fourth transistor T4b may include a fourth gate electrode GE4b, a fourth active pattern ACT4b, a fourth source electrode SE4b, and a fourth drain electrode DE4b. Hereinafter, the fourth gate electrode GE4a and the fourth gate electrode GE4b are referred to as the fourth gate electrode GE4, the fourth active pattern ACT4a and the fourth active pattern ACT4b are referred to as the fourth active pattern ACT4, the fourth source electrode SE4a and the fourth source electrode SE4b are referred to as the fourth source electrode SE4, and the fourth drain electrode DE4a and the fourth drain electrode DE4b are referred to as the fourth drain electrode DE4.

[0154] The fourth gate electrode GE4 may be connected to the (i-1)th first scan line S1i-1. The fourth gate electrode GE4 may be provided as part of the (i-1)th first scan line S1i-1, or it may be provided in a shape protruding from the (i-1)th first scan line S1i-1. For example, the 4a gate electrode GE4a may be provided as part of the (i-1)th first scan line S1i-1. The 4b gate electrode GE4b may be provided in a shape protruding from the (i-1)th first scan line S1i-1.

[0155] The fourth active pattern ACT4, the fourth source electrode SE4, and the fourth drain electrode DE4 can be formed from an undoped or doped semiconductor layer. For example, the fourth source electrode SE4 and the fourth drain electrode DE4 can be formed from a doped semiconductor layer, and the fourth active pattern ACT4 can be formed from an undoped semiconductor layer. The fourth active pattern ACT4 corresponds to the portion that overlaps with the fourth gate electrode GE4.

[0156] One end of the fourth source electrode SE4 can be connected to the fourth active pattern ACT4. The other end of the fourth source electrode SE4 can be connected to the initialization power line IPL of the first pixel PXL1 in the (i-1)th row and the seventh drain electrode DE7 of the seventh transistor T7 of the first pixel PXL1 in the (i-1)th row. An auxiliary connection line AUX can be provided between the fourth source electrode SE4 and the initialization power line IPL. One end of the auxiliary connection line AUX can be connected to the fourth source electrode SE4 through the ninth contact hole (e.g., the ninth contact opening) CH9. The other end of the auxiliary connection line AUX can be connected to the initialization power line IPL in the (i-1)th row through the eighth contact hole (e.g., the eighth contact opening) CH8 of the first pixel PXL1 in the (i-1)th row.

[0157] One end of the fourth drain electrode DE4 can be connected to the fourth active pattern ACT4. The other end of the fourth drain electrode DE4 can be connected to the third drain electrode DE3 of the third transistor T3. In addition, the fourth drain electrode DE4 can be connected to the first gate electrode GE1 of the first transistor T1 through the first connecting line CNL1, the second contact hole CH2 and the first contact hole CH1.

[0158] The fifth transistor T5 may include a fifth gate electrode GE5, a fifth active pattern ACT5, a fifth source electrode SE5, and a fifth drain electrode DE5.

[0159] The fifth gate electrode GE5 may be connected to the first light-emitting control line E1i. The fifth gate electrode GE5 may be provided as part of the first light-emitting control line E1i, or it may be provided in a shape that protrudes from the first light-emitting control line E1i.

[0160] The fifth active pattern ACT5, the fifth source electrode SE5, and the fifth drain electrode DE5 can be formed from an undoped or doped semiconductor layer. For example, the fifth source electrode SE5 and the fifth drain electrode DE5 can be formed from a doped semiconductor layer, and the fifth active pattern ACT5 can be formed from an undoped semiconductor layer. The fifth active pattern ACT5 corresponds to the portion that overlaps with the fifth gate electrode GE5.

[0161] One end of the fifth source electrode SE5 can be connected to the fifth active pattern ACT5. The other end of the fifth source electrode SE5 can be connected to the power line PL through the fifth contact hole (e.g., the fifth contact opening) CH5. One end of the fifth drain electrode DE5 can be connected to the fifth active pattern ACT5. The other end of the fifth drain electrode DE5 can be connected to the first source electrode SE1 of the first transistor T1 and the second drain electrode DE2 of the second transistor T2.

[0162] The sixth transistor T6 may include a sixth gate electrode GE6, a sixth active pattern ACT6, a sixth source electrode SE6, and a sixth drain electrode DE6.

[0163] The sixth gate electrode GE6 may be connected to the first light-emitting control line E1i. The sixth gate electrode GE6 may be provided as part of the first light-emitting control line E1i, or it may be provided in a shape that protrudes from the first light-emitting control line E1i.

[0164] The sixth active pattern ACT6, the sixth source electrode SE6, and the sixth drain electrode DE6 can be formed from an undoped or doped semiconductor layer. For example, the sixth source electrode SE6 and the sixth drain electrode DE6 can be formed from a doped semiconductor layer, and the sixth active pattern ACT6 can be formed from an undoped semiconductor layer. The sixth active pattern ACT6 corresponds to the portion that overlaps with the sixth gate electrode GE6.

[0165] One end of the sixth source electrode SE6 can be connected to the sixth active pattern ACT6. The other end of the sixth source electrode SE6 can be connected to the first drain electrode DE1 of the first transistor T1 and the third source electrode SE3 of the third transistor T3. One end of the sixth drain electrode DE6 can be connected to the sixth active pattern ACT6. The other end of the sixth drain electrode DE6 can be connected to the seventh source electrode SE7 of the seventh transistor T7.

[0166] The seventh transistor T7 may include a seventh gate electrode GE7, a seventh active pattern ACT7, a seventh source electrode SE7, and a seventh drain electrode DE7.

[0167] The seventh gate electrode GE7 can be connected to the (i+1)th first scan line S1i+1. The seventh gate electrode GE7 can be provided as part of the (i+1)th first scan line S1i+1, or it can be provided in a shape that protrudes from the (i+1)th first scan line S1i+1.

[0168] The seventh active pattern ACT7, the seventh source electrode SE7, and the seventh drain electrode DE7 can be formed from an undoped or doped semiconductor layer. For example, the seventh source electrode SE7 and the seventh drain electrode DE7 can be formed from a doped semiconductor layer, and the seventh active pattern ACT7 can be formed from an undoped semiconductor layer. The seventh active pattern ACT7 corresponds to the portion that overlaps with the seventh gate electrode GE7.

[0169] One end of the seventh source electrode SE7 can be connected to the seventh active pattern ACT7. The other end of the seventh source electrode SE7 can be connected to the sixth drain electrode DE6 of the sixth transistor T6. One end of the seventh drain electrode DE7 can be connected to the seventh active pattern ACT7. The other end of the seventh drain electrode DE7 can be connected to the initialization power line IPL.

[0170] The storage capacitor Cst may include a lower electrode LE and an upper electrode UE. The lower electrode LE may be formed as the first gate electrode GE1 of the first transistor T1. The upper electrode UE overlaps with the first gate electrode GE1, and when viewed from a top view or a plan view, the upper electrode UE may cover the lower electrode LE. As the overlap area between the upper electrode UE and the lower electrode LE widens, the capacitance of the storage capacitor Cst may increase.

[0171] In some embodiments, the upper electrode UE may extend in a first direction DR1. A voltage having the same or substantially the same level as the first power supply may be applied to the upper electrode UE. The upper electrode UE may have an opening OPN in a region containing a first contact hole CH1, wherein the first gate electrode GE1 and the first connection line CNL1 are in contact with each other through the first contact hole CH1.

[0172] An organic light-emitting diode (OLED) may include a first electrode AD, a second electrode CD, and an emission layer EML provided between the first electrode AD and the second electrode CD.

[0173] A first electrode AD can be provided in the light-emitting area corresponding to each pixel PXL. The first electrode AD can be connected to the seventh source electrode SE7 of the seventh transistor T7 and the sixth drain electrode DE6 of the sixth transistor T6 via a seventh contact hole (e.g., a seventh contact opening) CH7 and a tenth contact hole (e.g., a tenth contact opening) CH10. A bridging pattern BRP can be provided between the seventh contact hole CH7 and the tenth contact hole CH10. The bridging pattern BRP connects the first electrode AD to the sixth drain electrode DE6 and the seventh source electrode SE7.

[0174] The following text will refer to Figures 5 to 7 The structure of a display device according to embodiments of the present disclosure is described in stacking order.

[0175] First, an active pattern layer may be disposed on a substrate SUB. In some embodiments, active patterns ACT1 to ACT7 (hereinafter referred to as "ACT") may be provided in the active pattern layer. In some embodiments, the active pattern ACT may include a first active pattern ACT1 to a seventh active pattern ACT7. The first active pattern ACT1 to the seventh active pattern ACT7 may be formed of a semiconductor material. In some embodiments, a buffer layer may be provided between the substrate SUB and the first active pattern ACT1 to the seventh active pattern ACT7.

[0176] A first insulating layer GI may be provided on a substrate SUB on which first active patterns ACT1 to seventh active patterns ACT7 are provided. In some embodiments, the first insulating layer GI may be a gate insulating layer disposed between the active patterns ACT1 to ACT7 of transistors T1 to T7 provided in pixel PXL and gate electrodes GE1 to GE7. In some embodiments, the first insulating layer GI may include one or more inorganic layers and / or one or more organic layers. For example, the first insulating layer GI may be configured to include SiO2. x SiN x Inorganic layers of materials and / or similar materials; however, this disclosure is not limited thereto. For example, the first insulating layer GI may comprise inorganic or organic insulating materials, such as SiO2. x SiN x SiON, SiOF, AlO x and / or similar materials. The first insulating layer GI may be a single layer or multiple layers comprising at least one of these materials.

[0177] In embodiments of this disclosure, the first insulating layer GI may have a thickness limited to a set or predetermined range to facilitate driving transistors T1 to T7. For example, the first insulating layer GI may have... to The thickness, for example, approximately The thickness of the first insulating layer GI is not limited thereto. In some embodiments, the first insulating layer GI may be formed together in multiple display areas, such as the first to third display areas PXA1, PXA2 and PXA3; however, this disclosure is not limited thereto.

[0178] A first conductive layer (e.g., a first gate layer) may be disposed on a first insulating layer GI. In some embodiments, first control lines S1i-1, S1i, S1i+1, and E1i, and gate electrodes GE1 to GE7 may be provided in the first conductive layer. In some embodiments, one electrode (e.g., the lower electrode LE) of the storage capacitor Cst may be provided in the first conductive layer. For example, the (i-1)th first scan line S1i-1, the ith first scan line S1i, the (i+1)th first scan line S1i+1, the light emission control line E1i, and the first gate electrodes GE1 to the seventh gate electrodes GE7 may be provided in the first conductive layer on the first insulating layer GI. In some embodiments, the first gate electrode GE1 may become the lower electrode LE of the storage capacitor Cst. That is, in some embodiments, the first gate electrode GE1 and the lower electrode LE of the storage capacitor Cst may be integrally formed. In some embodiments, the second gate electrode GE2 and the third gate electrode GE3 may be integrally formed with the ith first scan line S1i. In some embodiments, the fourth gate electrode GE4 may be integrally formed with the (i-1)th first scan line S1i-1. In some embodiments, the fifth gate electrode GE5 and the sixth gate electrode GE6 may be integrally formed with the light emission control line E1i. In some embodiments, the seventh gate electrode GE7 may be integrally formed with the (i+1)th first scan line S1i+1.

[0179] In some embodiments, the first control lines S1i-1, S1i, S1i+1 and E1i, the gate electrodes GE1 to GE7 and / or the lower electrode LE of the storage capacitor Cst disposed in the first conductive layer may be formed of the same or substantially the same material. For example, the first control lines S1i-1, S1i, S1i+1 and E1i, the gate electrodes GE1 to GE7 and / or the lower electrode LE of the storage capacitor Cst may be formed of a first gate metal (e.g., a predetermined first gate metal).

[0180] In some embodiments, examples of metals capable of forming the first gate metal may be Ti, Cu, Mo, Al, Au, Cr, TiN, Ag, Pt, Pd, Ni, Sn, Co, Rh, Ir, Fe, Ru, Os, Mn, W, Nb, Ta, Bi, Sb, Pb, and the like, and may include various suitable metals as well as the aforementioned metals. Examples of alloys capable of forming the first gate metal may be MoTi, AlNiLa, and the like, and may include various suitable alloys as well as the aforementioned alloys. Examples of multilayers capable of forming the first gate metal may be Ti / Cu, Ti / Au, Mo / Al / Mo, ITO / Ag / ITO, TiN / Ti / Al / Ti, TiN / Ti / Cu / Ti, and the like, and may include various suitable conductive materials having a multilayer structure as well as the aforementioned multilayers.

[0181] The material constituting the lower electrode LE of the first control lines S1i-1, S1i, S1i+1 and E1i, gate electrodes GE1 to GE7 and / or storage capacitor Cst arranged in the first conductive layer is not necessarily limited to metal. That is, any material capable of providing conductivity to a degree (e.g., a sufficiently low degree) that allows the first pixel PXL1 to be smoothly driven can be used as the material constituting the lower electrode LE of the first control lines S1i-1, S1i, S1i+1 and E1i, gate electrodes GE1 to GE7 and / or storage capacitor Cst.

[0182] For example, the lower electrode LE of the first control lines S1i-1, S1i, S1i+1 and E1i, the gate electrodes GE1 to GE7 and / or the storage capacitor Cst may be formed of a conductive polymer or a conductive metal oxide. Examples of conductive polymers capable of constituting the lower electrode LE of the first control lines S1i-1, S1i, S1i+1 and E1i, the gate electrodes GE1 to GE7 and / or the storage capacitor Cst may be polythiophene-based, polypyrrole-based, polyaniline-based, polyacetylene-based and polyphenylene compounds, mixtures thereof and the like, and specifically may include PEDOT / PSS compounds in polythiophene-based compounds. Examples of conductive metal oxides capable of constituting the lower electrode LE of the first control lines S1i-1, S1i, S1i+1 and E1i, the gate electrodes GE1 to GE7 and / or the storage capacitor Cst may be ITO, IZO, AZO, ITZO, ZnO, SnO2 and / or the like.

[0183] A second insulating layer IL1 may be provided on the first conductive layer. In some embodiments, the second insulating layer IL1 may be a first interlayer insulating layer disposed between the lower electrode LE and the upper electrode UE of the storage capacitor Cst. In some embodiments, the second insulating layer IL1 may have a thickness limited to a set or predetermined range so as to sufficiently obtain the capacity of the storage capacitor Cst within the limited area. In some embodiments, the second insulating layer IL1 may have a thickness similar to that of the first insulating layer GI. For example, the second insulating layer IL1 may have... to The thickness, for example, approximately The thickness of the second insulating layer IL1 is not limited thereto. In some embodiments, the second insulating layer IL1 may be formed together in multiple display areas, such as the first to third display areas PXA1, PXA2 and PXA3; however, this disclosure is not limited thereto.

[0184] In some embodiments, the second insulating layer IL1 may include one or more inorganic layers and / or one or more organic layers. For example, the second insulating layer IL1 may be configured to include SiO2. x SiN xInorganic layers of materials and / or similar materials; however, this disclosure is not limited thereto. For example, the second insulating layer IL1 may comprise inorganic or organic insulating materials, such as SiO2. x SiN x SiON, SiOF, AlO x and / or similar materials. The second insulating layer IL1 may be a single layer or multiple layers comprising at least one of these materials.

[0185] A second conductive layer (e.g., a second gate layer) may be disposed on the second insulating layer IL1. In some embodiments, the upper electrode UE and the initialization power line IPL of the storage capacitor Cst may be provided in the second conductive layer. In some embodiments, the upper electrode UE may cover the lower electrode LE. Since the upper electrode UE overlaps with the lower electrode LE, and the second insulating layer IL1 is disposed between the upper electrode UE and the lower electrode LE, the upper electrode UE together with the lower electrode LE can form the storage capacitor Cst.

[0186] In some embodiments, the upper electrode UE and initialization power line IPL of the storage capacitor Cst disposed in the second conductive layer may be formed of the same or substantially the same material. For example, the upper electrode UE and initialization power line IPL of the storage capacitor Cst may be formed of a second gate metal (e.g., a predetermined second gate metal). In some embodiments, the second gate metal may be one of the metals proposed in the example of the first gate metal described above; however, this disclosure is not limited thereto. In addition, the materials constituting the upper electrode UE and initialization power line IPL of the storage capacitor Cst disposed in the second conductive layer are not necessarily limited to metals. That is, any material capable of providing conductivity to a degree (e.g., a sufficiently low degree) that allows the first pixel PXL1 to be smoothly driven may be used as the material constituting the upper electrode UE and initialization power line IPL of the storage capacitor Cst. For example, the upper electrode UE and initialization power line IPL of the storage capacitor Cst may be formed of a conductive polymer or a conductive metal oxide.

[0187] A third insulating layer IL2 may be provided on the second conductive layer. In some embodiments, the third insulating layer IL2 may be a second interlayer insulating layer. In some embodiments, the third insulating layer IL2 may have a thickness greater than that of the first insulating layer GI and the second insulating layer IL1. For example, the third insulating layer IL2 may have a thickness equal to or greater than the sum of the thickness of the first insulating layer GI and the thickness of the second insulating layer IL1. For example, the third insulating layer IL2 may have a thickness of approximately The thickness of the third insulating layer IL2 is not limited to this; however, the thickness of the third insulating layer IL2 is not limited to this. If the third insulating layer IL2 is formed to have a sufficient thickness greater than the sum of the thickness of the first insulating layer GI and the thickness of the second insulating layer IL1, electrical stability between components disposed on the bottom and top of the third insulating layer IL2 can be ensured. Therefore, short circuits can be effectively prevented, or the occurrence of short circuits can be substantially reduced. In some embodiments, the third insulating layer IL2 may be formed together in multiple display areas, such as the first to third display areas PXA1, PXA2 and PXA3; however, this disclosure is not limited to this.

[0188] In some embodiments, the third insulating layer IL2 may include one or more inorganic layers and / or one or more organic layers. For example, the third insulating layer IL2 may be configured to include SiO2. x SiN x Inorganic layers of materials and / or similar materials; however, this disclosure is not limited thereto. For example, the third insulating layer IL2 may comprise inorganic or organic insulating materials, such as SiO2. x SiN x SiON, SiOF, AlO x and / or similar materials. The third insulating layer IL2 may be a single layer or multiple layers comprising at least one of these materials.

[0189] A third conductive layer (e.g., a source-drain layer) may be disposed on a third insulating layer IL2. In some embodiments, a data line Dj, a power line PL, a first connection line CNL1, an auxiliary connection line AUX, and a bridging pattern BRP may be provided in the third conductive layer.

[0190] In some embodiments, the data line Dj can be connected to the second source electrode SE2 through a sixth contact hole CH6 passing through the first insulating layer GI, the second insulating layer IL1, and the third insulating layer IL2.

[0191] In some embodiments, the power line PL can be connected to the upper electrode UE of the storage capacitor Cst through the third contact hole CH3 and the fourth contact hole CH4 passing through the third insulating layer IL2. Furthermore, the power line PL can be connected to the fifth source electrode SE5 through the fifth contact hole CH5 passing through the first insulating layer GI, the second insulating layer IL1, and the third insulating layer IL2.

[0192] In some embodiments, the first connection line CNL1 can be connected to the first gate electrode GE1 through a first contact hole CH1 passing through the second insulating layer IL1 and the third insulating layer IL2. Furthermore, the first connection line CNL1 can be connected to the third drain electrode DE3 and the fourth drain electrode DE4 through a second contact hole CH2 passing through the first insulating layer GI, the second insulating layer IL1, and the third insulating layer IL2.

[0193] In some embodiments, the auxiliary connection line AUX can be connected to the initialization power line IPL via the eighth contact hole CH8 passing through the third insulating layer IL2. Furthermore, the auxiliary connection line AUX can be connected to the seventh drain electrode DE7 via the ninth contact hole CH9 passing through the first insulating layer GI, the second insulating layer IL1, and the third insulating layer IL2.

[0194] In some embodiments, the bridging pattern BRP may be a pattern provided as a medium connecting the sixth drain electrode DE6 and the first electrode AD. The bridging pattern BRP may be connected to the sixth drain electrode DE6 and the seventh source electrode SE7 through a seventh contact hole CH7 passing through the first insulating layer GI, the second insulating layer IL1, and the third insulating layer IL2.

[0195] In some embodiments, the data lines Dj, power lines PL, first connection lines CNL1, auxiliary connection lines AUX, and / or bridging patterns BRP disposed in the third conductive layer may be formed of the same or substantially the same material. For example, the data lines Dj, power lines PL, first connection lines CNL1, auxiliary connection lines AUX, and / or bridging patterns BRP may be formed of source-drain metal (e.g., a predetermined source-drain metal).

[0196] In some embodiments, the source-drain metal may be one of the metals proposed in the examples of the first gate metal and / or the second gate metal described above; however, this disclosure is not limited thereto. Furthermore, the materials constituting the data line Dj, power line PL, first connection line CNL1, auxiliary connection line AUX, and / or bridging pattern BRP arranged in the third conductive layer are not necessarily limited to metals. That is, any material capable of providing conductivity to a degree (e.g., a sufficiently low degree) that allows the first pixel PXL1 to be smoothly driven can be used as the material constituting the data line Dj, power line PL, first connection line CNL1, auxiliary connection line AUX, and / or bridging pattern BRP. For example, the data line Dj, power line PL, first connection line CNL1, auxiliary connection line AUX, and / or bridging pattern BRP may be formed of a conductive polymer or a conductive metal oxide.

[0197] In some embodiments, at least two of the first gate metal, the second gate metal, and the source-drain metal may be made of the same or substantially the same material. For example, although the first gate metal and the second gate metal are arranged in different layers, the first gate metal and the second gate metal may be made of the same or substantially the same material. However, this disclosure is not limited thereto. For example, in another embodiment, all of the first gate metal, the second gate metal, and the source-drain metal may be made of different materials.

[0198] A fourth insulating layer PSV may be provided on the third conductive layer. In some embodiments, the fourth insulating layer PSV may include a passivation layer and / or a planarization layer.

[0199] An organic light-emitting diode (OLED) can be provided on a fourth insulating layer (PSV). An OLED may include a first electrode (AD), a second electrode (CD), and an emission layer (EML) provided between the first electrode (AD) and the second electrode (CD).

[0200] In some embodiments, the first electrode AD may be provided on the fourth insulating layer PSV. The first electrode AD can be connected to the bridging pattern BRP through the tenth contact hole CH10 through the fourth insulating layer PSV. Since the bridging pattern BRP is connected to the sixth drain electrode DE6 and the seventh source electrode SE7 through the seventh contact hole CH7, the first electrode AD can ultimately be connected to the sixth drain electrode DE6 and the seventh source electrode SE7.

[0201] In some embodiments, a pixel defining layer PDL defining a light-emitting area corresponding to each pixel PXL may be provided on a substrate SUB on which a first electrode AD is disposed. The pixel defining layer PDL exposes the upper surface of the first electrode AD and may protrude from the substrate SUB along the outer periphery of the pixel PXL.

[0202] An emissive layer EML may be provided in the light-emitting region surrounded by a pixel-defining layer PDL, and a second electrode CD may be provided on the emissive layer EML. In some embodiments, an encapsulation layer SLM covering the second electrode CD may be provided on the second electrode CD.

[0203] In some embodiments, one of the first electrode AD and the second electrode CD can be an anode, and the other of the first electrode AD and the second electrode CD can be a cathode. For example, the first electrode AD can be an anode, and the second electrode CD can be a cathode.

[0204] At least one of the first electrode AD and the second electrode CD can be a transmission electrode. For example, when the OLED is a bottom-emitting OLED, the first electrode AD can be a transmission electrode, and the second electrode CD is a reflection electrode. When the OLED is a top-emitting OLED, the first electrode AD can be a reflection electrode, and the second electrode CD can be a transmission electrode. When the OLED is a dual-emitting OLED, both the first electrode AD and the second electrode CD can be transmission electrodes. In this embodiment, the case where the OLED is a top-emitting OLED and the first electrode AD is the anode has been described as an example. Furthermore, in this embodiment, the OLED has been used as a light source; however, this disclosure is not limited thereto. For example, the OLED can be replaced by another type of light-emitting diode.

[0205] In some embodiments, the first electrode AD may include a reflective layer capable of reflecting light and a transparent conductive layer disposed on top of or below the reflective layer. At least one of the transparent conductive layer and the reflective layer may be connected to the sixth drain electrode DE6 and the seventh source electrode SE7.

[0206] In some embodiments, the reflective layer may include a material capable of reflecting light. For example, the reflective layer may include aluminum (Al), silver (Ag), chromium (Cr), molybdenum (Mo), platinum (Pt), nickel (Ni), and / or alloys thereof.

[0207] In some embodiments, the transparent conductive layer may include a transparent conductive oxide. For example, the transparent conductive layer may include at least one transparent conductive oxide selected from indium tin oxide (ITO), indium zinc oxide (IZO), zinc aluminum oxide (AZO), gallium-doped zinc oxide (GZO), zinc tin oxide (ZTO), gallium tin oxide (GTO), and fluorine-doped tin oxide (FTO).

[0208] In some embodiments, the pixel defining layer (PDL) may include an organic insulating material. For example, the pixel defining layer (PDL) may include polystyrene, polymethyl methacrylate (PMMA), polyacrylonitrile (PAN), polyamide (PA), polyimide (PI), polyaryl ether (PAE), heterocyclic polymers, parylene, epoxy resins, benzocyclobutene (BCB), siloxane resins, silane resins, and / or the like.

[0209] The emitter layer EML can be disposed on the exposed surface of the first electrode AD. The emitter layer EML can have a multilayer thin film structure including at least a light-generating layer (LGL). For example, the emitter layer EML may include: a hole injection layer (HIL) for injecting holes; a hole transport layer (HTL) with superior hole transport characteristics, the HTL being used to increase the chance of hole and electron recombination by suppressing the movement of unbound electrons in the LGL; an LGL for emitting light by the recombination of injected electrons and holes; a hole blocking layer (HBL) for suppressing the movement of unbound holes in the LGL; an electron transport layer (ETL) for smoothly transporting electrons to the LGL; and an electron injection layer (EIL) for injecting electrons.

[0210] In some embodiments, the color of the light generated in the LGL can be one of red, green, blue, and white; however, this disclosure is not limited thereto. For example, the color of the light generated in the LGL of the emissive layer EML can also be one of magenta, cyan, and yellow.

[0211] In some embodiments, HIL, HTL, HBL, ETL, and EIL can be common layers connected to adjacent light-emitting regions.

[0212] In some embodiments, the second electrode CD can be a semi-transparent reflective layer. For example, the second electrode CD can be a thin metal layer with a thickness through which light emitted from the emitting layer EML can pass. The second electrode CD allows a portion of the light emitted from the emitting layer EML to pass through and reflects the remaining light emitted from the emitting layer EML.

[0213] In some embodiments, the second electrode CD may comprise a material having a lower work function than the transparent conductive layer. For example, the second electrode CD may comprise molybdenum (Mo), tungsten (W), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), and / or the like, as well as any alloys thereof.

[0214] A portion of the light emitted from the emissive layer EML can bypass the second electrode CD, and the light reflected from the second electrode CD can be reflected again from the reflective layer. In other words, the light emitted from the emissive layer EML can resonate between the reflective layer and the second electrode CD. Through this light resonance, the light extraction efficiency of the organic light-emitting diode (OLED) can be improved (e.g., increased).

[0215] In some embodiments, the encapsulation layer SLM prevents or substantially prevents oxygen and moisture from penetrating into the organic light-emitting diode (OLED). For this purpose, the encapsulation layer SLM may include an inorganic layer. The inorganic layer may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, zirconium oxide, tin oxide, and / or the like. The encapsulation layer SLM at least covers the display area PXA and may extend upwards beyond the display area PXA.

[0216] In the embodiments of this disclosure, the second pixel PXL2 provided in the second display area PXA2 and the third pixel PXL3 provided in the third display area PXA3 have a pixel structure that is substantially the same as that of the first pixel PXL1, so their descriptions need not be repeated.

[0217] Figure 8 Illustration Figure 1 An embodiment of the detailed structure of the second pixel and the dummy region corresponding to region P1 is shown. Figure 9 The diagram shows along Figure 8 The cross section intercepted by line III-III'. Figure 10 The diagram shows the following: Figure 8 The cross section intercepted by line IV-IV'. Figures 8 to 10 In, with Figures 5 to 7 Components that are similar to or identical to those shown are designated by the same reference numerals, and their detailed descriptions need not be repeated.

[0218] Based on a second pixel PXL2_k located in the i-th row and k-th column (k is a natural number) of the second display area PXA2 and a second pixel PXL2_k+1 located in the i-th row and (k+1)-th column of the second display area PXA2, Figures 8 to 10 The diagram illustrates three second scan lines S2i-1, S2i, and S2i+1 connected to the two second pixels PXL2_k and PXL2_k+1, one second light emission control line E2i, and two second data lines Dk and Dk+1. Additionally, Figure 8 The illustration shows two second pixels, PXL2_k and PXL2_k+1, arranged adjacent to the dummy region DMP. However, other second pixels PXL2 may also have essentially the same structure.

[0219] In embodiments of this disclosure, a second control line for controlling the drive of each of the second pixels PXL2 may include multiple second scan lines S2i-1, S2i, and S2i+1 connected to the second pixels PXL2 and a second light emission control line E2i. Here, the second scan line S2i on the i-th row on which the second pixels PXL2 are arranged may be the current scan line for supplying a scan signal to the second pixels PXL2 on the i-th row. In addition, the other scan lines S2i-1 and S2i+1 connected to the second pixels PXL2 are used as initialization control lines for controlling initialization, and may be used as current scan lines in the second pixels PXL2 on adjacent rows (e.g., the (i-1)th row and the (i+1)th row). The second scan lines S2i-1, S2i, and S2i+1 extend along the first direction DR1 in the second display area PXA2 and may have a length corresponding to the second width W2.

[0220] exist Figures 8 to 10 In the diagram, the second scan line in row (i-1) is called "the (i-1)th second scan line S2i-1", the second scan line in row i is called "the ith second scan line S2i", the second scan line in row (i+1) is called "the (i+1)th second scan line S2i+1", the second light emission control line in row i is called "the light emission control line E2i", the data line in column k is called "the kth data line Dk", the data line in column (k+1) is called "the (k+1)th data line Dk+1", the power line in column k is called "the kth power line PLk", and the power line in column (k+1) is called "the (k+1)th power line PLk+1".

[0221] refer to Figures 8 to 10 Combination Figure 1In the display device according to embodiments of the present disclosure, a dummy area DMP is used, and a structure with different parasitic capacitances for corresponding display areas can be applied to compensate for differences in load values ​​between display areas PXA. For example, the dummy area DMP can be provided in a first surrounding area PPA1 corresponding to the first display area PXA1 to compensate for differences in load values ​​between control lines (scan lines and / or light emission control lines) in the first display area PXA1 and control lines (scan lines and / or light emission control lines) in the second display area PXA2 and the third display area PXA3. Additionally, a dummy area DMP in which dummy lines DMLi1 to DMLi4 (hereinafter referred to as "DML") are respectively connected to the second pixel PXL2 and the third pixel PXL3 can be located in a second surrounding area PPA2 corresponding to the second display area PXA2 and a third surrounding area PPA3 corresponding to the third display area PXA3. Although not shown in the figures, the dummy area DMP can also be provided to an additional surrounding area APA. The virtual area DMP can be arranged adjacent to the display area (e.g., the second display area PXA2 and the third display area PXA3) connected to the virtual area DMP; however, the location of the virtual area DMP is not limited to this.

[0222] The display device according to embodiments of the present disclosure may include a substrate SUB, line units, and pixels PXL, such as second pixels PXL2_k and PXL2_k+1 (hereinafter referred to as "PXL2").

[0223] The line unit supplies drive signals and / or drive power to each of the second pixels PXL2. In some embodiments, the line unit may include second scan lines S2i-1, S2i and S2i+1, data lines Dk and Dk+1, light emission control line E2i, power lines PLk and PLk+1, and initialization power line IPL.

[0224] Second scan lines S2i-1, S2i, and S2i+1 are provided in the second display area PXA2 and may extend in the second display area PXA2 along the first direction DR1. In some embodiments, the second scan lines S2i-1, S2i, and S2i+1 may be arranged in substantially the same layer as the aforementioned first scan lines S1i-1, S1i, and S1i+1. For example, the second scan lines S2i-1, S2i, and S2i+1 may be arranged in a first conductive layer (first gate layer) on a first insulating layer GI, wherein the first insulating layer GI is provided on a substrate SUB.

[0225] In some embodiments, the second scan lines S2i-1, S2i, and S2i+1 may include the (i-1)th second scan line S2i-1, the ith second scan line S2i, and the (i+1)th second scan line S2i+1 arranged sequentially in the second direction DR2 intersecting the first direction DR1. The second scan lines S2i-1, S2i, and S2i+1 may be applied with scan signals. For example, the (i-1)th second scan line S2i-1 may be applied with the (i-1)th second scan signal, the ith second scan line S2i may be applied with the ith second scan signal, and the (i+1)th second scan line S2i+1 may be applied with the (i+1)th second scan signal.

[0226] Here, the second scan lines S2i-1, S2i, and S2i+1 may have a length different from that of the first scan lines S11 to S1n provided in the first display area PXA1. That is, since the second display area PXA2 has a shorter width than the first display area PXA1, the second scan lines S2i-1, S2i, and S2i+1 extending in the width direction (i.e., the first direction DR1) in the second display area PXA2 may have a shorter length than the first scan lines S11 to S1n extending in the width direction (i.e., the first direction DR1) in the first display area PXA1.

[0227] The light-emitting control line E2i may extend in the second display area PXA2 along the first direction DR1. A light-emitting control signal may be applied to the light-emitting control line E2i. In some embodiments, the light-emitting control line E2i provided in the second display area PXA2 and the aforementioned light-emitting control line E1i provided in the first display area PXA1 may be arranged in substantially the same layer. For example, the light-emitting control line E2i provided in the second display area PXA2 may be arranged in a first conductive layer (first gate layer) on a first insulating layer GI, wherein the first insulating layer GI is provided on the substrate SUB.

[0228] In some embodiments, the second pixels PXL2_k and PXL2_k+1 may have a structure substantially the same as that of the first pixel PXL1 described above. For example, each of the second pixels PXL2_k and PXL2_k+1 may include at least one transistor (e.g., first transistor T1 to seventh transistor T7) connected to a set or predetermined second control line, a storage capacitor Cst, and an organic light-emitting diode (OLED).

[0229] In some embodiments, similar to the first transistors T1 to T7 of the first pixel PXL1 described above, the first transistors T1 to T7 of the second pixels PXL2_k and PXL2_k+1 may include active patterns ACT1 to ACT7 located in an active patterning layer, source electrodes SE1 to SE7 and drain electrodes DE1 to DE7 connected to the active patterns ACT1 to ACT7, and gate electrodes GE1 to GE7 overlapping with the corresponding active patterns ACT1 to ACT7 on a first conductive layer (first gate layer), wherein the active patterning layer is provided between the substrate SUB and the first insulating layer GI, and the first conductive layer is provided on the first insulating layer GI. In some embodiments, at least some of the first transistors T1 to T7 (e.g., the gate electrodes GE2 to GE7 of the second transistors T2 to T7) may be connected to a defined or predetermined second control line. For example, the second gate electrodes GE2 to the seventh gate electrodes GE7 may be integrally formed with the defined or predetermined second control line.

[0230] In some embodiments, the storage capacitor Cst may include a lower electrode LE and an upper electrode UE, the lower electrode LE being located in a first conductive layer together with gate electrodes GE1 to GE7 and a second control line, and the upper electrode UE being located in a second conductive layer (second gate layer) provided on a second insulating layer IL1.

[0231] In some embodiments, the second control lines S2i-1, S2i, S2i+1, and E2i disposed in the first conductive layer, the gate electrodes GE1 to GE7, and / or the lower electrode LE of the storage capacitor Cst may be formed of the same or substantially the same material. For example, the second control lines S2i-1, S2i, S2i+1, and E2i, the gate electrodes GE1 to GE7, and / or the lower electrode LE of the storage capacitor Cst may be formed of a first gate metal (e.g., a predetermined first gate metal). In some embodiments, the first gate metal may include, for example, Figures 5 to 7 The description refers to at least one of the materials mentioned in the first gate metal; however, this disclosure is not limited thereto. Furthermore, the materials constituting the lower electrode LE of the second control lines S2i-1, S2i, S2i+1, and E2i, the gate electrodes GE1 to GE7, and / or the storage capacitor Cst arranged in the first conductive layer are not necessarily limited to metals. That is, any material (including conductive polymers, conductive metal oxides, or the like) capable of providing conductivity to a degree (e.g., a sufficiently low degree) that allows the second pixel PXL2 to be smoothly driven can be used as the material constituting the lower electrode LE of the second control lines S2i-1, S2i, S2i+1, and E2i, the gate electrodes GE1 to GE7, and / or the storage capacitor Cst.

[0232] In some embodiments, the upper electrode UE and the initialization power line IPL of the storage capacitor Cst disposed in the second conductive layer may be formed of the same or substantially the same material. For example, the upper electrode UE and the initialization power line IPL of the storage capacitor Cst may be formed of a second gate metal (e.g., a predetermined second gate metal). In some embodiments, the second gate metal may be the same as or substantially the same as the first gate metal; however, this disclosure is not limited thereto. That is, the second gate metal may be the same as or different from the first gate metal. In some embodiments, the second gate metal may include, for example, Figures 5 to 7 The description of the second gate metal includes at least one of the materials mentioned; however, this disclosure is not limited thereto. Furthermore, the materials constituting the upper electrode UE of the storage capacitor Cst and the initialization power line IPL arranged in the second conductive layer are not necessarily limited to metals. That is, any material (including conductive polymers, conductive metal oxides, and / or the like) capable of providing conductivity to a degree (e.g., a sufficiently low degree) that allows the second pixel PXL2 to be smoothly driven can be used as the material constituting the upper electrode UE of the storage capacitor Cst and the initialization power line IPL.

[0233] Furthermore, in some embodiments, the data lines Dk and Dk+1, power lines PLk and PLk+1, etc., disposed in the third conductive layer may be formed of the same or substantially the same material. For example, the data lines Dk and Dk+1, power lines PLk and PLk+1, etc., may be formed of source-drain metal (e.g., a predetermined source-drain metal). In some embodiments, the source-drain metal may include, for example, Figures 5 to 7 The description refers to at least one of the materials mentioned in the source-drain metal; however, this disclosure is not limited thereto. Furthermore, the materials constituting the data lines Dk and Dk+1, power lines PLk and PLk+1, etc., arranged in the third conductive layer are not necessarily limited to metals. That is, any material (including conductive polymers, conductive metal oxides, and / or the like) capable of providing conductivity to the degree that allows the second pixel PXL2 to be smoothly driven can be used as the material constituting the data lines Dk and Dk+1, power lines PLk and PLk+1, etc.

[0234] Each of the second pixels PXL2_k and PXL2_k+1 can have the same as... Figures 4 to 7 The structure is essentially the same as that of the first pixel PXL1 described herein. Therefore, detailed descriptions of the transistors T1 to T7, the storage capacitor Cst, and / or the organic light-emitting diodes (OLEDs) configured in the second pixels PXL2_k and PXL2_k+1, or their interconnections, are not required.

[0235] In embodiments of this disclosure, each of the second control lines (i.e., the second scan lines S2i-1, S2i, and S2i+1 and the light emission control line E2i) may be connected to at least one dummy line DML arranged in the dummy region DMP. For example, each of the second scan lines S2i-1, S2i, and S2i+1 and the light emission control line E2i may be connected to any dummy line DML extending in the second surrounding region PPA2 and / or the additional surrounding region APA to be provided in the dummy region DMP.

[0236] In some embodiments, the second control lines S2i-1, S2i, S2i+1, and E2i, which are subjected to different signals at different times, can be connected to different dummy lines DML. For example, when different signals are applied to the four second control lines (i.e., the second scan lines S2i-1, S2i, and S2i+1 and the light emission control line E2i arranged in the i-th row and k-th column of the second display area PXA2), the second scan lines S2i-1, S2i, and S2i+1 and the light emission control line E2i can be connected to different dummy lines DML.

[0237] For example, the (i-1)th second scan line S2i-1 may be connected to the first dummy line DMLi1 provided in the dummy region DMP, and the i-th second scan line S2i may be connected to the second dummy line DMLi2 provided in the dummy region DMP. Additionally, the light emission control line E2i may be connected to the third dummy line DMLi3 provided in the dummy region DMP, and the (i+1)th second scan line S2i+1 may be connected to the fourth dummy line DMLi4 provided in the dummy region DMP. In some embodiments, at least some of the second scan lines S2i-1, S2i, and S2i+1 and the light emission control line E2i may extend to the second surrounding region PPA2 and / or the additional surrounding region APA.

[0238] The dummy region DMP includes dummy lines DMLi1, DMLi2, DMLi3, and DMLi4 connected to the second control lines S2i-1, S2i, S2i+1, and E2i, respectively, and a first power line ELVDD overlapping the dummy lines DMLi1, DMLi2, DMLi3, and DMLi4. In other words, the dummy region DMP may include multiple dummy lines DMLi1, DMLi2, DMLi3, and DMLi4 corresponding to each of the second control lines S2i-1, S2i, S2i+1, and E2i.

[0239] For example, a first dummy line DMLi1 connected to the (i-1)th second scan line S2i-1 extending upwards to the dummy region DMP, a second dummy line DMLi2 connected to the ith second scan line S2i extending upwards to the dummy region DMP, a third dummy line DMLi3 connected to the light emission control line E2i extending upwards to the dummy region DMP, and a fourth dummy line DMLi4 connected to the (i+1)th second scan line S2i+1 extending upwards to the dummy region DMP can be provided in the dummy region DMP. In this way, multiple dummy lines DML corresponding to the second control lines S2i-1, S2i, S2i+1, and E2i arranged on each row of the second display area PXA2 can be provided in the dummy region DMP.

[0240] In some embodiments, such as Figure 9 As shown, the dummy line DML can be disposed in a second conductive layer (second gate layer), wherein the second conductive layer is provided on the second insulating layer IL1. That is, in some embodiments, the dummy line DML can be disposed in a different conductive layer than the second control lines S2i-1, S2i, S2i+1, and E2i. For example, the second control lines S2i-1, S2i, S2i+1, and E2i can be disposed in the first conductive layer (first gate layer) together with the gate electrodes GE1 to GE7 provided in each of the second pixels PXL2, and the dummy line DML can be disposed in the second conductive layer (second gate layer) together with the upper electrode UE of the storage capacitor Cst provided in each of the second pixels PXL2. In some embodiments, the dummy line DML can be formed of the same or substantially the same material as the upper electrode UE of the storage capacitor Cst disposed in the same layer. For example, the dummy line DML can be formed of a second gate metal (e.g., a predetermined second gate metal). However, this disclosure is not limited thereto, and the materials constituting the dummy line DML can be varied appropriately.

[0241] In other words, in embodiments of this disclosure, for example, the dummy lines DML of the second control lines S2i-1, S2i, S2i+1, and E2i connected to the second display area PXA2 can be arranged in a different layer than the layer in which the second control lines S2i-1, S2i, S2i+1, and E2i are arranged, in order to compensate for differences in the load values ​​between the display areas PXA. For example, the second control lines S2i-1, S2i, S2i+1, and E2i are separated from the active pattern ACT of a set or predetermined transistor, such that a region of each of the second control lines S2i-1, S2i, S2i+1, and E2i that overlaps with the active pattern ACT of the transistor has only a first insulating layer GI, and the first insulating layer GI placed between them has a relatively thin thickness. In other words, the second control lines S2i-1, S2i, S2i+1 and E2i that overlap each other in the second display area PXA2 are separated from the active pattern ACT by a distance corresponding to the thickness of the first insulating layer GI along the thickness direction of the first insulating layer GI (e.g., the Z direction perpendicular to the XY plane when the substrate SUB and the first insulating layer GI are arranged on the XY plane).

[0242] The dummy line DML and the eighth active pattern ACT8 constituting the first power line ELVDD are separated from each other by a plurality of insulating layers (i.e., the first insulating layer GI and the second insulating layer IL1) placed between them. That is, the dummy line DML and the eighth active pattern ACT8, which overlap each other in the dummy region DMP, are separated from each other along the thickness direction of the first insulating layer GI and the second insulating layer IL1 (e.g., the Z direction perpendicular to the XY plane when the substrate SUB and the first insulating layer GI and the second insulating layer IL1 are arranged on the XY plane) at a distance corresponding to the sum of the thicknesses of the first insulating layer GI and the second insulating layer IL1 (e.g., substantially equal to or greater than the sum of the thicknesses of the first insulating layer GI and the second insulating layer IL1).

[0243] According to embodiments of this disclosure, in response to control signals applied from the second control lines S2i-1, S2i, S2i+1, and E2i, set or predetermined transistors whose gate electrodes are connected to the second control lines S2i-1, S2i, S2i+1, and E2i can be smoothly driven. Furthermore, the distance (gap) between the dummy line DML and the eighth active pattern ACT8 is adequately obtained in the dummy region DMP, thus preventing or substantially reducing the occurrence rate of short circuits between the dummy line DML and the eighth active pattern ACT8.

[0244] As described above, in embodiments of this disclosure, the second control lines S2i-1, S2i, S2i+1, and E2i, which are interconnected, are arranged in different layers from the dummy line DML. Therefore, the display device according to embodiments of this disclosure further includes conductive bridges BRi1 to BRi4 (hereinafter referred to as "BR") for electrically connecting the second control lines S2i-1, S2i, S2i+1, and E2i to the dummy line DML. For example, each of the dummy lines DML is connected to a defined or predetermined second control line via one or more conductive bridges BR. That is, conductive bridges BRi1 to BRi4 for electrically connecting the corresponding second control lines S2i-1, S2i, S2i+1, and E2i to the dummy lines DMLi1, DMLi2, DMLi3, or DMLi4 are provided between the second control lines S2i-1, S2i, S2i+1, and E2i and the dummy line DML.

[0245] In some embodiments, such as Figure 10 As shown, the conductive bridge BR can be disposed in a third conductive layer on the third insulating layer IL2, for example, in a source-drain layer. In embodiments of this disclosure, the conductive bridge BR can be formed of the same or substantially the same material as the data lines Dk and Dk+1 and / or power lines PLk and PLk+1 disposed in the same layer. For example, the conductive bridge BR can be formed of source-drain metal (e.g., a predetermined source-drain metal). However, this disclosure is not limited thereto, and the materials constituting the conductive bridge BR can be varied in various suitable ways.

[0246] In some embodiments, one end of the conductive bridge BR can be connected to a set or predetermined second control line, such as the (i+1)th second scan line S2i+1, through a contact hole (e.g., a contact opening) CNT1 passing through the second insulating layer IL1 and the third insulating layer IL2. Additionally, the other end of the conductive bridge BR can be connected to a set or predetermined dummy line, such as the fourth dummy line DMLi4, through a contact hole CNT2 passing through the third insulating layer IL2.

[0247] In some embodiments, the conductive bridge BR is arranged adjacent to the second display area PXA2. For example, the conductive bridge BR may be arranged in a second surrounding area PPA2 located on one side of the second display area PXA2. However, the position of the conductive bridge BR can be appropriately changed in various ways.

[0248] In some embodiments, the first power line ELVDD overlaps with the dummy line DML at least in the dummy region DMP. In embodiments of this disclosure, the first power line ELVDD is formed as a multilayer structure at least in the dummy region DMP. For example, as Figure 9 As shown, the first power line ELVDD may include the main bus PLB and the eighth active pattern ACT8.

[0249] In some embodiments, the eighth active pattern ACT8 and the active patterns ACT1 to ACT7 of transistors T1 to T7 provided in the second pixels PXL2_k and PXL2_k+1 may be provided in the same layer. For example, the eighth active pattern ACT8 may be located in an active pattern layer provided between the substrate SUB and the first insulating layer GI.

[0250] The eighth active pattern ACT8 may be formed from an undoped or impurity-doped semiconductor layer. In some embodiments, the eighth active pattern ACT8 may have a strip shape extending in the second direction DR2 and may be arranged in a plurality of such strips in the first direction DR1. However, this disclosure is not limited thereto. When viewed from a top view or plan view, the eighth active pattern ACT8 may partially overlap with the dummy line DML, and the eighth active pattern ACT8 and the dummy line DML are separated by a first insulating layer GI and a second insulating layer IL1 to maintain the state of insulation between the eighth active pattern ACT8 and the dummy line DML.

[0251] In some embodiments, the main bus PLB may extend from power lines PLk and PLk+1 connected to second pixels PXL2_k and PXL2_k+1 arranged adjacent to the dummy region DMP, and be integrally formed with the power lines PLk and PLk+1. The main bus PLB may be provided in the same layer as the data lines Dk and Dk+1 and the power lines PLk and PLk+1. For example, the main bus PLB may be arranged in a third conductive layer on a third insulating layer IL2, spaced apart from the dummy line DML, wherein the third insulating layer IL2 is provided on the second conductive layer. The main bus PLB may overlap with the eighth active pattern ACT8 and the dummy line DML, wherein the first insulating layer GI, the second insulating layer IL1 and / or the third insulating layer IL2 are located between the main bus PLB and the eighth active pattern ACT8 and the dummy line DML. The main bus PLB may cover all or part of the second surrounding region PPA2.

[0252] In some embodiments, a fixed voltage supplied to power lines PLk and PLk+1 may be applied to the main bus PLB. For example, the fixed voltage may be a first power supply applied to the first power line ELVDD.

[0253] In some embodiments, the main bus PLB and the eighth active pattern ACT8 can be electrically connected to each other via contact holes CNT3 passing through the first insulating layer GI, the second insulating layer IL1, and the third insulating layer IL2. In some embodiments, the contact holes CNT3 can be arranged in the region where the main bus PLB and the eighth active pattern ACT8 overlap. For example, the contact holes CNT3 can be provided in the region where the dummy line DML is not provided and the main bus PLB and the eighth active pattern ACT8 overlap. In some embodiments, at least one contact hole CNT3 can be provided; however, the number of contact holes CNT3 is not particularly limited. For example, multiple contact holes CNT3 can be evenly distributed in the dummy region DMP.

[0254] In some embodiments, a number of contact holes CNT3 having a number equal to or less than the number of contact holes CH1 to CH10 provided in each of the predetermined second pixels PXL2_k and PXL2_k+1 may be provided in the dummy region DMP. Here, the second pixels PXL2_k and PXL2_k+1 may be pixels arranged in the second display area PXA2 along the second direction DR2 closest to the dummy region DMP.

[0255] If multiple contact holes CNT3 are arranged in the dummy region DMP, the density of components (e.g., lines, active patterns, contact holes, etc.) arranged in the second pixels PXL2_k and PXL2_k+1 closest to the dummy region DMP can become similar to the density of components arranged in the dummy region DMP. Therefore, the second pixels PXL2_k and PXL2_k+1 can be easily formed as needed in the process using a mask.

[0256] A fourth insulating layer PSV may be provided on a substrate SUB on which a main bus PLB is formed. Additionally, a pixel defining layer PDL may be provided on the substrate SUB on which the fourth insulating layer PSV is formed. In some embodiments, the fourth insulating layer PSV and the pixel defining layer PDL may be organic insulating layers made of organic materials. An encapsulation layer SLM covering the pixel defining layer PDL may be provided on the pixel defining layer PDL.

[0257] In the above embodiments of this disclosure, the dummy line DML and the first power line ELVDD overlap each other at least in the dummy region DMP. Therefore, parasitic capacitance is formed in the dummy region DMP. Consequently, the load values ​​of the second control lines S2i-1, S2i, S2i+1, and E2i connected to the dummy line DML increase. Therefore, the difference between the load values ​​of the first control lines S1i-1, S1i, S1i+1, and E1i provided in the first display region PXA1 and the load values ​​of the second control lines S2i-1, S2i, S2i+1, and E2i provided in the second display region PXA2 can be compensated.

[0258] In some embodiments, the dimensions (length, width, area, thickness, etc.) and / or the materials constituting the dummy line DML may be configured such that the load values ​​of the first control lines S1i-1, S1i, S1i+1, and E1i are similar to or equal to the load values ​​of the second control lines S2i-1, S2i, S2i+1, and E2i. That is, in embodiments of this disclosure, the parasitic capacitance formed in the dummy line DML may be set differently depending on the load values ​​of the second control lines S2i-1, S2i, S2i+1, and E2i to be compensated.

[0259] In the embodiments described above, the second control lines S2i-1, S2i, S2i+1, and E2i are located in the first conductive layer (first gate layer) adjacent to the active pattern layer in which the active patterns ACT1 to ACT7 of transistors T1 to T7 are disposed. That is, as described above, a region of each of the second control lines S2i-1, S2i, S2i+1, and E2i overlaps with the active pattern ACT of a designated or predetermined transistor, wherein a first insulating layer GI of relatively thin thickness is disposed between them, such that the designated or predetermined transistor whose gate electrode is connected to the second control lines S2i-1, S2i, S2i+1, and E2i can be smoothly driven.

[0260] Unlike the second control lines S2i-1, S2i, S2i+1, and E2i, the dummy lines DMLi1, DMLi2, DMLi3, and DMLi4 are located in the second conductive layer (second gate layer) on the second insulating layer IL1 in at least the dummy region DMP. Therefore, the dummy lines DMLi1, DMLi2, DMLi3, and DMLi4 are separated from the eighth active pattern ACT8, with at least the first insulating layer GI and the second insulating layer IL1 positioned between them. Thus, although ESD and the like are introduced into the dummy region DMP, the probability of a short circuit occurring between the dummy lines DMLi1, DMLi2, DMLi3, and DMLi4 and the eighth active pattern ACT8 is reduced. In other words, according to the embodiments of this disclosure, since the dummy region DMP is located in the edge region of the substrate SUB, the dummy lines DMLi1, DMLi2, DMLi3 and DMLi4 are arranged in the second conductive layer in the dummy region DMP, which has a relatively high ESD that is likely to be introduced into the dummy region DMP, so that sufficient distance can be ensured between the eighth active pattern ACT8 and the dummy lines DMLi1, DMLi2, DMLi3 and DMLi4.

[0261] Although dummy lines DMLi1, DMLi2, DMLi3, and DMLi4 are arranged in the second conductive layer, they are separated from the main bus PLB by a third insulating layer IL2, which can be formed to be relatively thicker than the first insulating layer GI and the second insulating layer IL1. The third insulating layer IL2 has a relatively less restricted thickness compared to either the first insulating layer GI or the second insulating layer IL1, where the thickness of the first insulating layer GI is restricted to ensure the driving stability of transistors T1 to T7, and the thickness of the second insulating layer IL1 is restricted to ensure the capacitance of the storage capacitor Cst. For example, the third insulating layer IL2 can be formed to have a thickness greater than the sum of the thicknesses of the first insulating layer GI and the second insulating layer IL1.

[0262] For example, the first insulating layer GI and the second insulating layer IL1 can have similar thickness ranges, for example, to The range, and the third insulating layer IL2 can be set to a thickness of twice or greater than that of the first insulating layer GI or the second insulating layer IL1. For example, the third insulating layer IL2 can have approximately The thickness of the insulating layer. In some embodiments, each of the first insulating layer GI located between the active pattern ACT of the display area PXA and the gate electrode GE, and the second insulating layer IL1 located between the upper electrode UE and the lower electrode LE of the storage capacitor Cst, may have a thickness corresponding to approximately 15% to approximately 25% of the total thickness obtained by adding the thicknesses of the first to third insulating layers GI, IL1, and IL2. Since both the first insulating layer GI and the second insulating layer IL1 are located between the eighth active pattern ACT8 and the dummy line DML of the dummy region, the insulating layer between the eighth active pattern ACT8 and the dummy line DML may have a thickness corresponding to approximately 30% or greater (e.g., approximately 30% to approximately 50%) of the total thickness obtained by adding the thicknesses of the first to third insulating layers GI, IL1, and IL2. In addition, since the third insulating layer IL2 has a thickness equal to or greater than the total thickness of the first insulating layer GI and the second insulating layer IL1, the distance between the dummy line DML of the dummy region DMP and the main bus PLB may be equal to or greater than the distance between the eighth active pattern ACT8 and the dummy line DML. In other words, the third insulating layer IL2, placed between the dummy line DML and the main bus PLB, may have a thickness that corresponds to 50% or more of the total thickness obtained by adding the thicknesses of the first to third insulating layers GI, IL1 and IL2.

[0263] Therefore, although the dummy lines DMLi1, DMLi2, DMLi3, and DMLi4 are arranged in the second conductive layer, sufficient distance can be ensured between the dummy lines DMLi1, DMLi2, DMLi3, and DMLi4 and the main bus PLB. In other words, according to embodiments of this disclosure, the occurrence rate of short circuits between the dummy line DML and the first power line ELVDD can be prevented or substantially reduced.

[0264] As described above, according to embodiments of this disclosure, by compensating for the differences between the load values ​​of the first control lines S1i-1, S1i, S1i+1 and E1i and the load values ​​of the second control lines S1i-1, S2i, S2i+1 and E2i, a display device with a strong ESD-resistant structure can be provided while displaying images with uniform image quality.

[0265] For convenience, Figures 8 to 10 A dummy region DMP located in the second surrounding region PPA2 and including dummy lines DMLi1, DMLi2, DMLi3, and DMLi4 connected to the second pixel PXL2 has been illustrated, and the structure of the dummy region DMP has been described. However, in embodiments of this disclosure, a third control line connected to the third pixel PXL3 is included ( Figure 3 The dummy region DMP of the dummy lines (S31, S32, E31, and E32) can also be provided in the third surrounding region PPA3. That is, in some embodiments, the dummy region DMP located in the third surrounding region PPA3 can be configured to be substantially the same as the dummy region DMP located in the second surrounding region PPA2. Therefore, in the display device according to the embodiments of the present disclosure, the occurrence rate of short circuits in the dummy region DMP located in the third surrounding region PPA3 can be prevented or substantially reduced.

[0266] Figure 11 Illustration Figure 1 An embodiment of the detailed structure of the second pixel and the dummy region corresponding to region P1 is shown. Figure 11 The diagram shows... Figure 8 The structure of the virtual region shown has been partially modified. Figure 11 In, with Figures 8 to 10 Components that are similar to or identical to those shown are designated by the same reference numerals, and their detailed descriptions need not be repeated.

[0267] refer to Figure 11The number and / or distribution of contact holes CNT3 in the dummy region DMP can be changed, wherein the eighth active pattern ACT8 and the main bus PLB are electrically connected to each other through contact holes CNT3. For example, contact holes CNT3 are not provided in the region between dummy lines DMLi1, DMLi2, DMLi3 and DMLi4, and can be provided at the edges of the dummy region DMP (e.g., only one edge). For example, contact holes CNT3 can be provided at the upper edge of the dummy region DMP (e.g., the upper edge of the substrate SUB) and the lower edge of the dummy region DMP (e.g., between the second display region PXA2 and the dummy region DMP). In another embodiment, contact holes CNT3 can be provided at the upper edge of the dummy region DMP (e.g., only the upper edge), or can be provided at the lower edge of the dummy region DMP (e.g., only the lower edge). However, the location of contact holes CNT3 is not limited to this and can be changed and implemented in various suitable forms.

[0268] In some embodiments, the first power line ELVDD may include a plurality of eighth active patterns ACT8, a main bus PLB, and a plurality of contact holes CNT3, wherein the plurality of eighth active patterns ACT8 extend between the substrate SUB and the first insulating layer GI in a direction intersecting with dummy lines DMLi1, DMLi2, DMLi3, and DMLi4, the main bus PLB is located in a third conductive layer on the third insulating layer IL2 to overlap with the eighth active patterns ACT8, and the plurality of contact holes CNT3 are provided at the edge of the dummy region DMP, the plurality of contact holes CNT3 electrically connecting the eighth active patterns ACT8 and the main bus PLB passing through them.

[0269] In other words, in the display device according to embodiments of the present disclosure, the contact structure between the eighth active pattern ACT8, which constitutes the first power line ELVDD, and the main bus PLB is not particularly limited. For example, the eighth active pattern ACT8 and the main bus PLB can be connected in various suitable forms, taking into account the area of ​​the available surrounding area PPA, the process environment, etc.

[0270] Figure 12 Illustration Figure 1 An embodiment of the detailed structure of the second pixel and the dummy region corresponding to region P1 is shown. Figure 12 The diagram shows... Figure 8 The connection structure between the dummy line and the second control line shown has been partially modified. Figure 12 In, with Figures 8 to 10 Components that are similar to or identical to those shown are designated by the same reference numerals, and their detailed descriptions need not be repeated.

[0271] refer to Figure 12In some embodiments, the position of the conductive bridge BR can be appropriately changed in various ways. That is, in the display device according to embodiments of the present disclosure, the connection positions between the second control lines S2i-1, S2i, S2i+1 and E2i and the dummy lines DMLi1, DMLi2, DMLi3 and DMLi4 can be changed.

[0272] For example, at least some conductive bridges BR can be arranged on one side of the second display area PXA2 to be adjacent to the second display area PXA2, and other conductive bridges BR can be arranged on one side of the dummy area DMP to be adjacent to the dummy area DMP. For example, odd-numbered dummy lines DMLi1 and DMLi3 and their corresponding second control lines S2i-1 and E2i can be connected to conductive bridges BRi1 and BRi3 arranged on one side of the dummy area DMP. In addition, even-numbered dummy lines DMLi2 and DMLi4 and their corresponding second control lines S2i and S2i+1 can be connected by conductive bridges BRi2 and BRi4 arranged on one side of the second display area PXA2.

[0273] In other words, in some embodiments, a conductive bridge (e.g., BRi1 or BRi3) for connecting a pair of second control lines (e.g., S2i-1 or E2i) and dummy lines (e.g., DMLi1 or DMLi3) among the second control lines S2i-1, S2i, S2i+1 and E2i and dummy lines DMLi1, DMLi2, DMLi3 and DMLi4 may be arranged on one side of the dummy region DMP. Additionally, a conductive bridge (e.g., BRi2 or BRi4) for connecting the second control lines S2i-1, S2i, S2i+1, and E2i and the dummy lines DMLi1, DMLi2, DMLi3, and DMLi4 adjacent to the pair of second control lines (e.g., S2i-1 or E2i) and dummy lines (e.g., DMLi1 or DMLi3) may be arranged on one side of the second display area PXA2.

[0274] In embodiments of this disclosure, second control lines S2i-1 and E2i, connected to dummy lines (e.g., predetermined dummy lines) DMLi1 and DMLi3 via conductive bridges BRi1 and BRi3 arranged on one side of the dummy region DMP, can extend from the second display region PXA2 as a whole to the second surrounding region PPA2 in which conductive bridges BRi1 and BRi3 are arranged. In embodiments of this disclosure, dummy lines DMLi2 and DMLi4, connected to second control lines (e.g., predetermined second control lines) S2i and E2i+1 via conductive bridges BRi2 and BRi4 arranged on one side of the second display region PXA2, can extend from the dummy region DMP as a whole to the second surrounding region PPA2 on one side of the second display region PXA2.

[0275] There is no particular limitation on the number of contact holes CNT1 and CNT2 formed in each of the conductive bridges BRi1, BRi2, BRi3, and BRi4. For example, the number of contact holes CNT1 and CNT2 formed in the conductive bridges BRi1, BRi2, BRi3, and BRi4 can be adjusted by taking into account safety design space, contact resistance, etc.

[0276] In the embodiments described above, the extensions of the predetermined or set second control lines S2i-1 and E2i located in the first conductive layer and the extensions of the predetermined or set dummy lines DMLi2 and DMLi4 located in the second conductive layer are alternately arranged in the wiring region between the second display area PXA2 and the dummy area DMP. Since the first and second conductive layers are spaced apart from each other, with the second insulating layer IL1 placed therebetween, the extensions of the second control lines (e.g., predetermined second control lines) S2i-1 and E2i and the extensions of the dummy lines (e.g., predetermined dummy lines) DMLi2 and DMLi4 can be arranged in the wiring region, thus narrowing the distance between the extensions. As described above, according to embodiments of this disclosure, even when the number of second control lines S2i-1, S2i, S2i+1 and E2i and dummy lines DMLi1, DMLi2, DMLi3 and DMLi4 increases, or when the wiring area as a surrounding area is not sufficiently obtained, for example, when the second surrounding area PPA2 becomes narrower, the second control lines S2i-1, S2i, S2i+1 and E2i and dummy lines DMLi1, DMLi2, DMLi3 and DMLi4 can be easily connected.

[0277] According to this disclosure, a display device can be provided that, by compensating for differences in the load values ​​between lines, displays an image with uniform image quality while having a strong ESD-resistant structure.

[0278] It will be understood that while the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another. Therefore, the first element, component, region, layer, or portion discussed below may be referred to as the second element, component, region, layer, or portion without departing from the spirit and scope of the inventive concept.

[0279] For ease of description, spatial relative terms such as “below,” “under,” “down,” “below,” “above,” and “above” are used herein to describe the relationship of one element or feature relative to another element(s) as shown in the figures. It should be understood that spatial relative terms are intended to encompass different orientations of the device in use or operation, other than those depicted in the figures. For example, if the device in the figure is flipped, an element described as “below,” “under,” or “below” to other elements or features would be oriented “above” to other elements or features. Thus, the example terms “below” and “under” can encompass both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Additionally, it will be understood that when a layer is referred to as being “between” two layers, it may be the only layer between those two layers, or one or more intermediate layers may exist.

[0280] The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit the inventive concept. As used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of…”, when placed after a list of elements, modify the entire list of elements and not individual elements in the list. Furthermore, in describing embodiments of the inventive concept, the word “may” is used to refer to “one or more embodiments of the inventive concept.” Additionally, the term “exemplary” indicates an example or illustration.

[0281] It will be understood that when an element or layer is referred to as being "on", "connected to", "coupled to", or "adjacent to" another element or layer, it may be directly on, directly connected to, coupled to, or adjacent to the other element or layer, or there may be one or more intermediate elements or intermediate layers. When an element or layer is referred to as being "directly on", "directly connected to", "directly coupled to", or "immediately adjacent to" another element or layer, there are no intermediate elements or intermediate layers.

[0282] As used herein, the terms “substantially,” “approximately,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to take into account the inherent biases in the measured or calculated values ​​that would be recognized by those skilled in the art.

[0283] As used in this article, the term “use” can be considered synonymous with the term “utilize”.

[0284] Furthermore, any numerical range described herein is intended to include all sub-intervals containing the same numerical precision within the described range. For example, the range "1.0 to 10.0" is intended to include all sub-intervals between the described minimum value of 1.0 and the described maximum value of 10.0 (inclusive), that is, a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit described herein is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to amend this specification (including the claims) to clearly state any sub-intervals contained within the ranges clearly described herein. All such ranges are intended to be inherently described in this specification.

[0285] Example embodiments have been disclosed herein, and although specific terminology has been used, they are used and interpreted in a general and descriptive sense and not for limiting purposes. In some cases, as will be apparent to those skilled in the art at the time of filing this application, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless expressly stated otherwise. Therefore, those skilled in the art will understand that various suitable changes to form and detail may be made without departing from the spirit and scope of this disclosure as set forth in the following claims and their equivalents.

Claims

1. A display device, comprising: The substrate includes a first display area having a first width in a first direction, a second display area having a second width in the first direction that is less than the first width, a surrounding area surrounding the first display area and the second display area, and a dummy area in the surrounding area; The first pixel located in the first display area; The second pixel located in the second display area; A first control line is connected to the first pixel, and the first control line is in the first display area; A second control line connected to the second pixel, a portion of which is in the second display area; A dummy line connected to the second control line, a portion of which is located within the dummy region; A conductive bridge for connecting the second control line and the dummy line; as well as The power line located in the surrounding area, the power line at least partially overlapping the dummy line, The second control line is located at the first conductive layer on the first insulating layer, the first insulating layer is located on the substrate, the dummy line is located at the second conductive layer on the second insulating layer, and the second insulating layer is located on the first conductive layer.

2. The display device according to claim 1, wherein the conductive bridge is located on a third conductive layer on a third insulating layer, and the third insulating layer is located on the second conductive layer.

3. The display device according to claim 2, further comprising: An active pattern located between the substrate and the first insulating layer, wherein the active pattern is located in the dummy region. The portion of the dummy line overlaps with the active pattern in the dummy region.

4. The display device according to claim 1, wherein the conductive bridge is located on one side of the second display area.

5. The display device according to claim 1, wherein the conductive bridge is located on one side of the dummy region.

6. The display device of claim 1, wherein the second pixel is connected to a plurality of second control lines to which different signals are applied, and a plurality of dummy lines connected to different second control lines among the plurality of second control lines are located in the dummy region.

7. The display device according to claim 6, wherein the second control line among the plurality of second control lines and the dummy line corresponding to the second control line among the plurality of dummy lines are connected to each other through one of the first conductive bridges located on one side of the second display area, and The second control line among the plurality of second control lines and the dummy line among the plurality of dummy lines corresponding to the other second control line are connected to each other by one of the second conductive bridges located on one side of the dummy region.

8. The display device according to claim 7, wherein the dummy lines among the plurality of dummy lines connected to the first conductive bridge located on one side of the second display area and the dummy lines among the plurality of dummy lines connected to the second conductive bridge located on one side of the dummy area are alternately arranged in the dummy area.

9. The display device according to claim 1, wherein the power cord comprises: An active pattern located between the substrate and the first insulating layer; as well as The main bus is located at the third conductive layer on the third insulating layer, which is located on the second conductive layer, and the main bus is connected to the active pattern through a contact opening.

10. The display device according to claim 9, wherein the thickness of the third insulating layer is greater than the thickness of the first insulating layer and the thickness of the second insulating layer.

11. The display device according to claim 10, wherein the thickness of the third insulating layer is equal to or greater than the sum of the thickness of the first insulating layer and the thickness of the second insulating layer.

12. The display device according to claim 1, wherein the power cord comprises: A plurality of active patterns are located between the substrate and the first insulating layer, the plurality of active patterns extending in a direction intersecting the dummy line; The main bus is located at the third conductive layer on the third insulating layer, the third insulating layer is located on the second conductive layer, and the main bus overlaps with the active pattern; as well as Multiple contact openings located at the edge of the dummy region facilitate electrical connection between the active pattern and the main bus.

13. The display device of claim 1, wherein the second pixel includes at least one transistor connected to the second control line.

14. The display device of claim 13, wherein the transistor comprises: An active pattern located between the substrate and the first insulating layer; The source electrode and drain electrode are connected to the active pattern; as well as A gate electrode located on the first conductive layer and overlapping the active pattern, the first conductive layer being located on the first insulating layer, the gate electrode being connected to the second control line.

15. The display device according to claim 14, wherein the gate electrode is integrally connected to the second control line.

16. The display device of claim 1, wherein the second pixel includes at least one capacitor, the capacitor including a first electrode located at the first conductive layer and a second electrode located at the second conductive layer.

17. The display device according to claim 1, wherein the second control line includes at least one of the scan line, the light emission control line, and the initialization control line of the second pixel.

18. The display device according to claim 1, wherein the first pixel and the second pixel have the same structure.

Images