Test structure for evaluating peak current of metal interconnect lines and method of use thereof

Abstract

The application provides a test structure for evaluating peak current of metal interconnection line, which comprises first to fourth pads; first to third test lines are connected in parallel between the second and third pads; first to third high-voltage diodes are connected in series on the first to third test lines respectively; the positive poles of the first to third high-voltage diodes are connected with the second pad and the negative poles are connected with the third pad; a first monitoring line is connected between the first pad and the positive pole of the third high-voltage diode; a first monitoring high-voltage diode is connected in series on the first monitoring line; the positive pole of the first monitoring high-voltage diode is connected with the first pad and the negative pole is connected with the positive pole of the third high-voltage diode; a second monitoring line is connected between the fourth pad and the positive pole of the first high-voltage diode. The application is a new parallel test structure for the peak current of the later-stage interconnection line, and the high-voltage diode and the monitoring line are added to solve the problem that the peak current test of the parallel structure cannot be monitored.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a test structure for evaluating the peak current of metal interconnects and a method for using it. Background Technology

[0002] As integrated circuit technology continues to evolve, interconnect peak current has become a crucial factor in downstream reliability assessment. Currently, most interconnect peak current reliability assessment structures use single interconnects, which facilitates post-failure analysis, modeling, and localization. However, parallel interconnect structures more closely reflect actual circuit usage and represent the most stringent application scenarios compared to single interconnects. However, current parallel structure testing methods cannot directly determine the failure location through electrical signals; instead, physical fragmentation and scanning electron microscopy are required. This process is cumbersome and time-consuming, preventing its practical application in real-world testing and assessment.

[0003] To address the aforementioned issues, a novel test structure and its application method for evaluating the peak current of metal interconnects are required. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a test structure and method for evaluating the peak current of metal interconnects, which solves the problem that in the prior art, the failure location cannot be directly determined by electrical signals when testing parallel structures. Instead, the failure location can only be determined by physical fragmentation and scanning microscopy, which is a cumbersome and time-consuming process that prevents it from being truly used in actual testing and evaluation.

[0005] To achieve the above and other related objectives, the present invention provides a test structure for evaluating the peak current of a metal interconnect, comprising:

[0006] First to fourth solder pads;

[0007] The second and third pads are connected in parallel with the first to third test lines, and the first to third high voltage diodes are connected in series on the first to third test lines respectively. The positive terminals of the first to third high voltage diodes are connected to the second pad and the negative terminals are connected to the third pad respectively.

[0008] A first monitoring line is connected between the first solder pad and the positive terminal of the third high-voltage diode. A first monitoring high-voltage diode is connected in series on the first monitoring line. The positive terminal of the first monitoring high-voltage diode is connected to the first solder pad, and the negative terminal is connected to the positive terminal of the third high-voltage diode.

[0009] A second monitoring line is connected between the fourth pad and the positive terminal of the first high-voltage diode. A second monitoring high-voltage diode is connected in series on the second monitoring line. The positive terminal of the second monitoring high-voltage diode is connected to the fourth pad, and the negative terminal is connected to the positive terminal of the first high-voltage diode.

[0010] The test structure includes a test mode and a monitoring mode;

[0011] When the test mode is working: the first, third, and fourth solder pads are grounded, and the second solder pad is connected to a positive voltage;

[0012] When the monitoring mode is working: the first and fourth pads are connected to positive voltage, the second pad is grounded, and the third pad is disconnected or connected to a voltage slightly greater than the positive voltage connected to the first and fourth pads.

[0013] Preferably, the first to fourth solder pads are all rectangular in shape.

[0014] Preferably, the test structure is formed using a patterning process for a metal layer.

[0015] Preferably, the spacing between the first to third test lines is greater than or equal to the minimum design size under the corresponding process; the width of the first to third test lines is greater than or equal to the minimum design size under the corresponding process.

[0016] Preferably, the material of the first to fourth bonding pads is aluminum.

[0017] Preferably, the material of the first to third test connections is copper or aluminum.

[0018] Preferably, the material of the first and second monitoring connection is copper or aluminum.

[0019] The present invention also provides a method of using a test structure for evaluating the peak current of a metal interconnect, comprising: providing first to fourth pads;

[0020] The second and third pads are connected in parallel with the first to third test lines, and the first to third high voltage diodes are connected in series on the first to third test lines respectively. The positive terminals of the first to third high voltage diodes are connected to the second pad and the negative terminals are connected to the third pad respectively.

[0021] A first monitoring line is connected between the first solder pad and the positive terminal of the third high-voltage diode. A first monitoring high-voltage diode is connected in series on the first monitoring line. The positive terminal of the first monitoring high-voltage diode is connected to the first solder pad, and the negative terminal is connected to the positive terminal of the third high-voltage diode. A second monitoring line is connected between the fourth solder pad and the positive terminal of the first high-voltage diode. A second monitoring high-voltage diode is connected in series on the second monitoring line. The positive terminal of the second monitoring high-voltage diode is connected to the fourth solder pad, and the negative terminal is connected to the positive terminal of the first high-voltage diode.

[0022] The test structure includes a test mode and a monitoring mode:

[0023] When the test mode is working, the first, third, and fourth pads are grounded, and the second pad is connected to a positive voltage;

[0024] When the monitoring mode is working: the first and fourth pads are connected to positive voltage, the second pad is grounded, and the third pad is disconnected or connected to a voltage slightly greater than the positive voltage connected to the first and fourth pads.

[0025] Preferably, the test mode is used to determine whether the first to third test connections are open-circuited; the monitoring mode is used to determine which test connection is open-circuited. When the first and third test connections are connected, the test current when the second test connection blows is the peak current of the interconnecting lines of the first to third test connections connected in parallel.

[0026] As described above, the test structure and method for evaluating the peak current of metal interconnects of the present invention have the following beneficial effects:

[0027] This invention presents a novel parallel test structure for peak current in downstream interconnects. It adds a high-voltage diode and a monitoring connection to address the issue of unmonitored peak current testing in parallel structures. Utilizing the unidirectional conduction characteristic of the high-voltage diode, the testing and monitoring processes can be performed independently without interference. The addition of the monitoring section enables the parallel structure to accurately determine the timing and location of failure through electrical means, thus facilitating the feasibility of assessing the most stringent reliability conditions. Attached Figure Description

[0028] Figure 1 The diagram shown is a schematic representation of the test structure of this invention.

[0029] Figure 2 The diagram shows a test mode schematic of the test structure of the present invention.

[0030] Figure 3 The diagram shown illustrates the monitoring mode of the test structure of this invention.

[0031] Explanation of reference numerals in the attached figures:

[0032] First solder pad 101

[0033] Second solder pad 102

[0034] Third solder pad 103

[0035] Fourth solder pad 104

[0036] First test connection 105

[0037] Second test connection 106

[0038] Third test connection 107

[0039] First high-voltage diode 108

[0040] Second high-voltage diode 109

[0041] Third high-voltage diode 110

[0042] First monitoring line 111

[0043] First monitoring high-voltage diode 112

[0044] Second monitoring line 113

[0045] Second monitoring high voltage diode 114 Detailed Implementation

[0046] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0047] This invention provides a test structure for evaluating the peak current of a metal interconnect, comprising:

[0048] First to fourth solder pads 104;

[0049] In one alternative implementation, the first to fourth pads are all rectangular in shape.

[0050] In one alternative implementation, the test structure is formed using a patterning process for a metal layer, namely, after depositing a metal layer, a photoresist layer is formed on the metal layer, and then the desired test structure is formed by photolithography and etching.

[0051] The first to third test lines are connected in parallel between the second and third pads. The first to third high voltage diodes are connected in series on the first to third test lines respectively. The positive terminals of the first to third high voltage diodes are connected to the second pad 102 and the negative terminals are connected to the third pad 103 respectively.

[0052] A first monitoring line 111 is connected between the first pad 101 and the positive terminal of the third high-voltage diode. A first monitoring high-voltage diode 112 is connected in series on the first monitoring line 111. The positive terminal of the first monitoring high-voltage diode 112 is connected to the first pad 101, and the negative terminal is connected to the positive terminal of the third high-voltage diode.

[0053] A second monitoring line 113 is connected between the fourth pad 104 and the positive terminal of the first high voltage diode 108. A second monitoring high voltage diode 114 is connected in series on the second monitoring line 113. The positive terminal of the second monitoring high voltage diode 114 is connected to the fourth pad 104, and the negative terminal is connected to the positive terminal of the first high voltage diode.

[0054] In one alternative implementation, the spacing between the first to third test lines is greater than or equal to the minimum design size under the corresponding process; the width of the first to third test lines is greater than or equal to the minimum design size under the corresponding process.

[0055] In one alternative implementation, the first to fourth pads are made of aluminum.

[0056] In one alternative implementation, the material of the first to third test connections is copper or aluminum.

[0057] In one alternative implementation, the material of the first and second monitoring connection is copper or aluminum.

[0058] It should be noted that other types of materials can also be used for the test structure; no specific restrictions are made here.

[0059] The test structure includes test mode and monitoring mode;

[0060] When working in test mode: the first, third, and fourth pads are grounded, and the second pad 102 is connected to positive voltage;

[0061] When operating in monitoring mode: the first and fourth pads are connected to positive voltage, the second pad 102 is grounded, and the third pad 103 is disconnected or connected to a voltage slightly greater than the positive voltage connected to the first and fourth pads.

[0062] Specifically, the second and third pads form the first to third test connections to be tested. A high-voltage diode is added to the lead of each test connection to achieve unidirectional conduction. At this time, the second and third pads form the test path for the first to third test connections. The first test connection 105 has a second monitoring connection 113 to the fourth pad 104 added to the lead. A high-voltage diode is also added to the monitoring connection 113 to achieve unidirectional conduction. At this time, the second pad 102 and the fourth pad 104 form the monitoring path for the first test connection 105. Similarly, the first pad 101 and the second pad 102 form the monitoring path for the third test connection 107.

[0063] During testing, the first, third, and fourth pads are grounded, and the second pad 102 is connected to a positive voltage. The diode in the test path is turned on, while the diode in the monitoring path is turned off. Therefore, the test signal flows from the second pad 102 to the third pad 103, and the test process proceeds normally.

[0064] During monitoring, the first and fourth pads are connected to a positive voltage, the second pad 102 is grounded, and the third pad 103 is either disconnected or connected to a voltage slightly greater than the positive voltages connected to the first and fourth pads. The test path diode is cut off, while the monitoring path diode is turned on. Therefore, the monitoring signal flows from the first pad 101 to the second pad 102 and from the fourth pad 104 to the second pad 102, and the monitoring process proceeds normally.

[0065] The failure mode of peak current testing for parallel interconnects is mostly the melting and opening of the innermost test connection. First, switch to test mode; a change in the test signal indicates an open circuit in the first to third test connections. By combining the monitoring signal with the monitoring mode, the connectivity of the first test connection 105 and the third test connection 107 can be determined. If both the first and third test connections are connected and there is an open circuit in the first to third test connections, it can be inferred that the second test connection 106 has melted. At this point, the test current is the peak current of the parallel interconnect.

[0066] The present invention also provides a method of using a test structure for evaluating the peak current of a metal interconnect, comprising: providing first to fourth pads 104;

[0067] The first to third test lines are connected in parallel between the second and third pads. The first to third high voltage diodes are connected in series on the first to third test lines respectively. The positive terminals of the first to third high voltage diodes are connected to the second pad 102 and the negative terminals are connected to the third pad 103 respectively.

[0068] A first monitoring line 111 is connected between the first pad 101 and the positive terminal of the third high-voltage diode. A first monitoring high-voltage diode 112 is connected in series on the first monitoring line 111. The positive terminal of the first monitoring high-voltage diode 112 is connected to the first pad 101, and the negative terminal is connected to the positive terminal of the third high-voltage diode. A second monitoring line 113 is connected between the fourth pad 104 and the positive terminal of the first high-voltage diode 108. A second monitoring high-voltage diode 114 is connected in series on the second monitoring line 113. The positive terminal of the second monitoring high-voltage diode 114 is connected to the fourth pad 104, and the negative terminal is connected to the positive terminal of the first high-voltage diode.

[0069] The test structure includes test mode and monitoring mode:

[0070] When working in test mode, the first, third, and fourth pads are grounded, and the second pad 102 is connected to a positive voltage;

[0071] When operating in monitoring mode: the first and fourth pads are connected to positive voltage, the second pad 102 is grounded, and the third pad 103 is disconnected or connected to a voltage slightly greater than the positive voltage connected to the first and fourth pads.

[0072] In one optional implementation, the test mode is used to determine whether the first to third test connections are open-circuited; the monitoring mode is used to determine which test connection is open-circuited. When the first and third test connections are connected, the test current when the second test connection 106 blows is the peak current of the interconnecting lines of the first to third test connections connected in parallel.

[0073] Specifically, the second and third pads form the first to third test connections to be tested. A high-voltage diode is added to the lead of each test connection to achieve unidirectional conduction. At this time, the second and third pads form the test path for the first to third test connections. The first test connection 105 has a second monitoring connection 113 to the fourth pad 104 added to the lead. A high-voltage diode is also added to the monitoring connection 113 to achieve unidirectional conduction. At this time, the second pad 102 and the fourth pad 104 form the monitoring path for the first test connection 105. Similarly, the first pad 101 and the second pad 102 form the monitoring path for the third test connection 107.

[0074] During testing, the first, third, and fourth pads are grounded, and the second pad 102 is connected to a positive voltage. The diode in the test path is turned on, while the diode in the monitoring path is turned off. Therefore, the test signal flows from the second pad 102 to the third pad 103, and the test process proceeds normally.

[0075] During monitoring, the first and fourth pads are connected to a positive voltage, the second pad 102 is grounded, and the third pad 103 is either disconnected or connected to a voltage slightly greater than the positive voltages connected to the first and fourth pads. The test path diode is cut off, while the monitoring path diode is turned on. Therefore, the monitoring signal flows from the first pad 101 to the second pad 102 and from the fourth pad 104 to the second pad 102, and the monitoring process proceeds normally.

[0076] The failure mode of peak current testing for parallel interconnects is mostly the melting and opening of the innermost test connection. First, switch to test mode; a change in the test signal indicates an open circuit in the first to third test connections. By combining the monitoring signal with the monitoring mode, the connectivity of the first test connection 105 and the third test connection 107 can be determined. If both the first and third test connections are connected and there is an open circuit in the first to third test connections, it can be inferred that the second test connection 106 has melted. At this point, the test current is the peak current of the parallel interconnect.

[0077] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0078] In summary, this invention provides a novel parallel test structure for peak current in downstream interconnects. By adding a high-voltage diode and monitoring wiring, it addresses the issue of unmonitored peak current testing in parallel structures. Utilizing the unidirectional conduction characteristic of the high-voltage diode, the testing and monitoring processes can be performed independently without interference. The addition of the monitoring component enables the parallel structure to accurately determine the timing and location of failure through electrical means, thus facilitating the feasibility of assessing the most stringent reliability conditions. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and possesses high industrial applicability.

[0079] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A test structure for evaluating the peak current of a metal interconnect, characterized in that, include: First to fourth solder pads; The second and third pads are connected in parallel with the first to third test lines. The first to third high voltage diodes are connected in series on the first to third test lines respectively. The positive terminals of the first to third high voltage diodes are connected to the second pad and the negative terminals are connected to the third pad respectively. A first monitoring line is connected between the first pad and the positive terminal of the third high-voltage diode. A first monitoring high-voltage diode is connected in series on the first monitoring line. The positive terminal of the first monitoring high-voltage diode is connected to the first pad, and the negative terminal is connected to the positive terminal of the third high-voltage diode. A second monitoring line is connected between the fourth pad and the positive terminal of the first high-voltage diode. A second monitoring high-voltage diode is connected in series on the second monitoring line. The positive terminal of the second monitoring high-voltage diode is connected to the fourth pad, and the negative terminal is connected to the positive terminal of the first high-voltage diode. The test structure includes a test mode and a monitoring mode; When the test mode is working: the first, third and fourth pads are grounded, and the second pad is connected to a positive voltage; When the monitoring mode is working: the first and fourth pads are connected to positive voltage, the second pad is grounded, and the third pad is disconnected or connected to a voltage slightly greater than the positive voltage connected to the first and fourth pads.

2. The test structure for evaluating the peak current of a metal interconnect according to claim 1, characterized in that: The first to fourth solder pads are all rectangular in shape.

3. The test structure for evaluating the peak current of a metal interconnect according to claim 1, characterized in that: The test structure is formed using a patterning process for metal layers.

4. The test structure for evaluating the peak current of a metal interconnect according to claim 1, characterized in that: The spacing between the first to third test lines is greater than or equal to the minimum design size under the corresponding process; the width of the first to third test lines is greater than or equal to the minimum design size under the corresponding process.

5. The test structure for evaluating the peak current of a metal interconnect according to claim 1, characterized in that: The material of the first to fourth bonding pads is aluminum.

6. The test structure for evaluating the peak current of a metal interconnect according to claim 1, characterized in that: The material of the first to third test connections is copper or aluminum.

7. The test structure for evaluating the peak current of a metal interconnect according to claim 1, characterized in that: The material of the first and second monitoring cables is copper or aluminum.

8. The method of using the test structure for evaluating the peak current of a metal interconnect according to any one of claims 1 to 7, characterized in that: Provide the first to fourth solder pads; The second and third pads are connected in parallel with the first to third test lines. The first to third high voltage diodes are connected in series on the first to third test lines respectively. The positive terminals of the first to third high voltage diodes are connected to the second pad and the negative terminals are connected to the third pad respectively. A first monitoring line is connected between the first solder pad and the positive terminal of the third high-voltage diode. A first monitoring high-voltage diode is connected in series on the first monitoring line. The positive terminal of the first monitoring high-voltage diode is connected to the first solder pad, and the negative terminal is connected to the positive terminal of the third high-voltage diode. A second monitoring line is connected between the fourth solder pad and the positive terminal of the first high-voltage diode. A second monitoring high-voltage diode is connected in series on the second monitoring line. The positive terminal of the second monitoring high-voltage diode is connected to the fourth solder pad, and the negative terminal is connected to the positive terminal of the first high-voltage diode. The test structure includes a test mode and a monitoring mode: When the test mode is working, the first, third, and fourth pads are grounded, and the second pad is connected to a positive voltage; When the monitoring mode is working: the first and fourth pads are connected to positive voltage, the second pad is grounded, and the third pad is disconnected or connected to a voltage slightly greater than the positive voltage connected to the first and fourth pads.

9. The method of using the test structure for evaluating the peak current of a metal interconnect according to claim 8, characterized in that: The test mode is used to determine whether the first to third test connections are open circuits; the monitoring mode is used to determine which test connection is open circuit; when the first and third test connections are connected and the second test connection is blown, the test current is the peak current of the interconnection line of the first to third test connections in parallel.

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