A low temperature coefficient CMOS reference voltage source and chip

Abstract

The present invention discloses a low temperature coefficient CMOS reference voltage source and chip, belonging to the technical field of integrated circuits. The reference voltage source includes: n T 2 Current generating circuit, used to generate a current with μ n V TH 2 The reference voltage output circuit includes a mirror unit and a reference unit, wherein the mirror unit is used to copy the current I1 according to a preset ratio to generate a current I2 to act on the reference unit; the reference unit includes an NMOS tube and a PMOS tube, wherein the V GS It is a concave curve, and the V SG It presents a convex curve, V GS and V SG The two are superimposed to obtain a low temperature coefficient reference voltage V REF The present invention utilizes the channel modulation effect to make the V GS It shows a concave curve, and the different temperature coefficients of electron and hole mobility are used to make the V SG The two curves are superimposed for secondary temperature compensation to obtain a low temperature coefficient CMOS reference voltage V REF , significantly reducing the temperature coefficient of the voltage reference.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a low temperature coefficient CMOS reference voltage source and a chip. Background Art

[0002] Reference voltage sources are widely used in analog integrated circuits and mixed analog-digital integrated circuits. With the popularization of electronic equipment in medical, automotive, server and consumer electronics fields, the requirements for key performance indicators such as temperature coefficient, power supply rejection ratio and linear regulation rate of reference voltage sources are becoming increasingly higher.

[0003] In existing CMOS reference voltage source technology, two transistors in series are often used. The first existing technical solution uses an operational amplifier for clamping to generate a precise bias current. This current flows through two standard NMOS transistors in series, and their gate-source voltages are weighted by two resistors to obtain a reference voltage. The reference voltage includes ΔV GS Positive temperature coefficient term and V with resistance ratio coefficient GS Negative temperature coefficient term, adjusting the resistor ratio can cancel the temperature coefficients of the two. Due to the use of operational amplifiers and resistors, its power consumption and area are limited, and the circuit accuracy depends on the accuracy of the resistor model. The existing second technical solution uses self-bias current to flow through two sub-threshold PMOS, through its ΔV GS Constructing a positive temperature coefficient voltage V PTAT , and then by superimposing the negative temperature coefficient V GS_PMOS The reference voltage is obtained because of the self-bias current structure, startup circuit, pre-regulation structure, and V GS_PMOS There are high-order temperature coefficients, the overall circuit is more complex, and the temperature coefficient, power consumption and area are larger. The existing third technical solution uses self-bias current to flow through the high threshold voltage NMOS and low threshold voltage NMOS in series to obtain a reference voltage. The reference voltage includes ΔV GSThe generated positive temperature coefficient term and the negative temperature coefficient term of the threshold voltage difference can be offset by adjusting the ratio of their width-to-length ratios. However, due to the presence of a self-biased current source structure, a capacitor startup circuit, and the high-order temperature coefficient of the positive temperature coefficient term, the circuit power consumption, area, and temperature coefficient are large. The fourth existing technical solution utilizes an intrinsic NMOS in series with a standard NMOS to obtain a reference voltage based on equal currents. The reference voltage includes a negative temperature coefficient term of the threshold voltage difference and a positive temperature coefficient term adjusted by the width-to-length ratio. Due to the high-order temperature coefficient of the positive temperature coefficient term, the circuit temperature coefficient is large. The fifth existing technical solution utilizes a depletion-type NMOS in series with a standard NMOS to obtain a reference voltage based on equal currents. The reference voltage is equal to the difference in threshold voltages based on the width-to-length ratio coefficient. Adjusting the width-to-length ratio can offset the two threshold voltage temperature coefficients. However, due to differences in the mobility temperature coefficients of different types of NMOS transistors, the temperature coefficient of this reference circuit is limited. Existing CMOS reference voltage sources have problems such as high temperature coefficients, complex circuits, and the use of passive components. Summary of the Invention

[0004] In order to solve at least one of the technical problems existing in the prior art to a certain extent, the present invention aims to provide a low temperature coefficient CMOS reference voltage source and chip.

[0005] The technical solution adopted in the present invention is:

[0006] A low temperature coefficient CMOS reference voltage source, comprising:

[0007] μ n T 2 Current generating circuit, used to generate a current with μ n V TH 2 The current I1 is proportional to the reference voltage output circuit, providing a bias current; where V TH is the threshold voltage of MOS;

[0008] The reference voltage output circuit includes a mirror unit and a reference unit. The mirror unit is used to copy the current I1 according to a preset ratio to generate a current I2 to act on the reference unit. The reference unit includes an NMOS tube and a PMOS tube, wherein the V GS It is a concave curve, and the V SG It presents a convex curve, V GS and V SG The two are superimposed and secondary temperature compensation is performed to obtain a low temperature coefficient reference voltage V REF .

[0009] Furthermore, the μ n T 2The current generating circuit includes a first PMOS transistor, a second PMOS transistor and a seventh NMOS transistor;

[0010] The source of the first PMOS transistor is connected to the power supply voltage VDD, and the drain and gate of the first PMOS transistor are both connected to the source of the second PMOS transistor;

[0011] The drain and gate of the second PMOS transistor are both connected to the drain of the seventh NMOS transistor;

[0012] The source and gate of the seventh NMOS transistor are both grounded.

[0013] Furthermore, the seventh NMOS transistor is a depletion-type NMOS transistor.

[0014] Furthermore, the expression of the current I1 is:

[0015]

[0016] Among them, μ n is the electron mobility, C ox is the gate oxide capacitance, (W / L)7 is the width-to-length ratio of the seventh NMOS tube, V THN is the threshold voltage of the seventh NMOS tube.

[0017] Furthermore, the mirror unit includes a third PMOS tube and a fourth PMOS tube;

[0018] The source of the third PMOS transistor is connected to the power supply voltage VDD, the gate of the third PMOS transistor is connected to the gate of the first PMOS transistor, and the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor;

[0019] The gate of the fourth PMOS transistor is connected to the gate of the second PMOS transistor, and the drain of the fourth PMOS transistor outputs current I2.

[0020] Furthermore, the reference unit includes a fifth PMOS transistor and a sixth NMOS transistor;

[0021] The source of the fifth PMOS transistor inputs current I2, and the gate and drain of the fifth PMOS transistor are both connected to the drain of the sixth NMOS transistor;

[0022] The gate of the sixth NMOS transistor is connected to the gate of the fifth PMOS transistor, and the source of the sixth NMOS transistor is grounded;

[0023] The source of the fifth PMOS tube outputs a low temperature coefficient reference voltage V REF .

[0024] Furthermore, the V on the fifth PMOS tube SG5 The expression is:

[0025]

[0026] The V GS6 The expression is:

[0027]

[0028] Among them, μ n is the electron mobility, C ox is the gate oxide capacitance, (W / L)5 is the width-to-length ratio of the fifth PMOS transistor, (W / L)6 is the width-to-length ratio of the sixth NMOS transistor, V THP5 is the threshold voltage of the fifth PMOS tube, V THN6 is the threshold voltage of the sixth NMOS tube.

[0029] Another technical solution adopted in the present invention is:

[0030] A chip includes the low temperature coefficient CMOS reference voltage source as described above.

[0031] The beneficial effect of the present invention is that the present invention utilizes the channel modulation effect to make the V GS It shows a concave curve, and the different temperature coefficients of electron and hole mobility are used to make the V SG The two curves are superimposed for secondary temperature compensation to obtain a low temperature coefficient CMOS reference voltage V REF , significantly reducing the temperature coefficient of the voltage reference. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following introduction is made to the drawings of the embodiments of the present invention or the related technical solutions in the prior art. It should be understood that the drawings introduced below are only for the convenience of clearly describing some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative work.

[0033] Figure 1 A circuit diagram of a low temperature coefficient CMOS reference voltage source according to an embodiment of the present invention;

[0034] Figure 2 This is a temperature characteristic simulation diagram of a low temperature coefficient CMOS reference voltage source according to an embodiment of the present invention;

[0035] Figure 3A power supply rejection ratio simulation diagram of a low temperature coefficient CMOS reference voltage source according to an embodiment of the present invention;

[0036] Figure 4 This is a simulation diagram of the linear regulation rate of a low temperature coefficient CMOS reference voltage source according to an embodiment of the present invention;

[0037] Figure 5 This is a power-on startup simulation diagram of a low temperature coefficient CMOS reference voltage source in an embodiment of the present invention. DETAILED DESCRIPTION

[0038] The embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention and are not to be construed as limiting the present invention. The step numbers in the following embodiments are provided for ease of explanation only and do not limit the order of the steps. The order of execution of the steps in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0039] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present invention.

[0040] In the description of the present invention, "several" means one or more, "many" means more than two, "greater than," "less than," and "exceed" are understood to exclude the number itself, while "above," "below," and "within" are understood to include the number itself. The use of "first" and "second" in the description is solely for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, implicitly specifying the number of the indicated technical features, or implicitly specifying the order of the indicated technical features.

[0041] Furthermore, in the description of this invention, unless otherwise specified, "plurality" refers to two or more. "And / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0042] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, and connecting should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0043] In view of the problems and shortcomings of the existing technology, in order to solve the problems of the existing CMOS reference with high temperature coefficient, complex circuit, and use of passive components, this application proposes a low temperature coefficient CMOS reference voltage source. The reference voltage source of this application does not use resistors and bipolar transistors, but uses a depletion-type NMOS tube to generate a voltage with μ n V THN 2 The stable current is proportional to the current, and no startup circuit is required. The current is copied to the PMOS and NMOS working in the saturation region through the cascode current mirror, and the channel modulation effect is used to make the V GS It shows a concave curve, and the different temperature coefficients of electron and hole mobility are used to make the V SG It presents a convex curve, so that the two voltages are superimposed and secondary temperature compensation is performed to obtain a reference voltage V with a low temperature coefficient. REF .

[0044] like Figure 1 As shown, this embodiment provides a low temperature coefficient CMOS reference voltage source, including:

[0045] μ n T 2 Current generating circuit, used to generate a current with μ n V TH 2 The current I1 is proportional to the reference voltage output circuit, providing a bias current; where V TH is the threshold voltage of MOS;

[0046] The reference voltage output circuit includes a mirror unit and a reference unit. The mirror unit is used to copy the current I1 according to a preset ratio to generate a current I2 to act on the reference unit. The reference unit includes an NMOS tube and a PMOS tube, wherein the V GS It is a concave curve, and the V SG It presents a convex curve, V GS and V SG The two are superimposed and secondary temperature compensation is performed to obtain a low temperature coefficient reference voltage V REF .

[0047] In this embodiment, μ n V THN 2 The current generating circuit generates μ n V THN 2 current, the reference voltage output circuit copies μ n V THN 2The current is made to flow through the PMOS and NMOS working in the saturation region, and the V GS It shows a concave curve, and the different temperature coefficients of electron and hole mobility are used to make the V SG The two curves are superimposed for secondary temperature compensation to obtain a low temperature coefficient CMOS reference voltage V REF .

[0048] See also Figure 1 As an optional implementation, the μ n T 2 The current generating circuit includes a first PMOS transistor M1, a second PMOS transistor M2 and a seventh NMOS transistor M7;

[0049] The source of the first PMOS transistor M1 is connected to the power supply voltage VDD, and the drain and gate of the first PMOS transistor M1 are both connected to the source of the second PMOS transistor M2;

[0050] The drain and gate of the second PMOS transistor M2 are both connected to the drain of the seventh NMOS transistor M7;

[0051] The source and gate of the seventh NMOS transistor M7 are both grounded.

[0052] μ n V THN 2 The seventh NMOS transistor M7 in the current generating circuit is a depletion-type NMOS transistor, whose gate terminal is connected to GND. The generated current I1 is:

[0053]

[0054] where μ n is the electron mobility, C ox is the gate oxide capacitance, (W / L)7 is the width-to-length ratio of the seventh NMOS transistor M7, V THN7 is the threshold voltage of the seventh NMOS transistor M7. From formula (1), we can see that I1 and μ n V THN 2 The operating current can be adjusted by adjusting the width-to-length ratio of the seventh NMOS transistor M7.

[0055] See also Figure 1 As an optional implementation, the mirror unit includes a third PMOS transistor M3 and a fourth PMOS transistor M4;

[0056] The source of the third PMOS transistor M3 is connected to the power supply voltage VDD, the gate of the third PMOS transistor M3 is connected to the gate of the first PMOS transistor M1, and the drain of the third PMOS transistor M3 is connected to the source of the fourth PMOS transistor M4;

[0057] The gate of the fourth PMOS transistor M4 is connected to the gate of the second PMOS transistor M2 , and the drain of the fourth PMOS transistor M4 outputs current I2 .

[0058] The reference unit includes a fifth PMOS transistor M5 and a sixth NMOS transistor M6;

[0059] The source of the fifth PMOS transistor M5 inputs the current I2, and the gate and drain of the fifth PMOS transistor M5 are both connected to the drain of the sixth NMOS transistor M6;

[0060] The gate of the sixth NMOS transistor M6 is connected to the gate of the fifth PMOS transistor M5, and the source of the sixth NMOS transistor M6 is grounded;

[0061] The source of the fifth PMOS transistor M5 outputs a low temperature coefficient reference voltage V REF .

[0062] The reference voltage output circuit copies I1 in the same proportion through PMOS tubes M3~M4 to generate I2, which flows to the fifth PMOS tube M5 and the sixth NMOS tube M6 working in the saturation region. The V GS6 for:

[0063]

[0064] Where V THN6 is the threshold voltage of the sixth NMOS tube M6, which has a negative temperature coefficient. n V THN 2 The seventh NMOS transistor M7 in the generating circuit is affected by the channel modulation effect, so I2 is proportional to μ n V THN 2 (1+λV DS7 ), λ is the channel modulation effect coefficient of the seventh NMOS tube M7, V DS7 is the drain-source voltage of the seventh NMOS tube M7. Since the width-to-length ratio of the first PMOS tube M1 and the second PMOS tube M2 is small, V DS7 It shows a positive temperature coefficient. Therefore, in formula (2), the positive temperature coefficient of the latter term is less than the negative temperature coefficient of the threshold voltage at low temperatures, and the positive temperature coefficient of the latter term is greater than the negative temperature coefficient of the threshold voltage at high temperatures. Therefore, V GS6 It presents a concave curve.

[0065] Its M5 VSG5 for:

[0066]

[0067] Where V THP5 is the threshold voltage of the fifth PMOS tube M5, which has a negative temperature coefficient, μ p is the hole mobility, since μ p Temperature coefficient greater than μ n Temperature coefficient, so the positive temperature coefficient of the latter term in formula (3) is greater than the negative temperature coefficient of the threshold voltage at low temperatures, and the positive temperature coefficient of the latter term is less than the negative temperature coefficient of the threshold voltage at high temperatures, so V SG5 It presents a convex curve.

[0068] Therefore, the reference voltage V REF for:

[0069] V REF =V GS6 +V SG5 (4)

[0070] The reference voltage is V SG5 Convex curve and V GS6 The superposition of concave curves is used to perform secondary temperature compensation, further reducing V REF Temperature coefficient.

[0071] As an optional implementation, the MOS transistors M1 to M6 are all 3.3V MOS transistors.

[0072] The voltage reference source of this embodiment does not use bipolar transistors or resistors, reducing layout area and cost. Instead, it utilizes a single depletion-mode NMOS transistor to form a stable current source, eliminating the need for a startup circuit. This simplifies the circuit and reduces power consumption. The reference voltage is also subjected to secondary temperature compensation, achieving a low temperature coefficient. The CMOS voltage reference source of this application was simulated using the Cadence Virtuoso tool platform in an X-FAB 0.35μm process. The layout area of ​​this embodiment is 45μm × 100μm. Figure 2 This is the temperature characteristic simulation diagram of the CMOS reference voltage source of this application. Under the power supply voltage of 3V and the temperature range of -40℃~125℃, the reference voltage source V REF The temperature coefficient is 0.96ppm / ℃; Figure 3 This is a simulation diagram of the power supply rejection ratio of the CMOS reference voltage source of this application. Under a power supply voltage of 3V, the power supply rejection ratio of this reference voltage source is -67.205dB at 10Hz; Figure 4 This is a simulation diagram of the linear regulation rate of the CMOS reference voltage source of this application. The reference voltage source has a linear regulation rate of 0.0095% / V and a total current of 80nA. Figure 5This is the power-on simulation diagram of the CMOS reference voltage source of this application. 5μs after power-on, V REF These simulation results verify that the reference voltage source has the characteristics of low temperature coefficient, low linear regulation rate and self-starting.

[0073] In the above description of this specification, reference to the terms "one embodiment / example," "another embodiment / example," or "certain embodiments / examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0074] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the claims and their equivalents.

[0075] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A low temperature coefficient CMOS reference voltage source, characterized in that: include: μ n T 2 Current generating circuit, used to generate a current with μ n V TH 2 The proportional current I1 provides bias current for the reference voltage output circuit; Among them, V TH is the threshold voltage of MOS; The reference voltage output circuit includes a mirror unit and a reference unit. The mirror unit is used to copy the current I1 according to a preset ratio to generate a current I2 to act on the reference unit. The reference unit includes an NMOS tube and a PMOS tube, wherein the V GS It is a concave curve, and the V SG It presents a convex curve, V GS and V SG The two are superimposed and secondary temperature compensation is performed to obtain a low temperature coefficient reference voltage V REF ; The μ n T 2 The current generating circuit includes a first PMOS transistor, a second PMOS transistor and a seventh NMOS transistor; The source of the first PMOS transistor is connected to the power supply voltage VDD, and the drain and gate of the first PMOS transistor are both connected to the source of the second PMOS transistor; The drain and gate of the second PMOS transistor are both connected to the drain of the seventh NMOS transistor; The source and gate of the seventh NMOS transistor are both grounded; The mirror unit includes a third PMOS tube and a fourth PMOS tube; The source of the third PMOS transistor is connected to the power supply voltage VDD, the gate of the third PMOS transistor is connected to the gate of the first PMOS transistor, and the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor; The gate of the fourth PMOS transistor is connected to the gate of the second PMOS transistor, and the drain of the fourth PMOS transistor outputs current I2; The reference unit includes a fifth PMOS transistor and a sixth NMOS transistor; The source of the fifth PMOS transistor inputs current I2, and the gate and drain of the fifth PMOS transistor are both connected to the drain of the sixth NMOS transistor; The gate of the sixth NMOS transistor is connected to the gate of the fifth PMOS transistor, and the source of the sixth NMOS transistor is grounded; The source of the fifth PMOS tube outputs a low temperature coefficient reference voltage V REF .

2. A low temperature coefficient CMOS reference voltage source according to claim 1, characterized in that: The seventh NMOS transistor is a depletion-type NMOS transistor.

3. A low temperature coefficient CMOS reference voltage source according to claim 1, characterized in that: The expression of the current I1 is: Among them, μ n is the electron mobility, C ox is the gate oxide capacitance, (W / L)7 is the width-to-length ratio of the seventh NMOS tube, V THN is the threshold voltage of the seventh NMOS tube.

4. A low temperature coefficient CMOS reference voltage source according to claim 1, characterized in that: The V SG5 The expression is: The V GS6 The expression is: Among them, μ n is the electron mobility, C ox is the gate oxide capacitance, (W / L)5 is the width-to-length ratio of the fifth PMOS transistor, (W / L)6 is the width-to-length ratio of the sixth NMOS transistor, V THP5 is the threshold voltage of the fifth PMOS tube, V THN6 is the threshold voltage of the sixth NMOS tube.

5. A chip, characterized in that: The invention comprises a low temperature coefficient CMOS reference voltage source as claimed in any one of claims 1 to 4.

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