Storage System

Abstract

One embodiment of the present invention provides a storage system capable of responding to changes in interface standards. The storage system (1) of the embodiment is connectable to a host device (100). The storage system (1) includes a non-volatile memory (10) and a controller (20), the controller (20) controlling the non-volatile memory (10) and supplying it with a first voltage. The storage system (1) also includes circuits (31, 32) that, when connected to the host device 100 and receiving a first signal (VIO 1.8) and a second signal (CLKREQ#) from the host device 100, and the first and second signals having a second voltage (VDD1) lower than the first voltage (VDD2), convert the second voltage of the second signal to the first voltage; when connected to the host device 100 and receiving a second signal instead of a first signal from the host device 100, and the second signal having the first voltage, do not convert the first voltage of the second signal.

Description

[0001] This application is a divisional application of application number 202111002793.7, filed on August 30, 2021, entitled "Storage System". Technical Field

[0002] Embodiments of the present invention relate to storage systems. Background Technology

[0003] Solid-state drives (SSDs) are known as storage systems, equipped with NAND flash memory. SSDs are connected to host devices such as personal computers and servers. When an SSD is connected to a host device, signal transmission and reception between the SSD and the host device follows, for example, the PCI Express (registered trademark) (PCIe) standard, which is one of the interface standards. Summary of the Invention

[0004] One embodiment of the present invention provides a storage system capable of responding to changes in interface standards.

[0005] The storage system of this embodiment is connectable to a host device. The storage system includes: a non-volatile memory; and a controller that controls the non-volatile memory and is supplied with a first voltage. The storage system also includes circuitry that, when connected to the host device and receiving a first signal and a second signal from the host device, and the first signal and the second signal having a second voltage lower than the first voltage, converts the second voltage of the second signal to the first voltage; and when connected to the host device and receiving a second signal instead of the first signal, and the second signal having the first voltage, does not convert the first voltage of the second signal. Attached Figure Description

[0006] Figure 1 (a) is a side view showing the external structure of a storage system according to one embodiment.

[0007] Figure 1 (b) is a top view showing the external structure of a storage system according to one embodiment.

[0008] Figure 2 This is a block diagram illustrating the structure of a storage system according to one implementation method.

[0009] Figure 3 This is a table showing an example of the pin configuration of the connector of the memory system involved in the implementation.

[0010] Figure 4This is a circuit diagram of an automatic power switching circuit for a storage system according to one implementation method.

[0011] Figure 5 This is a circuit diagram of a level shifting circuit for a storage system according to one implementation method.

[0012] Figure 6 This is a circuit diagram of another level shifting circuit of a storage system according to one implementation method.

[0013] Label Explanation

[0014] 1. Storage System

[0015] 2 Printed substrate

[0016] 4 PCIe interfaces

[0017] 10. Non-volatile memory

[0018] 20 Controllers

[0019] 31. Automatic Voltage Switching Circuit (Circuit 1)

[0020] 32-level shift circuit (Circuit 2)

[0021] 40 interfaces

[0022] 100 Main Units Detailed Implementation

[0023] The embodiments will now be described with reference to the accompanying drawings. The drawings are schematic or conceptual. Furthermore, in the drawings, the same or equivalent parts are given the same reference numerals. Additionally, for simplicity, sometimes even parts that are the same or equivalent are not given reference numerals.

[0024] Figure 1 This is a diagram showing the external structure of a storage system 1 according to one embodiment. Figure 1 (a) is a side view schematically representing an example of the external structure of storage system 1. Figure 1 (b) is a top view schematically representing an example of the external structure of storage system 1. Figure 2 This is a block diagram representing the interconnected storage system 1 and host device 100.

[0025] Storage system 1 is a non-volatile storage device such as an SSD, USB memory, SD card, hard disk drive, or hybrid hard disk drive.

[0026] The host device 100 is, for example, an information processing device such as a personal computer or server, a testing device, a manufacturing device, a shooting device such as a still camera or video camera, a portable terminal such as a tablet computer or smartphone, a gaming device, or a vehicle navigation system (vehicle terminal).

[0027] The host device 100 is, for example, an information processing device such as a personal computer or server, a portable terminal such as a tablet computer or smartphone, a shooting device such as a still camera or video camera, a testing device, a manufacturing device, a gaming device, or a vehicle navigation system (vehicle terminal).

[0028] The following describes the case where the storage system 1 is an SSD, the host device 100 is a personal computer, and the signal transmission and reception between the storage system 1 and the host device 100 follows the PCIe standard.

[0029] like Figure 1 As shown, the storage system 1 includes a printed circuit board 2, a non-volatile memory 10, a controller 20, an interface circuit 30, and a connector 40.

[0030] The printed circuit board 2 has a first main surface 2a and a second main surface 2b. The second main surface 2b is the main surface opposite to the first main surface 2a. A non-volatile memory 10, a controller 20, and a connector 40 are disposed on the first main surface 2a.

[0031] The non-volatile memory 10 includes NAND flash memory, which is mounted on the main surface 2a of the printed circuit board 2 in a packaged form. The non-volatile memory 10 is mounted, for example, in a BGA (Ball Grid Array) manner.

[0032] Interface circuit 30 is a PCIe compliant circuit, including automatic voltage switching circuit 31 and level shifting circuit 32 connected thereto. Figure 2 ).

[0033] The controller 20 is mounted on the main surface 2a of the printed circuit board 2 in a packaged form. The controller 20 is mounted, for example, using a BGA. For example, the controller 20 controls the non-volatile memory 10.

[0034] Connector 40 has a shape that follows M.2 as one of the form factors and is configured as an insulated connector. Connector 40 includes a plurality of pins 40-1 to 40-10. Figure 3 This is a table showing an example of the pin configuration of connector 40. In Figure 3 In the example, the number of pins is 75, but Figure 1In (b), the number of pins is set to 10 for simplicity. Each pin 40-1 to 40-10 of connector 40 is connected to interface circuit 30 and controller 20 via substrate wiring (not shown) in printed circuit board 2.

[0035] Connector 40 forms multiple ports UP1, UP2, UP3, UP4, UP5 ( Figure 2 Connector 40 has different pins assigned to each port UP1, UP2, UP3, UP4, and UP5. The number of pins assigned to each port UP1, UP2, UP3, UP4, and UP5 is multiple. Ports UP1, UP2, and UP3 are connected to level shifting circuit 32. Ports UP4 and UP5 are connected to automatic voltage switching circuit 31.

[0036] The host device 100 includes a controller 102 and a connector (not shown). Figure 2 The connector comprises multiple ports DP1, DP2, DP3, DP4, and DP5. Different pins of the connector are assigned to each port DP1, DP2, DP3, DP4, and DP5. Logic signals from controller 102 are provided to each port DP1, DP2, DP3, DP4, and DP5. For example, the clock request signal CLKREQ# from controller 102 is provided to port DP1, the wake-up signal PEWAKE# from controller 102 is provided to port DP2, the reset signal PERST# from controller 102 is provided to port DP3, and the VIO 1.8 signal from controller 102 is provided to port DP4. "#" indicates a low-level active signal.

[0037] Communication lines CL1, CL2, CL3, and CL4 are connected to ports UP1, UP2, UP3, and UP4 of connector 40, respectively. Ports UP1, UP2, UP3, and UP4 are connected to ports DP1, DP2, DP3, and DP4 of host device 100 via communication lines CL1, CL2, CL3, and CL4. As a result, storage system 1 and host device 100 are connected.

[0038] The multiple ports UP1 to UP4 of the storage system 1, the multiple communication lines CL1 and CL2 (communication line group CL), and the multiple ports DP1 to DP4 of the host device 100 constitute the PCIe interface 4 between the storage system 1 and the host device 100. In addition, other interfaces such as low-speed interfaces and power interfaces may also be formed between the storage system 1 and the host device 100.

[0039] Storage system 1 receives control signals (commands) from host device 100 via PCIe interface 4 and performs control actions in accordance with the received commands. Additionally, storage system 1 sends control signals (requests) to host device 100 via PCIe interface 4.

[0040] The controller 20 includes I / O circuits 21 and 22, and a core unit 23. I / O circuit 21 includes a driver 21a and a receiver 21b. Driver 21a includes an NMOS transistor. Receiver 21b includes an NMOS transistor and a PMOS transistor forming an inverter. The connection node N1 between driver 21a and receiver 21b is connected to level shift circuit 32 via signal line SL1. I / O circuit 22 includes receiver 22b. Receiver 22b includes an NMOS transistor and a PMOS transistor forming an inverter. The connection node N2 between the gates of these NMOS transistors and the gates of the PMOS transistor is connected to level shift circuit 32 via signal line SL2. The voltage VDD2 (power supply voltage) supplied to I / O circuits 21 and 22 is 3.3V.

[0041] The core unit 23 receives signals via I / O circuits 21 and 22 and performs predetermined control according to the received signals. For example, when the core unit 23 receives a write command and data via I / O circuits 21 and 22, it writes the data to the non-volatile memory 10 according to the write command. Additionally, the core unit 23 outputs signals via I / O circuits 21 and 22 according to predetermined control. For example, when the core unit 23 receives a read command via I / O circuits 21 and 22, it reads data from the NAND flash memory 10 and outputs the read data via I / O circuits 21 and 22.

[0042] Storage system 1 transmits and receives high-speed differential signals (TX, RX) conforming to the PCIe standard with host device 100 via PCIe interface 4. Additionally, storage system 1 transmits and receives control signals required for its operation with host device 100 via PCIe interface 4. Such control signals include, for example,... Figure 2 The logic signals shown are the clock request signal CLKREQ#, the wake-up signal PEWAKE#, and the reset signal PERST#. The clock request signal CLKREQ# is input to a pin on port DP1. The reset signal PEWAKE# is input to a pin on port DP2. The reset signal PERST# is input to a pin on port DP3.

[0043] The clock request signal CLKREQ# is used to request a reference clock signal from a clock generator (not shown). The clock generator is located externally or internally to the host device 100. The wake-up signal PEWAKE# is sent from the host device 100 to the storage system 1 when the host device 100 wants to start the storage system 1. The reset signal PERST# is sent from the host device 100 to the storage system 1 when the host device 100 wants to initialize the storage system 1.

[0044] The voltage VDD1 of the logic signals such as the clock requirement signal CLKREQ#, the reference clock signal REFCLK, and the reset signal PERST# is currently 3.3V. However, the voltage VDD1 is planned to be 1.8V in the future.

[0045] In the process of mass-producing SSDs, if there is a schedule to switch the voltage VDDl from 3.3V to 1.8V, in order to cope with this switch, it is necessary to prepare separate substrates for 3.3V and 1.8V, or to install and select jumper wires on a single substrate according to the voltage.

[0046] In this embodiment, to accommodate the switching from 3.3V to 1.8V, the interface circuit 30 in the storage system 1 includes an automatic voltage switching circuit 31. The automatic voltage switching circuit 31 is connected to port UP4, and port UP4 is connected to port DP4 of the host device 100.

[0047] With voltage VDD1 at 1.8V, a pin for transmitting the VIO 1.8V signal (first signal) is provided at port DP4 of the host device 100. As a result, the VIO 1.8V signal is input from the controller 102 of the host device 100 to port DP4 and then to the voltage automatic switching circuit 31 via port UP4.

[0048] On the other hand, when the voltage VDD1 is 3.3V, no pin for transmitting the VIO 1.8V signal is provided at port DP4 of the host device 100. As a result, the VIO 1.8V signal is not input to the automatic voltage switching circuit 31.

[0049] When a VIO 1.8V signal is input to the automatic voltage switching circuit 31, the circuit outputs a first output signal with a voltage of 1.8V. Conversely, when no VIO 1.8V signal is input to the automatic voltage switching circuit 31, it outputs a second output signal with a voltage of 3.3V. Thus, in this embodiment, the automatic voltage switching circuit 31 outputs different voltage signals (first output signal, second output signal) depending on whether a VIO 1.8V signal is input. In this embodiment, the first output signal is lower than the second output signal.

[0050] The voltage automatic switching circuit 31 inputs either a first output signal or a second output signal to the level shifting circuit 32. When the first output signal is input, the level shifting circuit 32 transforms the voltage of the input logic signals (CLKREQ#, PEVAKE#, PERST#) from 1.8V to 3.3V. Conversely, when the second output signal is input, the level shifting circuit 32 does not transform the voltage of the input logic signals (CLKREQ#, PEVAKE#, PERST#).

[0051] Figure 4 This is a circuit diagram of the automatic voltage switching circuit 31. The automatic voltage switching circuit 31 includes bipolar transistors Q1 to Q5, resistors R1 to R5, and capacitor C1. Bipolar transistors Q1 to Q3, Q5, and Q6 are NPN type bipolar transistors, and bipolar transistor Q4 is a PNP type bipolar transistor.

[0052] The base of bipolar transistor Q1 is connected to ground via resistor R1, and is also connected to the collector of bipolar transistor Q5.

[0053] The collector of bipolar transistor Q1 is connected to a 3.3V power supply via resistor R2, and is also connected to the bases of bipolar transistors Q2, Q3, and Q6. The emitter of bipolar transistor Q1 is connected to ground, and is also connected to the emitters of bipolar transistors Q2, Q3, and Q6 and capacitor C1.

[0054] In addition, capacitor C1 is used to adjust the timing of when bipolar transistor Q5 becomes on, but it is not necessarily required.

[0055] The collector of bipolar transistor Q2 is connected to a 3.3V power supply voltage via resistor R3, and is also connected to the base of bipolar transistor Q4.

[0056] The collector of bipolar transistor Q3 is connected to a 3.3V power supply voltage via resistor R4 and to ground via capacitor C1, and is also connected to the base of bipolar transistor Q5.

[0057] The collector of bipolar transistor Q4 is connected to the emitter of bipolar transistor Q5.

[0058] In addition, the emitter of the bipolar transistor Q4 is connected to a 3.3V power supply voltage.

[0059] The collector of bipolar transistor Q5 is connected to the pin of the output VIO 1.8V signal in port UP4.

[0060] The collector of bipolar transistor Q6 is connected to the pin of the output VIO CFG signal in port UP5.

[0061] With a logic signal of 3.3V, port UP4 of storage system 1 has a pin for transmitting the VIO 1.8V signal, but port DP4 of host device 100 does not have a pin for transmitting the VIO 1.8V signal. Therefore, port UP4 becomes an open-circuit state (Not Connected), and through resistor R1 connected to the base of bipolar transistor Q1, the base of bipolar transistor Q1 becomes ground (GND), thus making bipolar transistor Q1 a cutoff state.

[0062] As a result, bipolar transistors Q2, Q3, Q4, and Q6 are turned on, and the output voltage becomes 3.3V.

[0063] When the logic signal is 3.3V, the collector current of bipolar transistor Q6 can be used as the VIO CFG signal. The VIO CFG signal is used to notify the host device 100 that the logic signal of the storage system 1 is 3.3V; when this signal is at ground level, it indicates that the logic signal of the storage system 1 is 3.3V. In this case, a pin for transmitting the VIO CFG signal is provided in port UP5 of the storage system 1.

[0064] With a logic signal of 1.8V, pins for transmitting the VIO 1.8V signal are located within ports UP4 and DP4. Therefore, when the VIO 1.8V signal is input to the base of bipolar transistor Q1 and the collector of bipolar transistor Q5, bipolar transistor Q1 becomes on. As a result, bipolar transistors Q2, Q3, Q4, and Q6 become on, and bipolar transistor Q5 becomes on via resistor 4, resulting in an output voltage of 1.8V.

[0065] Figure 5 This is the circuit diagram of level shifter circuit 32. This circuit diagram uses... Figure 4 The circuit diagram for the case of the automatic voltage switching circuit 31.

[0066] The level shifting circuit 32 includes NMOS transistors NM1, NMOS transistors NM2 and NMOS transistors NM3, and pull-up resistors 11, 12 and R13.

[0067] The gate of NMOS transistor NM1 is connected to the collector of bipolar transistor Q4 and the emitter of bipolar transistor Q5. The source (S) of NMOS transistor NM1 is connected to the pin of port DP1 where the clock request signal CLKREQ# is provided. The drain (D) of NMOS transistor NM1 is connected to one end of pull-up resistor R11. The other end of pull-up resistor R11 is connected to a 3.3V power supply voltage. The drain D outputs the clock request signal CLKREQB as an output. "B" indicates that the signal is used as a low-level active signal. A parasitic diode D1 exists between the source (S) and drain (D) of NMOS transistor NM1. The anode and cathode of parasitic diode D1 are connected to the source (S) and drain (D), respectively.

[0068] The clock request signals CLKREQ# and CLKREQB are bidirectional signals. A low-level signal from the pin used for the clock request signal CLKREQB in port UP1 causes the source S of the NMOS transistor NM1 to drop through the parasitic diode D1, creating a potential difference between the gate G and the source S. As a result, the NMOS transistor NM1 becomes on, and the low-level signal is transmitted to the pin used for the clock request signal CLKREQ# in port DP1.

[0069] The gate of NMOS transistor NM2 is connected to the collector of bipolar transistor Q4 and the emitter of bipolar transistor Q5. The source (S) of NMOS transistor NM2 is connected to the pin in port DP2 where the wake-up signal PEVAKE# is provided. The drain (D) of NMOS transistor NM2 is connected to one end of pull-up resistor R12. The other end of pull-up resistor R12 is connected to a 3.3V power supply. The drain D outputs the wake-up signal PEVAKEB as an output. A parasitic diode D2 exists between the source (S) and drain (D) of NMOS transistor NM2. The anode and cathode of parasitic diode D2 are connected to the source (S) and drain (D), respectively. The wake-up signals PEVAKE# and PEVAKEB are bidirectional signals. A low-level signal from the wake-up signal PEVAKEB passes through parasitic diode D2, causing the potential of the source (S) of NMOS transistor NM2 to decrease. As a result, a potential difference is generated between the gate G and the source S of the NMOS transistor NM2, and the NMOS transistor NM2 becomes turned on. Therefore, a low-level signal is transmitted to port UP2.

[0070] The wake-up signals PEVAKE# and PEVAKEB are bidirectional signals. A low-level signal from the PEVAKEB pin in port UP2 passes through the parasitic diode D2, causing the potential of the source S of the NMOS transistor NM2 to drop, creating a potential difference between the gate G and the source S. As a result, NM2 becomes on, and the low-level signal is transmitted to the wake-up signal PEVAKE# pin in port DP.

[0071] The gate of NMOS transistor NM3 is connected to the collector of bipolar transistor Q4 and the emitter of bipolar transistor Q5. The source (S) of NMOS transistor NM3 is connected to the pin in port DP3 where the reset signal PERST# is provided. The drain (D) of NMOS transistor NM3 is connected to one end of pull-up resistor R13. The other end of pull-up resistor R13 is connected to a 3.3V power supply. The drain D outputs the reset signal PERSTB as an output. A parasitic diode D3 exists between the source (S) and drain (D) of NMOS transistor NM3. The anode and cathode of parasitic diode D3 are connected to the source (S) and drain (D), respectively.

[0072] When the logic signal is 3.3V, bipolar transistor Q4 is in the ON state, and bipolar transistor Q5 is in the OFF state. The output voltage of bipolar transistor Q4 in the ON state is 3.3V. This output voltage is input to the gates of NMOS transistors NM1 to NM3.

[0073] As a result, when the logic signal is 3.3V, the pull-up resistor R11 connected to the drain D of NMOS transistor NM1 is used as the 3.3V clock request signal and output from the drain D of NMOS transistor NM1 as CLKREQB. The 3.3V wake-up signal PEVAKE# input to the source S of NMOS transistor NM2 is not voltage-transformed and is output from the drain D of NMOS transistor NM1 as the 3.3V wake-up signal PEVAKEB. The 3.3V reset signal PERST# input to the source S of NMOS transistor NM3 is not voltage-transformed and is output from the drain D of NMOS transistor NM3 as the 3.3V reset signal PERSTB. The clock request signal CLKREQB and the wake-up signal PEVAKEB are input to the output node N1 of I / O circuit 21. In addition, the reset signal PERSTB is input to node N2 of I / O circuit 22.

[0074] On the other hand, when the logic signal is 1.8V, bipolar transistor Q4 is in the off state, and bipolar transistor Q5 is in the on state. The output voltage of bipolar transistor Q5 in the on state is 1.8V. This output voltage is input to the gates of NMOS transistors NM1 to NM3.

[0075] As a result, when the logic signal is 1.8V, the 1.8V clock request signal CLKREQ# input to the source S of NMOS transistor NM1 is output from the drain D of NMOS transistor NM1 as a 3.3V clock request signal CLKREQB pulled up by pull-up resistor 11. The 1.8V wake-up signal PEWAKE# input to the source S of NMOS transistor NM2 is output from the drain D of NMOS transistor NM1 as a 3.3V wake-up signal PEWAKEB pulled up by pull-up resistor 12. The 1.8V reset signal PERST# input to the source S of NMOS transistor NM3 is output from the drain D of NMOS transistor NM3 as a 3.3V reset signal PERSTB pulled up by pull-up resistor 11.

[0076] Furthermore, in the embodiments described above, the automatic voltage switching circuit 31 and the level shifting circuit 32 are disposed within the interface circuit 30, but the automatic voltage switching circuit 31 and the level shifting circuit 32 may also be disposed outside the interface circuit 30. Additionally, in Figure 5 NMOS transistors MN1 to MN3 were used, but as Figure 6 As shown, a level shifting circuit using bipolar transistors BP1 to BP3 can also be implemented.

[0077] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A storage system capable of connecting to a host device, comprising: Non-volatile memory; A controller, which controls the non-volatile memory, is supplied with a first voltage; and The circuit, in a state where the storage system is connected to the host device, under a first condition where a first signal and a second signal are input from the host device and both the first signal and the second signal have a second voltage lower than the first voltage, outputs a third signal with the first voltage based on the second signal having the second voltage to the controller; under a second condition where the storage system is connected to the host device and the first signal is not input from the host device but the second signal is input and the second signal has the first voltage, outputs a fourth signal with the first voltage based on the second signal having the first voltage to the controller.

2. The storage system according to claim 1, The circuit includes a first circuit, in which the output of the first circuit becomes a first state in the first case, and in which the output of the first circuit becomes a second state different from the first state in the second case.

3. The storage system according to claim 2, The circuit includes a second circuit that outputs the third signal when the output of the first circuit is in the first state.

4. The storage system according to claim 3, When the output of the first circuit becomes the second state, the second circuit outputs the fourth signal.

5. The storage system according to claim 1, It also has a connector that can be connected to the host device. The connector includes a first pin and a second pin. The first pin and the second pin are connected to the circuit. The first signal is input to the first pin. The second signal is input to the second pin.

6. The storage system according to claim 5, The connector has a shape that conforms to the M.2 standard.

7. The storage system according to claim 1, The signal transmission and reception between the storage system and the host device follows the PCIe standard. The first signal is a VIO 1.8 signal. The second signal is a clock request signal CLKREQ#, a wake-up signal PEVAKE#, or a reset signal PERST#.

8. The storage system according to claim 7, When the first signal is not input to the circuit, the circuit outputs the VIO CFG signal.

9. The storage system according to claim 1, The circuit includes a transistor, which outputs the second signal passing through the transistor as either the third signal or the fourth signal.

10. The storage system according to claim 1, It also has a substrate. The non-volatile memory, the controller, and the circuitry are mounted on the substrate.

11. The storage system according to claim 1, The first voltage is 3.3V. The second voltage is 1.8V.

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