A method and system for deterministic latency of SDRAM

Abstract

The application discloses a SDRAM deterministic delay method and system, and solves the problem of low delay accuracy of a SDRAM-based DRFM system. The deterministic delay method comprises the following steps: in response to delay updating and completion of all read-write processes of current ping-pong operation, obtaining data lengths of input and output data stream buffers; judging the relationship between the write address of the SDRAM in the write state in the ping-pong operation and the new delay amount, and updating the starting position of a new round of ping-pong operation; and compensating and correcting the delay drift caused by the change of the input and output buffer data depth. The application compensates and corrects the delay drift caused by the change of the input and output buffer data depth through the FPGA internal BRAM, and finally realizes the deterministic delay of the DRFM system based on the double-SDRAM ping-pong read-write.

Description

Technical Field

[0001] This application relates to the field of microwave signal storage and forwarding technology, and in particular to a deterministic delay method and system based on SDRAM. Background Technology

[0002] A Digital Radio Frequency Storage and Forwarding (DRFM) system is a microwave signal store-and-forward system used to sample, store, modulate, and forward radio frequency signals, simulating the range, velocity, and RCS characteristics of radar targets. DRFM systems can adapt to variable, rapidly changing, and complex signal environments, maintaining coherence between target echo / jamming signals and the radar, and generating realistic complex electromagnetic environments. Therefore, DRFM systems have been widely used in electronic warfare and hardware-in-the-loop simulation systems, becoming an indispensable part of modern warfare.

[0003] In a DRFM system, signal store-and-forward refers to storing the received radar signal, reading it out after a certain delay, modulating it, and finally outputting the signal via a digital-to-analog converter for simulating radar target range. For delayed forwarding processing, data storage bandwidth and capacity are key system indicators. SDRAM, with its high read / write bandwidth and large storage capacity, and the ability to expand bandwidth and capacity through multi-chip concatenation, is widely used in DRFM systems. Because SDRAM shares both data and address interfaces for reading and writing, a single chip cannot perform read / write operations simultaneously. Typically, two sets of SDRAM are used for ping-pong read / write to ensure data continuity. However, the complexity of SDRAM read / write operations—requiring pre-charging, row / column selection, and other operations—makes the timing of read / write actions uncertain. This leads to drift in the actual store-and-forward time during delayed updates in SDRAM-based DRFM systems, reducing the delay accuracy of the DRFM system. Therefore, a deterministic delay method is needed to meet the delay accuracy requirements of SDRAM-based DRFM systems. Summary of the Invention

[0004] This application provides a deterministic delay method and system for SDRAM, which solves the problem of low delay accuracy in SDRAM-based DRFM systems.

[0005] This application provides an SDRAM deterministic delay method, comprising the following steps:

[0006] In response to a delayed update and the completion of all read and write operations for the current ping-pong operation, obtain the data length of the input and output data stream buffers;

[0007] Determine the relationship between the write address of the SDRAM in the write state during the ping-pong operation and the new delay amount, and update the starting position of the new round of ping-pong operation.

[0008] Compensation and correction are performed to address delay drift caused by changes in the depth of input and output buffer data.

[0009] Furthermore, the specific process of the ping-pong operation between the two SDRAMs also includes the following steps:

[0010] Determine the relationship between the write address and latency of the first SDRAM in write state;

[0011] In response to the write address of the first SDRAM being not less than the delay amount, the first SDRAM prepares to enter the read state and the second SDRAM prepares to enter the write state; or in response to the write address of the first SDRAM being less than the delay amount, the first SDRAM prepares to continue the write state and the second SDRAM prepares to enter the read state.

[0012] Update the status and address of the two SDRAM chips based on the current latency.

[0013] Preferably, the delay drift is compensated and corrected using the FPGA's internal BRAM.

[0014] Preferably, cache data length monitoring is set in both the input data stream cache and the output data stream cache.

[0015] Furthermore, in response to the delay update, the relationship between the write address and the delay of the SDRAM in the write state is reassessed.

[0016] Furthermore, in response to the delayed output being turned off, the two SDRAM chips alternately store the input data stream.

[0017] Furthermore, the output data stream buffer is reset and cleared.

[0018] This application also provides an SDRAM deterministic latency system for implementing the deterministic latency method described in the above embodiments, comprising an input data stream buffer, a ping-pong read / write engine, an output data stream buffer, and latency compensation storage. The input data stream passes through the input data stream buffer and enters the ping-pong read / write engine, the output data stream buffer, and the latency compensation storage. The input data stream buffer is used for matching the data bandwidth between the input data stream and the ping-pong read / write engine and for cross-clock domain processing. The ping-pong read / write engine is used to perform ping-pong operations and data stream management. The output data stream buffer is used for matching the data bandwidth between the ping-pong read / write engine and the output data stream and for cross-clock domain processing. The latency compensation storage is used to compensate for latency drift caused by changes in the data depth of the input and output buffers during latency updates and to send the output data stream.

[0019] Furthermore, the ping-pong read / write engine includes a main control state machine, an SDRAM write driver, and an SDRAM read driver. The main control state machine is used for SDRAM read / write direction control, address management, and data scheduling. The SDRAM write driver is used for the low-level implementation of SDRAM write operations. The SDRAM read driver is used for the low-level implementation of SDRAM read operations.

[0020] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the methods described in any of the above embodiments.

[0021] The above-described technical solutions adopted in the embodiments of this application can achieve the following beneficial effects:

[0022] This application compensates for and corrects the delay drift caused by changes in the depth of input and output buffer data through the internal BRAM of the FPGA, and finally realizes the deterministic delay of the DRFM system based on dual SDRAM ping-pong read and write. Attached Figure Description

[0023] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0024] Figure 1 This is a flowchart of a deterministic delay method according to an embodiment of this application;

[0025] Figure 2 This is a flowchart illustrating the ping-pong operation of two SDRAMs in an embodiment of this application.

[0026] Figure 3 This is a structural diagram of a deterministic delay system according to an embodiment of this application;

[0027] Figure 4 This is a control flowchart of a deterministic delay system according to an embodiment of this application;

[0028] Figure 5 This is a structural diagram of the ping-pong read / write engine in an embodiment of this application. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] The technical solutions provided by the various embodiments of this application are described in detail below with reference to the accompanying drawings.

[0031] Figure 1 This is a flowchart of a deterministic delay method according to an embodiment of this application.

[0032] This application provides an SDRAM deterministic delay method, comprising the following steps:

[0033] Step 110: In response to the delayed update and the completion of all read and write operations for the current ping-pong operation, obtain the data length of the input and output data stream buffers;

[0034] Preferably, cache data length monitoring is set in both the input data stream cache and the output data stream cache.

[0035] For example, monitoring of cached data length can be added to the input and output data stream caches connected to an SDRAM-based ping-pong read / write engine to obtain the cached data length.

[0036] During delayed updates, wait for all read and write operations in the current PingPong read and write engine to complete, and then obtain the data length of the input and output data stream buffers.

[0037] Step 120: Determine the relationship between the write address of the SDRAM in the write state during the ping-pong operation and the new delay amount, and update the starting position of the new round of ping-pong operation.

[0038] For example, determine the relationship between the write address of the SDRAM in the write state in the ping-pong read-write engine and the new latency, and update the starting position of the new round of read-write operations in the ping-pong read-write engine.

[0039] Step 130: Compensate and correct the delay drift caused by changes in the depth of input and output buffer data.

[0040] Since internal BRAM has stronger anti-interference capabilities and is more stable than external BRAM, it is preferable to use the FPGA's internal BRAM to compensate for and correct delay drift.

[0041] The delay drift caused by changes in the depth of input and output buffer data is compensated and corrected using the FPGA's internal BRAM;

[0042] Furthermore, it also includes the following steps:

[0043] Step 140: Begin a new round of ping-pong operations to ensure uninterrupted and stable output of the data stream. Continue in this manner until all delayed ping-pong operations are completed.

[0044] Figure 2 This is a flowchart illustrating the ping-pong operation of two SDRAMs in an embodiment of this application.

[0045] Furthermore, the specific process of the ping-pong operation between the two SDRAMs also includes the following steps:

[0046] Step 111: Determine the relationship between the write address and latency of the first SDRAM in write state;

[0047] Step 112: In response to the write address of the first SDRAM being not less than the delay amount, the first SDRAM prepares to enter the read state and the second SDRAM prepares to enter the write state; or in response to the write address of the first SDRAM being less than the delay amount, the first SDRAM prepares to continue the write state and the second SDRAM prepares to enter the read state.

[0048] Step 113: Update the status and address of the two SDRAM chips according to the current latency.

[0049] The current delay refers to the delay amount in the next round after the delay update.

[0050] Furthermore, it also includes the following steps:

[0051] Step 114: In response to the delay update, re-determine the relationship between the write address and the delay of the SDRAM in the write state.

[0052] When the delay value is updated, proceed to step 111;

[0053] Each time the delay amount is updated, the delay relationship between the write address and the delay amount of the SDRAM in the write state is reassessed.

[0054] Furthermore, it also includes the following steps:

[0055] Step 115: Response delay output is turned off, and the two SDRAMs alternately store the input data stream.

[0056] When the DRFM system starts working, the delayed output is turned off, the ping-pong read / write module is in the pre-storage state, the input data stream enters the ping-pong read / write engine after passing through the FIFO_IN buffer, the two SDRAMs are stored alternately, no read output is performed, and the data storage depth is the maximum storage depth of the SDRAM.

[0057] It should be noted that before and after the DRFM system starts working, two SDRAM chips are needed to alternately store the input data stream.

[0058] Furthermore, the output data stream buffer is reset and cleared.

[0059] After the operation is completed and the delay is turned off, the two SDRAM chips alternately store the input data stream and reset and clear the output data stream buffer FIFO_OUT, waiting for the delay to be restarted.

[0060] Figure 3 This is a structural diagram of a deterministic delay system according to an embodiment of this application.

[0061] This application also provides an SDRAM deterministic delay system for implementing the deterministic delay method described in the above embodiments, comprising an input data stream buffer 1, a ping-pong read / write engine 2, an output data stream buffer 3, and a delay compensation storage 4.

[0062] The input data stream buffer is used for matching the data bandwidth between the input data stream and the ping-pong read / write engine and for cross-clock domain processing.

[0063] The ping-pong read / write engine is used to complete ping-pong read / write operations on two SDRAM chips.

[0064] The output data stream buffer is used for matching the data bandwidth between the ping-pong read / write engine and the output data stream, and for cross-clock domain processing.

[0065] The delay compensation storage, implemented inside the FPGA, is used to compensate for delay drift caused by changes in the depth of input and output buffer data during delay updates and to send the output data stream.

[0066] Figure 4 This is a control flowchart of a deterministic delay system according to an embodiment of this application.

[0067] This application also provides a control flowchart for a deterministic delay system based on SDRAM, used to implement the control of the deterministic delay system described in the above embodiments, including the following steps:

[0068] Step 410: When the system starts working, the delayed output is turned off, the ping-pong read-write module is in the pre-storage state, the data stream enters the ping-pong read-write engine after being buffered by the input data stream, the two SDRAMs are stored alternately, no read output is performed, and the data storage depth is the maximum storage depth of the SDRAM.

[0069] Step 420: Determine whether delay is enabled. If enabled, wait for all current read and write operations to complete and proceed to step 430; otherwise, continue to step 410.

[0070] Step 430: Determine the relationship between the current write address and the delay in the SDRAM. If the current write address is not less than the delay, the write-state SDRAM is ready to enter a read operation, and the read-state SDRAM is ready to enter a write operation; otherwise, the write-state SDRAM is ready to continue the write operation, and the read-state SDRAM is ready to enter a new read operation.

[0071] Step 440: Update the read / write status, read / write address and other parameters of the two SDRAMs based on the current latency.

[0072] Step 450: Obtain the data lengths in the current input data stream buffer and output data stream buffer, calculate and update the latency amount of the latency compensation storage;

[0073] Step 460: Enable the ping-pong read / write mode of the SDRAM. When the write operation of the SDRAM in write mode is completed and the read operation of the SDRAM in read mode is completed, switch the read / write operation of the two SDRAMs and start a new round of read / write operations to ensure the continuity of input and output data.

[0074] Step 470: When the delay value is updated, wait for all current read and write states to complete, then proceed to step 303;

[0075] Step 480: When the delay is turned off, proceed to step 410 and reset and clear the output data stream buffer, waiting for the delay to be turned on again.

[0076] Figure 5 This is a structural diagram of the ping-pong read / write engine in an embodiment of this application.

[0077] Furthermore, such as Figure 5 As shown, the ping-pong read / write engine includes a main control state machine, an SDRAM write driver, and an SDRAM read driver.

[0078] The main control state machine is used for SDRAM read / write direction control, address management, and data scheduling.

[0079] The SDRAM write driver is used for the underlying implementation of SDRAM write operations;

[0080] The SDRAM read driver is used for the underlying implementation of SDRAM read operations.

[0081] The basic principle of ping-pong read / write is: the storage architecture consists of two sets of SDRAM chips. Storage and reading are performed simultaneously in the two sets of SDRAM. When the storage SDRAM is finished writing and the reading SDRAM chip is empty, the operation of the two sets of SDRAM is seamlessly alternated, so as to ensure the continuity of data storage and reading.

[0082] The deterministic delay method described in this application makes a special judgment on the SDRAM ping-pong read / write switching time. Under the premise of ensuring the deterministic delay of the dual SDRAM read / write modules, it obtains the data depth of the input buffer and output buffer used to match different data bandwidths at this moment. By using the FPGA's internal BRAM to compensate and correct the delay drift caused by the change in the data depth of the input and output buffers, the deterministic delay of the DRFM system based on dual SDRAM ping-pong read / write is finally realized.

[0083] Using the method described in this application, a digital radio frequency (DRFM) storage system can accurately acquire the system delay drift introduced by the uncertainty of SDRAM read / write operation timing when the delay amount is updated. This delay drift is reflected in the ping-pong read / write module as a change in the input and output data buffer delay. By using the FPGA's internal BRAM to compensate for and correct the delay drift, deterministic delay of the DRFM system based on dual SDRAM ping-pong read / write is achieved.

[0084] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0085] Therefore, this application also proposes a computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements the methods described in any embodiment of this application.

[0086] Furthermore, this application also proposes an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method described in any embodiment of this application.

[0087] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0088] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0089] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0090] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, a network interface, and memory. Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0091] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0092] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A deterministic delay method for SDRAM, characterized in that, Includes the following steps: In response to a delayed update and the completion of all read and write operations for the current ping-pong operation, obtain the data length of the input and output data stream buffers; Determine the relationship between the write address of the SDRAM in the write state during the ping-pong operation and the new delay amount; in response to the first SDRAM's write address being not less than the delay amount, the first SDRAM prepares to enter the read state and the second SDRAM prepares to enter the write state, or in response to the first SDRAM's write address being less than the delay amount, the first SDRAM prepares to continue the write state and the second SDRAM prepares to enter the read state; update the state and address of the two SDRAMs according to the current delay amount. Compensation and correction are provided for delay drift caused by changes in the depth of input and output buffer data. Buffer data length monitoring is set in both the input and output data stream buffers.

2. The SDRAM deterministic delay method according to claim 1, characterized in that, The delay drift is compensated and corrected using the FPGA's internal BRAM.

3. The SDRAM deterministic delay method according to claim 1, characterized in that, In response to the delay update, the relationship between the write address and the delay of the SDRAM in the write state is reassessed.

4. The SDRAM deterministic delay method according to claim 1, characterized in that, In response to the delayed output being turned off, the two SDRAM chips alternately store the input data stream.

5. The deterministic delay method according to claim 4, characterized in that, Reset and clear the output data stream buffer.

6. An SDRAM deterministic delay system for implementing the deterministic delay method of claim 1, characterized in that, It includes an input data stream buffer, a ping-pong read / write engine, an output data stream buffer, and latency-compensated storage; The input data stream passes through the input data stream buffer into the Ping-Pong read / write engine, the output data stream buffer, and the latency compensation storage; The input data stream buffer is used for matching the data bandwidth between the input data stream and the ping-pong read / write engine and for cross-clock domain processing. The ping-pong read / write engine is used to complete ping-pong operations and data stream management; The output data stream buffer is used for matching the data bandwidth between the ping-pong read / write engine and the output data stream and for cross-clock domain processing. The delay compensation storage is used to compensate for the delay drift caused by changes in the depth of input and output buffer data during the correction delay update, and to send the output data stream.

7. The SDRAM deterministic delay system according to claim 6, characterized in that, The ping-pong read / write engine includes a main control state machine, an SDRAM write driver, and an SDRAM read driver; The main control state machine is used for SDRAM read / write direction control, address management, and data scheduling. The SDRAM write driver is used for the underlying implementation of SDRAM write operations; The SDRAM read driver is used for the underlying implementation of SDRAM read operations.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 1-5.

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