Single-bit systolic array architecture supporting different computing modes

Abstract

The application discloses a single-bit systolic array structure supporting different computing modes, comprising a selection circuit and a plurality of systolic array units arranged in an array. Each systolic array unit is composed of an input register, a weight register, three non-gates, three three-input AND gates, a three-input OR gate, an accumulator and a partial sum register, and the selection circuit is connected with the accumulator of the last row of systolic array units in the systolic array structure. The application uses logic gates to process single-bit computing, and uses a computing mode selection signal to realize different computing schemes, thereby improving the adaptability of the systolic array to different computing modes.

Description

Technical Field

[0001] This invention relates to the field of artificial intelligence, specifically to a single-bit pulsating array structure that supports different computing modes. Background Technology

[0002] With the rise of artificial intelligence, deep learning is being applied more and more in various fields. Among these applications, matrix multiplication is extremely common. Currently, a convenient and efficient method for matrix operations is using systolic arrays. The basic idea of ​​a systolic array is: in the matrix multiplication operation A*B=Y, matrix B is fixed, and A flows through the systolic array cells to continuously output Y; or A and B flow through the systolic array cells, and the result Y is stored in the systolic array cells. This invention improves upon the former approach by first storing matrix A in the register of the corresponding array cell, inputting matrix B, and then allowing the calculation result to flow through the array cells and be output via a selection circuit.

[0003] In neural networks, single-bit matrix multiplication is frequently performed. However, single-bit matrix multiplication is often not limited to conventional multiplication and accumulation calculations. In many cases, multiplication calculations are replaced with other calculations such as XOR, XOR, AND, and NAND, and then accumulated.

[0004] Therefore, there is an urgent need for a solution to improve the adaptability of pulsating arrays to different computing modes. Summary of the Invention

[0005] To overcome the shortcomings of the prior art, the present invention provides a single-bit systolic array structure that supports different computing modes, thereby improving the adaptability of the systolic array to different computing modes.

[0006] This invention is implemented according to the following technical solution:

[0007] A single-bit systolic array structure supporting different computing modes includes a selection circuit and multiple systolic array units arranged in an array. Each of the systolic array units includes an input register, a weight register, a partial sum register, a first NOT gate, a second NOT gate, a third NOT gate, a first three-input AND gate, a second three-input AND gate, a third three-input AND gate, a three-input OR gate, and an accumulator.

[0008] The output of the input register is connected to the input of the first NOT gate, the output of the weight register is connected to the input of the second NOT gate, and the input of the third NOT gate receives the internal selection signal. The input of the partial sum register is connected to the output of the accumulator of the previous systolic array unit, the output of the partial sum register is connected to the first input of the accumulator, the second input of the accumulator is connected to the output of the three-input OR gate, and the three inputs of the three-input OR gate are respectively connected to the outputs of the first three-input AND gate, the second three-input AND gate, and the third three-input AND gate. The inputs of the first three-input AND gate are respectively connected to the outputs of the input register, the weight register, and the third NOT gate. The inputs of the second three-input AND gate are respectively connected to the output of the second NOT gate, the output of the input register, and the internal selection signal. The input of the third three-input AND gate is respectively connected to the outputs of the weight register, the first NOT gate, and the third NOT gate.

[0009] The selection circuit is connected to the accumulator of the last row of pulsating array units in the pulsating array structure. Based on the external selection signal, the calculation result of the accumulator of the last row of pulsating array units is either inverted bit by bit and then output or directly output.

[0010] Optionally, the single-bit pulse array structure further includes a selection circuit for receiving an external selection signal.

[0011] Optionally, when the external selection signal = 0 and the internal selection signal = 0, the single-bit pulsating array structure performs a single-bit AND operation.

[0012] Optionally, when the external selection signal = 0 and the internal selection signal = 1, the single-bit pulsating array structure performs a single-bit XOR operation.

[0013] Optionally, when the external selection signal = 1 and the internal selection signal = 1, the single-bit pulsating array structure performs a single-bit XOR operation.

[0014] Optionally, when the external selection signal = 1 and the internal selection signal = 0, the single-bit pulsating array structure performs a single-bit NAND operation.

[0015] Optionally, the external selection signal and the internal selection signal remain unchanged in the same calculation.

[0016] Optionally, the rows of pulsating array units are arranged in a rectangular array;

[0017] For pulsating array cells located in the same row, the output of the input register of the current column of the pulsating array cell is connected to the input of the input register of the next column of the pulsating array cell;

[0018] For systolic array cells located in the same column, the output of the weight register of the current row systolic array cell is connected to the input of the weight register of the next row systolic array cell, and the output of the accumulator of the current row systolic array cell is connected to the input of the partial sum register of the next row systolic array cell.

[0019] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0020] This invention modifies the original systolic array by first storing matrix A in the register of the corresponding array unit, inputting matrix B, and then the calculation results of the two matrices flow in the array unit and are output through the selection circuit. This allows the systolic array to better support four different types of single-bit matrix multiplication calculations: XOR, XNOR, AND, and NAND. This effectively improves the adaptability of the systolic array to different types of matrix multiplication. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the pulsating array unit structure according to an embodiment of the present invention.

[0022] Figure 2 This is a schematic diagram of a pulsating array structure according to an embodiment of the present invention.

[0023] Figure 3 This is a schematic diagram illustrating the calculation principle of a pulsating array according to an embodiment of the present invention.

[0024] In the diagram: 1. First NOT gate; 2. Second NOT gate; 3. Third NOT gate; 4. First three-input AND gate; 5. Second three-input AND gate; 6. Third three-input AND gate. Detailed Implementation

[0025] The technical solutions of various embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0027] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows for communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0028] For single-bit matrix multiplication, it is often not limited to conventional multiplication and accumulation calculations, but requires replacing multiplication calculations with other calculations such as XOR, XOR, AND, NAND, etc., and then accumulating them. This invention uses logic gates to process single-bit calculations and uses calculation mode selection signals to implement different calculation schemes, thereby improving the adaptability of the pulsating array to different calculation modes.

[0029] This invention improves upon the existing pulsating array approach, which involves allowing matrices A and B to flow within pulsating array cells while storing the result Y within those cells. In matrix operations, matrix A is first stored in the register of the corresponding array cell, matrix B is input, and the calculation result flows within the array cell and is output via a selection circuit.

[0030] like Figure 1 As shown, a single-bit systolic array structure supporting different computing modes includes a selection circuit and multiple systolic array cells arranged in an array. Each systolic array cell consists of an input register, a weight register, three NOT gates, three three-input AND gates, a three-input OR gate, an accumulator, and a partial sum register.

[0031] Define the three NOT gates as the first NOT gate, the second NOT gate, and the third NOT gate, respectively, and define the three three-input AND gates as the first three-input AND gate, the second three-input AND gate, and the third three-input AND gate, respectively.

[0032] like Figure 1As shown, the output of the input register is connected to the input of the first NOT gate, the output of the weight register is connected to the input of the second NOT gate, and the input of the third NOT gate receives the internal selection signal (i.e., the calculation mode selection signal D in the figure). The input of the partial sum register is connected to the output of the accumulator of the previous systolic array unit, the output of the partial sum register is connected to the first input of the accumulator, the second input of the accumulator is connected to the output of the three-input OR gate, and the three inputs of the three-input OR gate are respectively connected to the outputs of the first three-input AND gate, the second three-input AND gate, and the third three-input AND gate. The inputs of the first three-input AND gate are respectively connected to the outputs of the input register, the weight register, and the third NOT gate. The inputs of the second three-input AND gate are respectively connected to the output of the second NOT gate, the output of the input register, and the calculation mode selection signal D. The inputs of the third three-input AND gate are respectively connected to the outputs of the weight register, the first NOT gate, and the third NOT gate.

[0033] The selection circuit is connected to the accumulator of the last row of pulsating array units in the pulsating array structure. Based on the external selection signal, the calculation result of the accumulator of the last row of pulsating array units is either inverted bit by bit and then output or directly output.

[0034] Each row of systolic array cells is arranged in a rectangular array. For systolic array cells in the same row, the output of the input register of the current column of systolic array cells is connected to the input of the input register of the next column of systolic array cells. For systolic array cells in the same column, the output of the weight register of the current row of systolic array cells is connected to the input of the weight register of the next row of systolic array cells, and the output of the accumulator of the current row of systolic array cells is connected to the input of the partial sum register of the next row of systolic array cells.

[0035] The computation mode selection signals C and D are used to select the mode of single-bit operation. Among them, the computation mode selection signal C is an external selection signal, which acts on the selection circuit outside the pulsating array unit.

[0036] In one implementation, when C=0 and D=0, the single-bit systolic array structure performs a single-bit AND operation; when C=0 and D=1, it performs a single-bit XOR operation; when C=1 and D=1, it performs a single-bit XNOR operation; and when C=1 and D=0, it performs a single-bit NAND operation. The calculation mode selection signal C does not act within the systolic array unit but rather on the selection circuit outside the systolic array unit. The calculation mode selection signal D acts within the systolic array unit.

[0037] Figure 2To illustrate the connection method between pulsating array units, taking a 3×3 pulsating array as an example, numerous pulsating array units form a complete pulsating array. The three lines between two vertically adjacent pulsating array units are used to transmit weight data A, calculate the mode selection signal D, and the partial sum of that array unit. The lines between two horizontally adjacent pulsating array units are used to transmit input data B, corresponding to the diagram above.

[0038] The selection circuit consists of a bit-inverting circuit and a 2-to-1 selector. When C=1, the calculation result of the accumulator is inverted; when C=0, the calculation result of the accumulator is directly output.

[0039] The following diagram illustrates the input method for a systolic array, using a 3×3 systolic array as an example. The matrix multiplication calculation is as follows:

[0040]

[0041] The calculation mode selection signals C and D remain unchanged within the same calculation. During calculation, the weight matrix is ​​pre-stored in the weight register of the array cell, and the input data is as follows: Figure 3 Input as shown.

[0042] Conventional matrix multiplication implements a multiply-accumulate operation, but in practical single-bit neural network computations, it is often necessary to replace multiplication with operations such as XOR, XOR, AND, and NAND. This invention addresses this need by implementing different types of single-bit matrix computations, effectively improving the adaptability of systolic arrays to different types of matrix multiplication.

[0043] This invention improves the traditional systolic array destructure, enabling it to adapt to matrix multiplication operations in four different single-bit computation modes, thereby enhancing the adaptability of the systolic array to different computation modes.

[0044] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the technical solutions of the embodiments of the present invention.

Claims

1. A single-bit pulsating array structure supporting different computing modes, characterized in that, It includes a selection circuit and multiple pulsating array units arranged in an array. Each of the pulsating array units includes an input register, a weight register, a partial sum register, a first NOT gate, a second NOT gate, a third NOT gate, a first three-input AND gate, a second three-input AND gate, a third three-input AND gate, a three-input OR gate, and an accumulator. The output of the input register is connected to the input of the first NOT gate, the output of the weight register is connected to the input of the second NOT gate, and the input of the third NOT gate receives the internal selection signal. The input of the partial sum register is connected to the output of the accumulator of the previous systolic array unit, the output of the partial sum register is connected to the first input of the accumulator, the second input of the accumulator is connected to the output of the three-input OR gate, and the three inputs of the three-input OR gate are respectively connected to the outputs of the first three-input AND gate, the second three-input AND gate, and the third three-input AND gate. The inputs of the first three-input AND gate are respectively connected to the outputs of the input register, the weight register, and the third NOT gate. The inputs of the second three-input AND gate are respectively connected to the output of the second NOT gate, the output of the input register, and the internal selection signal. The inputs of the third three-input AND gate are respectively connected to the outputs of the weight register, the first NOT gate, and the third NOT gate. The selection circuit is connected to the accumulator of the last row of pulsating array units in the pulsating array structure. According to the external selection signal, the calculation result of the accumulator of the last row of pulsating array units is either inverted bit by bit and then output or directly output. Among them, each row of pulsating array units is arranged in a rectangular array; For pulsating array cells located in the same row, the output of the input register of the current column of the pulsating array cell is connected to the input of the input register of the next column of the pulsating array cell; For systolic array cells located in the same column, the output of the weight register of the current row systolic array cell is connected to the input of the weight register of the next row systolic array cell, and the output of the accumulator of the current row systolic array cell is connected to the input of the partial sum register of the next row systolic array cell.

2. The single-bit pulsating array structure supporting different computing modes according to claim 1, characterized in that, When the external selection signal = 0 and the internal selection signal = 0, the single-bit pulsating array structure performs a single-bit AND operation.

3. The single-bit pulsating array structure supporting different computing modes according to claim 1, characterized in that, When the external selection signal = 0 and the internal selection signal = 1, the single-bit pulsating array structure performs a single-bit XOR operation.

4. The single-bit pulsating array structure supporting different computing modes according to claim 1, characterized in that, When the external selection signal = 1 and the internal selection signal = 1, the single-bit pulsating array structure performs a single-bit XOR operation.

5. The single-bit pulsating array structure supporting different computing modes according to claim 1, characterized in that, When the external selection signal = 1 and the internal selection signal = 0, the single-bit pulsating array structure performs a single-bit NAND operation.

6. The single-bit pulsating array structure supporting different computing modes according to claim 1, characterized in that, The external selection signal and the internal selection signal remain unchanged in the same calculation.

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