A UART interface data receiving module, a UART interface data sending module and a processor based on AXI4 bus packaging of ZYNQ

Abstract

The embodiment of the application provides a UART interface data receiving module, a UART interface data sending module and a processor based on an AXI4 bus package of ZYNQ, and belongs to the technical field of integrated circuits.The data receiving module comprises at least two data receiving links and a data splicing unit, each data receiving link is used for receiving external input UART interface data, and the data splicing unit is used for splicing and processing the UART interface data;the data sending module comprises at least two data sending links and a data splitting unit, the data splitting unit is used for receiving unsplit UART interface data and splitting according to data valid bits therein, and the data sending link is used for receiving the split UART interface data;and the processor comprises the data receiving module, the data sending module and a processing module as described above.The UART interface data receiving module, the UART interface data sending module and the processor can provide reception and sending of at least two paths of UART interface data.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to a UART interface data receiving module, a UART interface data transmitting module, and a processor based on a ZYNQ AXI4 bus package. Background Technology

[0002] ZYNQ is a new generation of fully programmable system-on-a-chip (SoC) from Xilinx, combining a dual-core ARM A9 processor with a traditional field-programmable gate array (FPGA). Because it combines the functions of both an FPGA and a CPU, it is widely used in data transmission, image processing, and other fields. ZYNQ uses the AXI4 bus to achieve data interaction between the ZYNQ soft core (PS) and the logic core (PL). Considering the relatively limited number of peripherals on the PS side, developers typically implement various interface protocols on the logic core, such as UART, SPI, and I2C, and encapsulate these protocols through the AXI4 bus interface to form AXI4 interface IPs. These IP peripherals can be connected to the AXI bus, and the PS side controls or reads data by accessing the addresses of each IP peripheral on the AXI4 bus. UART is a commonly used communication interface. In some aviation electromechanical equipment monitoring terminals, multiple external UART interfaces are required to receive, process, and record data sent by external devices. Traditional CPUs, due to the limited number of UART interfaces, can only expand the number of interfaces by using PCIe to UART bridge chips. However, this method requires a large number of components, resulting in high power consumption. Choosing ZYNQ as the controller requires only a single chip to solve the problem of data transmission across multiple UART interfaces. ZYNQ's built-in CPU handles data processing, while the PL implements the UART protocol and encapsulates the UART logic via the AXI4 bus to form an AXI_UART IP, allowing it to connect to the AXI4 bus for the CPU to read data.

[0003] However, the traditional AXI4 UART encapsulation method can only achieve the reception and transmission of data for one UART channel. When receiving data, an interrupt signal needs to be generated on the AXI bus to notify the PS end to read the data. Since the number of external interrupts from the ZYNQ PL end to the PS end is limited to only 16, IPs using this encapsulation method can only expand to a maximum of 16 UART interfaces, which cannot meet the application needs of more UART interface devices. Summary of the Invention

[0004] The purpose of this invention is to provide a UART interface data receiving module, a UART interface data transmitting module, and a processor based on the ZYNQ AXI4 bus package. The UART interface data receiving module, UART interface data transmitting module, and processor can provide reception and transmission of at least two channels of UART interface data.

[0005] To achieve the above objectives, embodiments of the present invention provide a UART interface data receiving module based on the ZYNQ AXI4 bus package, including at least two data receiving links and a data splicing unit. Each of the data receiving links is used to receive externally input UART interface data, and the data splicing unit is connected to the data receiving link and is used to splice and process the UART interface data.

[0006] Optionally, the data receiving link includes:

[0007] A serial receiving unit, wherein the serial receiving unit is used to receive corresponding UART interface data;

[0008] A baud rate generator, corresponding one-to-one with each of the serial receiving units, is used to adjust the data receiving rate of the corresponding serial receiving unit;

[0009] Each of the serial receiving units corresponds to a buffer queue and is used to store the data written to the buffer queue by the corresponding serial receiving unit.

[0010] Optionally, the data receiving module includes:

[0011] The serial port configuration register is used to store the configuration information of the baud rate generator;

[0012] A serial port enable register, wherein at least 3 bits of the serial port enable register are used to store an indication code indicating whether the serial receiving unit can continue to receive data and write it into the buffer queue;

[0013] A serial port data receiving register, connected to the data splicing unit, is used to store the data spliced ​​and processed by the data splicing unit;

[0014] A logic judgment unit, connected to each of the cache queues, is used to determine whether any cache queue currently stores data.

[0015] Optionally, the data element output by the data splicing unit is 32 bits, of which at most 24 bits are used for every 8 bits to store UART interface data of one data receiving link, and at least 3 of the remaining 8 bits are used to store an indication code indicating the validity of the UART interface data.

[0016] On the other hand, the present invention also provides a UART interface data transmission module based on the ZYNQ AXI4 bus package. The data transmission module includes at least two data transmission links and a data splitting unit. The data splitting unit is used to receive unsplit UART interface data and split the UART interface data according to the valid data bits therein. The data transmission links are connected to the data splitting unit and are used to receive the split UART interface data.

[0017] Optionally, the data transmission link includes:

[0018] A serial transmission unit, connected to the data splitting unit, is used to transmit the split UART interface data to the outside.

[0019] A baud rate generator, corresponding to each of the serial transmission units, is used to adjust the data transmission rate of the corresponding serial transmission unit.

[0020] Optionally, the data transmission module includes:

[0021] The serial port configuration register is used to store the configuration information of the baud rate generator;

[0022] The serial port data transmission register is used to store the UART interface data to be transmitted;

[0023] A serial port transmission status register, connected to the serial transmission unit, is used to determine whether the serial transmission unit is currently in an idle state.

[0024] Optionally, the data splitting unit receives 32-bit data elements, of which at most 24 bits are used for every 8 bits to store UART interface data of one data receiving link, and at least 3 of the remaining 8 bits are used to store an indication code indicating the validity of the UART interface data.

[0025] Furthermore, the present invention also provides a processor based on a ZYNQ AXI4 bus package, the processor comprising:

[0026] The data receiving module described above is used to receive the UART interface data, perform splicing processing, and send out the spliced ​​UART interface data.

[0027] The processing module, connected to the data receiving module, is used to receive and process the spliced ​​UART interface data, and to send out the UART interface data to be sent.

[0028] The data transmission module described above is connected to the processing module and is used to split the UART interface data to be transmitted and send the split UART interface data.

[0029] Through the above technical solution, the UART interface data receiving module, UART interface data transmitting module and processor based on ZYNQ AXI4 bus package provided by the present invention receive and transmit multiple UART interface data by setting data splicing unit and data splitting unit, and combine with preset data valid bits to ensure effective data identification, thereby providing at least two UART interface data reception and transmission, expanding the number of UART interfaces.

[0030] Other features and advantages of the embodiments of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0031] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:

[0032] Figure 1 This is a schematic diagram of a UART interface data receiving module based on a ZYNQ AXI4 bus package according to an embodiment of the present invention.

[0033] Figure 2 This is a detailed schematic diagram of a UART interface data receiving module based on a ZYNQ AXI4 bus package according to an embodiment of the present invention.

[0034] Figure 3 This is a schematic diagram of a UART interface data transmission module based on a ZYNQ AXI4 bus package according to an embodiment of the present invention.

[0035] Figure 4 This is a detailed schematic diagram of a UART interface data transmission module based on a ZYNQ AXI4 bus package according to an embodiment of the present invention.

[0036] Figure 5 This is a schematic diagram of a processor based on a ZYNQ AXI4 bus package according to an embodiment of the present invention.

[0037] Explanation of reference numerals in the attached figures

[0038] A. Data receiving link B. Data sending link

[0039] FIFO, buffer queue, OR, logical judgment unit Detailed Implementation

[0040] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the scope of the present invention.

[0041] In embodiments of the present invention, unless otherwise stated, directional terms such as "upper," "lower," "top," and "bottom" are generally used to describe the relative positional relationships of components in relation to the directions shown in the accompanying drawings or in relation to the vertical, perpendicular, or gravitational directions.

[0042] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0043] like Figure 1 The diagram shows a UART interface data receiving module based on a ZYNQ AXI4 bus package according to an embodiment of the present invention. Figure 1 The data receiving module includes at least two data receiving links A and a data splicing unit. Each data receiving link A is used to receive externally input UART interface data, and the data splicing unit is connected to the data receiving link A to splice and process the UART interface data.

[0044] Figure 2 This is a detailed schematic diagram of a UART interface data receiving module based on a ZYNQ AXI4 bus package according to an embodiment of the present invention. In this embodiment, the specific form of the data receiving link A can be of various forms known to those skilled in the art. In a preferred example of the present invention, the data receiving link A may include a serial receiving unit, a baud rate generator, and a buffer queue FIFO, such as... Figure 2 As shown in the diagram. The serial receiving unit can be used to receive data from one corresponding UART interface channel. A baud rate generator corresponds one-to-one with each serial receiving unit, used to adjust the data receiving rate of the corresponding serial receiving unit, thereby ensuring that UART interface data can be effectively received. A buffer queue (FIFO) corresponds one-to-one with each serial receiving unit, used to store the data written to the buffer queue (FIFO) by the corresponding serial receiving unit.

[0045] Based on the above, to ensure the effectiveness of multi-channel data reception, the data reception rates of the serial receiving units in each data receiving link A are different. To address this inconsistency, in one embodiment of the present invention, the data receiving module may further include a serial port configuration register. This serial port configuration register can be used to store configuration information of the baud rate generators corresponding to the multiple serial receiving units. To control whether the serial receiving units can continue to receive data and write it to the buffer queue FIFO, in one embodiment of the present invention, the data receiving module may further include a serial port enable register. At least three bits of the data stored in the serial port enable register are used to store an indication code indicating whether the serial receiving unit can continue to receive data and write it to the buffer queue FIFO. The ZYNQ soft core controls whether the serial receiving unit can continue to receive data and write it to the buffer queue FIFO by reading the data stored in the serial port enable register. To store the data processed by the data splicing unit, in one embodiment of the present invention, the data receiving module may further include a serial port data receiving register. This serial port data receiving register is connected to the data splicing unit and is used to store the data processed by the data splicing unit. The ZYNQ's soft core reads the data stored in the serial port data receive register to complete the data reception process. To ensure that data is read as soon as it is stored in any buffer queue FIFO, in one embodiment of the invention, the data receiving module may further include a logic judgment unit OR. This logic judgment unit OR is connected to each buffer queue FIFO and is used to determine whether any buffer queue FIFO currently stores data. The logic judgment unit OR outputs an interrupt signal. If any buffer queue FIFO contains data, the interrupt signal output by the logic judgment unit OR is set to a high level; if all buffer queue FIFOs are empty, the interrupt signal output by the logic judgment unit OR is set to a low level. The ZYNQ's soft core determines whether to trigger a serial receiving unit interrupt and read the data stored in the buffer queue FIFO by reading the interrupt signal. If the interrupt signal is high, the ZYNQ's soft core triggers a serial receiving unit interrupt and reads the data stored in the buffer queue FIFO; otherwise, no interrupt is triggered.

[0046] In this embodiment, the number of bits for the data elements output by the data splicing unit can be any of the values ​​known to those skilled in the art, such as 64, 32, etc. Considering that the registers in the ZYNQ chip are typically 32-bit registers, in a preferred example of this invention, the data elements output by the data splicing unit are 32 bits. In a computer, a byte is 8 bits, and a byte is usually used as the basic unit for data transmission of the serial receiving unit in the UART interface data receiving module based on the ZYNQ AXI4 bus package provided by this invention. To receive multiple UART interface data, data bits need to be reserved to indicate whether the received data is valid. Since the registers in the ZYNQ chip are typically 32-bit registers, in the UART interface data receiving module based on the ZYNQ AXI4 bus package provided by this invention, a maximum of 3 UART interface data can be received, and at most 24 bits are used for each 8 bits to store the UART interface data of one data receiving link A, and at least 3 of the remaining 8 bits are used to store an indication code indicating the validity of the UART interface data.

[0047] Based on the above, the ZYNQ's soft core reads the data stored in the serial port enable register to determine whether the corresponding serial receiving unit needs to receive data and write it into the buffer queue FIFO. It controls the data receiving rate of the corresponding serial receiving unit through the baud rate generator configuration information stored in the serial port enable register, ensuring effective data reception. When data exists in any buffer queue FIFO, an interrupt signal is issued through the logic judgment unit OR, interrupting the serial receiving unit's data reception. The unit then reads the data in the buffer and performs data concatenation. If data exists in the current buffer queue FIFO, the corresponding valid data bit in the data element output by the data concatenation unit is set to indicate a valid code; otherwise, it is set to an invalid code. The data concatenated by the data concatenation unit is stored in the serial port data receiving register. The soft core reads the data stored in the serial port data receiving register and determines whether the corresponding data is valid through the valid data bit, completing the data reception process.

[0048] On the other hand, the present invention also provides a UART interface data transmission module based on the ZYNQ AXI4 bus package. For example... Figure 3 The diagram shows a UART interface data transmission module based on a ZYNQ AXI4 bus package according to an embodiment of the present invention. Figure 3 The data transmission module may include at least two data transmission links B and a data splitting unit. The data splitting unit receives the unsplit UART interface data and splits it according to the valid data bits. Data transmission link B is connected to the data splitting unit and receives the split UART interface data.

[0049] Figure 4 This is a detailed schematic diagram of a UART interface data transmission module based on a ZYNQ AXI4 bus package according to an embodiment of the present invention. The specific form of this data transmission link B can be various forms known to those skilled in the art. In a preferred embodiment of the present invention, the data transmission link B may include a serial transmission unit and a baud rate generator, such as... Figure 4 As shown in the diagram, the serial transmission unit is connected to the data splitting unit and is used to transmit the split UART interface data. A baud rate generator corresponds one-to-one with each serial transmission unit, used to adjust the data transmission rate of the corresponding serial transmission unit to ensure that the UART interface data can be effectively transmitted.

[0050] Based on the above, to ensure the effectiveness of multi-channel data transmission, the data transmission rates of the serial transmission units in each data transmission link B are different. To address this inconsistency, in one embodiment of the present invention, the data transmission module may further include a serial port configuration register. This serial port configuration register can be used to store configuration information of the baud rate generators corresponding to the multiple serial transmission units. To store the UART interface data to be transmitted, in one embodiment of the present invention, the data transmission module may further include a serial port data transmission register. This serial port data transmission register is used to store the UART interface data to be transmitted from the ZYNQ's soft core. The ZYNQ's soft core needs to determine whether the serial transmission unit is idle before filling it with the UART interface data to be transmitted. To facilitate this determination, in one embodiment of the present invention, the data transmission module may further include a serial port transmission status register. This serial port transmission status register is connected to the serial transmission unit and is used to determine whether the current serial transmission unit is in an idle state.

[0051] In this embodiment, the number of bits of the data element output by the data splitting unit can be any of the values ​​known to those skilled in the art, such as 64, 32, etc. Considering that the registers in the ZYNQ chip are usually 32-bit registers, in a preferred example of the present invention, the data element received by the data splitting unit is 32 bits. In a computer, a byte is 8 bits, and a byte is usually used as the basic unit of data transmission for the serial transmission unit in the UART interface data transmission module based on the ZYNQ AXI4 bus package provided by the present invention. To realize the transmission of multiple UART interface data, it is necessary to reserve data bits to indicate whether the transmitted data is valid. Since the registers in the ZYNQ chip are usually 32-bit registers, in the UART interface data transmission module based on the ZYNQ AXI4 bus package provided by the present invention, a maximum of 3 UART interface data transmissions can be realized, and at most 24 bits of each 8 bits are used to store the UART interface data of one data transmission link B, and at least 3 of the remaining 8 bits are used to store the indication code indicating the validity of the UART interface data.

[0052] Based on the above, the soft core of ZYNQ determines whether the corresponding serial transmission unit is idle by using the data stored in the serial port transmission status register. If it is idle, it fills the serial port data transmission register with the data to be transmitted. The valid bits in the data determine whether the corresponding data is valid. The data to be transmitted stored in the serial port data transmission register is split and processed by the data splitting unit and then transmitted through the serial transmission unit. The baud rate generator configuration information stored in the serial port configuration register controls the data transmission rate of the corresponding serial transmission unit to complete the effective transmission of data.

[0053] Furthermore, the present invention also provides a processor based on the ZYNQ AXI4 bus package, the processor comprising: a data receiving module as described above, configured to receive UART interface data and perform splicing processing, and transmit the spliced ​​UART interface data; a processing module, connected to the data receiving module, configured to receive the spliced ​​UART interface data and perform processing, and transmit the UART interface data to be transmitted; and a data transmitting module as described above, connected to the processing module, configured to split the UART interface data to be transmitted, and transmit the split UART interface data. Figure 5 This is a schematic diagram of a processor based on a ZYNQ AXI4 bus package according to an embodiment of the present invention, wherein the processor is as follows: Figure 5 As shown, the data receiving module is specifically as follows: Figures 1 to 2 As shown, the data sending module is as follows: Figures 3 to 4 As shown.

[0054] like Figure 1The diagram shows a UART interface data receiving module based on a ZYNQ AXI4 bus package according to an embodiment of the present invention. Figure 1 The data receiving module includes at least two data receiving links A and a data splicing unit. Each data receiving link A is used to receive externally input UART interface data, and the data splicing unit is connected to the data receiving link A to splice and process the UART interface data.

[0055] Figure 2 This is a detailed schematic diagram of a UART interface data receiving module based on a ZYNQ AXI4 bus package according to an embodiment of the present invention. In this embodiment, the specific form of the data receiving link A can be of various forms known to those skilled in the art. In a preferred example of the present invention, the data receiving link A may include a serial receiving unit, a baud rate generator, and a buffer queue FIFO, such as... Figure 2 As shown in the diagram. The serial receiving unit can be used to receive data from one corresponding UART interface channel. A baud rate generator corresponds one-to-one with each serial receiving unit, used to adjust the data receiving rate of the corresponding serial receiving unit, thereby ensuring that UART interface data can be effectively received. A buffer queue (FIFO) corresponds one-to-one with each serial receiving unit, used to store the data written to the buffer queue (FIFO) by the corresponding serial receiving unit.

[0056] Based on the above, to ensure the effectiveness of multi-channel data reception, the data reception rates of the serial receiving units in each data receiving link A are different. To address this inconsistency, in one embodiment of the present invention, the data receiving module may further include a serial port configuration register. This serial port configuration register can be used to store configuration information of the baud rate generators corresponding to the multiple serial receiving units. To control whether the serial receiving units can continue to receive data and write it to the buffer queue FIFO, in one embodiment of the present invention, the data receiving module may further include a serial port enable register. At least three bits of the data stored in the serial port enable register are used to store an indication code indicating whether the serial receiving unit can continue to receive data and write it to the buffer queue FIFO. The ZYNQ soft core controls whether the serial receiving unit can continue to receive data and write it to the buffer queue FIFO by reading the data stored in the serial port enable register. To store the data processed by the data splicing unit, in one embodiment of the present invention, the data receiving module may further include a serial port data receiving register. This serial port data receiving register is connected to the data splicing unit and is used to store the data processed by the data splicing unit. The ZYNQ's soft core reads the data stored in the serial port data receive register to complete the data reception process. To ensure that data is read as soon as it is stored in any buffer queue FIFO, in one embodiment of the invention, the data receiving module may further include a logic judgment unit OR. This logic judgment unit OR is connected to each buffer queue FIFO and is used to determine whether any buffer queue FIFO currently stores data. The logic judgment unit OR outputs an interrupt signal. If any buffer queue FIFO contains data, the interrupt signal output by the logic judgment unit OR is set to a high level; if all buffer queue FIFOs are empty, the interrupt signal output by the logic judgment unit OR is set to a low level. The ZYNQ's soft core determines whether to trigger a serial receiving unit interrupt and read the data stored in the buffer queue FIFO by reading the interrupt signal. If the interrupt signal is high, the ZYNQ's soft core triggers a serial receiving unit interrupt and reads the data stored in the buffer queue FIFO; otherwise, no interrupt is triggered.

[0057] In this embodiment, the number of bits for the data elements output by the data splicing unit can be any of the values ​​known to those skilled in the art, such as 64, 32, etc. Considering that the registers in the ZYNQ chip are typically 32-bit registers, in a preferred example of this invention, the data elements output by the data splicing unit are 32 bits. In a computer, a byte is 8 bits, and a byte is usually used as the basic unit for data transmission of the serial receiving unit in the UART interface data receiving module based on the ZYNQ AXI4 bus package provided by this invention. To receive multiple UART interface data, data bits need to be reserved to indicate whether the received data is valid. Since the registers in the ZYNQ chip are typically 32-bit registers, in the UART interface data receiving module based on the ZYNQ AXI4 bus package provided by this invention, a maximum of 3 UART interface data can be received, and at most 24 bits are used for each 8 bits to store the UART interface data of one data receiving link A, and at least 3 of the remaining 8 bits are used to store an indication code indicating the validity of the UART interface data.

[0058] Based on the above, the ZYNQ's soft core reads the data stored in the serial port enable register to determine whether the corresponding serial receiving unit needs to receive data and write it into the buffer queue FIFO. It controls the data receiving rate of the corresponding serial receiving unit through the baud rate generator configuration information stored in the serial port enable register, ensuring effective data reception. When data exists in any buffer queue FIFO, an interrupt signal is issued through the logic judgment unit OR, interrupting the serial receiving unit's data reception. The unit then reads the data in the buffer and performs data concatenation. If data exists in the current buffer queue FIFO, the corresponding valid data bit in the data element output by the data concatenation unit is set to indicate a valid code; otherwise, it is set to an invalid code. The data concatenated by the data concatenation unit is stored in the serial port data receiving register. The soft core reads the data stored in the serial port data receiving register and determines whether the corresponding data is valid through the valid data bit, completing the data reception process.

[0059] like Figure 3 The diagram shows a UART interface data transmission module based on a ZYNQ AXI4 bus package according to an embodiment of the present invention. Figure 3 The data transmission module may include at least two data transmission links B and a data splitting unit. The data splitting unit receives the unsplit UART interface data and splits it according to the valid data bits. Data transmission link B is connected to the data splitting unit and receives the split UART interface data.

[0060] Figure 4This is a detailed schematic diagram of a UART interface data transmission module based on a ZYNQ AXI4 bus package according to an embodiment of the present invention. The specific form of this data transmission link B can be various forms known to those skilled in the art. In a preferred embodiment of the present invention, the data transmission link B may include a serial transmission unit and a baud rate generator, such as... Figure 4 As shown in the diagram, the serial transmission unit is connected to the data splitting unit and is used to transmit the split UART interface data. A baud rate generator corresponds one-to-one with each serial transmission unit, used to adjust the data transmission rate of the corresponding serial transmission unit to ensure that the UART interface data can be effectively transmitted.

[0061] Based on the above, to ensure the effectiveness of multi-channel data transmission, the data transmission rates of the serial transmission units in each data transmission link B are different. To address this inconsistency, in one embodiment of the present invention, the data transmission module may further include a serial port configuration register. This serial port configuration register can be used to store configuration information of the baud rate generators corresponding to the multiple serial transmission units. To store the UART interface data to be transmitted, in one embodiment of the present invention, the data transmission module may further include a serial port data transmission register. This serial port data transmission register is used to store the UART interface data to be transmitted from the ZYNQ's soft core. The ZYNQ's soft core needs to determine whether the serial transmission unit is idle before filling it with the UART interface data to be transmitted. To facilitate this determination, in one embodiment of the present invention, the data transmission module may further include a serial port transmission status register. This serial port transmission status register is connected to the serial transmission unit and is used to determine whether the current serial transmission unit is in an idle state.

[0062] In this embodiment, the number of bits of the data element output by the data splitting unit can be any of the values ​​known to those skilled in the art, such as 64, 32, etc. Considering that the registers in the ZYNQ chip are usually 32-bit registers, in a preferred example of the present invention, the data element received by the data splitting unit is 32 bits. In a computer, a byte is 8 bits, and a byte is usually used as the basic unit of data transmission for the serial transmission unit in the UART interface data transmission module based on the ZYNQ AXI4 bus package provided by the present invention. To realize the transmission of multiple UART interface data, it is necessary to reserve data bits to indicate whether the transmitted data is valid. Since the registers in the ZYNQ chip are usually 32-bit registers, in the UART interface data transmission module based on the ZYNQ AXI4 bus package provided by the present invention, a maximum of 3 UART interface data transmissions can be realized, and at most 24 bits of each 8 bits are used to store the UART interface data of one data transmission link B, and at least 3 of the remaining 8 bits are used to store the indication code indicating the validity of the UART interface data.

[0063] Based on the above, the soft core of ZYNQ determines whether the corresponding serial transmission unit is idle by using the data stored in the serial port transmission status register. If it is idle, it fills the serial port data transmission register with the data to be transmitted. The valid bits in the data determine whether the corresponding data is valid. The data to be transmitted stored in the serial port data transmission register is split and processed by the data splitting unit and then transmitted through the serial transmission unit. The baud rate generator configuration information stored in the serial port configuration register controls the data transmission rate of the corresponding serial transmission unit to complete the effective transmission of data.

[0064] Through the above technical solution, the UART interface data receiving module, UART interface data transmitting module and processor based on ZYNQ AXI4 bus package provided by the present invention receive and transmit multiple UART interface data by setting data splicing unit and data splitting unit, and combine with preset data valid bits to ensure effective data identification, thereby providing at least two UART interface data reception and transmission, expanding the number of UART interfaces.

[0065] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0066] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A UART interface data receiving module based on the ZYNQ AXI4 bus package, characterized in that, The data receiving module includes at least two data receiving links and a data splicing unit. Each data receiving link is used to receive externally input UART interface data. The data splicing unit is connected to the data receiving link and is used to splice and process the UART interface data. The data receiving link includes: a serial receiving unit for receiving data from a corresponding UART interface; a baud rate generator, corresponding to each serial receiving unit, for adjusting the data receiving rate of each serial receiving unit; and a buffer queue, corresponding to each serial receiving unit, for storing the data written to the buffer queue by each serial receiving unit. The data receiving module includes: a serial port configuration register for storing configuration information of the baud rate generator; a serial port enable register, wherein at least 3 bits of the serial port enable register are used to store an indication code indicating whether the serial receiving unit can continue to receive data and write it to the buffer queue; a serial port data receiving register connected to the data splicing unit for storing the data spliced ​​and processed by the data splicing unit; and a logic judgment unit connected to each of the buffer queues for determining whether any buffer queue currently stores data. The data element output by the data splicing unit is 32 bits, of which at most 24 bits are used for every 8 bits to store UART interface data of the data receiving link, and at least 3 of the remaining 8 bits are used to store an indication code indicating the validity of the UART interface data.

2. A UART interface data transmission module based on the ZYNQ AXI4 bus package, characterized in that, The data transmission module includes at least two data transmission links and a data splitting unit. The data splitting unit receives unsplit UART interface data and splits the UART interface data according to the valid data bits. The data transmission links are connected to the data splitting unit and are used to receive the split UART interface data. The data transmission link includes: a serial transmission unit connected to the data splitting unit, used to transmit the split UART interface data to the outside; and a baud rate generator, corresponding one-to-one with the serial transmission unit, used to adjust the data transmission rate of the corresponding serial transmission unit respectively. The data transmission module includes: a serial port configuration register for storing configuration information of the baud rate generator; a serial port data transmission register for storing UART interface data to be transmitted; and a serial port transmission status register connected to the serial transmission unit for determining whether the serial transmission unit is currently in an idle state. The data splitting unit receives 32-bit data elements, of which at most 24 bits are used for every 8 bits to store UART interface data of one data receiving link, and at least 3 of the remaining 8 bits are used to store an indication code indicating the validity of the UART interface data.

3. A processor based on the ZYNQ AXI4 bus package, characterized in that, The processor includes: The data receiving module as described in claim 1 is used to receive the UART interface data, perform splicing processing, and send out the spliced ​​UART interface data; The processing module, connected to the data receiving module, is used to receive and process the spliced ​​UART interface data, and to send out the UART interface data to be sent. The data transmission module as described in claim 2 is connected to the processing module and is used to split the UART interface data to be transmitted and send the split UART interface data.

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