A chip design data synchronization method, device, equipment and storage medium

Abstract

The application discloses a chip design data synchronization method and device, equipment and a storage medium. The method comprises the following steps: obtaining a chip configuration file, determining a target storage structure according to the configuration file; obtaining to-be-synchronized data, verifying the to-be-synchronized data to generate a data verification result; when the data verification result is valid data, performing chip design data synchronization on the to-be-synchronized data according to the target storage structure. The obtained chip configuration file is matched with a query command input by a user to determine the target storage structure, the to-be-synchronized data is verified to generate the data verification result, when the data verification result is valid data, the to-be-synchronized data is synchronized according to the target storage structure, the configuration file comprises a unified storage structure configuration, the problem of low management and access efficiency caused by scattered design data is solved, the design version of each level is clear, version synchronization control can be conveniently performed, and the difficulty of design data synchronization is reduced.

Description

Technical Field

[0001] This invention relates to the field of chip physical design technology, and in particular to a chip design data synchronization method, apparatus, device, and storage medium. Background Technology

[0002] As integrated circuit technology continues to advance, chip integration density increases, and functions become more complex. Consequently, the complexity of chip back-end physical design also rises. Physical design necessitates block-based and hierarchical design to reduce machine resource requirements and shorten the execution time of a single design iteration. The increasing number of hierarchical and block-based physical designs results in more fragmented and massive amounts of design data. This necessitates effective organization and management of physical design data to enable parallel processing of different levels of physical design, improving design efficiency. Simultaneously, it requires providing simple and efficient methods for accessing design data.

[0003] In existing technologies, design data is relatively scattered and lacks a unified storage structure configuration, making design data access inefficient and not simple. Furthermore, the coordination between different design levels is poor, resulting in poor design parallelism and impacting design efficiency. Moreover, the lack of clarity regarding design versions at each level makes synchronous design iteration difficult. Summary of the Invention

[0004] This invention provides a chip design data synchronization method, apparatus, device, and storage medium to manage and synchronize design data at different levels of a chip.

[0005] According to one aspect of the present invention, a chip design data synchronization method is provided, the method comprising:

[0006] Obtain the chip configuration file and determine the target storage structure based on the configuration file. The configuration file contains the storage structure of the chip design data.

[0007] Acquire the data to be synchronized and verify the data to be synchronized to generate data verification results;

[0008] When the data verification result shows that the data is valid, chip data synchronization is performed on the data to be synchronized according to the target storage structure.

[0009] Optionally, the chip configuration file is obtained, including: obtaining chip configuration information input by the user, wherein the configuration information includes the storage area name and storage path; establishing a storage structure corresponding to the chip configuration information, wherein the storage structure includes a sub-level design data area, a design data verification area and an upper-level design synthesis area; and generating a configuration file based on each storage structure.

[0010] Optionally, the target storage structure is determined based on the configuration file, including: obtaining the query command input by the user, wherein the query command includes keywords of the target storage structure; matching the query command with the configuration file; and when a match is successful, using the storage structure in the configuration file corresponding to the query command as the target storage structure.

[0011] Optionally, after matching the query command through the configuration file, the method further includes: generating a first prompt message based on the query command when the match fails; and sending the first prompt message to the user terminal for display.

[0012] Optionally, the data to be synchronized is verified to generate a data verification result, including: extracting verification information from the data to be synchronized, wherein the verification information includes shape, area, metal layer used, port location and design rules; determining whether the verification information meets preset conditions, if so, determining that the data verification result is valid; otherwise, determining that the data verification result is invalid.

[0013] Optionally, after verifying the data to be synchronized and generating a data verification result, the method further includes: when the data verification result is invalid, generating a second prompt message based on the data verification result; and triggering an alarm in a specified manner based on the second prompt message.

[0014] Optionally, chip design data synchronization is performed on the data to be synchronized according to the target storage structure, including: determining the target storage path corresponding to the target storage structure; and writing the data to be synchronized to the target storage path for chip design data synchronization.

[0015] According to another aspect of the present invention, a chip design data synchronization device is provided, the device comprising:

[0016] The chip configuration file acquisition module is used to acquire the chip configuration file and determine the target storage structure based on the configuration file. The configuration file contains the storage structure of the chip design data.

[0017] The data verification result determination module is used to acquire the data to be synchronized and to verify the data to be synchronized to generate data verification results.

[0018] The chip design data synchronization module is used to synchronize the chip design data according to the target storage structure when the data verification result shows that the data is valid.

[0019] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0020] At least one processor; and

[0021] A memory communicatively connected to the at least one processor; wherein,

[0022] The memory stores a computer program that can be executed by the at least one processor, which enables the at least one processor to perform a chip data synchronization method according to any embodiment of the present invention.

[0023] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement a chip data synchronization method according to any embodiment of the present invention.

[0024] The technical solution of this invention matches the user-input query command with the obtained chip configuration file to determine the target storage structure, and generates a data verification result by validating the obtained data to be synchronized. When the data verification result is valid, chip design data synchronization is performed on the data to be synchronized according to the target storage structure. The configuration file includes a unified storage structure configuration, which solves the problem of low management and access efficiency caused by scattered design data. The design versions at each level are clear, which can facilitate version synchronization control and reduce the difficulty of data synchronization.

[0025] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a flowchart of a chip design data synchronization method provided in Embodiment 1 of the present invention;

[0028] Figure 2 A schematic diagram of a chip design hierarchy provided in Embodiment 1 of the present invention;

[0029] Figure 3 This is a flowchart of another chip design data synchronization method provided in Embodiment 2 of the present invention;

[0030] Figure 4 This is a schematic diagram of a chip design data synchronization device according to Embodiment 3 of the present invention;

[0031] Figure 5This is a schematic diagram of the structure of an electronic device that implements a chip design data synchronization method according to an embodiment of the present invention. Detailed Implementation

[0032] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0033] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0034] Example 1

[0035] Figure 1 This is a flowchart illustrating a chip design data synchronization method according to Embodiment 1 of the present invention. This embodiment is applicable to situations involving updating and synchronizing chip design data versions. The method can be executed by a chip design data synchronization device, which can be implemented in hardware and / or software and can be configured within the chip. Figure 1 As shown, the method includes:

[0036] S110. Obtain the chip configuration file and determine the target storage structure based on the configuration file. The configuration file contains the storage structure of the chip design data.

[0037] Here, "chip" refers to an integrated circuit, a method in electronics for miniaturizing circuits (mainly semiconductor devices, but also passive components), often manufactured on the surface of a semiconductor wafer. "Configuration file" refers to a user settings file, containing all user-specific configuration settings; in this embodiment, the configuration file mainly includes the chip's design hierarchy. "Memory structure" refers to the memory paths corresponding to each design hierarchy within the chip.

[0038] Furthermore, when using the technical solution of this embodiment for physical design data management, the user needs to establish a configuration file, define the configuration information of all design layers according to the chip design hierarchy, and the supporting software tools establish the corresponding storage structure according to the configuration information of the configuration file. The storage structure includes a sub-level design data area, a design data verification area, and an upper-level design synthesis area. The storage locations of the sub-level design data area and the upper-level design synthesis area can also be determined by the designers to increase flexibility. At the same time, software tools are provided for designers to manage and operate the stored data.

[0039] Optionally, the chip configuration file is obtained, including: obtaining chip configuration information input by the user, wherein the configuration information includes the storage area name and storage path; establishing a storage structure corresponding to the chip configuration information, wherein the storage structure includes a sub-level design data area, a design data verification area and an upper-level design synthesis area; and generating a configuration file based on each storage structure.

[0040] Specifically, the configuration information includes the storage area name and storage path input by the designer. The controller can establish a storage structure corresponding to the chip configuration information. The storage structure includes a sub-level design data area, a design data verification area, and an upper-level design synthesis area. Based on the established storage structure, a configuration file can be generated. The storage structure corresponds to the chip's design level.

[0041] Specifically, Figure 2 This embodiment provides a schematic diagram of the chip design hierarchy. Figure 2 In this chip, the TOP layer comprises n sub-layers: Func A, Func B, ..., Func N. Func A comprises i sub-layers: A1, A2, ..., Ai. Similarly, Func B and Func N comprise j and k sub-layers, respectively. During physical design, the design of the TOP layer depends on its sub-layers Func A, Func B, and Func N. The physical design of each Func layer, in turn, depends on its own sub-layers; for example, the physical design of Func A depends on the design data of A1, A2, ..., Ai. A1, A2...Ai, B1, B2...Bj, N1, N2...Nk are collectively referred to as Blocks.

[0042] Furthermore, during the design process, the physical design at the sub-level is performed first, resulting in Data 1 to Data n sub-design data. This sub-design data is checked out to the design data verification area using a specially developed software tool. In the verification area, upper-level designers use the software tool to perform validity checks on the checked-out data. Sub-design data must meet the upper-level design constraints to be considered valid design data, such as requirements regarding shape, area, metal layers used, port locations, and design rules. Data that passes the validity check is checked into the upper-level design synthesis area by the upper-level designers for their use. Data that fails the validity check is returned to the sub-level designers with error messages for them to identify problems and update the design.

[0043] Optionally, the target storage structure is determined based on the configuration file, including: obtaining the query command input by the user, wherein the query command includes keywords of the target storage structure; matching the query command with the configuration file; and when a match is successful, using the storage structure in the configuration file corresponding to the query command as the target storage structure.

[0044] Specifically, users can enter query commands through a user terminal connected to the chip design data to find configuration information. The user terminal refers to a mobile terminal device, including but not limited to mobile phones, laptops, digital radio receivers, PDAs (Personal Digital Assistants), PADs (Tablet PCs), and PMPs (Portable Multimedia Players). The query command includes keywords for the target storage structure. The query command is matched against a configuration file. Matching refers to comparing the keywords with the storage structure names in the configuration file. When a match is successful, the storage structure corresponding to the query command in the configuration file can be obtained as the target storage structure.

[0045] Optionally, after matching the query command through the configuration file, the method further includes: generating a first prompt message based on the query command when the match fails; and sending the first prompt message to the user terminal for display.

[0046] Specifically, matching failures may occur, possibly due to an incorrect user-entered query command. In this case, an error message will be displayed, data synchronization will cease, and a first prompt message will be generated based on the query command. Further, the controller will issue an alarm in a specified manner based on the prompt message. The alarm is to alert the user, allowing them to promptly check and adjust their query command to ensure proper synchronization of subsequent chip design data. Specified methods include voice or image. Voice can be broadcast through a speaker connected to the controller; for example, the voice content could be: "Query command does not conform to specifications." Images can be displayed through a user terminal connected to the controller to alert the user.

[0047] S120. Obtain the data to be synchronized and verify the data to be synchronized to generate data verification results.

[0048] Specifically, data synchronization refers to the process of updating the design version of chip design data. During data synchronization, the validity of the data to be synchronized also needs to be verified. It should be noted that the validity verification is completed in the data verification area. When performing validity verification, the data verification result is determined to be valid only if the shape, area, metal layer used, port location, design rule checks, etc. all meet the requirements; otherwise, the data verification result is determined to be invalid.

[0049] S130. When the data verification result is that the data is valid, perform chip design data synchronization on the data to be synchronized according to the target storage structure.

[0050] Optionally, chip design data synchronization is performed on the data to be synchronized according to the target storage structure, including: determining the target storage path corresponding to the target storage structure; and writing the data to be synchronized to the target storage path for chip design data synchronization.

[0051] Specifically, chip design data synchronization will only be performed when the data verification result is valid. At this time, it is necessary to first determine the target storage path corresponding to the target storage structure, and then write the data to be synchronized to the target storage path to perform chip design data synchronization.

[0052] Detailed Implementation: When synchronizing chip design data, for example, if the entire chip design needs to be synchronized to version V02, the process is as follows: 1. Block designers update their Block design to version V02. 2. Block designers checkout their Block design data to the design data verification area. 3. Func designers perform a validity check on the Block design data in the design data verification area. 4. If the validity check fails, the Func designer returns the Block design data along with the error message to the Block designer, and the process restarts from step "1". 5. If the validity check passes, the Block is considered to have completed a valid checkout, and the Func designer checks in the Block design data to the Func layer design synthesis area. 6. Func layer designers update their Func design data to V02. 7. Func designers checkout their V02 design data to the design data verification area. 8. Top layer designers perform a validity check on the Func design data in the design data verification area. 9. If the validity check fails, the TOP designer returns the Func design data along with the error message to the Func designer, who then restarts the process from step "6". 10. If the validity check passes, the TOP designer checks in the Func design data to the TOP layer design synthesis area. 11. The TOP designer updates the TOP layer design to version V02. Steps 1-11 complete one version V02 iteration update. If an iteration update to another version is required, all designs repeat the above steps. If a sub-design is optimized after a valid checkout in version V02 and needs to be synthesized into the upper-level design, only that sub-design and its upper-level design need to complete the above steps.

[0053] Specifically, after a Block or Func completes a valid checkout, the design data for that version has been checked in to the upper-level design composition area. Therefore, the design of a Block or Func located in a sub-level design area can be modified. For example, the sub-level can continue to optimize its design or be updated for subsequent versions. Modifications to the sub-level do not affect the upper-level design. After completing a checkout and checkin, the data in the design data verification area can be deleted or retained according to version for historical reference.

[0054] It's important to note that because the configuration information for all design layers of the chip is defined in a unified configuration file, designers don't need to know the specific storage location of the design data when accessing it at a particular design layer. They don't need to use system commands to navigate to the storage directory; instead, they only need to use the accompanying software tool, specifying the name of the design layer to access. The software tool then retrieves the configuration information for that design layer from the configuration file and accesses the data storage location. Various physical design checking, verification, and analysis tools developed based on this configuration file only require specifying the name of the object being operated on, without needing to specify its specific storage path. Designers no longer need to remember numerous and complex data paths; simply remembering the design layer name allows them to access the design data at that layer, making data access fast and simple.

[0055] The technical solution of this invention matches the user-input query command with the obtained chip configuration file to determine the target storage structure, and generates a data verification result by validating the obtained data to be synchronized. When the data verification result is valid, chip data synchronization is performed on the data to be synchronized according to the target storage structure. The configuration file includes a unified storage structure configuration, which solves the problem of low management and access efficiency caused by scattered design data. The design versions at each level are clear, which can facilitate version synchronization control and reduce the difficulty of data synchronization.

[0056] Example 2

[0057] Figure 3 This is a flowchart of a chip design data synchronization method provided in Embodiment 2 of the present invention. This embodiment adds a detailed description of the process of verifying the data to be synchronized and generating data verification results based on Embodiment 1. The specific content of steps S210 and S260 is largely the same as steps S110 and S130 in Embodiment 1, and therefore will not be repeated in this embodiment. Figure 3 As shown, the method includes:

[0058] S210. Obtain the chip configuration file and determine the target storage structure based on the configuration file. The configuration file contains the storage structure of the chip design data.

[0059] Optionally, the chip configuration file is obtained, including: obtaining chip configuration information input by the user, wherein the configuration information includes the storage area name and storage path; establishing a storage structure corresponding to the chip configuration information, wherein the storage structure includes a sub-level design data area, a design data verification area and an upper-level design synthesis area; and generating a configuration file based on each storage structure.

[0060] Optionally, the target storage structure is determined based on the configuration file, including: obtaining the query command input by the user, wherein the query command includes keywords of the target storage structure; matching the query command with the configuration file; and when a match is successful, using the storage structure in the configuration file corresponding to the query command as the target storage structure.

[0061] Optionally, after matching the query command through the configuration file, the method further includes: generating a first prompt message based on the query command when the match fails; and sending the first prompt message to the user terminal for display.

[0062] S220. Obtain the data to be synchronized and extract the verification information from the data to be synchronized. The verification information includes shape, area, metal layer used, port location and design rules.

[0063] S230. Determine whether the verification information meets the preset conditions. If yes, execute S250-S260; otherwise, execute S240.

[0064] S240. The data verification result is determined to be invalid.

[0065] S250. Confirm that the data verification result is valid.

[0066] Specifically, when validating the data to be synchronized, verification information needs to be extracted first. This verification information includes shape, area, metal layer used, port location, and design rules. During validity verification, each piece of verification information is compared with preset conditions. If the verification information meets the preset conditions, the data is deemed valid, and subsequent chip design data synchronization can proceed. If the verification information does not meet the preset conditions, the data is deemed invalid, and the synchronized data and error information are pushed back to the upper-level designers.

[0067] S260. When the data verification result is that the data is valid, perform chip design data synchronization on the data to be synchronized according to the target storage structure.

[0068] Optionally, chip design data synchronization is performed on the data to be synchronized according to the target storage structure, including: determining the target storage path corresponding to the target storage structure; and writing the data to be synchronized to the target storage path for chip design data synchronization.

[0069] The technical solution of this invention matches the user-input query command with the obtained chip configuration file to determine the target storage structure. It verifies the validity of the obtained data to be synchronized to generate a data verification result. When the data verification result is valid, chip design data synchronization is performed on the data to be synchronized according to the target storage structure. The configuration file includes a unified storage structure configuration, which solves the problem of low management and access efficiency caused by scattered design data. The design versions at each level are clear, which can facilitate version synchronization control and reduce the difficulty of chip design data synchronization.

[0070] Example 3

[0071] Figure 4 This is a schematic diagram of a chip design data synchronization device provided in Embodiment 3 of the present invention. Figure 4 As shown, the device includes: a chip configuration file acquisition module 310, used to acquire a chip configuration file and determine a target storage structure based on the configuration file, wherein the configuration file contains a storage structure for chip design data;

[0072] The data verification result determination module 320 is used to acquire the data to be synchronized and to verify the data to be synchronized to generate a data verification result.

[0073] The chip data synchronization module 330 is used to perform chip design data synchronization on the data to be synchronized according to the target storage structure when the data verification result is that the data is valid.

[0074] Optionally, the chip configuration file acquisition module 310 specifically includes: a chip configuration file acquisition unit, used for: acquiring chip configuration information input by the user, wherein the configuration information includes the storage area name and storage path; establishing a storage structure corresponding to the chip configuration information, wherein the storage structure includes a sub-level design data area, a design data verification area and an upper-level design synthesis area; and generating a configuration file according to each storage structure.

[0075] Optionally, the chip configuration file acquisition module 310 specifically includes: a target storage structure determination unit, comprising: a query command acquisition subunit, used to: acquire a query command input by the user, wherein the query command includes keywords of the target storage structure; a query command matching subunit, used to: match the query command through the configuration file; and a target storage structure determination subunit, used to: when the match is successful, use the storage structure in the configuration file corresponding to the query command as the target storage structure.

[0076] Optionally, the target storage structure determination unit further includes: a first prompt information generation subunit, used to generate a first prompt information according to the query command after matching the query command through the configuration file, when the matching fails; and send the first prompt information to the user terminal for display.

[0077] Optionally, the data verification result determination module 320 specifically includes: a data verification result determination unit, used to: extract verification information from the data to be synchronized, wherein the verification information includes shape, area, metal layer used, port location and design rules; determine whether the verification information meets preset conditions, if so, determine that the data verification result is valid; otherwise, determine that the data verification result is invalid.

[0078] Optionally, the device further includes: a second prompt information generation unit, used to generate a second prompt information based on the data verification result after verifying the data to be synchronized and generating a data verification result, when the data verification result is invalid; and to trigger an alarm in a specified manner based on the second prompt information.

[0079] Optionally, the chip design data synchronization module 330 specifically includes: a chip design data synchronization unit, used to: determine the target storage path corresponding to the target storage structure; and write the data to be synchronized into the target storage path to perform chip design data synchronization.

[0080] The technical solution of this invention matches the user-input query command with the obtained chip configuration file to determine the target storage structure. It verifies the validity of the obtained data to be synchronized to generate a data verification result. When the data verification result is valid, chip design data synchronization is performed on the data to be synchronized according to the target storage structure. The configuration file includes a unified storage structure configuration, which solves the problem of low management and access efficiency caused by scattered design data. The design versions at each level are clear, which can facilitate version synchronization control and reduce the difficulty of data synchronization.

[0081] The chip design data synchronization device provided in this embodiment of the invention can execute the chip design data synchronization method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the method.

[0082] Example 4

[0083] Figure 5 A schematic diagram of an electronic device 10 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0084] like Figure 5 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 may also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0085] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0086] Processor 11 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, central processing unit (CPU), graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processors (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as a chip design data synchronization method. That is: obtaining a chip configuration file, determining a target storage structure based on the configuration file, wherein the configuration file contains the storage structure of chip design data; obtaining the data to be synchronized, and verifying the data to be synchronized to generate a data verification result; when the data verification result indicates that the data is valid, synchronizing the chip design data to be synchronized according to the target storage structure.

[0087] In some embodiments, a chip design data synchronization method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the chip design data synchronization method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform a chip design data synchronization method by any other suitable means (e.g., by means of firmware).

[0088] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0089] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0090] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0091] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0092] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0093] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0094] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0095] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A chip design data synchronization method, characterized in that, include: Obtain the chip configuration file and determine the target storage structure based on the configuration file, wherein the configuration file contains the storage structure of the chip design data; Acquire the data to be synchronized, and verify the data to be synchronized to generate data verification results; When the data verification result indicates that the data is valid, chip design data synchronization is performed on the data to be synchronized according to the target storage structure. The process of obtaining the chip configuration file includes: Obtain chip configuration information input by the user, wherein the configuration information includes the storage area name and storage path; Establish a storage structure corresponding to the chip configuration information, wherein the storage structure includes a sub-level design data area, a design data verification area, and an upper-level design synthesis area; The configuration file is generated according to each of the aforementioned storage structures; The method further includes: Extract sub-design data from the sub-level design data area to the design data verification area for validity verification. Store the verified sub-design data into the upper-level design synthesis area. Add error information to the data that fails verification and return it to the sub-level designers. The step of verifying the data to be synchronized and generating a data verification result includes: Extract the verification information from the data to be synchronized, wherein the verification information includes shape, area, metal layer used, port location and design rules; Determine whether the verification information meets the preset conditions; if so, determine that the data verification result is valid. Otherwise, the data validation result is determined to be invalid.

2. The method according to claim 1, characterized in that, Determining the target storage structure based on the configuration file includes: Obtain the query command input by the user, wherein the query command includes the keyword of the target storage structure; The query command is matched using the configuration file. When a match is successful, the storage structure in the configuration file corresponding to the query command is used as the target storage structure.

3. The method according to claim 2, characterized in that, After matching the query command through the configuration file, the process further includes: When a match fails, a first prompt message is generated based on the query command; The first prompt message is sent to the user's terminal for display.

4. The method according to claim 1, characterized in that, After verifying the data to be synchronized and generating a data verification result, the method further includes: When the data verification result indicates that the data is invalid, a second prompt message is generated based on the data verification result. The alarm will be triggered in the specified manner according to the second prompt message.

5. The method according to claim 1, characterized in that, The step of synchronizing the data to be synchronized according to the target storage structure includes: Determine the target storage path corresponding to the target storage structure; The data to be synchronized is written to the target storage path for chip design data synchronization.

6. A chip design data synchronization device, characterized in that, include: A chip configuration file acquisition module is used to acquire a chip configuration file and determine a target storage structure based on the configuration file, wherein the configuration file contains a storage structure for chip design data; The data verification result determination module is used to acquire the data to be synchronized and to verify the data to be synchronized to generate a data verification result. A chip design data synchronization module is used to synchronize the data to be synchronized with the target storage structure when the data verification result is that the data is valid. The chip configuration file acquisition module is specifically used to: acquire chip configuration information input by the user, wherein the configuration information includes the storage area name and storage path; Establish a storage structure corresponding to the chip configuration information, wherein the storage structure includes a sub-level design data area, a design data verification area, and an upper-level design synthesis area; The configuration file is generated according to each of the aforementioned storage structures; The chip configuration file acquisition module is further configured to: extract sub-design data from the sub-level design data area to the design data verification area for validity verification, store the verified sub-design data into the upper-level design synthesis area, and add error information to the data that fails verification and return it to the sub-level designer. The data verification result determination module is specifically used to: extract verification information from the data to be synchronized, wherein the verification information includes shape, area, metal layer used, port location and design rules; Determine whether the verification information meets the preset conditions; if so, determine that the data verification result is valid. Otherwise, the data validation result is determined to be invalid.

7. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-5.

8. A computer storage medium, characterized in that, The computer storage medium stores computer instructions that are used to cause a processor to execute the method of any one of claims 1-5.

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