SpMV parallel block calculation method and system based on dense packing
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF COMPUTING TECH CHINESE ACAD OF SCI
- Filing Date
- 2023-02-01
- Publication Date
- 2026-06-05
AI Technical Summary
Existing technologies do not fully utilize the temporal data locality of sparse matrix iterative computation, mainly focusing on a single SpMV computation and introducing additional overhead, failing to effectively optimize the performance of multiple iterative computations.
A tiling block method is proposed to convert a sparse matrix into a graph G. Multiple subgraphs are obtained by partitioning the tiling graph, and the row order is reordered and calculated according to the update number of the subgraphs, so as to achieve efficient parallel computation of sparse matrix and dense vector.
It improves the performance of sparse matrix iterative computation, reduces redundant computation, and realizes high-concurrency SpMV iterative computation, especially showing a significant acceleration effect in large-scale sparse matrices.
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