A current model calculation method of GaAs pHEMT considering DIBL
By constructing a GaAs pHEMT current model that considers the DIBL effect, the problem of insufficient accuracy of existing models is solved, and higher accuracy of current model characterization is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- UNIV OF ELECTRONICS SCI & TECH OF CHINA
- Filing Date
- 2023-06-14
- Publication Date
- 2026-07-21
AI Technical Summary
The existing GaAs pHEMT current model fails to effectively account for the DIBL effect caused by drain-source voltage, resulting in insufficient accuracy.
A GaAs pHEMT current model considering the DIBL effect is constructed by adopting a quasi-physical basis current model based on region partitioning and a physical basis DIBL model with equivalent threshold voltage, through least squares fitting and equivalent gate voltage replacement.
The accuracy of the GaAs pHEMT current model was improved, which made up for the lack of accuracy of the existing model and improved the fitting effect by 4.76%.
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Figure CN116822170B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of microwave semiconductor device modeling technology, and in particular to a method for calculating GaAs pHEMT current models considering DIBL. Background Technology
[0002] Device models serve as a crucial bridge connecting semiconductor devices and circuits. Accurate device models are essential for guiding and optimizing circuit design and device fabrication processes. GaAs pHEMTs (Pseudo-morphic high-electron-mobility transistors) possess advantages such as high electron mobility, making them widely used in power amplifiers. For such power amplifier designs, accurate current models are particularly important. When the device channel is short, a large drain-source voltage Vds lowers the potential barrier between the drain and source, resulting in a smaller threshold voltage and a positive output conductance, known as the drain-induced barrier reduction (DIBL) effect. Therefore, this effect must be considered in the current model.
[0003] In 2007, Hamdy Abd El Hamid et al. from the University of Rovira-Vergeili in Spain proposed a two-dimensional analytical threshold voltage and subthreshold swing model suitable for dual-gate metal-oxide-semiconductor field-effect transistors (MOSFETs). The model was derived from the two-dimensional Poisson equation, and the model's characterization ability in DIBL, subthreshold swing, and threshold voltage roll-off was verified by comparing with two-dimensional numerical simulation results.
[0004] In 2012, Mohd Khairuddin Md Arshad et al. from KU Leuven in Belgium analyzed the DIBL effect in ultrathin silicon, ultrathin silicon and thin buried oxide layer MOSFETs. The proposed model, which includes the extended MASTAR equation, showed good agreement with the experimental DIBL.
[0005] In 2013, Mamoun F. AI-Mistarihi et al. from the Jordan University of Science and Technology proposed a new accurate model for DIBL tunneling in silicon-on-insulator (SOI) MOSFETs and discussed the effects of drain-source voltage and substrate voltage variations on the DIBL effect.
[0006] As can be seen from the above existing technologies, DIBL is already widely used in MOSFET models. However, for GaAs pHEMT devices, there is an urgent need for a physical basis current model that considers the DIBL effect to make up for the insufficient accuracy caused by the incomplete consideration of second-order effects in the existing GaAs pHEMT current model.
[0007] Therefore, how to provide a physical basis current model that can take into account the DIBL effect to improve the accuracy of current model characterization and how to provide a DIBL-considered GaAs pHEMT current model calculation method is an urgent problem to be solved by those skilled in the art. Summary of the Invention
[0008] In view of this, the present invention proposes a method for calculating the GaAs pHEMT current model considering DIBL.
[0009] To achieve the above objectives, the present invention adopts the following technical solution:
[0010] Consider the calculation method of GaAs pHEMT current model for DIBL, including:
[0011] Step (1): Perform least squares fitting based on the saturation current under each gate-source voltage to obtain the numerical expression of the saturation current;
[0012] Step (2): Substitute the numerical expression of the saturation current into the nonlinear current expression, and obtain the critical electric field corresponding to each bias point based on the drain-source current at each bias point.
[0013] Step (3): Based on the equivalent thermal resistance of GaAs pHEMT, obtain the channel temperature under different biases, and combine it with the critical electric field to perform least squares fitting to obtain the numerical expression of the critical electric field.
[0014] Step (4): Substitute the numerical expressions for the saturation current and the critical electric field into the nonlinear current expression, and replace the gate-source voltage with the equivalent gate voltage considering DIBL to obtain the GaAs pHEMT current model considering DIBL.
[0015] Optionally, in step (1), the saturation current at each gate-source voltage is obtained by performing a static IV test on the device under test at 25°C.
[0016] Optionally, in step (1), the numerical expression for the saturation current is as follows:
[0017]
[0018] Among them, I sat q is the saturation current of the device; W is the gate width of the device; q is the electron charge; v sat For saturated electron velocity; A n B n a n b n c n d n e n All of these are fitting parameters.
[0019] Optionally, in step (2), the expression for the nonlinear current is as follows:
[0020]
[0021] Among them, I ds For nonlinear current, I sat V is the saturation current of the device; ds This is the drain-source voltage; E c Critical electric field; l s l d These are the access region lengths for the source and drain, respectively; l g β is the gate length of the device; β is the order of the velocity field.
[0022] Optionally, in step (3), the equivalent thermal resistance of GaAs pHEMT is obtained by performing a pulse IV test on the device under test at 125°C and combining the results of the static IV test.
[0023] Optionally, in step (3), the channel temperature under different biases is obtained based on the equivalent thermal resistance of GaAs pHEMT, as follows:
[0024] T ch =T amb +V ds I ds R theq ;
[0025] Among them, T ch V represents the channel temperature under different biases. ds I is the drain-source voltage; ds It is a nonlinear current; R theq This represents the equivalent thermal resistance of GaAspHEMT.
[0026] Optionally, in step (3), the numerical expression for the critical electric field is as follows:
[0027]
[0028] Among them, E c Critical electric field; B gs T is the gate-source voltage; ch The channel temperatures are denoted by ; a0, a1, b0, b1, and b2 are all fitting parameters.
[0029] Optionally, in step (4), the equivalent gate voltage of DIBL is considered as follows:
[0030] V gseff =V gs +V ds exp(K);
[0031] Among them, V gseff To account for the equivalent gate voltage of DIBL; V gs V is the gate-source voltage; ds is the drain-source voltage; K is the effect fitting parameter.
[0032] Optionally, the effect fitting parameter K is obtained by performing a pulse IV test on the device under test at 25°C.
[0033] As can be seen from the above technical solution, compared with the prior art, this invention proposes a GaAs pHEMT current model calculation method considering DIBL. Through a quasi-physical basis current model based on region partitioning and a physical basis DIBL model based on equivalent threshold voltage, a GaAs pHEMT current model considering the DIBL effect is obtained. Experiments show that the GaAs pHEMT current model considering DIBL proposed in this invention can effectively improve the accuracy of the current model characterization and overcome the problem of insufficient accuracy caused by the incomplete consideration of second-order effects in existing GaAs pHEMT current models. Attached Figure Description
[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0035] Figure 1 This is a schematic diagram of the method flow of the present invention.
[0036] Figure 2 This is a schematic diagram of the measured and simulated saturation current curve of the present invention.
[0037] Figure 3 This is a schematic diagram of the measured and simulated critical electric field curve of the present invention.
[0038] Figure 4 This is a schematic diagram of the measured and simulated pulse IV curve of the present invention.
[0039] Figure 5 This is a schematic diagram of the measured and simulated DC IV curve of the present invention. Detailed Implementation
[0040] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0041] Example 1:
[0042] Embodiment 1 of this invention discloses a method for calculating the pHEMT current model of GaAs considering DIBL, such as... Figure 1 As shown, it includes:
[0043] Step (1): Perform static IV testing (V) on the device under test at 25℃ (room temperature). gs =0~1.2V, V ds =0~6V), obtain the gate-source voltage V for each voltage level. gs The saturation current under each gate-source voltage is I. sat (each gate-source voltage V) gs Different drain-source voltages V ds The corresponding drain-source current I ds The maximum value I sat The least squares method was used for fitting, and the fitting result was as follows: Figure 2 As shown, the numerical expression for the saturation current is obtained as follows:
[0044]
[0045] Among them, I sat q is the saturation current of the device; W is the gate width of the device; q is the electron charge; v sat For saturated electron velocity; A n B n a n b n c n d n e n All of these are fitting parameters.
[0046] Step (2): Set the saturation current I sat Substituting the numerical expression into the nonlinear current I ds In the expression, and based on the drain-source current I at each bias point ds Obtain the critical electric field E corresponding to each bias point. c ;
[0047] A region partitioning model is adopted, dividing the device channel into several regions based on the electric field distribution or carrier distribution. Within each region, the IV relationship is described using corresponding physical equations according to the main operating principle of the device in that region. Then, based on the continuity of physical quantities such as voltage and current at the boundaries between regions, the equations for all regions are solved simultaneously to obtain the IV characteristics of the device, resulting in the nonlinear current expression I. ds ,as follows:
[0048]
[0049] Among them, I ds For nonlinear current, I sat The saturation current of the device can be expressed as I. sat =Wqn s (V gs )v sat Where W is the gate width of the device, n s (V gs ) represents the electron surface density; V ds This is the drain-source voltage; E c Critical electric field; l s l d These are the access region lengths for the source and drain, respectively; l g β is the gate length of the device; β is the order of the velocity field, which adopts the second-order field-velocity relation, i.e., β = 2.
[0050] Step (3): Perform pulse IV test (static bias point V) on the device under test at 125℃ (high temperature). gsq =0V, V dsq =0V), and combined with the results of static IV testing, the equivalent thermal resistance R of GaAspHEMT is obtained. theq According to the equivalent thermal resistance R of GaAs pHEMT theq Obtain the channel temperature T under different biases ch And combined with the critical electric field E c The least squares method was used for fitting, and the fitting result was as follows: Figure 3 As shown, the critical electric field E is obtained. c Numerical expressions;
[0051] Channel temperature T under different biases ch ,as follows:
[0052] T ch =T amb +V ds I ds R theq ;
[0053] Among them, T chV represents the channel temperature under different biases. ds I is the drain-source voltage; ds It is a nonlinear current; R theq This represents the equivalent thermal resistance of GaAspHEMT.
[0054] Critical electric field E c The numerical expression for it is as follows:
[0055]
[0056] Among them, E c Critical electric field; V gs T is the gate-source voltage; ch The channel temperatures are denoted by ; a0, a1, b0, b1, and b2 are all fitting parameters.
[0057] Step (4): Set the saturation current I sat Numerical expression and critical electric field E c Substituting the numerical expression into the nonlinear current expression I ds In, considering the equivalent gate voltage V of DIBL gseff Replace gate-source voltage V gs Thus, the GaAspHEMT current model considering DIBL is obtained.
[0058] By embedding the DIBL into the current model using the equivalent threshold voltage method, the equivalent gate voltage V considering the DIBL is obtained. gseff ,as follows:
[0059] V gseff =V gs +V ds exp(K);
[0060] Among them, V gseff To account for the equivalent gate voltage of DIBL; V gs V is the gate-source voltage; ds The drain-source voltage is given by [value]; K is the effect fitting parameter, which is obtained by performing a pulse IV test on the device under test at 25℃ (room temperature) (static bias point V). gsq =0V, V dsq =0V) was obtained, and the fitting effect is as follows Figure 4 As shown.
[0061] Taking a multi-gate finger GaAs pHEMT current model with a gate length of 0.25 μm and a gate width of 10 × 125 μm as an example, the above calculation method for the GaAs pHEMT current model considering DIBL is used to obtain the GaAs pHEMT current model considering DIBL. The fitting effect is as follows: Figure 5 As shown, and Figure 5The simulation results without considering the DIBL effect are also marked. In comparison, the model proposed in this invention improves the characterization accuracy by 4.76%.
[0062] This invention discloses a method for calculating the GaAs pHEMT current model considering the second-order effect (DIBL). By using a quasi-physical basis current model based on region partitioning and a physical basis DIBL model based on the equivalent threshold voltage, a GaAs pHEMT current model considering the DIBL effect is obtained. Experiments show that the GaAs pHEMT current model considering DIBL proposed in this invention can effectively improve the accuracy of the current model characterization and overcome the problem of insufficient accuracy caused by the incomplete consideration of second-order effects in existing GaAs pHEMT current models.
[0063] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.
[0064] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A method for calculating the pHEMT current model of GaAs considering DIBL, characterized in that, include: Step (1): Perform least squares fitting based on the saturation current under each gate-source voltage to obtain the numerical expression of the saturation current; Step (2): Substitute the numerical expression of the saturation current into the nonlinear current expression, and obtain the critical electric field corresponding to each bias point based on the drain-source current at each bias point. Step (3): Based on the equivalent thermal resistance of GaAs pHEMT, obtain the channel temperature under different biases, and combine it with the critical electric field to perform least squares fitting to obtain the numerical expression of the critical electric field. Step (4): Substitute the numerical expression of the saturation current and the numerical expression of the critical electric field into the nonlinear current expression, and replace the gate-source voltage with the equivalent gate voltage considering DIBL to obtain the GaAspHEMT current model considering DIBL. In step (2), the expression for the nonlinear current is as follows: in, It is a nonlinear current. This is the saturation current of the device; This is the drain-source voltage; The critical electric field; , These are the access region lengths for the source and drain, respectively; The gate length of the device; Let be the order of the velocity field.
2. The method for calculating the GaAs pHEMT current model considering DIBL according to claim 1, characterized in that, In step (1), the saturation current under each gate-source voltage is obtained by performing a static IV test on the device under test at 25°C.
3. The method for calculating the GaAs pHEMT current model considering DIBL according to claim 1, characterized in that, In step (1), the numerical expression for the saturation current is as follows: in, This is the saturation current of the device; This refers to the gate width of the device. It represents the electron charge. This represents the saturated electron velocity. , , , , , , All are fitted parameters; This is the gate-source voltage.
4. The method for calculating the GaAs pHEMT current model considering DIBL according to claim 2, characterized in that, In step (3), the equivalent thermal resistance of the GaAs pHEMT is obtained by performing a pulse IV test on the device under test at 125°C and combining the results of the static IV test.
5. The method for calculating the GaAs pHEMT current model considering DIBL according to claim 1, characterized in that, In step (3), the channel temperature under different biases is obtained based on the equivalent thermal resistance of GaAs pHEMT, as follows: in, Channel temperature under different biases; Room temperature; This is the drain-source voltage; It is a nonlinear current; This represents the equivalent thermal resistance of the GaAs pHEMT.
6. The method for calculating the GaAs pHEMT current model considering DIBL according to claim 1, characterized in that, In step (3), the numerical expression for the critical electric field is as follows: in, The critical electric field; This is the gate-source voltage; Channel temperature under different biases; , , , , All of these are fitting parameters.
7. The method for calculating the GaAs pHEMT current model considering DIBL according to claim 1, characterized in that, In step (4), the equivalent gate voltage of DIBL is considered as follows: in, To account for the equivalent gate voltage of DIBL; This is the gate-source voltage; This is the drain-source voltage; These are the parameters for fitting the effect.
8. The method for calculating the GaAs pHEMT current model considering DIBL according to claim 7, characterized in that, The effect fitting parameters This was obtained by performing a pulse IV test on the device under test at 25°C.