Drive circuit, drive module and display device

Abstract

This invention provides a driving circuit, a driving module, and a display device. The driving circuit is included in the driving module and includes a first input circuit and a second input circuit. The first input circuit controls the potential of a first node under the control of a first control signal; the second input circuit controls the potential of the first node under the control of a second control signal. The first input circuit includes a first transistor, and the second input circuit includes a second transistor. The gate and first electrode of the first transistor are electrically connected to a first control terminal, and the second electrode of the first transistor is electrically connected to the first node. The gate and first electrode of the second transistor are both electrically connected to a second control terminal, and the second electrode of the second transistor is electrically connected to the first node. This invention can improve the horizontal stripe defect phenomenon while achieving bidirectional scanning.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a driving circuit, a driving module, and a display device. Background Technology

[0002] In the relevant driving circuit, the first input circuit is electrically connected to the first control terminal, the first scan voltage terminal, and the first node, respectively, and is used to write the first scan voltage provided by the first scan voltage terminal into the first node under the control of the first control signal provided by the first control terminal; the second input circuit is electrically connected to the second control terminal, the second scan voltage terminal, and the first node, respectively, and is used to write the second scan voltage provided by the second scan voltage terminal into the first node under the control of the second control signal provided by the second control terminal. When the relevant driving circuits are operating, in forward scanning mode, the first scanning voltage terminal provides a high-voltage signal. The transistors included in the first input circuit are in a biased state for a long time. After high-temperature reliability testing, the threshold voltage of the transistors in the first input circuit experiences severe drift. At this time, input signal false rises caused by noise, coupling, etc., may cause the transistor to turn on erroneously, resulting in a potential rise at the first node. In the non-operating row driving circuit, the potential of the second node remains high. The transistor whose gate is electrically connected to the second node and is used for noise reduction at the first node is in a forward biased state. The threshold voltage of this transistor experiences positive drift, reducing its noise reduction capability at the first node and failing to eliminate the false potential rise at the first node. This causes the output transistor to turn on erroneously, resulting in erroneous output from the driving circuit and causing horizontal stripe defects. At the same time, as the input signal of the next-level driving circuit, the erroneous output of this stage of driving circuit will be propagated and continuously aggravated, so there will be more severe horizontal stripes at the bottom of the display screen than at the top. In reverse scanning mode, the state of the transistors included in the second input circuit is the same as that of the transistors included in the first input circuit in forward scanning mode. Changing the scanning direction cannot eliminate the horizontal stripe defects. Summary of the Invention

[0003] The driving circuit described in this embodiment of the invention is included in a driving module, and the driving circuit includes a first input circuit and a second input circuit;

[0004] The first input circuit is electrically connected to the first control terminal and the first node respectively, and is used to control the potential of the first node under the control of the first control signal provided by the first control terminal;

[0005] The second input circuit is electrically connected to the second control terminal and the first node respectively, and is used to control the potential of the first node under the control of the second control signal provided by the second control terminal;

[0006] The first input circuit includes a first transistor, and the second input circuit includes a second transistor;

[0007] The gate and the first terminal of the first transistor are both electrically connected to the first control terminal, and the second terminal of the first transistor is electrically connected to the first node.

[0008] The gate and the first terminal of the second transistor are both electrically connected to the second control terminal, and the second terminal of the second transistor is electrically connected to the first node.

[0009] Optionally, the first control terminal is electrically connected to the drive signal output terminal of the adjacent first n-stage drive circuit; the second control terminal is electrically connected to the drive signal output terminal of the adjacent last m-stage drive circuit.

[0010] Both n and m are positive integers.

[0011] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a first reset circuit;

[0012] The first reset circuit is electrically connected to the reset control clock signal terminal, the first voltage terminal, and the first node, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the reset control clock signal provided by the reset control clock signal terminal.

[0013] Optionally, when the drive module performs a forward scan, the first input circuit is used to control the potential of the first node under the control of a first control signal provided by the first control terminal during the input phase; the first reset circuit is used to control the connection between the first node and the first voltage terminal under the control of the reset control signal during the reset phase after the input phase, so as to reset the potential of the first node.

[0014] Optionally, when the drive module performs a reverse scan, the second input circuit is used to control the potential of the first node under the control of the second control signal provided by the second control terminal during the input phase; the first reset circuit is used to control the connection between the first node and the first voltage terminal under the control of the reset control clock signal during the reset phase set after the input phase, so as to reset the potential of the first node.

[0015] Optionally, the effective level time period of the first control signal does not overlap with the effective level time period of the reset control clock signal;

[0016] The effective level time period of the second control signal does not overlap with the effective level time period of the reset control clock signal.

[0017] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a second reset circuit and a third reset circuit;

[0018] The third reset circuit is electrically connected to the first reset terminal, the first voltage terminal, and the first node, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the first reset signal provided by the first reset terminal;

[0019] The second reset circuit is electrically connected to the second reset terminal, the first voltage terminal, and the first node, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the second reset signal provided by the second reset terminal.

[0020] Optionally, the second reset terminal is electrically connected to the drive signal output terminal of the adjacent subsequent a-stage drive circuit, and the first reset terminal is electrically connected to the drive signal output terminal of the adjacent preceding b-stage drive circuit.

[0021] Both a and b are positive integers.

[0022] Optionally, the effective level time period of the first reset signal does not overlap with the effective level time period of the first control signal;

[0023] The effective level time period of the first reset signal does not overlap with the effective level time period of the second control signal;

[0024] The effective time period of the second reset signal does not overlap with the effective time period of the first control signal;

[0025] The effective time period of the second reset signal does not overlap with the effective time period of the second control signal.

[0026] Optionally, the first reset circuit includes a third transistor;

[0027] The gate of the third transistor is electrically connected to the reset control clock signal terminal, the first terminal of the third transistor is electrically connected to the first voltage terminal, and the second terminal of the third transistor is electrically connected to the first node.

[0028] Optionally, the second reset circuit includes a fourth transistor, and the third reset circuit includes a fifth transistor;

[0029] The gate of the fourth transistor is electrically connected to the second reset terminal, the first terminal of the fourth transistor is electrically connected to the first voltage terminal, and the second terminal of the fourth transistor is electrically connected to the first node.

[0030] The gate of the fifth transistor is electrically connected to the first reset terminal, the first terminal of the fifth transistor is electrically connected to the first voltage terminal, and the second terminal of the fifth transistor is electrically connected to the first node.

[0031] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a first node control circuit, a second node control circuit, an output circuit, and an energy storage circuit;

[0032] The first node control circuit is electrically connected to the second node, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node;

[0033] The second node control circuit is electrically connected to the second voltage terminal, the first node, the second node, and the first voltage terminal, respectively, and is used to control the potential of the second node under the control of the second voltage signal provided by the second voltage terminal and the potential of the first node;

[0034] The energy storage circuit is electrically connected to the first node and the drive signal output terminal respectively, and is used to store electrical energy.

[0035] The output circuit is electrically connected to the first node, the second node, the output clock signal terminal, the drive signal output terminal, and the first voltage terminal, respectively. It is used to control the connection between the output clock signal terminal and the drive signal output terminal under the control of the potential of the first node, and to control the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the second node.

[0036] Optionally, the driving circuit described in at least one embodiment of the present invention further includes a first node reset circuit and an output reset circuit;

[0037] The first node reset circuit is electrically connected to the frame reset terminal, the first node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal.

[0038] The output reset circuit is electrically connected to the frame reset terminal, the drive signal output terminal, and the first voltage terminal, respectively, and is used to control the connection between the drive signal output terminal and the first voltage terminal under the control of the frame reset signal.

[0039] Optionally, the first node control circuit includes a sixth transistor, the second node control circuit includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; the output circuit includes an eleventh transistor and a twelfth transistor, and the energy storage circuit includes a storage capacitor.

[0040] The gate of the sixth transistor is electrically connected to the second node, the first terminal of the sixth transistor is electrically connected to the first node, and the second terminal of the sixth transistor is electrically connected to the first voltage terminal.

[0041] The gate and the first terminal of the seventh transistor are both electrically connected to the second voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first terminal of the eighth transistor.

[0042] The gate of the eighth transistor is electrically connected to the first node, and the second terminal of the eighth transistor is electrically connected to the first voltage terminal.

[0043] The gate of the ninth transistor is electrically connected to the second terminal of the seventh transistor, the first terminal of the ninth transistor is electrically connected to the second voltage terminal, and the second terminal of the ninth transistor is electrically connected to the second node.

[0044] The gate of the tenth transistor is electrically connected to the first node, the first terminal of the tenth transistor is electrically connected to the second node, and the second terminal of the tenth transistor is electrically connected to the first voltage terminal.

[0045] The gate of the eleventh transistor is electrically connected to the first node, the first terminal of the eleventh transistor is electrically connected to the output clock signal terminal, and the second terminal of the eleventh transistor is electrically connected to the drive signal output terminal.

[0046] The gate of the twelfth transistor is electrically connected to the second node, the first terminal of the twelfth transistor is electrically connected to the drive signal output terminal, and the second terminal of the twelfth transistor is electrically connected to the first voltage terminal.

[0047] The first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the drive signal output terminal.

[0048] The first node reset circuit includes a thirteenth transistor, and the output reset circuit includes a fourteenth transistor;

[0049] The gate of the thirteenth transistor is electrically connected to the frame reset terminal, the first terminal of the thirteenth transistor is electrically connected to the first node, and the second terminal of the thirteenth transistor is electrically connected to the first voltage terminal.

[0050] The gate of the fourteenth transistor is electrically connected to the frame reset terminal, the first terminal of the fourteenth transistor is electrically connected to the drive signal output terminal, and the second terminal of the fourteenth transistor is electrically connected to the first voltage terminal.

[0051] The driving module described in this embodiment of the invention includes multiple stages of the aforementioned driving circuits.

[0052] The display device described in this embodiment of the invention includes the driving module described above. Attached Figure Description

[0053] Figure 1This is a circuit diagram of the driving circuit according to at least one embodiment of the present invention;

[0054] Figure 2 This is a circuit diagram of the driving circuit according to at least one embodiment of the present invention;

[0055] Figure 3 This is a circuit diagram of the driving circuit according to at least one embodiment of the present invention;

[0056] Figure 4 This is a circuit diagram of the driving circuit according to at least one embodiment of the present invention;

[0057] Figure 5 This is a circuit diagram of the driving circuit according to at least one embodiment of the present invention;

[0058] Figure 6 This is a circuit diagram of the driving circuit according to at least one embodiment of the present invention;

[0059] Figure 7 It includes multiple levels Figure 6 The waveform of the drive signal output by the drive circuit in row 182 after a reliability test of the drive module of at least one embodiment of the drive circuit shown.

[0060] Figure 8 This is a structural diagram of the drive module according to at least one embodiment of the present invention;

[0061] Figure 9 yes Figure 8 The waveforms of the drive signals provided by G1, G3, and G5, as well as the clock signal provided by CLK7, are shown in the diagram.

[0062] Figure 10 It is a waveform diagram of the clock signals provided by each clock signal line;

[0063] Figure 11 This is a structural diagram of the drive module according to at least one embodiment of the present invention;

[0064] Figure 12 yes Figure 11 Waveform diagrams of the drive signals provided by G1, G3, G5, G7, CLK9, and G11;

[0065] Figure 13 It is a waveform diagram of the clock signals provided by each level of clock signal lines;

[0066] Figure 14 This is a circuit diagram of the driving circuit according to at least one embodiment of the present invention;

[0067] Figure 15It includes multiple levels Figure 14 The waveform of the drive signal output by the drive circuit in row 182 after a reliability test of the drive module of at least one embodiment of the drive circuit shown.

[0068] Figure 16 This is a structural diagram of the drive module according to at least one embodiment of the present invention;

[0069] Figure 17 yes Figure 16 Waveforms of the drive signals output by G1, G3, G5, G7, and G9.

[0070] Figure 18 yes Figure 16 The waveform diagram of the clock signals provided by the clock signal lines at each stage. Detailed Implementation

[0071] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0072] In all embodiments of this invention, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In these embodiments, to distinguish between the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal, and the other as the second terminal.

[0073] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0074] The driving circuit described in this embodiment of the invention is included in a driving module, and the driving circuit includes a first input circuit and a second input circuit;

[0075] The first input circuit is electrically connected to the first control terminal and the first node respectively, and is used to control the potential of the first node under the control of the first control signal provided by the first control terminal;

[0076] The second input circuit is electrically connected to the second control terminal and the first node respectively, and is used to control the potential of the first node under the control of the second control signal provided by the second control terminal;

[0077] The first input circuit includes a first transistor, and the second input circuit includes a second transistor;

[0078] The gate and the first terminal of the first transistor are both electrically connected to the first control terminal, and the second terminal of the first transistor is electrically connected to the first node.

[0079] The gate and the first terminal of the second transistor are both electrically connected to the second control terminal, and the second terminal of the second transistor is electrically connected to the first node.

[0080] In the relevant driving circuit, the first input circuit is electrically connected to the first control terminal, the first scan voltage terminal, and the first node, respectively, and is used to write the first scan voltage provided by the first scan voltage terminal into the first node under the control of the first control signal provided by the first control terminal; the second input circuit is electrically connected to the second control terminal, the second scan voltage terminal, and the first node, respectively, and is used to write the second scan voltage provided by the second scan voltage terminal into the first node under the control of the second control signal provided by the second control terminal. When the relevant driving circuits are operating, in forward scanning mode, the first scanning voltage terminal provides a high-voltage signal. The transistors included in the first input circuit are in a biased state for a long time. After high-temperature reliability testing, the threshold voltage of the transistors in the first input circuit experiences severe drift. At this time, input signal false rises caused by noise, coupling, etc., may cause the transistor to turn on erroneously, resulting in a potential rise at the first node. In the non-operating row driving circuit, the potential of the second node remains high. The transistor whose gate is electrically connected to the second node and is used for noise reduction at the first node is in a forward biased state. The threshold voltage of this transistor experiences positive drift, reducing its noise reduction capability at the first node and failing to eliminate the false potential rise at the first node. This causes the output transistor to turn on erroneously, resulting in erroneous output from the driving circuit and causing horizontal stripe defects. At the same time, as the input signal of the next-level driving circuit, the erroneous output of this stage of driving circuit will be propagated and continuously aggravated, so there will be more severe horizontal stripes at the bottom of the display screen than at the top. In reverse scanning mode, the state of the transistors included in the second input circuit is the same as that of the transistors included in the first input circuit in forward scanning mode. Changing the scanning direction cannot eliminate the horizontal stripe defects.

[0081] To address the above-mentioned problems, in at least one embodiment of the present invention, the gate and first electrode of the first transistor included in the first input circuit are electrically connected to the first control terminal, and the second electrode of the first transistor is electrically connected to the first node; the gate and first electrode of the second transistor included in the second input circuit are electrically connected to the second control terminal, and the second electrode of the second transistor is electrically connected to the first node, so as to improve the threshold voltage drift phenomenon of the first transistor and the threshold voltage drift phenomenon of the second transistor, so as to improve the horizontal stripe defect phenomenon while realizing bidirectional scanning.

[0082] In practical implementation, when the drive module performs a forward scan, the first control terminal is the input terminal;

[0083] When the drive module performs a reverse scan, the second control terminal is the input terminal.

[0084] In at least one embodiment of the present invention, the first control terminal is electrically connected to the drive signal output terminal of the adjacent first n-stage drive circuit; the second control terminal is electrically connected to the drive signal output terminal of the adjacent last m-stage drive circuit.

[0085] Both n and m are positive integers.

[0086] Optionally, n and m can both be equal to 1, but this is not a limitation. In practice, n can also be other positive integers, and m can also be other positive integers.

[0087] like Figure 1 As shown, the driving circuit described in this embodiment of the invention is included in the driving module, and the driving circuit includes a first input circuit 11 and a second input circuit 12.

[0088] The first input circuit 11 is electrically connected to the first control terminal I1 and the first node PU respectively, and is used to control the potential of the first node PU under the control of the first control signal provided by the first control terminal I1;

[0089] The second input circuit 12 is electrically connected to the second control terminal I2 and the first node PU, respectively, and is used to control the potential of the first node PU under the control of the second control signal provided by the second control terminal I2;

[0090] The first input circuit 11 includes a first transistor M1, and the second input circuit 12 includes a second transistor M2;

[0091] The gate and source of the first transistor M1 are both electrically connected to the first control terminal I1, and the drain of the first transistor M1 is electrically connected to the first node PU1.

[0092] The gate and source of the second transistor M2 are both electrically connected to the second control terminal I2, and the drain of the second transistor M2 is electrically connected to the first node PU.

[0093] exist Figure 1 In at least one embodiment of the driving circuit shown, both M1 and M2 are n-type transistors. In specific implementations, M1 and M2 may also be replaced with p-type transistors.

[0094] The driving circuit described in at least one embodiment of the present invention further includes a first reset circuit;

[0095] The first reset circuit is electrically connected to the reset control clock signal terminal, the first voltage terminal, and the first node, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the reset control clock signal provided by the reset control clock signal terminal.

[0096] In a specific implementation, the driving circuit may include a first reset circuit, which resets the potential of the first node under the control of a reset control signal.

[0097] Optionally, the first voltage terminal can be a low voltage terminal, but is not limited thereto.

[0098] like Figure 2 As shown, in Figure 1 Based on at least one embodiment of the driving circuit shown, the driving circuit of at least one embodiment of the present invention further includes a first reset circuit 21;

[0099] The first reset circuit 21 is electrically connected to the reset control clock signal terminal CLKB, the first voltage terminal V1 and the first node PU respectively, and is used to control the connection between the first node PU and the first voltage terminal V1 under the control of the reset control clock signal provided by the reset control clock signal terminal CLKB.

[0100] This invention Figure 2 In at least one embodiment of the driving circuit shown, during operation, in forward scanning mode, M1 is turned on, pulling up the potential of the first node PU, and the driving circuit starts to work. After the signal output is completed, the voltage of the reset control clock signal provided by CLKB is turned on, and the transistors included in the first reset circuit 21 are turned on to pull down the potential of the first node PU, thereby resetting the driving circuit.

[0101] In reverse scan mode, M2 is turned on, pulling the potential of the first node PU high, and the driving circuit starts to work. After the signal output is completed, the voltage of the reset control clock signal provided by CLKB is high, and the transistors included in the first reset circuit 21 are turned on to pull the potential of the first node PU low, thus resetting the driving circuit.

[0102] In at least one embodiment of the present invention, when the driving module performs a forward scan, the first input circuit is used to control the potential of the first node under the control of a first control signal provided by the first control terminal during the input phase; the first reset circuit is used to control the connection between the first node and the first voltage terminal under the control of the reset control signal during a reset phase set after the input phase, so as to reset the potential of the first node.

[0103] In at least one embodiment of the present invention, when the driving module performs reverse scanning, the second input circuit is used to control the potential of the first node under the control of the second control signal provided by the second control terminal during the input phase; the first reset circuit is used to control the connection between the first node and the first voltage terminal under the control of the reset control clock signal during the reset phase set after the input phase, so as to reset the potential of the first node.

[0104] In at least one embodiment of the present invention, the effective level time period of the first control signal does not overlap with the effective level time period of the reset control clock signal, so that the first transistor and the transistor included in the first reset circuit will not be turned on at the same time and a short circuit will not occur.

[0105] The effective level time period of the second control signal does not overlap with the effective level time period of the reset control clock signal, so that the second transistor and the transistor included in the first reset circuit will not be turned on at the same time, and a short circuit will not occur.

[0106] In a specific implementation, when the first transistor is an n-type transistor, the effective level time period of the first control signal is the time period during which the potential of the first control signal is high voltage;

[0107] When the first transistor is a p-type transistor, the effective level time period of the first control signal is: the time period during which the potential of the first control signal is low.

[0108] When the second transistor is an n-type transistor, the effective level time period of the second control signal is: the time period during which the potential of the second control signal is high voltage;

[0109] When the second transistor is a p-type transistor, the effective level time period of the second control signal is: the time period during which the potential of the second control signal is low;

[0110] When the transistor included in the first reset circuit is an n-type transistor, the effective level time period of the reset control clock signal can refer to the time period during which the potential of the reset control clock signal is high.

[0111] When the transistor included in the first reset circuit is a p-type transistor, the effective level time period of the reset control clock signal can refer to the time period during which the potential of the reset control clock signal is low.

[0112] The driving circuit described in at least one embodiment of the present invention further includes a second reset circuit and a third reset circuit;

[0113] The third reset circuit is electrically connected to the first reset terminal, the first voltage terminal, and the first node, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the first reset signal provided by the first reset terminal;

[0114] The second reset circuit is electrically connected to the second reset terminal, the first voltage terminal, and the first node, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the second reset signal provided by the second reset terminal.

[0115] In a specific implementation, the driving circuit may further include a second reset circuit and a third reset circuit. During forward scanning, the second reset circuit resets the potential of the first node; during reverse scanning, the third reset circuit resets the potential of the first node.

[0116] like Figure 3 As shown, in Figure 1 Based on at least one embodiment of the driving circuit shown, the driving circuit of at least one embodiment of the present invention further includes a second reset circuit 31 and a third reset circuit 32;

[0117] The third reset circuit 32 is electrically connected to the first reset terminal R1, the first voltage terminal V1 and the first node PU respectively, and is used to control the connection between the first node PU and the first voltage terminal V1 under the control of the first reset signal provided by the first reset terminal R1.

[0118] The second reset circuit 31 is electrically connected to the second reset terminal R2, the first voltage terminal V1 and the first node PU respectively, and is used to control the connection between the first node PU and the first voltage terminal V1 under the control of the second reset signal provided by the second reset terminal R2.

[0119] This invention Figure 3 At least one embodiment of the driving circuit shown, when in operation,

[0120] In forward scanning mode, M1 is turned on, which raises the potential of the first node PU. The driving circuit starts to work. After the signal output is completed, the voltage of the second reset signal provided by the second reset terminal R2 is high. The transistor included in the second reset circuit 31 is turned on to pull the potential of the first node PU low, thus resetting the driving circuit.

[0121] In reverse scan mode, M2 is turned on, raising the potential of the first node PU. The driving circuit starts working. After the signal output is completed, the first reset signal provided by the first reset terminal R1 is at a high position. The transistors included in the third reset circuit 32 are turned on to pull the potential of the first node PU low, thus resetting the driving circuit.

[0122] Optionally, the second reset terminal is electrically connected to the drive signal output terminal of the adjacent subsequent a-stage drive circuit, and the first reset terminal is electrically connected to the drive signal output terminal of the adjacent preceding b-stage drive circuit.

[0123] Both a and b are positive integers.

[0124] In at least one embodiment of the present invention, a and b can both be equal to 3, but are not limited thereto. In specific implementations, a can be other positive integers, and b can be other positive integers.

[0125] In at least one embodiment of the present invention, the effective level time period of the first reset signal does not overlap with the effective level time period of the first control signal, so that the transistors included in the third reset circuit and the first transistor will not be turned on at the same time, thus avoiding a short circuit.

[0126] The effective level time period of the first reset signal does not overlap with the effective level time period of the second control signal, so that the transistors and the second transistor included in the third reset circuit will not be turned on at the same time, thus avoiding a short circuit.

[0127] The effective level time period of the second reset signal does not overlap with the effective level time period of the first control signal, so that the transistors included in the second reset circuit and the first transistor will not be turned on at the same time, thus avoiding a short circuit.

[0128] The effective level time period of the second reset signal does not overlap with the effective level time period of the second control signal, so that the transistors and the second transistor included in the second reset circuit will not be turned on at the same time, thus avoiding a short circuit.

[0129] Optionally, the first reset circuit includes a third transistor;

[0130] The gate of the third transistor is electrically connected to the reset control clock signal terminal, the first terminal of the third transistor is electrically connected to the first voltage terminal, and the second terminal of the third transistor is electrically connected to the first node.

[0131] Optionally, the second reset circuit includes a fourth transistor, and the third reset circuit includes a fifth transistor;

[0132] The gate of the fourth transistor is electrically connected to the second reset terminal, the first terminal of the fourth transistor is electrically connected to the first voltage terminal, and the second terminal of the fourth transistor is electrically connected to the first node.

[0133] The gate of the fifth transistor is electrically connected to the first reset terminal, the first terminal of the fifth transistor is electrically connected to the first voltage terminal, and the second terminal of the fifth transistor is electrically connected to the first node.

[0134] The driving circuit described in at least one embodiment of the present invention further includes a first node control circuit, a second node control circuit, an output circuit, and an energy storage circuit;

[0135] The first node control circuit is electrically connected to the second node, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node;

[0136] The second node control circuit is electrically connected to the second voltage terminal, the first node, the second node, and the first voltage terminal, respectively, and is used to control the potential of the second node under the control of the second voltage signal provided by the second voltage terminal and the potential of the first node;

[0137] The energy storage circuit is electrically connected to the first node and the drive signal output terminal respectively, and is used to store electrical energy.

[0138] The output circuit is electrically connected to the first node, the second node, the output clock signal terminal, the drive signal output terminal, and the first voltage terminal, respectively. It is used to control the connection between the output clock signal terminal and the drive signal output terminal under the control of the potential of the first node, and to control the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the second node.

[0139] In at least one embodiment of the present invention, the driving circuit may further include a first node control circuit, a second node control circuit, an output circuit, and an energy storage circuit; the first node control circuit controls the potential of the first node under the control of the potential of the second node; the second node control circuit controls the potential of the second node under the control of the second voltage signal and the potential of the first node; the output circuit controls the driving signal output terminal to provide a driving signal under the control of the potential of the first node and the potential of the second node.

[0140] Optionally, the second voltage terminal can be a high voltage terminal, but is not limited thereto.

[0141] The driving circuit described in at least one embodiment of the present invention further includes a first node reset circuit and an output reset circuit;

[0142] The first node reset circuit is electrically connected to the frame reset terminal, the first node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal.

[0143] The output reset circuit is electrically connected to the frame reset terminal, the drive signal output terminal, and the first voltage terminal, respectively, and is used to control the connection between the drive signal output terminal and the first voltage terminal under the control of the frame reset signal.

[0144] In a specific implementation, the driving circuit may further include a first node reset circuit and an output reset circuit. The first node reset circuit resets the first node under the control of the frame reset signal, and the output reset circuit resets the driving signal provided by the driving signal output terminal under the control of the frame reset signal.

[0145] In at least one embodiment of the present invention, between two display frames, the frame reset terminal can provide an effective voltage signal, and the first node reset circuit, under the control of the frame reset signal, controls the connection between the first node and the first voltage terminal; the output reset circuit, under the control of the frame reset signal, controls the connection between the drive signal output terminal and the first voltage terminal.

[0146] like Figure 4 As shown, in Figure 2 Based on at least one embodiment of the driving circuit shown, the driving circuit of at least one embodiment of the present invention may further include a first node control circuit 41, a second node control circuit 42, an output circuit 43, an energy storage circuit 44, a first node reset circuit 45, and an output reset circuit 46.

[0147] The first node control circuit 41 is electrically connected to the second node PD, the first node PU and the first voltage terminal V1 respectively, and is used to control the connection between the first node PU and the first voltage terminal V1 under the control of the potential of the second node PD.

[0148] The second node control circuit 42 is electrically connected to the second voltage terminal V2, the first node PU, the second node PD and the first voltage terminal V1 respectively, and is used to control the potential of the second node PD under the control of the second voltage signal provided by the second voltage terminal V2 and the potential of the first node PU.

[0149] The energy storage circuit 44 is electrically connected to the first node PU and the drive signal output terminal OT respectively, and is used to store electrical energy.

[0150] The output circuit 43 is electrically connected to the first node PU, the second node PD, the output clock signal terminal CLKA, the drive signal output terminal OT, and the first voltage terminal V1, respectively. It is used to control the connection between the output clock signal terminal CLKA and the drive signal output terminal OT under the control of the potential of the first node PU, and to control the connection between the drive signal output terminal OT and the first voltage terminal V1 under the control of the potential of the second node PD.

[0151] The first node reset circuit 45 is electrically connected to the frame reset terminal STV0, the first node PU and the first voltage terminal V1 respectively, and is used to control the connection between the first node PU and the first voltage terminal V1 under the control of the frame reset signal provided by the frame reset terminal STV0.

[0152] The output reset circuit 46 is electrically connected to the frame reset terminal STV0, the drive signal output terminal OT, and the first voltage terminal V1, respectively, and is used to control the connection between the drive signal output terminal OT and the first voltage terminal V1 under the control of the frame reset signal.

[0153] like Figure 5 As shown, in Figure 3 Based on at least one embodiment of the driving circuit shown, the driving circuit of at least one embodiment of the present invention may further include a first node control circuit 41, a second node control circuit 42, an output circuit 43, an energy storage circuit 44, a first node reset circuit 45, and an output reset circuit 46.

[0154] The first node control circuit 41 is electrically connected to the second node PD, the first node PU and the first voltage terminal V1 respectively, and is used to control the connection between the first node PU and the first voltage terminal V1 under the control of the potential of the second node PD.

[0155] The second node control circuit 42 is electrically connected to the second voltage terminal V2, the first node PU, the second node PD and the first voltage terminal V1 respectively, and is used to control the potential of the second node PD under the control of the second voltage signal provided by the second voltage terminal V2 and the potential of the first node PU.

[0156] The energy storage circuit 44 is electrically connected to the first node PU and the drive signal output terminal OT respectively, and is used to store electrical energy.

[0157] The output circuit 43 is electrically connected to the first node PU, the second node PD, the output clock signal terminal CLKA, the drive signal output terminal OT, and the first voltage terminal V1, respectively. It is used to control the connection between the output clock signal terminal CLKA and the drive signal output terminal OT under the control of the potential of the first node PU, and to control the connection between the drive signal output terminal OT and the first voltage terminal V1 under the control of the potential of the second node PD.

[0158] The first node reset circuit 45 is electrically connected to the frame reset terminal STV0, the first node PU and the first voltage terminal V1 respectively, and is used to control the connection between the first node PU and the first voltage terminal V1 under the control of the frame reset signal provided by the frame reset terminal STV0.

[0159] The output reset circuit 46 is electrically connected to the frame reset terminal STV0, the drive signal output terminal OT, and the first voltage terminal V1, respectively, and is used to control the connection between the drive signal output terminal OT and the first voltage terminal V1 under the control of the frame reset signal.

[0160] Optionally, the first node control circuit includes a sixth transistor, the second node control circuit includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; the output circuit includes an eleventh transistor and a twelfth transistor, and the energy storage circuit includes a storage capacitor.

[0161] The gate of the sixth transistor is electrically connected to the second node, the first terminal of the sixth transistor is electrically connected to the first node, and the second terminal of the sixth transistor is electrically connected to the first voltage terminal.

[0162] The gate and the first terminal of the seventh transistor are both electrically connected to the second voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first terminal of the eighth transistor.

[0163] The gate of the eighth transistor is electrically connected to the first node, and the second terminal of the eighth transistor is electrically connected to the first voltage terminal.

[0164] The gate of the ninth transistor is electrically connected to the second terminal of the seventh transistor, the first terminal of the ninth transistor is electrically connected to the second voltage terminal, and the second terminal of the ninth transistor is electrically connected to the second node.

[0165] The gate of the tenth transistor is electrically connected to the first node, the first terminal of the tenth transistor is electrically connected to the second node, and the second terminal of the tenth transistor is electrically connected to the first voltage terminal.

[0166] The gate of the eleventh transistor is electrically connected to the first node, the first terminal of the eleventh transistor is electrically connected to the output clock signal terminal, and the second terminal of the eleventh transistor is electrically connected to the drive signal output terminal.

[0167] The gate of the twelfth transistor is electrically connected to the second node, the first terminal of the twelfth transistor is electrically connected to the drive signal output terminal, and the second terminal of the twelfth transistor is electrically connected to the first voltage terminal.

[0168] The first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the drive signal output terminal.

[0169] The first node reset circuit includes a thirteenth transistor, and the output reset circuit includes a fourteenth transistor;

[0170] The gate of the thirteenth transistor is electrically connected to the frame reset terminal, the first terminal of the thirteenth transistor is electrically connected to the first node, and the second terminal of the thirteenth transistor is electrically connected to the first voltage terminal.

[0171] The gate of the fourteenth transistor is electrically connected to the frame reset terminal, the first terminal of the fourteenth transistor is electrically connected to the drive signal output terminal, and the second terminal of the fourteenth transistor is electrically connected to the first voltage terminal.

[0172] like Figure 6 As shown, in Figure 4 Based on at least one embodiment of the driving circuit shown, the first reset circuit includes a third transistor M3;

[0173] The gate of the third transistor M3 is electrically connected to the reset control clock signal terminal CLKB, the source of the third transistor M3 is electrically connected to the low voltage terminal VGL, and the drain of the third transistor M3 is electrically connected to the first node PU.

[0174] The first node control circuit includes a sixth transistor M6, the second node control circuit includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9 and a tenth transistor M10; the output circuit includes an eleventh transistor M11 and a twelfth transistor M12, and the energy storage circuit includes a storage capacitor C.

[0175] The gate of the sixth transistor M6 is electrically connected to the second node PD, the source of the sixth transistor M6 is electrically connected to the first node PU, and the drain of the sixth transistor M6 is electrically connected to the low voltage terminal VGL.

[0176] The gate and source of the seventh transistor M7 are both electrically connected to the high-voltage terminal GCH, and the drain of the seventh transistor M7 is electrically connected to the source of the eighth transistor M8.

[0177] The gate of the eighth transistor M8 is electrically connected to the first node PU, and the drain of the eighth transistor M8 is electrically connected to the low voltage terminal VGL.

[0178] The gate of the ninth transistor M9 is electrically connected to the drain of the seventh transistor M7, the source of the ninth transistor M9 is electrically connected to the high voltage terminal GCH, and the drain of the ninth transistor M9 is electrically connected to the second node PD.

[0179] The gate of the tenth transistor M10 is electrically connected to the first node PU, the source of the tenth transistor M10 is electrically connected to the second node PD, and the drain of the tenth transistor M10 is electrically connected to the low voltage terminal VGL.

[0180] The gate of the eleventh transistor M11 is electrically connected to the first node PU, the source of the eleventh transistor M11 is electrically connected to the output clock signal terminal CLKA, and the drain of the eleventh transistor M11 is electrically connected to the drive signal output terminal OT.

[0181] The gate of the twelfth transistor M12 is electrically connected to the second node PD, the source of the twelfth transistor M12 is electrically connected to the drive signal output terminal OT, and the drain of the twelfth transistor M12 is electrically connected to the low voltage terminal VGL.

[0182] The first end of the storage capacitor C is electrically connected to the first node PU, and the second end of the storage capacitor C is electrically connected to the drive signal output terminal OT.

[0183] The first node reset circuit includes a thirteenth transistor M13, and the output reset circuit includes a fourteenth transistor M14;

[0184] The gate of the thirteenth transistor M13 is electrically connected to the frame reset terminal STV0, the source of the thirteenth transistor M13 is electrically connected to the first node PU, and the drain of the thirteenth transistor M13 is electrically connected to the low voltage terminal VGL.

[0185] The gate of the fourteenth transistor M14 is electrically connected to the frame reset terminal STV0, the source of the fourteenth transistor M14 is electrically connected to the drive signal output terminal OT, and the drain of the fourteenth transistor M14 is electrically connected to the low voltage terminal VGL.

[0186] exist Figure 6 In at least one embodiment of the driving circuit shown, all transistors are n-type transistors, but this is not a limitation.

[0187] exist Figure 6 In at least one embodiment of the driving circuit shown, the channel width-to-length ratio of M3 may be the same as that of M2, but is not limited thereto.

[0188] Figure 7 It includes multiple levels Figure 6 The waveform of the drive signal output by the drive circuit in row 182 is shown after a reliability test of the drive module of at least one embodiment of the drive circuit shown.

[0189] like Figure 7 As shown, the waveform of the drive signal is relatively flat and outputs without errors, proving that... Figure 6 At least one embodiment of the driving circuit shown can be adapted to high-temperature reliability environments.

[0190] In a specific implementation, the display device may include a first driving module disposed on a first side of the display area and a second driving module disposed on a second side of the display area. The driving circuits of each stage in the first driving module are electrically connected to odd-numbered row gate lines, and the driving circuits of each stage in the second driving module are electrically connected to even-numbered row gate lines. The first side and the second side are opposite sides; for example, the first side can be the left side and the second side can be the right side, but this is not a limitation. The driving circuits of each stage in the first driving module may be electrically connected to odd-numbered clock signal lines, and the driving circuits of each stage in the second driving module may be electrically connected to even-numbered clock signal lines.

[0191] like Figure 8 As shown, S1 is the first-stage driving circuit, S2 is the second-stage driving circuit, S3 is the third-stage driving circuit, and S4 is the fourth-stage driving circuit.

[0192] The output clock signal terminal of the first-stage driver circuit S1 is electrically connected to the first-stage clock signal line CLK1, and the reset control clock signal terminal of the first-stage driver circuit S1 is electrically connected to the fifth-stage clock signal line CLK5; the second control terminal of the first-stage driver circuit S1 is electrically connected to the drive signal output terminal of the second-stage driver circuit S2, and the drive signal output terminal of the first-stage driver circuit S1 is electrically connected to the first row gate line G1.

[0193] The output clock signal terminal of the second-stage driver circuit S2 is electrically connected to the third-stage clock signal line CLK3. The first control terminal of the second-stage driver circuit S2 is electrically connected to the drive signal output terminal of the first-stage driver circuit S1. The reset control clock signal terminal of the second-stage driver circuit S2 is electrically connected to the seventh-stage clock signal line CLK7. The second control terminal of the second-stage driver circuit S2 is electrically connected to the drive signal output terminal of the third-stage driver circuit S3. The drive signal output terminal of the second-stage driver circuit S2 is electrically connected to the third row gate line G3.

[0194] The output clock signal terminal of the third-stage driver circuit S3 is electrically connected to the fifth-stage clock signal line CLK5. The first control terminal of the third-stage driver circuit S3 is electrically connected to the drive signal output terminal of the second-stage driver circuit S2. The reset control clock signal terminal of the third-stage driver circuit S3 is electrically connected to the first-stage clock signal line CLK1. The second control terminal of the third-stage driver circuit S3 is electrically connected to the drive signal output terminal of the fourth-stage driver circuit S4. The drive signal output terminal of the third-stage driver circuit S3 is electrically connected to the fifth row gate line G5.

[0195] The output clock signal terminal of the fourth-stage driver circuit S4 is electrically connected to the seventh-stage clock signal line CLK7. The first control terminal of the fourth-stage driver circuit S4 is electrically connected to the drive signal output terminal of the third-stage driver circuit S3. The reset control clock signal terminal of the fourth-stage driver circuit S4 is electrically connected to the third-stage clock signal line CLK3. The drive signal output terminal of the fourth-stage driver circuit S4 is electrically connected to the seventh row gate line G7.

[0196] exist Figure 8 In the diagram, I1 is the first control terminal, I2 is the second control terminal, CLKA is the output clock signal terminal, CLKB is the reset control clock signal terminal, and OT is the drive signal output terminal.

[0197] Figure 9 yes Figure 8 The waveforms of the drive signals provided by G1, G3, and G5, as well as the clock signal provided by CLK7, are shown in the diagram.

[0198] In specific implementation, the first control terminal of S2 is electrically connected to G1, the drive signal output terminal of S2 is electrically connected to G3, the second control terminal of S2 is electrically connected to G5, and the reset control clock signal terminal of S2 is electrically connected to CLK7. The clock signal provided by CLK7 is used to reset the first node in S2.

[0199] In at least one embodiment of the present invention, the first driving module in the display device can be electrically connected to the odd-numbered clock signal lines among the eight clock signal lines, and the second driving module in the display device can be electrically connected to the even-numbered clock signal lines among the eight clock signal lines. In this case, the duty cycle of the clock signal provided by each clock signal line needs to be less than 25% to avoid the effective level time period of the reset signal overlapping with the effective level time period of the first control signal, and to avoid the effective level time period of the reset signal overlapping with the effective level time period of the second control signal, and to avoid M1 and M3 being turned on simultaneously, and to avoid M2 and M3 being turned on simultaneously.

[0200] In practical implementation, if M1 and M3 in the second-stage drive circuit S2 are turned on at the same time, the first control signal provided by I1 will be pulled, affecting the normal operation of the first-stage drive circuit S1. If M2 and M3 are turned on at the same time, the second control signal provided by I2 will be pulled, affecting the normal operation of the third-stage drive circuit S3.

[0201] Figure 10 It is a waveform diagram of the clock signals provided by each clock signal line.

[0202] exist Figure 10In the diagram, CLK1 is the first-level clock signal line, CLK2 is the second-level clock signal line, CLK3 is the third-level clock signal line, CLK4 is the fourth-level clock signal line, CLK5 is the fifth-level clock signal line, CLK6 is the sixth-level clock signal line, CLK7 is the seventh-level clock signal line, and CLK8 is the eighth-level clock signal line.

[0203] exist Figure 10 In the table, Fn represents the display time of the nth frame, Fn+1 represents the display time of the (n+1)th frame, and TB represents the blank time period; n is a positive integer.

[0204] In at least one embodiment of the present invention, the first driving module in the display device can be electrically connected to the odd-numbered clock signal lines among the twelve clock signal lines, and the second driving module in the display device can be electrically connected to the even-numbered clock signal lines among the twelve clock signal lines. In this case, the duty cycle of the clock signal provided by each clock signal line needs to be less than 33% to avoid overlap between the effective level time period of the reset signal and the effective level time period of the first control signal, and to avoid overlap between the effective level time period of the reset signal and the effective level time period of the second control signal, thus preventing M1 and M3 from being turned on simultaneously, and preventing M2 and M3 from being turned on simultaneously. Compared to a driving module using eight clock signal lines, a driving module using twelve clock signal lines has a longer single-row on-time, which is beneficial for ensuring the operating performance of the driving circuit in low-temperature environments.

[0205] like Figure 11 As shown, S1 is the first-stage driving circuit, S2 is the second-stage driving circuit, S3 is the third-stage driving circuit, S4 is the fourth-stage driving circuit, S5 is the fifth-stage driving circuit, and S6 is the sixth-stage driving circuit.

[0206] The output clock signal terminal of S1 is electrically connected to the first-stage clock signal line CLK1, the reset control clock signal terminal of S1 is electrically connected to the seventh-stage clock signal line CLK7, the second control terminal of S1 is electrically connected to the drive signal output terminal of S2, and the drive signal output terminal of S1 is electrically connected to the first row gate line G1.

[0207] The first control terminal of S2 is electrically connected to the drive signal output terminal of S1. The output clock signal terminal of S2 is electrically connected to the third-level clock signal line CLK3. The reset control clock signal terminal of S2 is electrically connected to the ninth-level clock signal line CLK9. The second control terminal of S2 is electrically connected to the drive signal output terminal of S3. The drive signal output terminal of S2 is electrically connected to the third row gate line G3.

[0208] The first control terminal of S3 is electrically connected to the drive signal output terminal of S2. The output clock signal terminal of S3 is electrically connected to the fifth-level clock signal line CLK5. The reset control clock signal terminal of S3 is electrically connected to the eleventh-level clock signal line CLK11. The second control terminal of S3 is electrically connected to the drive signal output terminal of S4. The drive signal output terminal of S3 is electrically connected to the fifth row gate line G5.

[0209] The first control terminal of S4 is electrically connected to the drive signal output terminal of S3, the output clock signal terminal of S4 is electrically connected to the seventh-level clock signal line CLK7, the reset control clock signal terminal of S4 is electrically connected to the first-level clock signal line CLK1, the second control terminal of S4 is electrically connected to the drive signal output terminal of S5, and the drive signal output terminal of S4 is electrically connected to the seventh row gate line G7.

[0210] The first control terminal of S5 is electrically connected to the drive signal output terminal of S4, the output clock signal terminal of S5 is electrically connected to the ninth-level clock signal line CLK9, the reset control clock signal terminal of S5 is electrically connected to the third-level clock signal line CLK3, the second control terminal of S5 is electrically connected to the drive signal output terminal of S6, and the drive signal output terminal of S5 is electrically connected to the ninth row gate line G9.

[0211] The first control terminal of S6 is electrically connected to the drive signal output terminal of S5. The output clock signal terminal of S6 is electrically connected to the eleventh-level clock signal line CLK11. The reset control clock signal terminal of S6 is electrically connected to the fifth-level clock signal line CLK5. The drive signal output terminal of S6 is electrically connected to the eleventh row gate line G11.

[0212] Figure 12 yes Figure 11 The waveforms of the drive signals provided by G1, G3, G5, G7, CLK9, and G11 are shown.

[0213] In specific implementation, the first control terminal of S2 is electrically connected to G1, the drive signal output terminal of S2 is electrically connected to G3, the second control terminal of S2 is electrically connected to G5, and the reset control clock signal terminal of S2 is electrically connected to CLK9. The clock signal provided by CLK9 is used to reset the first node in S2.

[0214] Figure 13 It is a waveform diagram of the clock signals provided by each clock signal line.

[0215] exist Figure 13In the diagram, CLK1 is the first-level clock signal line, CLK2 is the second-level clock signal line, CLK3 is the third-level clock signal line, CLK4 is the fourth-level clock signal line, CLK5 is the fifth-level clock signal line, CLK6 is the sixth-level clock signal line, CLK7 is the seventh-level clock signal line, CLK8 is the eighth-level clock signal line, CLK9 is the ninth-level clock signal line, CLK10 is the tenth-level clock signal line, CLK11 is the eleventh-level clock signal line, and CLK12 is the twelfth-level clock signal line.

[0216] exist Figure 13 In the table, Fn represents the display time of the nth frame, Fn+1 represents the display time of the (n+1)th frame, and TB represents the blank time period; n is a positive integer.

[0217] like Figure 14 As shown, in Figure 5 Based on at least one embodiment of the driving circuit shown,

[0218] The second reset circuit includes a fourth transistor M4, and the third reset circuit includes a fifth transistor M5;

[0219] The gate of the fourth transistor M4 is electrically connected to the second reset terminal R2, the source of the fourth transistor M4 is electrically connected to the low voltage terminal VGL, and the drain of the fourth transistor M4 is electrically connected to the first node PU.

[0220] The gate of the fifth transistor M5 is electrically connected to the first reset terminal R1, the source of the fifth transistor M5 is electrically connected to the low voltage terminal VGL, and the drain of the fifth transistor M5 is electrically connected to the first node PU.

[0221] The first node control circuit includes a sixth transistor M6, the second node control circuit includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9 and a tenth transistor M10; the output circuit includes an eleventh transistor M11 and a twelfth transistor M12, and the energy storage circuit includes a storage capacitor C.

[0222] The gate of the sixth transistor M6 is electrically connected to the second node PD, the source of the sixth transistor M6 is electrically connected to the first node PU, and the drain of the sixth transistor M6 is electrically connected to the low voltage terminal VGL.

[0223] The gate and source of the seventh transistor M7 are both electrically connected to the high-voltage terminal GCH, and the drain of the seventh transistor M7 is electrically connected to the source of the eighth transistor M8.

[0224] The gate of the eighth transistor M8 is electrically connected to the first node PU, and the drain of the eighth transistor M8 is electrically connected to the low voltage terminal VGL.

[0225] The gate of the ninth transistor M9 is electrically connected to the drain of the seventh transistor M7, the source of the ninth transistor M9 is electrically connected to the high voltage terminal GCH, and the drain of the ninth transistor M9 is electrically connected to the second node PD.

[0226] The gate of the tenth transistor M10 is electrically connected to the first node PU, the source of the tenth transistor M10 is electrically connected to the second node PD, and the drain of the tenth transistor M10 is electrically connected to the low voltage terminal VGL.

[0227] The gate of the eleventh transistor M11 is electrically connected to the first node PU, the source of the eleventh transistor M11 is electrically connected to the output clock signal terminal CLKA, and the drain of the eleventh transistor M11 is electrically connected to the drive signal output terminal OT.

[0228] The gate of the twelfth transistor M12 is electrically connected to the second node PD, the source of the twelfth transistor M12 is electrically connected to the drive signal output terminal OT, and the drain of the twelfth transistor M12 is electrically connected to the low voltage terminal VGL.

[0229] The first end of the storage capacitor C is electrically connected to the first node PU, and the second end of the storage capacitor C is electrically connected to the drive signal output terminal OT.

[0230] The first node reset circuit includes a thirteenth transistor M13, and the output reset circuit includes a fourteenth transistor M14;

[0231] The gate of the thirteenth transistor M13 is electrically connected to the frame reset terminal STV0, the source of the thirteenth transistor M13 is electrically connected to the first node PU, and the drain of the thirteenth transistor M13 is electrically connected to the low voltage terminal VGL.

[0232] The gate of the fourteenth transistor M14 is electrically connected to the frame reset terminal STV0, the source of the fourteenth transistor M14 is electrically connected to the drive signal output terminal OT, and the drain of the fourteenth transistor M14 is electrically connected to the low voltage terminal VGL.

[0233] exist Figure 14 In at least one embodiment of the driving circuit shown, all transistors are n-type transistors, but this is not a limitation.

[0234] Figure 15 It includes multiple levels Figure 14The waveform of the drive signal output by the drive circuit in row 182 is shown after a reliability test of the drive module of at least one embodiment of the drive circuit shown.

[0235] like Figure 15 As shown, the waveform of the drive signal is relatively flat and outputs without errors, proving that... Figure 14 At least one embodiment of the driving circuit shown can be adapted to high-temperature reliability environments.

[0236] like Figure 16 As shown, S1 is the first-stage driving circuit, S2 is the second-stage driving circuit, S3 is the third-stage driving circuit, S4 is the fourth-stage driving circuit, S5 is the fifth-stage driving circuit, and S6 is the sixth-stage driving circuit.

[0237] The output clock signal terminal of S1 is electrically connected to the first-stage clock signal line CLK1; the second control terminal of S1 is electrically connected to the drive signal output terminal of S2; the drive signal output terminal of S1 is electrically connected to the first row gate line G1; and the second reset terminal of S1 is electrically connected to the drive signal output terminal of S4.

[0238] The output clock signal terminal of S2 is electrically connected to the third-stage clock signal line CLK3. The first control terminal of S2 is electrically connected to the drive signal output terminal of S1. The second reset terminal of S2 is electrically connected to the drive signal output terminal of S5. The second control terminal of S2 is electrically connected to the drive signal output terminal of S3. The drive signal output terminal of S2 is electrically connected to the third row gate line G3.

[0239] The output clock signal terminal of S3 is electrically connected to the fifth-level clock signal line CLK5. The first control terminal of S3 is electrically connected to the drive signal output terminal of S2. The second reset terminal of S3 is electrically connected to the drive signal output terminal of S6. The second control terminal of S3 is electrically connected to the drive signal output terminal of S4. The drive signal output terminal of S3 is electrically connected to the fifth row gate line G5.

[0240] The output clock signal terminal of S4 is electrically connected to the seventh-level clock signal line CLK7. The first control terminal of S4 is electrically connected to the drive signal output terminal of S3. The first reset terminal of S4 is electrically connected to the drive signal output terminal of S1. The second control terminal of S4 is electrically connected to the drive signal output terminal of S5. The drive signal output terminal of S4 is electrically connected to the seventh row gate line G7.

[0241] The output clock signal terminal of S5 is electrically connected to the first-stage clock signal line CLK1, the first control terminal of S5 is electrically connected to the drive signal output terminal of S4, the first reset terminal of S5 is electrically connected to the drive signal output terminal of S2, the second control terminal of S5 is electrically connected to the drive signal output terminal of S6, and the drive signal output terminal of S5 is electrically connected to the ninth row gate line G9.

[0242] The output clock signal terminal of S6 is electrically connected to the third-level clock signal line CLK3. The first control terminal of S6 is electrically connected to the drive signal output terminal of S5. The first reset terminal of S6 is electrically connected to the drive signal output terminal of S3. The second control terminal of S6 is electrically connected to the drive signal output terminal of S5. The drive signal output terminal of S6 is electrically connected to the eleventh row gate line G11.

[0243] exist Figure 16 In the diagram, I1 is the first control terminal, I2 is the second control terminal, R1 is the first reset terminal, R2 is the second reset terminal, CLKA is the output clock signal terminal, and OT is the drive signal output terminal.

[0244] Figure 17 yes Figure 16 The waveforms of the drive signals output by G1, G3, G5, G7 and G9 are shown.

[0245] Figure 18 yes Figure 16 The waveform diagram of the clock signals provided by the clock signal lines at each stage.

[0246] exist Figure 18 In the diagram, CLK1 is the first-level clock signal line, CLK2 is the second-level clock signal line, CLK3 is the third-level clock signal line, CLK4 is the fourth-level clock signal line, CLK5 is the fifth-level clock signal line, CLK6 is the sixth-level clock signal line, CLK7 is the seventh-level clock signal line, and CLK8 is the eighth-level clock signal line.

[0247] exist Figure 18 In the table, Fn represents the display time of the nth frame, Fn+1 represents the display time of the (n+1)th frame, and TB represents the blank time period; n is a positive integer.

[0248] exist Figure 16 In at least one embodiment of the driving module shown, the first reset terminal of each driving circuit is electrically connected to the driving signal output terminal of the adjacent first three driving circuits, and the second reset terminal of each driving circuit is electrically connected to the driving signal output terminal of the adjacent last three driving circuits. The duty cycle of the clock signal provided by each clock signal line needs to be less than 50% to avoid the effective level time period of the reset signal overlapping with the effective level time period of the control signal. If the adjacent first four driving circuits and the adjacent last four driving circuits are used for reset, the duty cycle of each clock signal only needs to be less than 75%.

[0249] The driving module described in this embodiment of the invention includes multiple stages of the aforementioned driving circuits.

[0250] The display device described in this embodiment of the invention includes the driving module described above.

[0251] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A driving circuit, included in a driving module, characterized in that, The driving circuit includes a first input circuit, a second input circuit, and a first reset circuit; The first input circuit is electrically connected to the first control terminal and the first node respectively, and is used to control the potential of the first node under the control of the first control signal provided by the first control terminal; The second input circuit is electrically connected to the second control terminal and the first node respectively, and is used to control the potential of the first node under the control of the second control signal provided by the second control terminal; The first input circuit includes a first transistor, and the second input circuit includes a second transistor; The gate and the first terminal of the first transistor are both electrically connected to the first control terminal, and the second terminal of the first transistor is electrically connected to the first node. The gate and the first terminal of the second transistor are both electrically connected to the second control terminal, and the second terminal of the second transistor is electrically connected to the first node; When the drive module performs a forward scan, the first input circuit is used to control the potential of the first node during the input phase under the control of the first control signal provided by the first control terminal. The first reset circuit is used to control the connection between the first node and the first voltage terminal under the control of the reset control clock signal during the reset phase after the input phase, so as to reset the potential of the first node. When the drive module performs a reverse scan, the second input circuit is used to control the potential of the first node during the input phase under the control of the second control signal provided by the second control terminal; The first reset circuit is used to control the connection between the first node and the first voltage terminal under the control of the reset control clock signal during the reset phase after the input phase, so as to reset the potential of the first node. The effective level time period of the first control signal does not overlap with the effective level time period of the reset control clock signal; the effective level time period of the second control signal does not overlap with the effective level time period of the reset control clock signal.

2. The driving circuit as described in claim 1, characterized in that, The first control terminal is electrically connected to the drive signal output terminal of the adjacent first n-stage drive circuit; the second control terminal is electrically connected to the drive signal output terminal of the adjacent last m-stage drive circuit. Both n and m are positive integers.

3. The driving circuit as described in claim 1 or 2, characterized in that, The first reset circuit is electrically connected to the reset control clock signal terminal, the first voltage terminal, and the first node, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the reset control clock signal provided by the reset control clock signal terminal.

4. The driving circuit as described in claim 1 or 2, characterized in that, It also includes a second reset circuit and a third reset circuit; The third reset circuit is electrically connected to the first reset terminal, the first voltage terminal, and the first node, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the first reset signal provided by the first reset terminal; The second reset circuit is electrically connected to the second reset terminal, the first voltage terminal, and the first node, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the second reset signal provided by the second reset terminal.

5. The driving circuit as described in claim 4, characterized in that, The second reset terminal is electrically connected to the drive signal output terminal of the adjacent subsequent a-stage drive circuit, and the first reset terminal is electrically connected to the drive signal output terminal of the adjacent preceding b-stage drive circuit. Both a and b are positive integers.

6. The driving circuit as described in claim 5, characterized in that, The effective level time period of the first reset signal does not overlap with the effective level time period of the first control signal; The effective level time period of the first reset signal does not overlap with the effective level time period of the second control signal; The effective time period of the second reset signal does not overlap with the effective time period of the first control signal; The effective time period of the second reset signal does not overlap with the effective time period of the second control signal.

7. The driving circuit as described in claim 3, characterized in that, The first reset circuit includes a third transistor; The gate of the third transistor is electrically connected to the reset control clock signal terminal, the first terminal of the third transistor is electrically connected to the first voltage terminal, and the second terminal of the third transistor is electrically connected to the first node.

8. The driving circuit as described in claim 4, characterized in that, The second reset circuit includes a fourth transistor, and the third reset circuit includes a fifth transistor; The gate of the fourth transistor is electrically connected to the second reset terminal, the first terminal of the fourth transistor is electrically connected to the first voltage terminal, and the second terminal of the fourth transistor is electrically connected to the first node. The gate of the fifth transistor is electrically connected to the first reset terminal, the first terminal of the fifth transistor is electrically connected to the first voltage terminal, and the second terminal of the fifth transistor is electrically connected to the first node.

9. The driving circuit as described in claim 1 or 2, characterized in that, It also includes a first node control circuit, a second node control circuit, an output circuit, and an energy storage circuit; The first node control circuit is electrically connected to the second node, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node; The second node control circuit is electrically connected to the second voltage terminal, the first node, the second node, and the first voltage terminal, respectively, and is used to control the potential of the second node under the control of the second voltage signal provided by the second voltage terminal and the potential of the first node; The energy storage circuit is electrically connected to the first node and the drive signal output terminal respectively, and is used to store electrical energy. The output circuit is electrically connected to the first node, the second node, the output clock signal terminal, the drive signal output terminal, and the first voltage terminal, respectively. It is used to control the connection between the output clock signal terminal and the drive signal output terminal under the control of the potential of the first node, and to control the connection between the drive signal output terminal and the first voltage terminal under the control of the potential of the second node.

10. The driving circuit as described in claim 9, characterized in that, It also includes a first node reset circuit and an output reset circuit; The first node reset circuit is electrically connected to the frame reset terminal, the first node and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal. The output reset circuit is electrically connected to the frame reset terminal, the drive signal output terminal, and the first voltage terminal, respectively, and is used to control the connection between the drive signal output terminal and the first voltage terminal under the control of the frame reset signal.

11. The driving circuit as described in claim 10, characterized in that, The first node control circuit includes a sixth transistor, the second node control circuit includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; the output circuit includes an eleventh transistor and a twelfth transistor, and the energy storage circuit includes a storage capacitor; The gate of the sixth transistor is electrically connected to the second node, the first terminal of the sixth transistor is electrically connected to the first node, and the second terminal of the sixth transistor is electrically connected to the first voltage terminal. The gate and the first terminal of the seventh transistor are both electrically connected to the second voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first terminal of the eighth transistor. The gate of the eighth transistor is electrically connected to the first node, and the second terminal of the eighth transistor is electrically connected to the first voltage terminal. The gate of the ninth transistor is electrically connected to the second terminal of the seventh transistor, the first terminal of the ninth transistor is electrically connected to the second voltage terminal, and the second terminal of the ninth transistor is electrically connected to the second node. The gate of the tenth transistor is electrically connected to the first node, the first terminal of the tenth transistor is electrically connected to the second node, and the second terminal of the tenth transistor is electrically connected to the first voltage terminal. The gate of the eleventh transistor is electrically connected to the first node, the first terminal of the eleventh transistor is electrically connected to the output clock signal terminal, and the second terminal of the eleventh transistor is electrically connected to the drive signal output terminal. The gate of the twelfth transistor is electrically connected to the second node, the first terminal of the twelfth transistor is electrically connected to the drive signal output terminal, and the second terminal of the twelfth transistor is electrically connected to the first voltage terminal. The first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the drive signal output terminal. The first node reset circuit includes a thirteenth transistor, and the output reset circuit includes a fourteenth transistor; The gate of the thirteenth transistor is electrically connected to the frame reset terminal, the first terminal of the thirteenth transistor is electrically connected to the first node, and the second terminal of the thirteenth transistor is electrically connected to the first voltage terminal. The gate of the fourteenth transistor is electrically connected to the frame reset terminal, the first terminal of the fourteenth transistor is electrically connected to the drive signal output terminal, and the second terminal of the fourteenth transistor is electrically connected to the first voltage terminal.

12. A drive module, characterized in that, It includes multiple levels of drive circuits as described in any one of claims 1 to 11.

13. A display device, characterized in that, Includes the drive module as described in claim 12.

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