Method for manufacturing semiconductor memory device and semiconductor memory device

Abstract

Embodiments provide a manufacturing method of a semiconductor storage device capable of more reliably connecting a plurality of conductive layers with a plurality of contacts and a semiconductor storage device. In the manufacturing method of the semiconductor storage device of the embodiments, the following process is repeatedly performed a plurality of times: a process of etching and removing one set of the first insulating layer and the second insulating layer of a layered body that is exposed from a second mask layer while the second mask layer is made to retreat in a first direction toward a first edge by thinning, the second mask layer is removed after the plurality of times of thinning, and a first stop layer that is exposed at the first edge is removed, and the following process is repeatedly performed a plurality of times: a process of etching and removing one set of the first insulating layer and the second insulating layer of a layered body that is exposed from a first mask layer while the first mask layer is made to retreat in the first direction by thinning.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2022-044482 (filed on March 18, 2022). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] The embodiments of the present invention relate to a method for manufacturing a semiconductor memory device and a semiconductor memory device. Background Technology

[0004] In a three-dimensional non-volatile memory, memory cells are arranged in three dimensions, for example, in a stack of multiple conductive layers. Furthermore, by processing these multiple conductive layers into a stepped shape and connecting them to contacts, the multiple conductive layers can be electrically led out. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide a method for manufacturing a semiconductor memory device and a semiconductor memory device that can more reliably connect multiple conductive layers and multiple contacts.

[0006] In the manufacturing method of the semiconductor memory device according to the embodiment, a laminate is formed by alternately stacking a plurality of first insulating layers and a plurality of second insulating layers. A first mask layer having a first edge is formed on top of the laminate. A first stop layer is formed that at least covers the first edge. A second mask layer is formed that covers the first mask layer including the first edge. The following process is repeatedly performed multiple times: while thinning the second mask layer to move backward toward the first edge, a process is performed to etch away a set of first insulating layers and second insulating layers of the laminate exposed from the second mask layer. The second mask layer that has been thinned multiple times is removed, and the first stop layer exposed at the first edge is removed. The following process is repeatedly performed multiple times: while thinning the first mask layer to move backward in the first direction, a process is performed to etch away a set of first insulating layers and second insulating layers of the laminate exposed from the first mask layer. Attached Figure Description

[0007] Figure 1 This is a cross-sectional view showing an example of the configuration of the storage region in a semiconductor memory device according to the embodiment.

[0008] Figure 2 This is a cross-sectional view showing an example of the configuration of the stepped portion in the semiconductor memory device according to the embodiment.

[0009] Figure 3 This is a top view showing an example of the configuration of the stepped portion of the semiconductor memory device according to the embodiment.

[0010] Figure 4 This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0011] Figure 5 This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0012] Figure 6 This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0013] Figure 7 This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0014] Figure 8 This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0015] Figure 9 This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0016] Figure 10 This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0017] Figure 11 This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0018] Figure 12 This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0019] Figure 13 This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0020] Figure 14 This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0021] Figure 15 This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0022] Figure 16This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0023] Figure 17 This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0024] Figure 18 This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0025] Figure 19 This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0026] Figure 20 This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0027] Figure 21 This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0028] Figure 22 This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0029] Figure 23 This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0030] Figure 24 This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor memory device according to an embodiment.

[0031] Figure 25 This is a cross-sectional view illustrating a portion of the steps in the manufacturing method of the semiconductor memory device involved in the comparative example.

[0032] Figure 26 This is a cross-sectional view showing a portion of the steps of a method for forming a stepped portion in a semiconductor memory device according to a modified example 1 of the embodiments.

[0033] Figure 27 This is a cross-sectional view showing a portion of the steps of a method for forming a stepped portion in a semiconductor memory device according to a modified example 1 of the embodiments.

[0034] Figure 28 This is a cross-sectional view showing a portion of the steps of a method for forming a stepped portion in a semiconductor memory device according to a modified example 1 of the embodiments.

[0035] Figure 29 This is a top view showing an example of the configuration of the stepped portion of a semiconductor memory device according to a modified example 1 of the embodiment.

[0036] Figure 30 This is a cross-sectional view of a step in a method for forming a stepped portion in a semiconductor memory device according to a modified embodiment 2.

[0037] Figure 31 This is a cross-sectional view showing a state in which two stop layers are formed in a method for manufacturing a semiconductor memory device according to other variations of the embodiment. Detailed Implementation

[0038] The present invention will now be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below. Furthermore, the constituent elements in the following embodiments include elements readily conceived by those skilled in the art or substantially the same elements.

[0039] (Example of a semiconductor memory device)

[0040] Figure 1 This is a cross-sectional view showing an example of the configuration of the storage region MR in the semiconductor storage device 1 according to the embodiment. Figure 1 (a) is a cross-sectional view of the semiconductor memory device 1, including the memory region MR, along the Y direction. Figure 1 (b) is a partially enlarged cross-sectional view of the column PL of the semiconductor memory device 1.

[0041] Furthermore, in this specification, both the X and Y directions refer to the directions along the plane of the word line WL (described later), and the X and Y directions are orthogonal to each other. Additionally, the electrical lead-out direction of the word line WL (described later) is sometimes referred to as the first direction, which is along the X direction. Furthermore, the direction intersecting the first direction is sometimes referred to as the second direction, which is along the Y direction. However, since the semiconductor memory device 1 may contain manufacturing errors, the first and second directions are not necessarily orthogonal.

[0042] like Figure 1 As shown in (a), the semiconductor memory device 1 includes a source line SL and a stacked body LM.

[0043] Source lines SL are formed on a portion of a semiconductor substrate, such as a silicon substrate (not shown), or above it, away from the semiconductor substrate. The source lines SL include a lower source line DSLa, a middle source line BSL, and an upper source line DSLb. The middle source line BSL is disposed on the lower source line DSLa, and the upper source line DSLb is disposed on the middle source line BSL. The lower source line DSLa, the middle source line BSL, and the upper source line DSLb are, for example, conductive polysilicon layers.

[0044] A stack LM is disposed on the source line SL, which is formed by alternately stacking multiple word lines WL as conductive layers and multiple insulating layers OL. The word lines WL are, for example, tungsten layers or molybdenum layers. The insulating layers OL are, for example, silicon oxide layers. The number of word lines WL is arbitrary. The stack LM may also have at least one additional select gate line on at least one of the layers above the topmost word line WL and the layers below the bottommost word line WL. The stack LM also includes a memory region MR and step portions SR, SRd (see reference). Figure 2 ).

[0045] The upper surface of the laminate LM is covered by an insulating layer 52, such as a silicon oxide layer. An insulating layer 53, such as a silicon oxide layer, is disposed on the insulating layer 52. An insulating layer 54, such as a silicon oxide layer, is disposed on the insulating layer 53.

[0046] Multiple plate-shaped contacts LI are disposed on the laminate LM, and these plate-shaped contacts LI extend within the laminate LM in the lamination direction and the X direction. Thus, the multiple plate-shaped contacts LI divide the laminate LM in the Y direction. More specifically, each plate-shaped contact LI penetrates the insulating layer 52, the laminate LM, and the upper source line DSLb, reaching the intermediate source line BSL.

[0047] In addition, the plate-shaped contact LI includes an insulating layer 55 covering the sidewalls facing each other in the Y direction and a conductive layer 21 filling the inner portion of the plate-shaped contact LI held by the insulating layer 55. The insulating layer 55 is, for example, a silicon oxide layer, and the conductive layer 21 is, for example, a tungsten layer or a conductive polysilicon layer.

[0048] The lower end of conductive layer 21 is electrically connected to source line SL via intermediate source line BSL. The upper end of conductive layer 21 is electrically connected to upper layer wiring MX disposed in insulating layer 54 via plug V0 extending in insulating layer 53.

[0049] Based on the above configuration, the plate-shaped contact LI functions as a source line contact. However, instead of the plate-shaped contact LI, the laminate LM can be divided in the Y direction by a plate-shaped portion composed of an insulating layer or the like. In this case, the plate-shaped portion does not function as a source line contact.

[0050] In the region of the laminate LM held by adjacent plate-shaped contacts LI in the Y direction, multiple pillars PL are arranged. These pillars PL penetrate the laminate LM, the upper source line DSLb, and the middle source line BSL, reaching the lower source line DSLa. The region of the laminate LM with multiple pillars PL is, for example, called the memory region MR.

[0051] Within the storage region MR, when viewed from the stacking direction of the stack LM, multiple pillars PL are arranged in a staggered pattern, for example, dispersed. When viewed from the stacking direction of the stack LM, each pillar PL has, for example, a circular, elliptical, or oval shape.

[0052] Additionally, the pillar PL has a storage layer ME, a channel layer CN, and a core layer CR extending in the stacking direction of the stack LM, and a capping layer CP disposed in the insulating layer 52 as their upper ends.

[0053] like Figure 1 As shown in (b), the storage layer ME has a stacked structure consisting of a barrier insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN, sequentially stacked from the outer periphery of the pillar PL. The channel layer CN is disposed further inside the tunnel insulating layer TN. A core layer CR is filled further inside the channel layer CN.

[0054] In addition, no memory layer ME is configured at the height of the intermediate source line BSL, and the exposed channel layer CN is in direct contact with the intermediate source line BSL.

[0055] Barrier insulating layer BK, tunnel insulating layer TN, and core layer CR are, for example, silicon oxide layers. Charge storage layer CT is, for example, a silicon nitride layer. Channel layer CN and capping layer CP are, for example, amorphous silicon or polycrystalline silicon layers, or other semiconductor layers.

[0056] The upper end of the cover layer CP is electrically connected to the bit line BL disposed in the insulating layer 54 via a plug CH extending in the insulating layers 53 and 52. The bit line BL extends in the direction intersecting with the lead-out direction of the word line WL, that is, along the Y direction.

[0057] The upper end of the channel layer CN is connected to the cap layer CP. The channel layer CN is also connected to the intermediate source line BSL on the side, and is electrically connected to the source line SL through the intermediate source line BSL.

[0058] Based on the above configuration, memory cells MC are formed at the intersections of the column PL and the plurality of word lines WL. Data is written to and read from these memory cells MC by applying a predetermined voltage from the word lines WL located at the same height as these memory cells MC.

[0059] Furthermore, when the stacked body LM has a select gate line, a select gate is formed at the intersection of the select gate line and the pillar PL. By applying a specified voltage from the select gate line, the select gate is turned on or off, and the memory cell MC of the pillar PL to which the select gate belongs becomes selected or non-selected.

[0060] In this way, by arranging multiple storage cells MC in three dimensions within the storage region MR, the semiconductor storage device 1 of the embodiment is configured as a three-dimensional non-volatile memory, for example.

[0061] Figure 2 This is a cross-sectional view showing an example of the configuration of the stepped portions SR and SRd in the semiconductor memory device 1 according to the embodiment. Figure 2 (a) is a cross-sectional view of the semiconductor memory device 1 along the X direction, including the stepped portion SR. Figure 2 (b) is a cross-sectional view of the semiconductor memory device 1 along the Y direction, including the stepped portion SRd.

[0062] like Figure 2 As shown in (a), a stepped portion SR is disposed at at least one end of the laminate LM in the X direction, in which multiple word lines WL and multiple insulating layers OL are processed into a stepped shape and terminate. That is, the stepped portion SR increases in height toward the storage region MR disposed on the central side of the laminate LM. The entire stepped portion SR is covered by an insulating layer 51, such as a silicon oxide layer. The aforementioned insulating layers 52 to 54 are also formed on the upper surface of the insulating layer 51.

[0063] Each stage of the stepped section SR is composed of word lines WL and insulating layers OL. The X-direction end faces of the word lines WL and insulating layers OL constituting each stage of the stepped section SR are called the step difference surfaces SP, which serve as the first step difference surfaces. The upper surface of the word lines WL constituting each stage of the stepped section SR is called the plateau surface TR. Contacts CC are connected to the plateau surfaces TR of each of the multiple word lines WL.

[0064] Each contact CC penetrates the insulating layers 52 and 51, reaching the word lines WL of each level of the stepped section SR. Each contact CC has an insulating layer 56 covering its sidewalls and a conductive layer 22 filling the inner side of the insulating layer 56. The lower end of the conductive layer 22 is connected to the platform surface TR of the corresponding word line WL. The upper end of the conductive layer 22 is electrically connected to the upper wiring MX disposed in the insulating layer 54 via a plug V0 extending in the insulating layer 53.

[0065] Semiconductor memory device 1 includes peripheral circuitry (not shown), and upper layer wiring MX is electrically connected to the peripheral circuitry. The peripheral circuitry includes multiple transistors and contributes to the electrical operation of the memory cell MC. By applying the aforementioned voltage to the memory cell MC via the peripheral circuitry, upper layer wiring MX, contact CC, and word line WL, data can be read and written to the memory cell MC.

[0066] like Figure 2 As shown in (b), stepped portions SRd are disposed at both ends of the laminate LM in the Y direction, in which multiple word lines WL and multiple insulating layers OL are processed into a stepped shape and terminate. That is, the stepped portions SRd increase in height toward the storage region MR disposed on the central side of the laminate LM. In addition, the entire stepped portion SRd is also covered by insulating layer 51. The aforementioned insulating layers 52 to 54 are also formed on the upper surface of the insulating layer 51 covering the stepped portion SRd.

[0067] Each level of the stepped section SRd is composed of multiple word lines WL and insulating layers OL. As a result, the stepped section SRd has a steeper inclination than the stepped section SR at the X-direction end, and the step length, that is, the length from the top level to the bottom level, is shorter than that of the stepped section SR.

[0068] The Y-direction end faces of the word lines WL and insulating layer OL constituting each stage of the stepped portion SRd are referred to as the step difference surface SPd, which serves as the second step difference surface. The upper surface of the word lines WL constituting each stage of the stepped portion SRd is referred to as the plateau surface TRd. The stepped portion SRd at both ends in the Y direction is a dummy stepped portion that does not contribute to the function of the semiconductor memory device 1, and the aforementioned contact CC is not connected to the plateau surface TRd of the stepped portion SRd.

[0069] In addition, in this specification, the side to which the platform surfaces TR and TRd of the word lines WL of the stepped portions SR and SRd face is defined as the upper side of the semiconductor memory device 1.

[0070] Figure 3 This is a top view showing an example of the configuration of the stepped portions SR and SRd in the semiconductor memory device 1 according to the embodiment. Figure 3 (a) is a top view of the semiconductor memory device 1 including the stepped section SR. Figure 3 (b) is a top view of the semiconductor memory device 1 including the stepped portion SRd.

[0071] However, in Figure 3 In this text, the insulating layers 51-54 covering the stepped portions SR and SRd are omitted. Additionally, in... Figure 3 In (a), from the point of view of easy understanding of the figure, the plate-shaped contact LI is represented by a dashed line, and the state of the step portion SR below is shown through the plate-shaped contact LI.

[0072] like Figure 3 As shown in (a), in each region of the laminate LM, which is divided in the Y direction by multiple plate-shaped contacts LI, contacts CC are arranged on each level of the stepped portion SR.

[0073] Furthermore, when observing the stepped section SR from the upper surface, it can be seen that the multiple step difference surfaces SP constituting each level of the stepped section SR extend in the direction along the Y direction.

[0074] The lowest step surface SP of the stepped section SR extends substantially linearly along the Y direction. The second step surface SP from the lowest level of the stepped section SR has an arcuate shape with a prominent central portion in the Y direction. The third step surface SP from the lowest level of the stepped section SR has a shape with an even more prominent central portion in the Y direction and an increased degree of arcuate shape.

[0075] In this way, several of the step surfaces SP in the stepped section SR change shape from a substantially straight line extending towards the central part in the direction in which the stepped section SR becomes higher. Thus, the several step surfaces SP that change shape from a roughly straight line extending towards the central part are called the step surface group SPG.

[0076] The stepped section SR includes multiple sets of stepped surfaces SPG arranged from the lower side to the upper side. That is, the multiple stepped surfaces SP of the stepped section SR change shape from a substantially straight-line extending shape to a central part in the direction of increasing height of the stepped section SR, and then return to a substantially straight-line extending shape, and from there change shape again to a central part.

[0077] In this way, at multiple step surfaces SP of the stepped section SR, the shape that extends in a substantially straight line and protrudes towards the central part is repeatedly changed in the direction that the stepped section SR becomes higher.

[0078] like Figure 3 As shown in (b), when the stepped portion SRd is viewed from the upper surface, it can be seen that the multiple step difference surfaces SP of each level constituting the stepped portion SRd extend in the direction along the X direction.

[0079] In addition, the step surface SPd of the stepped portion SRd also includes: the step surface SPd that extends substantially in a straight line along the X direction as the fourth and fifth step surfaces, and the step surface SPd that has an arc-shaped shape with a central portion protruding in the X direction as the third step surface.

[0080] The step surfaces SPd, which have an arcuate shape, are distributed throughout the entire stepped portion SRd extending along the X direction. The step surfaces SPd extending substantially in a straight line along the X direction include: a step surface SPd as the fourth step surface located near the lowest level of the stepped portion SRd at point P1 (indicated by an arrow), and a step surface SPd as the fifth step surface located between the lowest and highest levels of the stepped portion SRd at point P2 (indicated by an arrow).

[0081] (Manufacturing method of semiconductor memory device)

[0082] Next, use Figures 4 to 24 An example of a method for manufacturing the semiconductor memory device 1 according to the embodiment will be described. Figures 4 to 24 This is a cross-sectional view illustrating a portion of the steps in the manufacturing method of the semiconductor memory device 1 according to the embodiments.

[0083] first, Figures 4 to 11 The state in which the stepped section SR is formed is shown. Figures 4 to 11 It is a cross-sectional view along the X direction of the stepped section SR during the manufacturing process.

[0084] like Figure 4 As shown in (a), a lower source line DSLa, an intermediate insulating layer SCN, and an upper source line DSLb are formed sequentially. The intermediate insulating layer SCN, for example, is a silicon nitride layer, which serves as a sacrificial layer that is later replaced by a polysilicon layer or the like to become the intermediate source line BSL.

[0085] A laminate LMs is formed on the upper source line DSLb by alternating layers of insulating layer NL (as a first insulating layer) and insulating layer OL (as a second insulating layer). The insulating layer NL, for example, is a silicon nitride layer, which serves as a sacrificial layer that is later replaced by a conductive layer to become the word line WL.

[0086] A resist layer 60, a stop layer STPa, and a resist layer 70 are sequentially formed on the upper surface of the laminate LMs.

[0087] The resist layer 60, which serves as the first mask layer, has, for example, a rectangular shape including a side 60y extending in the Y direction as the first side, and covers a portion of the upper surface of the laminate LMs.

[0088] The stop layer STPa, which serves as the first stop layer, is formed in such a way that it covers the upper surface of the resist layer 60, the side including the edge 60y, and the upper surface of the laminate LMs exposed from the resist layer 60.

[0089] The stop layer STPa is, for example, a semiconductor layer such as an amorphous silicon layer or a polycrystalline silicon layer, or a metal layer such as an aluminum layer, a tungsten layer, or a platinum layer. Such a stop layer STPa is formed, for example, by sputtering or low-temperature CVD (Chemical Vapor Deposition) at temperatures below 90°C. This allows for the suppression of deterioration of the formed resist layer 60.

[0090] The resist layer 70, serving as the second mask layer, is formed such that it covers the upper surface and the side surface including the edge 60y of the resist layer 60, separated by a stop layer STPa. Thus, the resist layer 70 also has a rectangular shape along the side surface including the edge 60y of the resist layer 60. Furthermore, a stop layer STPa is interposed between the resist layers 60 and 70.

[0091] like Figure 4 As shown in (b), the stop layer STPa is removed from the upper surface of the laminate LMs exposed from the resist layer 70. Additionally, one set of insulating layers NL and OL on the exposed surface of the laminate LMs is removed. That is, the uppermost set of insulating layers NL and OL of the laminate LMs is removed. At this time, the stepped portion formed by removing this set of insulating layers NL and OL has a substantially linear stepped surface that has been transferred with the shape of the resist layer 70, which has a rectangular shape along the edge 60y of the resist layer 60.

[0092] like Figure 5 As shown in (a), the resist layer 70 is thinned to form a resist layer 71, exposing the upper surface of the laminate LMs covered by the stop layer STPa. During the thinning of the resist layer 70, for example, the sides of the resist layer 70 are retracted by oxygen plasma, thereby forming a resist layer 71 with a smaller area and thickness than the resist layer 70 covering the laminate LMs.

[0093] Furthermore, the side of the resist layer 71, which is thinned and receded, becomes an arc shape with a slightly protruding central portion in the Y direction relative to the side of the resist layer 70, which extends substantially in a straight line.

[0094] like Figure 5 As shown in (b), the stop layer STPa is removed from the upper surface of the newly exposed laminate LMs, and further, a set of insulating layers NL and OL on the exposed surface of the laminate LMs is removed. Thus, the set of insulating layers NL and OL of the uppermost layer of the newly exposed laminate LMs and the set of insulating layers NL and OL of the layer below the removed uppermost layer are removed.

[0095] At this time, at the stepped portion formed by removing the first set of insulating layers NL and OL below the top layer, a stepped surface that extends substantially in a straight line is maintained. On the other hand, the stepped portion formed by removing the first set of insulating layers NL and OL has a stepped surface with a slightly protruding central portion in the Y direction, which is an arc shape to which the resist layer 71 has been transferred.

[0096] like Figure 6 As shown in (a), the resist layer 71 is further thinned to form a resist layer 72, exposing the upper surface of the laminate LMs covered by the stop layer STPa. At this point, the amount of protrusion on the side of the resist layer 72 becomes greater, and the degree of the arcuate shape increases.

[0097] like Figure 6 As shown in (b), the stop layer STPa is removed from the upper surface of the newly exposed laminate LMs, and further, a set of insulating layers NL and OL on the exposed surfaces of the laminate LMs are removed. Thus, the uppermost layer, the layer below the uppermost layer, and the lowermost set of insulating layers NL and OL on each exposed surface of the laminate LMs are removed.

[0098] In the stepped portion formed by removing the layer below the top layer and the lowermost insulating layer NL and OL, the stepped surface maintains a slightly protruding shape in the center in the Y direction and a substantially straight shape, respectively.

[0099] On the other hand, the stepped portion formed by removing the topmost set of insulating layers NL and OL has a more prominent stepped surface in the central part of the Y direction with an arc shape and a resist layer 72 transferred on it.

[0100] In this way, the following process is repeated multiple times: while thinning the resist layer 70, a set of insulating layers NL and OL of the laminates LMs exposed from the resist layers 70, 71, and 72 are etched away. As a result, at the stepped portion formed by removing the set of insulating layers NL and OL, the multiple stepped surfaces change from a substantially linear shape to a shape that protrudes towards the central portion in the direction in which these stepped portions become higher.

[0101] like Figure 7 As shown in (a), the resist layer 72 is further thinned to expose the upper surface of the laminate LMs covered by the stop layer STPa. At this point, the resist layer 72 is completely removed, exposing the stop layer STPa located between the resist layers 60 and 72.

[0102] like Figure 7 As shown in (b), the exposed stop layer STPa is completely removed. Thus, the stop layer STPa is removed from the upper surface of the newly exposed laminate LMs, and from the upper surface and sides of the resist layer 60.

[0103] The side surface of the resist layer 60 exposed after removing the stop layer STPa, including the edge 60y, maintains the substantially straight shape that was formed when the resist layer 60 was formed. That is, by pre-existing the stop layer STPa between the resist layers 60 and 70, the arcuate shape formed due to thinning is reset once.

[0104] In this state, on each exposed surface of the laminate LM exposed from the resist layer 60, one set of insulating layers NL and OL is removed. At this time, the stepped portion formed by removing the newly exposed uppermost set of insulating layers NL and OL has a substantially linearly extending stepped surface with the shape of the rectangular resist layer 60 transferred onto it.

[0105] In this way, as the bow shape formed by thinning is reset by the stop layer STPa, the shape of the step surface that gradually protrudes from the center in the Y direction, which is in the direction of increasing height towards the stepped portion, is also reset once.

[0106] like Figure 8 As shown in (a), the resist layer 60 is thinned to form a resist layer 61, exposing the upper surface of the laminate LMs, and removing a set of insulating layers NL and OL on the exposed surface of the laminate LMs.

[0107] like Figure 8 As shown in (b), the resist layer 61 is further thinned to form the resist layer 62, so that the upper surface of the laminate LMs is newly exposed, and a set of insulating layers NL and OL on the exposed surface of the laminate LMs are removed.

[0108] In this way, the following process is repeated multiple times: while the resist layer 60 is thinned and retracted, the insulating layers NL and OL of the laminate LMs exposed from the resist layers 60, 61, and 62 are etched away. As a result, a stepped portion continues to be formed relative to the stepped portion SR formed by the thinning of the resist layer 70.

[0109] Furthermore, in the continuing step sections, multiple step surfaces change from a substantially straight-line shape to a shape that protrudes towards the central part in the direction in which these step sections become higher.

[0110] Subsequently, the residual resist layer 62 was removed by ashing using oxygen plasma and other methods.

[0111] like Figure 9 As shown in (a), a resist layer 80, a stop layer STPb, and a resist layer 90 are sequentially formed on the upper surface of the laminate LMs.

[0112] The resist layer 80, which serves as the third resist layer, has, for example, a rectangular shape including a side 80y extending in the Y direction as the second side, and covers a portion of the upper surface of the laminate LMs.

[0113] The stop layer STPb, serving as the second stop layer, is formed by covering the upper surface of the resist layer 80, the side surface including edge 80y, and the upper surface and stepped portion of the laminated body LMs exposed from the resist layer 80. Alternatively, the stop layer STPb may be a semiconductor layer such as an amorphous silicon layer or a polycrystalline silicon layer, or a metal layer such as an aluminum layer, a tungsten layer, or a platinum layer, formed by sputtering, low-temperature CVD at temperatures below 90°C, or the like.

[0114] The resist layer 90, serving as the fourth mask layer, is formed such that it covers the upper surface and the side surface including edge 80y of the resist layer 80, separated by a stop layer STPb. Thus, the resist layer 90 also has a rectangular shape along the side surface including edge 80y of the resist layer 80. The resist layer 90 is formed such that the side surface of the resist layer 90 on the edge 80y side is positioned slightly recessed from the uppermost level of the step portion SR during the formation process. Furthermore, the stop layer STPb is interposed between the resist layers 80 and 90.

[0115] Then, similar to the case of the resist layer 70 described above, the following process is repeated multiple times: while thinning the resist layer 90 to allow it to recede, the first set of insulating layers NL and OL of the sequentially exposed laminates LMs are etched away. As a result, at the stepped portions that continue to be formed on the already formed stepped portion SR, the multiple step surfaces change from a substantially linear shape extending towards the central portion in the direction in which these stepped portions become higher.

[0116] In this way, the shape of the step surface that gradually protrudes from the center of the newly formed resist layer 90, which replaces the resist layer 62, is also reset.

[0117] like Figure 9 As shown in (b), after repeated thinning of the resist layer 90, the resist layer 90, which gradually became an arc shape, was completely removed, exposing the stop layer STPb between the resist layers 80 and 90. Thus, the arc shape formed by thinning was reset once.

[0118] Then, similarly to the case of the resist layer 60 described above, the stop layer STPb covering the resist layer 80 and the laminate LMs is removed, and the following process is repeated multiple times: while the resist layer 80 is thinned and pushed back, the first set of insulating layers NL and OL of the laminate LMs that are exposed in sequence are etched away. Thus, a stepped portion is further formed relative to the stepped portion SR that has been formed so far.

[0119] Furthermore, in the continuing step section, the multiple step surfaces change shape from a substantially straight line extending towards the central part in the direction in which these step sections become higher. Thus, as described above, the shape of the step section SR is formed by repeatedly changing the shape of the multiple step surfaces from a substantially straight line extending towards the central part in the direction in which the step section SR becomes higher.

[0120] Then, after repeated thinning, for example by oxygen plasma, the resist layer 80 is ashed and removed.

[0121] like Figure 10 As shown in (a), a resist layer 100, a stop layer STPc, and a resist layer 110 are sequentially formed on the upper surface of the laminate LMs.

[0122] The resist layer 100 has, for example, a rectangular shape including a side 100y extending along the Y direction, and covers a portion of the upper surface of the laminate LMs.

[0123] The stop layer STPc is formed by covering the upper surface of the resist layer 100, the side surface including the edge 100y, and the upper surface and stepped portion of the laminated body LMs exposed from the resist layer 100. Alternatively, the stop layer STPc may be a semiconductor layer such as an amorphous silicon layer or a polycrystalline silicon layer, or a metal layer such as an aluminum layer, a tungsten layer, or a platinum layer, formed by sputtering, low-temperature CVD at temperatures below 90°C, etc.

[0124] The resist layer 110 is formed such that it covers the upper surface of the resist layer 100 and the side surface including the edge 100y, separated by a stop layer STPc. Thus, the resist layer 110 also has a rectangular shape along the side surface of the resist layer 100, including the edge 100y. The resist layer 110 is formed such that the side surface of the resist layer 110 on the edge 100y side is positioned slightly recessed from the uppermost level of the step portion SR during the formation process. Furthermore, the stop layer STPc is interposed between the resist layers 100 and 110.

[0125] Then, similar to the case of the resist layer 90 described above, the following process is repeated multiple times: while the resist layer 110 is thinned and retracted, the first set of insulating layers NL and OL of the sequentially exposed laminate LMs are etched away. As a result, at the stepped portion that continues to be formed on the already formed stepped portion SR, the multiple step surfaces change from a substantially linear shape extending towards the central portion in the direction in which these stepped portions become higher.

[0126] like Figure 10As shown in (b), after repeated thinning of the resist layer 110, the resist layer 110 is completely removed, exposing the stop layer STPc between the resist layers 100 and 110. Thus, the arc shape formed by the thinning is reset once.

[0127] Then, similar to the case of the resist layer 80 described above, the stop layer STPc covering the resist layer 100 and the stack LMs is removed, and the following process is repeated multiple times: while the resist layer 100 is thinned and pushed back, the first set of insulating layers NL and OL of the stack LMs that are exposed in sequence are etched away.

[0128] Therefore, in addition to the stepped portion SR that has been formed so far, a further stepped portion is formed. Furthermore, as described above, the shape of the stepped portion SR is further formed by repeatedly changing the shape of the shape in which multiple stepped surfaces extend from a substantially straight line towards the central portion in the direction that the stepped portion SR becomes higher.

[0129] Then, after repeated thinning, the resist layer 100 is ashed and removed, for example by oxygen plasma.

[0130] like Figure 11 As shown in (a), a resist layer 120 is formed on the upper surface of the laminate LMs. At this time, the resist layer 120 is formed in such a way that one side of the resist layer 120 is positioned slightly backward from the uppermost level of the step portion SR during the formation process.

[0131] Then, the following process is repeated multiple times: while the resist layer 120 is thinned and retreated, the first set of insulating layers NL and OL of the sequentially exposed laminate LMs are etched away. As a result, the shape of the stepped portion SR is further formed by repeatedly changing the shape of the multiple stepped surfaces protruding from a substantially straight shape in the direction that the stepped portion SR becomes higher.

[0132] like Figure 11 As shown in (b), when the etching process of insulating layers NL and OL is performed up to the bottom insulating layers NL and OL of the laminate LMs, the entire stepped portion SR is formed on the laminate LMs. In addition, the laminate LMs have a rectangular shape with ends on both sides in the X direction and both sides in the Y direction.

[0133] Then, the resist layer 122, which is formed by multiple thinnings of the resist layer 120, is removed by ashing, for example, by oxygen plasma.

[0134] As described above, whenever new resist layers 70, 90, 110, and 120 are formed, the stepped portions, which are substantially straight-lined shapes protruding towards the central portion, continue to form on their upper sides, thereby forming the aforementioned... Figure 3 The stepped portion SR of the stepped surface SP shown in (a).

[0135] In addition, in the above Figures 4 to 11 In the example, when the new resist layers 90, 110, and 120 are formed, the ends of these resist layers 90, 110, and 120 in the X direction are positioned near the top of the already formed stepped portion, and thinning begins.

[0136] However, the method for forming the stepped portion SR is not limited to this. For example, the X-direction end of the newly formed resist layer can be positioned at the exposed surface of the laminate LMs, which is located at the lowest level of the already formed stepped portion and away from the central portion of the laminate LMs, and thinning can begin. In this case, the exposed surface of the already formed stepped portion and the laminate LMs is largely covered by the new resist layer. By starting thinning from this state, the newly formed stepped portion is formed toward the lowest level of the already formed stepped portion.

[0137] According to this method, new stepped sections can be formed without exposing the already formed stepped sections to plasma processing, thus making it easier to obtain stepped sections SR of the desired shape.

[0138] first, Figures 12-18 The state in which the stepped section SRd is formed is shown. Figures 12-18 It is a cross-sectional view along the Y direction of the stepped section SRd during the manufacturing process.

[0139] like Figure 12 As shown in (a), through the above Figure 4 In the process of (a), in the region where the stepped portion SRd will be formed later, a resist layer 60, a stop layer STPa and a resist layer 70 are also formed sequentially on the upper surface of the laminate LMs.

[0140] As described above, the resist layer 60, having an edge 60y extending in the Y direction and covering a portion of the upper surface of the laminate LMs, also has an edge 60x extending in the X direction as a third edge. The stop layer STPa also covers the side of the resist layer 60 including the edge 60x. The resist layer 70 also covers the side of the resist layer 60 including the edge 60x.

[0141] like Figure 12 As shown in (b), through the above Figure 4 (b) Figure 7In the process of (a), the following process is also repeatedly performed on the side of the resist layer 70 extending in the X direction: while the resist layer 70 is thinned and retracted, the insulating layers NL and OL of the stacked bodies LMs that are exposed in sequence are etched away. At this time, through repeated thinning, the side of the resist layer 70 extending in the X direction also becomes an arc-shaped shape with a central protrusion in the X direction.

[0142] Therefore, on the side surface of the resist layer 70 extending in the X direction, the multiple stepped surfaces of the stepped portion formed by removing one set of insulating layers NL and OL also change from a shape that extends in a substantially straight line to a shape that protrudes towards the central portion in the direction in which these stepped portions become higher.

[0143] In addition, through repeated thinning processes, the resist layer 70 was completely removed, as described above. Figure 7 Similarly, in the treatment of (a), the stop layer STPa is also exposed on the side of the resist layer 60, including the edge 60x. As a result, the arcuate shape formed by thinning on the side of the resist layer 70 extending in the X direction is also reset once by the stop layer STPa.

[0144] like Figure 13 As shown in (a), through the above Figure 7 (b) Figure 8 In the process of (b), the following process is also repeatedly performed on the side 60x extending along the X direction of the resist layer 60: while the resist layer 60 is thinned and retracted, the insulating layers NL and OL of the sequentially exposed laminate LMs are etched away. At this time, through repeated thinning, the side of the resist layer 60 extending along the X direction also becomes an arc-shaped shape with a central protrusion in the X direction.

[0145] Therefore, on the side surface of the resist layer 60 extending in the X direction, the multiple stepped surfaces of the stepped portion formed by removing one set of insulating layers NL and OL also change from a shape that extends in a substantially straight line to a shape that protrudes towards the central portion in the direction in which these stepped portions become higher.

[0146] Subsequently, as described above, the residual resist layer 62 is removed by ashing using oxygen plasma or the like.

[0147] like Figure 13 As shown in (b), through the above Figure 9 In the process of (a), in the region where the stepped portion SRd will be formed later, a resist layer 80, a stop layer STPb and a resist layer 90 are also formed sequentially on the upper surface of the laminate LMs.

[0148] As described above, the resist layer 80, which has an edge 80y extending in the Y direction and covers a portion of the upper surface of the laminate LMs, also has an edge 80x extending in the X direction as a fourth edge. However, in the region where the stepped portion SRd is formed, the resist layer 80 is formed on the laminate LMs such that the edge 80x is positioned approximately equal to the position of the edge 60x of the aforementioned resist layer 60. Thus, the resist layer 80 covers a portion of the already formed stepped portion.

[0149] The stop layer STPb also covers the side surface of the resist layer 80, including edge 80x. As described above, the stop layer STPb exists between the resist layers 80 and 90.

[0150] The resist layer 90 also covers the side surface of the resist layer 80, including edge 80x. However, in the region where the stepped portion SRd is formed, the resist layer 90 is formed on the laminate LMs such that the side surface covering edge 80x is positioned approximately equal to the position of the side surface of the resist layer 70 before thinning, extending in the X direction. Thus, the resist layer 90 covers the entire stepped portion that has already been formed. Furthermore, the newly formed resist layer 90 reshapes the arcuate shape formed by thinning.

[0151] like Figure 14 As shown in (a), the stop layer STPb on the upper surface of the laminate LMs exposed from the resist layer 90 is removed. Further, one set of insulating layers NL and OL on the exposed surface of the laminate LMs is removed. At this time, the stepped portion resulting from removing these insulating layers NL and OL is formed at a position overlapping the lowest level of the already formed stepped portion. Thus, the lowest level stepped portion is composed of two sets of insulating layers NL and OL.

[0152] like Figure 14 As shown in (b), the resist layer 90 is thinned to form a resist layer 91, and the stop layer STPb exposed from the resist layer 91 is removed. Furthermore, one set of insulating layers NL and OL on the exposed surface of the laminate LMs is removed. At this time, the stepped portion resulting from removing these insulating layers NL and OL is formed at a position overlapping the lowest level of the already formed stepped portion and the second level from the lowest level. Thus, the lowest level and the second level stepped portion are composed of two sets of insulating layers NL and OL.

[0153] like Figure 15 As shown in (a), the resist layer 91 is further thinned to form a resist layer 92, the stop layer STPb exposed from the resist layer 92 is removed, and further, one set of insulating layers NL and OL on the exposed surface of the laminate LMs is removed. Thus, the step portions of the lowest level, the second level, and the third level are composed of two sets of insulating layers NL and OL.

[0154] In these processes, at the stepped portions that overlap with the already formed stepped portions, multiple step surfaces also change from a shape that extends substantially in a straight line to a shape that protrudes towards the central portion in the direction in which these stepped portions become higher.

[0155] like Figure 15 As shown in (b), by further thinning, the resist layer 92 is removed, exposing the stop layer STPb located between the resist layers 80 and 92. Thus, the arcuate shape formed by the thinning is reset once by the stop layer STPb.

[0156] like Figure 16 As shown in (a), on the side 80x extending along the X direction of the resist layer 80, the following process is also repeatedly performed: while the resist layer 80 is thinned and retracted, the insulating layers NL and OL of the sequentially exposed laminate LMs are etched away. At this time, through repeated thinning, the side of the resist layer 80 extending along the X direction also becomes an arc-shaped shape with a central protrusion in the X direction.

[0157] Thus, each level of the stepped section is composed of three sets of insulating layers NL and OL. In addition, on the side side of the resist layer 80 extending in the X direction, at the stepped section formed overlapping with the already formed stepped section, multiple step surfaces also change from a substantially straight-line extending shape to a shape protruding towards the central part in the direction in which these stepped sections become higher.

[0158] Subsequently, the resist layer 82, formed by multiple thinning of the resist layer 80, is removed by ashing using oxygen plasma or the like.

[0159] like Figure 16 As shown in (b), through the above Figure 10 In the process of (a), in the region where the stepped portion SRd will be formed later, a resist layer 100, a stop layer STPc and a resist layer 110 are also formed sequentially on the upper surface of the laminate LMs.

[0160] As described above, the resist layer 100, which has an edge 100y extending in the Y direction and covers a portion of the upper surface of the laminate LMs, also has an edge 100x extending in the X direction. However, in the region where the stepped portion SRd is formed, the resist layer 100 is formed on the laminate LMs such that the edge 100x is positioned approximately equal to the edge 80x of the aforementioned resist layer 80. Thus, the resist layer 100 covers a portion of the already formed stepped portion.

[0161] The stop layer STPc also covers the side surface of the resist layer 100, including edge 100x. As described above, the stop layer STPb exists between the resist layers 100 and 110.

[0162] The resist layer 110 also covers the side surface of the resist layer 100, including the edge 100x. However, in the region where the stepped portion SRd is formed, the resist layer 110 is formed on the laminate LMs such that the side surface covering the edge 100x is positioned approximately equal to the side surface of the resist layer 90 before thinning, which extends in the X direction. Thus, the resist layer 110 covers the entire stepped portion that has already been formed. In addition, the arcuate shape formed due to thinning is reset once by the newly formed resist layer 110.

[0163] like Figure 17 As shown in (a), the following process is repeated multiple times: while the resist layer 100 is thinned and retreated, the first set of insulating layers NL and OL of the sequentially exposed laminate LMs are etched away. As a result, a new stepped portion is formed, overlapping with a portion of the stepped portion SRd that has been formed so far.

[0164] At this time, at the stepped portion that overlaps with the already formed stepped portion SRd, multiple step surfaces also change from a shape that extends in a substantially straight line to a shape that protrudes towards the central portion in the direction in which these stepped portions become higher.

[0165] Furthermore, by repeatedly thinning and removing the resist layer 110, the stop layer STPc located between the resist layers 100 and 110 is exposed. As a result, the arc-shaped structure formed by the thinning is reset once by the stop layer STPc.

[0166] like Figure 17 As shown in (b), the following process is repeated multiple times: while the resist layer 100 is thinned and retreated, the first set of insulating layers NL and OL of the sequentially exposed laminate LMs are etched away. At this time, through multiple thinning, the side of the resist layer 100 extending in the X direction also becomes an arc-shaped shape with a central protrusion in the X direction.

[0167] Thus, each level of the stepped portion is composed of three sets of insulating layers NL and OL. In addition, on the side side of the resist layer 100 extending in the X direction, at the stepped portion formed overlapping with the already formed stepped portion, multiple step surfaces also change from a substantially straight-line extending shape to a shape protruding towards the central portion in the direction in which these stepped portions become higher.

[0168] Subsequently, the resist layer 102, which is formed by multiple thinning of the resist layer 100, is removed by ashing using oxygen plasma or the like.

[0169] like Figure 18 As shown in (a), through the above Figure 11 In the treatment of (a), a resist layer 120 is also formed on the upper surface of the laminate LMs in the formation area of ​​the stepped portion SRd.

[0170] As described above, the resist layer 120 covering a portion of the upper surface of the laminated bodies LMs also has a side extending in the X direction. However, in the region where the stepped portion SRd is formed, the resist layer 120 is formed on the laminated bodies LMs such that the side extending in the X direction is positioned approximately equal to the sidewalls of the edges 60x and 80x covering the aforementioned resist layers 70 and 90. Thus, the resist layer 120 covers the entire stepped portion that has been formed.

[0171] In addition, the arc shape formed due to thinning is reset once through the newly formed resist layer 120.

[0172] like Figure 18 As shown in (b), the following process is repeated multiple times: while the resist layer 120 is thinned and retreated, the first set of insulating layers NL and OL of the laminated LMs exposed sequentially are etched away. This forms a new stepped portion, overlapping with a portion of the stepped portion SRd already formed. Furthermore, the etching process of insulating layers NL and OL is continued until the bottom insulating layers NL and OL of the laminated LMs are reached, forming the entire stepped portion SRd on the laminated LMs.

[0173] At this time, at the stepped portion that overlaps with the already formed stepped portion SRd, multiple step surfaces also change from a shape that extends in a substantially straight line to a shape that protrudes towards the central portion in the direction in which these stepped portions become higher.

[0174] Subsequently, as described above, the residual resist layer 122 is removed by ashing using oxygen plasma or the like.

[0175] As described above, whenever new resist layers 70, 90, 110, and 120 are formed, multiple stepped portions with shapes that change from substantially linear extensions to protruding towards the central portion are formed in an overlapping manner, thereby forming a layer having the aforementioned characteristics. Figure 3 The stepped portion SRd of the stepped surface SPd shown in (b).

[0176] That is, in Figure 3 In (b), the step surface SPd located near the lowest level of the step portion SRd, which is one of the multiple step surfaces SPd that extend substantially in a straight line along the X direction, is formed by transferring the side surface of the newly formed resist layers 70, 90, 110, 120 before thinning.

[0177] In addition, Figure 3In (b), the step surface SPd at point P2, which is located between the lowest and highest levels of the step portion SRd, is formed by transferring the sides of the resist layers 60, 80, and 100 after removing the stop layers STPa, STPb, and STPc.

[0178] Then, an insulating layer 51 is formed covering the stepped portions SR and SRd. In addition, an insulating layer 52 is formed covering the unprocessed upper surface of the laminate LMs and the insulating layer 51 on the stepped portions SR and SRd.

[0179] then, Figures 19-21 The diagram shows the state in which column PL is formed. Figures 19-21 This is a cross-sectional view along the Y direction of the region that will later become the storage region MR.

[0180] like Figure 19 As shown in (a), in the region that subsequently becomes the storage region MR, a lower source line DSLa, an intermediate insulating layer SCN, and an upper source line DSLb are sequentially formed. Furthermore, a stacked body LMs is formed on the upper source line DSLb, which is formed by alternately stacking multiple insulating layers NL and multiple insulating layers OL. Additionally, an insulating layer 52 is formed on the upper surface of the stacked body LMs.

[0181] In this state, multiple memory holes MH are formed that penetrate the insulating layer 52, the stacked body LMs, the upper source line DSLb, and the intermediate insulating layer SCN to reach the lower source line DSLa.

[0182] like Figure 19 As shown in (b), a storage layer ME is formed within the memory hole MH. This storage layer ME is formed by sequentially stacking a barrier insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN from the outer periphery of the memory hole MH. The storage layer ME is also formed on the upper surface of the insulating layer 52. As described above, the barrier insulating layer BK and the tunnel insulating layer TN are, for example, silicon oxide layers, and the charge storage layer CT is, for example, a silicon nitride layer.

[0183] like Figure 19 As shown in (c), a channel layer CN, such as a polycrystalline silicon layer or an amorphous silicon layer, is formed inside the storage layer ME. The channel layer CN is also formed on the upper surface of the insulating layer 52, separated from the storage layer ME.

[0184] In addition, a core layer CR, such as a silicon oxide layer, is filled inside the channel layer CN. The core layer CR is also formed on the upper surface of the insulating layer 52, separated from the storage layer ME and the channel layer CN.

[0185] like Figure 20As shown in (a), the upper surface of the insulating layer 52 and the core layer CR within the memory hole MH are etched back. At this time, the channel layer CN of the substrate is used as a stop layer, and the core layer CR is etched while maintaining a selectivity ratio with the channel layer CN. This causes a partial depression of the core layer CR within the memory hole MH, forming a depression DN at the upper end of the memory hole MH. Furthermore, the core layer CR on the upper surface of the insulating layer 52 is removed, exposing the channel layer CN.

[0186] like Figure 20 As shown in (b), the upper surface of the insulating layer 52 and the channel layer CN within the memory hole MH are etched back. At this time, the memory layer ME of the substrate is used as a stop layer, and the channel layer CN is etched while establishing a selectivity ratio with the memory layer ME. As a result, a portion of the channel layer CN within the memory hole MH is pushed downwards, and the recess DN at the upper end of the memory hole MH is expanded. The upper end of the core layer CR protrudes from the center of the recess DN. Furthermore, the channel layer CN on the upper surface of the insulating layer 52 is removed, exposing the memory layer ME.

[0187] like Figure 20 As shown in (c), the upper surface of the insulating layer 52 and the memory layer ME within the memory hole MH are etched back. At this time, the etching amount is adjusted so as not to remove the insulating layer 52 of the substrate. As a result, the memory layer ME within the memory hole MH partially recedes downwards, and the recess DN at the upper end of the memory hole MH is further extended. The upper end of the core layer CR protruding towards the center of the recess DN is also removed, and the bottom surface of the recess DN becomes approximately flat. Furthermore, the memory layer ME on the insulating layer 52 is removed, exposing the insulating layer 52.

[0188] in addition, Figure 20 The processing of (a) to (c) is controlled to be, in Figure 20 After the treatment of (c), the bottom surface of the recessed DN remains at the height position within the insulation layer 52, without reaching the uppermost insulation layer NL.

[0189] like Figure 21 As shown in (a), a capping layer CP is formed by filling the interior of the recessed DN with a polycrystalline silicon layer or an amorphous silicon layer.

[0190] like Figure 21 As shown in (b), the upper surfaces of the insulating layer 52 and the capping layer CP are etched back together. As a result, the thickness of the insulating layer 52 and the capping layer CP is reduced.

[0191] like Figure 21 As shown in (c), an insulating layer 52, thinned by etch-back, is deposited. Thus, the upper surface of the capping layer CP is covered by the insulating layer 52, thereby forming a pillar PL in the region that subsequently becomes the storage region MR.

[0192] However, at this stage, the channel layer CN of the pillar PL is completely covered by the storage layer ME and does not come into contact with the intermediate insulating layer SCN, which will later become the intermediate source line BSL.

[0193] then, Figures 22-24 The diagram shows the state in which the intermediate source line BSL and word line WL are formed. This is consistent with the above. Figures 19-21 Similarly, Figures 22-24 The cross-section along the Y direction of the region that will later become the storage region MR is shown.

[0194] like Figure 22 As shown in (a), a slit ST is formed that penetrates the insulating layer 52, the laminate LMs, and the upper source line DSLb to reach the intermediate insulating layer SCN. The slit ST also extends within the laminate LMs in a direction along the X direction.

[0195] like Figure 22 As shown in (b), an insulating layer 55p is formed on the sidewall of the slit ST facing the Y direction.

[0196] like Figure 22 As shown in (c), the intermediate insulating layer SCN, which is held between the lower source line DSLa and the upper source line DSLb, is removed by a removal liquid such as hot phosphoric acid, which dissolves the silicon nitride layer, through a slit ST protected by the insulating layer 55p on the sidewall.

[0197] Thus, a gap layer GPs is formed between the lower source line DSLa and the upper source line DSLb. Additionally, a portion of the storage layer ME on the outer periphery of the pillar PL is exposed within the gap layer GPs. At this time, since the sidewalls of the slit ST are protected by the insulating layer 55p, it is possible to prevent the insulating layer NL within the laminated stack LMs from being removed.

[0198] like Figure 23 As shown in (a), the drug solution is allowed to flow appropriately into the interstitial layers GPs through the slit ST, sequentially removing the barrier insulation layer BK, charge storage layer CT, and tunnel insulation layer TN exposed within the interstitial layers GPs. Consequently, the storage layer ME is removed from a portion of the sidewall of the pillar PL, exposing a portion of the inner channel layer CN within the interstitial layers GPs.

[0199] like Figure 23 As shown in (b), a raw material gas, such as amorphous silicon, flows into the slit ST, whose sidewall is protected by an insulating layer 55p, and the interstitial layers GPs are filled with amorphous silicon. In addition, the entire structure including the laminate is heated to polycrystalline the amorphous silicon filled in the interstitial layers GPs, forming an intermediate source line BSL containing polycrystalline silicon.

[0200] Thus, a portion of the channel layer CN of the pillar PL is connected to the source line SL on the side via the intermediate source line BSL.

[0201] like Figure 23 As shown in (c), the insulating layer 55p of the slit ST sidewall is removed in one step.

[0202] like Figure 24 As shown in (a), a removal liquid, such as hot phosphoric acid, flows into the interior of the laminate LMs through the slit ST from which the insulating layer 55p on the sidewalls has been removed, thereby removing the insulating layer NL of the laminate LMs. This forms a laminate LMg having multiple gap layers GP with the insulating layer NL between the insulating layers OL removed.

[0203] Furthermore, a laminate containing multiple interstitial layers (GP) becomes a fragile structure. Such a fragile laminate, LMG, is supported, for example, by multiple pillars (PL). This helps to suppress the deflection of residual insulating layer (OL), and the tilting or collapse of the laminate, LMG.

[0204] like Figure 24 As shown in (b), for example, a raw material gas of conductive material such as tungsten or molybdenum flows into the interior of the laminate LMG through the slit ST, and the interstitial layer GP of the laminate LMG is filled with conductive material to form multiple word lines WL. Thus, a laminate LM is formed by alternating layers of multiple word lines WL and multiple insulating layers OL.

[0205] As described above, the process of forming the intermediate source line BSL from the intermediate insulating layer SCN and the process of forming the word line WL from the insulating layer NL are also called substitution processes.

[0206] Then, contacts CC are formed on the stepped portion SR. That is, multiple contact holes are formed simultaneously, penetrating the insulating layers 52 and 51 and reaching the word lines WL of each level constituting the stepped portion SR. An insulating layer 56 and a conductive layer 22 are formed in the contact holes (see reference). Figure 2 (a)

[0207] Additionally, a plate-shaped contact LI is formed as a source line contact. That is, an insulating layer 55 is formed on the sidewall of the slit ST, and a conductive layer 21 is filled inside the insulating layer 55. However, it is also possible to fill the slit ST with an insulating layer 55 instead of a conductive layer 21, thus forming a plate-shaped portion that does not function as a source line contact.

[0208] Furthermore, an insulating layer 53 is formed on the insulating layer 52, and a plug V0 is formed through the insulating layer 53 to connect with the plate-shaped contact LI and the contact CC, respectively. Additionally, a plug CH is formed through the insulating layers 53 and 52 to connect with the post PL. Further, an insulating layer 54 is formed on the insulating layer 53, and upper wiring MX and bit line BL, etc., are formed to connect with the plugs V0 and CH, respectively.

[0209] Alternatively, for example, by using a dual damascene method, plugs V0, CH, upper-layer routing MX, and bit lines BL can be formed simultaneously.

[0210] Based on the above description, a semiconductor memory device 1 according to the embodiment is manufactured.

[0211] (Comparative Example)

[0212] In semiconductor memory devices such as three-dimensional non-volatile memory, step portions are sometimes formed by processing the multiple word lines into a stepped shape, for example, in order to bring out multiple word lines stacked in a laminate. The step portions are formed, for example, by repeatedly thinning the resist layer and etching the laminate before replacement.

[0213] However, the amount of retreat of the resist layer's sides caused by thinning differs near the center and near the ends. That is, the retreat is small near the center of the resist layer's sides and large near the ends. Therefore, by repeatedly performing thinning, the resist layer's sides will become an arc-shaped structure with a protruding central portion.

[0214] This bow shape is also transferred onto multiple letter lines, and the stepped surfaces of these letter lines also change into a bow shape that protrudes towards the center in the direction of the step portion becoming higher. Figure 25 An example of the configuration of a semiconductor memory device having a stepped portion formed as described above is shown.

[0215] Figure 25 This is an XY cross-sectional view showing an example of the configuration of the stepped portions SRz and SRdz in the semiconductor memory device involved in the comparative example.

[0216] like Figure 25 As shown in (a), the stepped portion SRz of the comparative example has multiple step surfaces SPz, which change shape from a substantially straight line extending towards the central portion in the direction in which the stepped portion SRz increases in height. This change of the multiple step surfaces SPz is repeated multiple times from the lower side to the upper side of the stepped portion SRz.

[0217] Here, regarding the variation of multiple step surfaces SPz from a shape that extends substantially in a straight line to a shape that protrudes towards the central part, a resist layer will undergo multiple thinnings, only being reset at the time when the next resist layer is formed.

[0218] Therefore, at the stepped portion SRz near both ends of the laminate LMz in the Y direction, the arcuate shape of the step surface SPz becomes significant, and a portion of the contact CCz is positioned extending from the platform surface TRz of the word line WL to which it is connected. This could potentially lead to poor connection between the contact CCz and the word line WL, or a short circuit between the upper and lower word lines WL.

[0219] like Figure 25 As shown in (b), the comparative example semiconductor memory device also has a dummy stepped portion SRdz without a contact CCz. The stepped portion SRdz of the comparative example also has multiple stepped surfaces SPdz, which change from a substantially straight-line shape to a shape that protrudes towards the central portion in the direction in which the stepped portion SRdz becomes higher.

[0220] Here, when a resist layer is thinned multiple times and a new resist layer is formed, at the dummy step portion SRdz, the side of the next resist layer's step portion SRdz is positioned approximately equal to the position of the side of the previous resist layer before thinning. Thus, each time a new resist layer is formed, the stepped portions, repeatedly formed by thinning these resist layers, are formed in an overlapping manner.

[0221] Therefore, in the stepped section SRdz of the comparative example, the step surface SPdz, which extends substantially linearly in the X direction, is positioned near the lowest level of the stepped section SRdz. On the other hand, unlike the stepped section SRd of the above embodiment, in the stepped section SRdz of the comparative example, the step surface SPdz, which extends substantially linearly in the X direction, is not positioned between the lowest and highest levels of the stepped section SRd.

[0222] According to the manufacturing method of the semiconductor memory device 1 according to the embodiment, a resist layer 60 having an edge 60y is formed above the stacked body LMs, a stop layer STPa covering the edge 60y is formed, and a resist layer 70 covering the resist layer 60 including the edge 60y is formed. The following process is repeatedly performed multiple times: while thinning these resist layers 60 and 70 to move backward in the X direction, a set of insulating layers NL and OL of the stacked body LMs exposed from the resist layers 60 and 70 are etched away.

[0223] Therefore, the stepped portion SR can be formed while properly resetting the shape of multiple stepped surfaces SP that extend substantially in a straight line towards the central portion in the direction of increasing height of the stepped portion SR. Thus, it is possible to prevent the contact CC from detaching from the platform surface TR of the word line WL to which it is connected, and to more reliably connect multiple word lines WL to multiple contacts CC.

[0224] According to the manufacturing method of the semiconductor memory device 1 according to the embodiment, when forming the resist layer 90, the resist layer 90 is formed in such a way as covering the step portion SRd, and the following process is repeated multiple times: while the resist layer 90 is also moved backward in the Y direction by thinning, a set of insulating layers NL and OL of the laminate LMs exposed from the resist layer 90 are etched away.

[0225] Therefore, multiple sets of insulating layers NL and OL are overlapped with the already formed stepped portion SRd and processed into a stepped shape. Thus, the step length of the stepped portion SRd can be made, for example, shorter than that of the stepped portion SR. As described above, unlike the stepped portion SR which has the lead-out function of the word line WL, the dummy stepped portion SRd becomes an ineffective region in the semiconductor memory device 1. By shortening the step length of such a stepped portion SRd, the semiconductor memory device 1 can be miniaturized, or the memory region MR can be expanded, resulting in a higher-performance semiconductor memory device 1.

[0226] Furthermore, the stepped portion SRd formed as described above differs from the stepped portion SRdz of the comparative example. It has a step surface SPd that is disposed near the lowest level of the stepped portion SRd and extends substantially in a straight line, and a step surface SPd that is disposed between the lowest and highest levels of the stepped portion SRd and extends substantially in a straight line. Therefore, the fact that the stepped portion SRd has this shape can serve as evidence that the semiconductor memory device 1 is manufactured using the above-described manufacturing method of stop layers STPAa to STPc.

[0227] According to the manufacturing method of the semiconductor memory device 1 in the embodiment, the stop layers STPa to STPc are, for example, semiconductor layers such as amorphous silicon layers or polycrystalline silicon layers, or metal layers such as aluminum layers, tungsten layers, or platinum layers. Therefore, the stop layers STPa to STPc can remain without being removed by oxygen plasma or the like, and the arcuate shape of the sides of the resist layers 70, 90, and 110 can be reset.

[0228] (Variation Example 1)

[0229] Next, use Figures 26-29 The semiconductor memory device of Modification 1 of the Embodiment 1 will be described. In the semiconductor memory device of Modification 1, when the dummy step portion SRda is formed, each time a new resist layer 70a, 90a, 110a is formed, the position of the side of these resist layers 70a, 90a, 110a is offset, which is different from the embodiment described above.

[0230] Figures 26-28 This is a cross-sectional view showing a portion of the steps of a method for forming a stepped portion SRda in a semiconductor memory device according to a modified example 1 of the embodiments.

[0231] When forming the dummy step portion SRda of the semiconductor memory device in Modified Example 1, the same procedure as in the above embodiment is also performed. Figure 12 (a)~ Figure 13 (a) The same treatment.

[0232] like Figure 26 As shown in (a), in Figure 13The upper surface of the laminated LMs after treatment (a) is sequentially formed with a resist layer 80a, a stop layer STPd, and a resist layer 90a. That is, Figure 26 The process shown in (a) is the same as that described in the above embodiment. Figure 13 (b) equivalent treatment.

[0233] The resist layer 80a, which is the third resist layer, has a fourth side 80xa extending in the X direction. Here, when forming the resist layer 80a, the resist layer 80a is positioned without high-precision alignment on the dummy step portion SRda side. Therefore, sometimes the side 80xa of the resist layer 80a is positioned offset from the position of the side 60x of the aforementioned resist layer 60.

[0234] exist Figure 26 In example (a), the edge 80xa of the resist layer 80a is positioned slightly offset from the position of the edge 60x of the resist layer 60 to the inside of the laminate LMs.

[0235] The stop layer STPd, serving as the second stop layer, is formed by covering the side surface of the resist layer 80a, including the edge 80xa, and the stepped portion of the laminate LMs exposed from the resist layer 80a. Alternatively, the stop layer STPd may be a semiconductor layer such as an amorphous silicon layer or a polycrystalline silicon layer, or a metal layer such as an aluminum layer, a tungsten layer, or a platinum layer, formed by sputtering, low-temperature CVD at temperatures below 90°C, or the like.

[0236] The resist layer 90a, serving as the fourth mask layer, is formed such that it covers the side surface of the resist layer 80a, including the edge 80xa, across the stop layer STPd. Additionally, in Figure 26 In example (a), the resist layer 90a is also positioned slightly offset from the position of the side surface of the laminate LMs before thinning, which is provided with the resist layer 70 in the X direction.

[0237] like Figure 26 As shown in (b), the resist layers 90a and 80a, whose side positions are slightly offset inward towards the inside of the laminate LMs, are successively thinned, while multiple sets of insulating layers NL and OL are etched away, forming a new stepped portion that overlaps with the already formed stepped portion. Thus, the stepped portion SRda has a platform surface narrower than that of the stepped portion SRd in the above embodiment.

[0238] Then, the resist layer 82a formed by thinning the resist layer 80a is removed by ashing, for example, using oxygen plasma.

[0239] like Figure 27As shown in (a), a new resist layer 100a, a stop layer STPe, and a resist layer 110a are formed sequentially. That is, Figure 27 The process shown in (a) is the same as that described in the above embodiment. Figure 16 (b) equivalent treatment.

[0240] The resist layer 100a has an edge 100xa extending in the X direction. Here, when forming the resist layer 100a, the resist layer 100a is positioned on the dummy step portion SRda side without high-precision alignment. Therefore, sometimes the edge 100xa of the resist layer 100a may be positioned offset from a certain position of the edges 60x and 80xa of the aforementioned resist layers 60 and 80a.

[0241] exist Figure 27 In example (a), the edge 100xa of the resist layer 100a is positioned slightly offset from the position of the edge 60x of the resist layer 60 to the outside of the laminate LMs.

[0242] The stop layer STPe is formed in such a way that it covers the side surface of the resist layer 100a, including the edge 100xa, and the stepped portion of the laminate LMs exposed from the resist layer 100a. Alternatively, the stop layer STPde may be a semiconductor layer such as an amorphous silicon layer or a polycrystalline silicon layer, or a metal layer such as an aluminum layer, a tungsten layer, or a platinum layer, and is formed by sputtering, low-temperature CVD at temperatures below 90°C, etc.

[0243] The resist layer 110a is formed such that it covers the side surface of the resist layer 100a, including the edge 100xa, with a stop layer STPe in between. Additionally, in Figure 27 In example (a), the resist layer 110a is also positioned slightly offset from the position of the side surface of the laminate LMs before thinning, which is provided with the resist layer 70 in the X direction.

[0244] like Figure 27 As shown in (b), the resist layers 110a and 100a, which are slightly offset from the outside of the laminate LMs, are thinned in sequence, while multiple sets of insulating layers NL and OL are etched away, and new stepped portions are formed by overlapping with the already formed stepped portions.

[0245] Thus, the stepped section SRda has a shape in which stepped portions consisting of one set of insulating layers NL and OL are alternately repeated and formed by two sets of insulating layers NL and OL.

[0246] Then, the resist layer 102a, which is formed by multiple thinning of the resist layer 100a, is removed by ashing, for example, using oxygen plasma.

[0247] like Figure 28 As shown in (a), a new resist layer 120a is formed. That is, Figure 28 The process shown in (a) is the same as that described in the above embodiment. Figure 18 (a) equivalent treatment.

[0248] The resist layer 120a has a side extending in the X direction. Here, when forming the resist layer 120a, the resist layer 120a is positioned without high-precision alignment on the dummy step portion SRda side. Therefore, sometimes the side of the resist layer 120a may be positioned offset from a certain position of the edges 60x, 80xa, and 100xa where the aforementioned resist layers 60, 80a, and 100a are also disposed.

[0249] exist Figure 28 In example (a), the side of the resist layer 120a is positioned slightly offset from the position of the edge 60x of the resist layer 60 disposed therein towards the inside of the laminate LMs, and is located between the position of the edge 60x of the resist layer 60 and the position of the edge 80xa of the resist layer 80a.

[0250] like Figure 28 As shown in (b), the resist layer 120a, which is slightly offset from the side to the inside of the laminate LMs, is thinned in sequence, while multiple sets of insulating layers NL and OL are etched away, and a new stepped portion is formed by overlapping with the already formed stepped portion.

[0251] Therefore, the etching process of insulating layers NL and OL is carried out to the bottom insulating layers NL and OL of the laminate LMs, forming the entire stepped portion SRda on the laminate LMs.

[0252] Then, the resist layer 122a, which is formed by multiple thinning of the resist layer 120a, is removed by ashing, for example, using oxygen plasma.

[0253] exist Figure 29 The diagram shows a stepped section SRda that is formed as described above and subsequently replaced to become a stack of multiple word lines WL and multiple insulating layers OL.

[0254] Figure 29 This is a top view showing an example of the configuration of the stepped portions SR and SRda of the semiconductor memory device 2 according to the modified example 1 of the embodiment. Figure 29 (a) is a top view of the semiconductor memory device 2 including the stepped section SR. Figure 29 (b) is a top view of the semiconductor memory device 2 including the stepped section SRda.

[0255] like Figure 29As shown, the semiconductor memory device 2 includes a stack LMa, which comprises the above-mentioned... Figures 26-28 In the manufacturing process of the processing, multiple word lines WL and multiple insulating layers OL are stacked together through a replacement process. A stepped portion SR with the lead-out function of word lines WL and the aforementioned dummy stepped portion SRda are formed on the stacked body LMa.

[0256] like Figure 29 As shown in (a), the stepped portion SR of the semiconductor memory device 2 also has the same characteristics as in the above embodiment. Figure 3 The stepped section SR shown in (a) has the same configuration. That is, the stepped surface group SPG, which includes multiple stepped surfaces SP that change shape from a substantially straight shape to a central part, is repeatedly arranged from the lower side to the upper side of the stepped section SR.

[0257] like Figure 29 As shown in (b), the step surface SPda of the stepped portion SRda also includes: the step surface SPda that extends substantially in a straight line along the X direction as the fourth and fifth step surfaces, and the step surface SPda that has an arc-shaped shape with a central portion protruding in the X direction as the third step surface.

[0258] The step surfaces SPda, which have an arcuate shape, are distributed throughout the entire stepped portion SRda extending along the Y direction. The step surfaces SPda, which extend substantially in a straight line along the X direction, include: a plurality of step surfaces SPda as fourth step surfaces located in region A1 near the lowest level of the stepped portion SRda, and a plurality of step surfaces SPda as fifth step surfaces located in region A2 between the lowest and highest levels of the stepped portion SRda.

[0259] As described above, whenever new resist layers 70, 90a, 110a, and 120a are formed, the stepped portions of the multiple stepped surfaces SPda, which extend substantially in a straight line and protrude towards the central portion, are formed in a manner that overlaps each other with a slight forward and backward offset. Thus, a layer having the aforementioned... Figure 29 The stepped portion SRda of the stepped surface SPda shown in (b).

[0260] That is, the several stepped surfaces SPda that are arranged in the region A1 near the lowest level of the stepped portion SRda among the multiple stepped surfaces SPda that extend substantially in a straight line along the X direction are stepped surfaces SPda formed by transferring the side surfaces of the newly formed resist layers 70, 90a, 110a, and 120a before thinning.

[0261] In addition, several step surfaces SPda, which are substantially linearly extending along the X direction, and located in region A2 between the lowest and highest levels of the step section SRda, are step surfaces SPda formed by transferring the sides of the resist layers 60, 80a, and 100a after removing the stop layers STPa, STPd, and STPe.

[0262] Thus, even when the resist layers 70, 90a, 110a, and 120a are formed in a state of offset from each other, the stepped portion SRda is different from the stepped portion SRz of the comparative example above, and has several stepped surfaces SPda that are arranged between the lowest and highest levels of the stepped portion SRda and extend substantially in a straight line.

[0263] The manufacturing method of the semiconductor memory device 2 according to Modification 1 achieves the same effect as the manufacturing method of the semiconductor memory device 1 in the above embodiment.

[0264] (Variation Example 2)

[0265] Next, use Figure 30 The semiconductor memory device of Modification 2 of the Embodiment 2 will be described. In the semiconductor memory device of Modification 2, the unwanted portions are removed in advance when forming the stop layer, which is different from the embodiment described above.

[0266] Figure 30 This is a cross-sectional view of a step in a method for forming a stepped portion in a semiconductor memory device according to a modified embodiment 2. Figure 30 The process shown is equivalent to the process of forming the resist layer 60 and the stop layer STPa in the above embodiment.

[0267] like Figure 30 As shown in (a), similarly to the embodiment described above, a rectangular resist layer 60 is formed covering a portion of the upper surface of the laminated LMs. The resist layer 60, like in the embodiment described above, has a rectangular shape. Figure 30 The side 60x shown in (a) is the side surface extending in the X direction and the top surface extending in the Y direction.

[0268] In addition, similarly to the above embodiment, a stop layer STPa is formed covering the upper surface of the resist layer 60, the side surface extending in the X direction, and the upper surface of the laminate LMs exposed from the resist layer 60.

[0269] like Figure 30As shown in (b), the upper surface of the stop layer STPa is etched back to remove the stop layer STPa from the upper surface of the resist layer 60 and from the upper surface of the laminate LMs exposed from the resist layer 60. This forms a stop layer STPf covering the side surface of the resist layer 60 extending in the X direction.

[0270] Then, similarly to the above embodiment, a resist layer 70 is formed that covers the resist layer 60 with a stop layer STPf, and these resist layers 60 and 70 are used to form a stepped portion.

[0271] Furthermore, the above-described process of removing unwanted portions of the stop layer STPa can also be applied to the stop layers STPb and STPC of the above embodiments, as well as the stop layer STPe of the above-described variation 1.

[0272] According to the semiconductor memory device manufacturing method of Modification 2, when forming the stop layer STPf, the stop layer STPa is removed from the upper surface of the resist layer 60 and the upper surface of the laminate. This allows unwanted portions of the stop layer STPa to be removed simultaneously. Furthermore, by removing unwanted portions beforehand, the process of removing the stop layer STPf can be omitted during each repeated thinning of the resist layer 70.

[0273] Therefore, it is possible to reduce the number of processes and form stepped sections with simpler processing.

[0274] The manufacturing method of the semiconductor memory device 2 according to Modification 2, except that, achieves the same effect as the manufacturing method of the semiconductor memory device 1 in the above embodiment.

[0275] (Other variations)

[0276] Furthermore, in the above embodiments and variations 1 and 2, when forming the stepped portions SR and SRd, the formation of the resist layer containing the stop layers STPa to STPc is repeated four times. However, the number of times the resist layer is formed can be appropriately changed depending on the number of layers in the laminate LM. The number of times the resist layer is formed may be less than four times, or more than five times, or the entire stepped portion may be formed by forming the resist layer only once.

[0277] Furthermore, in the above-described embodiments and variations 1 and 2, only one stop layer STP is used within each resist layer. However, the number of stop layers STP within the resist layer is arbitrary, and multiple stop layers can be used within the resist layer. As an example, in Figure 31 The diagram shows the state of the two storage stop layers STPa and STPg.

[0278] Figure 31This is a cross-sectional view showing the state in which two stop layers STPa and STPg are formed during the manufacturing method of a semiconductor memory device according to other variations of the embodiment. For example... Figure 31 As shown, in other modified manufacturing methods, for example, a resist layer 130 covered by a stop layer STPg is also formed within the resist layer 60 of the above embodiment.

[0279] More specifically, a resist layer 130 is formed on a portion of the upper surface of the laminated LMs, a stop layer STPg is formed covering the resist layer 130 and the upper surface of the laminated LMs exposed from the resist layer 130, and a resist layer 60 is formed covering the resist layer 130 through the stop layer STPg. The subsequent steps are the same as in the embodiment described above.

[0280] In this way, a multi-layer stop layer STP is formed by forming a single resist, which allows for a more precise resetting of the arc shape of the stepped surface.

[0281] Alternatively, the method described in Modification 2 can also be applied under the above circumstances. That is, the unwanted portions of the stop layers STPg and STPa can be removed from the upper surfaces of the resist layers 130 and 60 and the laminate LMs before each formation of the respective stop layers STPg and STPa.

[0282] In the above embodiments and variations 1 and 2, the stepped portions SR, SRd, and SRda are respectively disposed at the ends of the laminate LM in the X and Y directions. However, stepped portions SR, SRd, and SRda, which are formed by machining multiple letter lines WL into a stepped shape, can also be disposed in the central portion of the laminate LM. In this case, for example, the central portion of the laminate LM can be machined into a mortar shape, so that the stepped portions SR disposed on one or both sides extending in the Y direction have an outgoing function. In this case, dummy stepped portions SRd and SRda are formed on both sides extending in the X direction.

[0283] In the above embodiments and variations 1 and 2, the channel layer CN of the pillar PL is connected to the source line SL on its side. However, the channel layer CN may also be connected to the source line SL on its bottom surface, etc. In this case, the storage layer ME on the bottom surface of the channel layer CN can be removed.

[0284] In the above-described embodiments and variations 1 and 2, insulating layers NL and OL are alternately stacked to form laminates LMs. However, laminates LMs can also be formed in multiple tiers, in which case pillars PL and stepped portions SR, SRd, and SRda can be formed in stages as each tier of laminate LMs is formed. This allows for a further increase in the number of layers in the word line WL.

[0285] In the above-described embodiments and variations 1 and 2, the semiconductor memory device includes peripheral circuitry that contributes to the operation of the memory cell MC. The peripheral circuitry may be located above, below, or at the same level as the stacked layer.

[0286] For example, when a portion of the surface of a semiconductor substrate is used as the source line SL, the peripheral circuit can be disposed on the semiconductor substrate outside the stacked body LM. In this case, the stacked body and the peripheral circuit are disposed at the same level. Alternatively, by forming the peripheral circuit on the semiconductor substrate, covering it with an interlayer insulating layer or the like, and forming the source line SL and the stacked body LM on the interlayer insulating layer, the peripheral circuit can be disposed below the stacked body LM.

[0287] Alternatively, by forming source lines SL and a stacked body LM on a support substrate, and attaching a semiconductor substrate with peripheral circuitry on top of the stacked body LM, the peripheral circuitry can be positioned on top of the stacked body LM.

[0288] While several embodiments of the invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope equivalent to the invention as described in the claims.

[0289] [Symbol Explanation]

[0290] 1, 2: Semiconductor memory devices; 60, 70, 80, 80a, 90, 90a, 100, 100a, 110, 110a, 120, 120a: Resist layers; 60x, 60y, 80x, 80xa, 80y, 100x, 100xa, 100y: Edges; CC: Contacts; LM, LMa, LMG, LMs: Laminates; NL, OL: Insulating layers; PL: Pillars; SL: Source lines; SP, SPd, SPda: Step surfaces; SPG: Step surface group; SR, SRd, SRda: Step portions; STPa~STPf: Stop layers; TR: Plateau surface; WL: Word lines.

Claims

1. A method for manufacturing a semiconductor memory device, wherein, This forms a laminate composed of multiple first insulating layers and multiple second insulating layers, stacked alternately layered one after another. A first mask layer with a first edge is formed on top of the laminate. Form a first stop layer that at least covers the first edge. A second mask layer is formed that covers the first mask layer, including the first edge. The following process is repeated multiple times: while thinning the second mask layer to move it backward in a first direction toward the first edge, a group of first and second insulating layers exposed from the second mask layer of the laminate is etched away. Remove the second mask layer that has undergone multiple thinning processes, and remove the first stop layer exposed at the first edge. The following process is repeated multiple times: while thinning the first mask layer to move it backward in the first direction, a group of first insulating layers and second insulating layers exposed from the first mask layer of the laminate are etched away.

2. The method for manufacturing a semiconductor memory device according to claim 1, wherein, When forming the first stop layer, a first stop layer is formed that covers the first edge and upper surface of the first mask layer, as well as the upper surface of the laminate exposed from the first mask layer. During the repeated thinning of the second mask layer and etching of the first and second insulating layers, the following process is repeatedly performed: while removing the first stop layer from the upper surface of the stack newly exposed by the thinning of the second mask layer, the first and second insulating layers are etched away.

3. The method for manufacturing a semiconductor memory device according to claim 1, wherein, When forming the first stop layer, a first stop layer is formed that covers the first edge and upper surface of the first mask layer, as well as the upper surface of the laminate exposed from the first mask layer. During the repeated thinning of the second mask layer and etching of the first and second insulating layers, the first stop layer is removed from the upper surface of the first mask layer and the upper surface of the laminate.

4. A method for manufacturing a semiconductor memory device according to any one of claims 1 to 3, wherein, The first stop layer is a semiconductor layer or a metal layer.

5. A semiconductor memory device comprising: A laminate, which is a laminate composed of multiple conductive layers and multiple insulating layers alternately stacked one on top of another, has a first stepped portion and a second stepped portion. In the first stepped portion, the multiple conductive layers are processed into a stepped shape, and the height of the first stepped portion changes in a direction intersecting the stacking direction of the multiple conductive layers. In the second stepped portion, the multiple conductive layers are processed into a stepped shape, and the height of the second stepped portion changes in a direction intersecting the direction of height change of the first stepped portion. A pillar, extending along the stacking direction within the stack, forms a memory cell at its intersection with at least a portion of the plurality of conductive layers. The first stepped portion includes a plurality of first stepped surfaces, which are the end faces of the plurality of conductive layers that have been processed into a stepped shape. The plurality of first step difference surfaces include a plurality of step difference surface groups arranged from the lower side to the upper side of the first step portion. Each step difference surface group is composed of a plurality of first step difference surfaces whose shape changes from a substantially straight line extending toward the central portion in the direction of increasing height of the first step portion. The second stepped portion includes a plurality of second stepped surfaces, which are the end faces of the plurality of conductive layers that have been processed into a stepped shape. The plurality of second-order difference surfaces include: Multiple third-order differential surfaces are distributed on the second step portion, forming a shape with a central protrusion. One or more fourth-order differential surfaces are arranged near the lowest level of the second step and extend substantially in a straight line; as well as One or more fifth-order differential surfaces are disposed between the lowest and highest levels of the second step section and extend substantially in a straight line.

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