A self-aligned nanosilicon via structure and method of making the same

Abstract

Provided are a self-aligned nano-silicon via structure and a preparation method thereof. The method comprises: growing a first SiO2 layer covering a fin structure on a silicon substrate; growing a sacrificial layer on a top surface, forming a first preset pattern on the sacrificial layer, etching an initial groove parallel to the fin structure, and filling the initial groove with a first filler; forming a second preset pattern on the top surface, etching a first initial blind hole, and filling the first initial blind hole with a second filler; removing the sacrificial layer and the first filler and the second filler in the sacrificial layer; growing a second SiO2 layer on the top surface, removing the fillers and the second SiO2 layer at positions corresponding to the fillers, and forming a target groove and a first target blind hole; filling the target groove and the first target blind hole with a third filler to a middle part of the fin, and then filling the middle part of the fin with a fourth filler; forming a third preset pattern on the top surface, etching the SiO2 layer and the fourth filler to expose the third filler, and filling the third filler with a fifth filler; and thinning from a bottom surface to expose the third filler in the first target blind hole, to obtain the self-aligned nano-silicon via structure.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, specifically to a self-aligned nano-silicon through-hole structure and its preparation method. Background Technology

[0002] With the miniaturization of basic integrated circuit units—Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and FinField-Effect Transistors (FinFETs)—Backside Power Delivery Network (BSPDN) technology, which saves cell area, will be widely used in future technology nodes. However, the application of current backside power delivery network technology is limited by the high interfacial contact resistance of buried power rails (BPRs) and nanometer through-silicon vias (N-TSVs). Potential photolithographic alignment problems between buried power rails and N-TSVs limit further miniaturization of MOSFET devices. Summary of the Invention

[0003] In view of this, the present disclosure provides a self-aligned nano-silicon through-hole (SANTSV) structure and its preparation method, which can at least partially solve the above problems.

[0004] According to a first aspect of this disclosure, a method for fabricating a self-aligned nano-silicon through-hole structure is provided, comprising: step S1, providing a silicon substrate, the silicon substrate including a fin structure extending upwardly perpendicular to the surface of the silicon substrate, growing a first SiO2 layer on the silicon substrate, the first SiO2 layer covering the fin and being at the same height as the fin, to obtain a first structure; step S2, growing a sacrificial layer on the top surface of the first structure, forming a first preset pattern on the top surface of the sacrificial layer, and sequentially etching the sacrificial layer, the first SiO2 layer, and the silicon substrate to a first preset depth from the top surface of the sacrificial layer according to the first preset pattern to form an initial trench parallel to the fin, the initial trench including a first trench, a second trench, and a third trench arranged sequentially; step S3, in the initial... Step S4: Fill the initial trench with a first filler until the first filler is flush with the top surface of the sacrificial layer. The first filler includes SiO2. Step S5: Form a second preset pattern on the top surface of the first filler. The second preset pattern is located at the position of the first trench and the second trench. Etch the silicon substrate from the top surface of the first filler downwards according to the second preset pattern to form a first initial blind via. Step S6: Fill the first initial blind via with a second filler until the second filler is flush with the top surface of the sacrificial layer. Remove the sacrificial layer and the first and second fillers located within the height range of the sacrificial layer to obtain a second structure. The second filler includes SiO2. Step S7: On the top surface of the second structure... A second SiO2 layer is grown; the second SiO2 layer at the position corresponding to the remaining first filler and the second SiO2 layer 6 at the position corresponding to the remaining second filler 45 are etched, and the remaining first filler is etched to form a target trench; the remaining second filler is etched to form a first target blind hole; in step S7, a third filler is filled into the target trench and the first target blind hole, the third filler being higher than the root of the fin and lower than the top of the fin, and a fourth filler is filled on the top surface of the third filler until the fourth filler is flush with the second SiO2 layer to obtain a third structure, the third filler including tungsten and the fourth filler including SiO2; in step S8, a third preset pattern is formed on the top surface of the third structure, and the third preset pattern is used to form a third structure. The top surface of the third structure is etched downwards to form the second SiO2 layer, the fourth filler, and the first SiO2 layer until the third filler is exposed. The fifth filler is then filled into the trenches created by the etching until the fifth filler is flush with the second SiO2 layer, resulting in the fourth structure. The fifth filler includes tungsten, and the third preset pattern does not include the position corresponding to the first target blind hole. In step S9, the fourth structure is thinned from the silicon substrate side until the third filler in the first target blind hole is exposed, resulting in a self-aligned nano-silicon via structure. The sacrificial layer material has an anisotropic etching selectivity ratio less than or equal to a preset ratio with the silicon substrate, the first SiO2 layer, the first filler, and the second filler. The preset ratio is 1:10.In step S7, before filling the target trench and the first target blind hole with the third filler, the method further includes: sequentially growing an electrical isolation layer, a diffusion barrier layer, and an adhesion layer on the bottom and sidewalls of the target trench and the first target blind hole.

[0005] According to a second aspect of this disclosure, based on the self-aligned nano-silicon through-hole structure obtained in step S9 above, a method for preparing another self-aligned nano-silicon through-hole structure is provided, the method comprising: step S10, etching a third filler in the first target blind hole exposed in step S9 to form a second target blind hole, the second target blind hole not exceeding the plane where the root of the fin is located; step S11, filling the second target blind hole with a sixth filler to obtain another self-aligned nano-silicon through-hole structure, the sixth filler comprising copper.

[0006] According to a third aspect of this disclosure, based on the structure obtained in step S10 above, a method for preparing another self-aligned nano-silicon through-hole structure is provided, the method comprising: step S11′, etching the silicon substrate surrounding the second target blind hole to obtain a third target blind hole, wherein the size of the third target blind hole gradually increases from one side of the second SiO2 layer to the thinned side; step S12′, filling the third target blind hole with a seventh filler to obtain another self-aligned nano-silicon through-hole structure, wherein the seventh filler includes copper or tungsten.

[0007] According to an embodiment of this disclosure, the first structure is obtained by performing a fin field-effect transistor process until the interfin isolation oxide filling step of the fin field-effect transistor process is completed, thereby obtaining the first structure.

[0008] According to an embodiment of this disclosure, step S2 includes: coating a photoresist on the upper surface of the sacrificial layer, forming a first preset pattern by exposure, wherein the first preset pattern is parallel to the direction of the fin and not above the fin; according to the first preset pattern, sequentially etching the sacrificial layer, the first SiO2 layer and the silicon substrate from the top surface of the sacrificial layer downwards, and removing the remaining photoresist to obtain an initial trench; wherein the operation of removing the remaining photoresist is performed after the operation of etching the sacrificial layer, or after sequentially etching the sacrificial layer, the first SiO2 layer and the silicon substrate from the top surface of the sacrificial layer downwards.

[0009] According to an embodiment of this disclosure, step S4 involves forming a second preset pattern on the top surface of the first filler, the second preset pattern being located at the positions of the first trench and the second trench. The process of etching the first filler and a silicon substrate of a second preset depth sequentially downwards from the top surface of the first filler to form a first initial blind hole includes: coating photoresist on both the top surface of the first filler and the top surface of the sacrificial layer; exposing the photoresist within a preset range along a direction perpendicular to the fin, and determining the position corresponding to the exposed first filler as the second preset pattern; etching the first filler and the silicon substrate of a second preset depth sequentially downwards from the top surface of the first filler according to the second preset pattern, and removing the remaining photoresist to form the first initial blind hole; wherein the removal of the remaining photoresist is performed after the etching of the first filler, or after the sequential etching of the first filler and the silicon substrate of a second preset depth from the top surface of the first filler.

[0010] According to an embodiment of this disclosure, step S6 further includes: after forming the target trench, continuing to etch the silicon substrate to a third preset depth and / or after forming the first target blind via, continuing to etch the silicon substrate to a fourth preset depth.

[0011] According to an embodiment of this disclosure, before etching the silicon substrate and the third filler around the second target blind hole in step S11′, the method further includes: sequentially removing the adhesion layer, diffusion barrier layer and electrical isolation layer of the sidewall of the second target blind hole.

[0012] According to an embodiment of this disclosure, before filling the third target blind hole with the seventh filler in step S12′, the method further includes: sequentially growing an electrical isolation layer, a diffusion barrier layer, and an adhesion layer on the sidewall of the third target blind hole.

[0013] According to a fourth aspect of this disclosure, a self-aligned nano-silicon through-hole structure is provided, which is prepared by the above-described preparation method.

[0014] According to a fifth aspect of this disclosure, an electronic device is provided, comprising the above-described self-aligned nanosilicon through-hole structure.

[0015] Compared with the prior art, the self-aligned nano-silicon through-hole structure and its preparation method provided in this disclosure have at least the following beneficial effects:

[0016] It is compatible with mainstream fin field-effect transistor (FET) processes, which can reduce fabrication costs. The depth of the buried power rail can be determined by etching the silicon substrate to a first preset depth, and the depth of the self-aligned nano-silicon via can be determined by etching the silicon substrate to a second preset depth or by thinning the fourth structure from one side of the silicon substrate. This allows for precise control over the depth of the buried power rail and the self-aligned nano-silicon via. A second preset pattern is formed based on the preset range and the positions of the first and second trenches. The first initial blind via is then etched according to the second preset pattern, which determines the position of the nano-silicon via and avoids potential photolithographic alignment problems between the buried power rail and the nano-silicon via, which is beneficial for further miniaturization of FET devices. By increasing the size of the nano-silicon via, the interface contact resistance between the buried power rail and the nano-silicon via is reduced. By replacing the tungsten filler in the enlarged via with copper, a material consistent with the back metal, the interface contact resistance is further reduced, which is beneficial for the widespread application of back-side power supply network technology. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating a method for preparing a self-aligned nano-silicon through-hole structure according to embodiments of this disclosure;

[0018] Figure 2 This is a top view of the first structure illustrated according to an embodiment of the present disclosure;

[0019] Figure 3 According to Figure 2 A sectional view of the first structure drawn along line AA;

[0020] Figure 4 This is a flowchart illustrating the formation of an initial trench in the first structure according to an embodiment of the present disclosure;

[0021] Figure 5 This is a top view illustrating the first structure after the initial trench has been formed, according to an embodiment of the present disclosure;

[0022] Figure 6 According to Figure 5 The cross-sectional view after the initial trench is formed in the first structure, as shown by line AA in the middle;

[0023] Figure 7 This is a top view illustrating the initial trench after filling with a first filler, according to an embodiment of the present disclosure;

[0024] Figure 8 According to Figure 7 A cross-sectional view of the initial trench after the first filler material has been filled, as shown by line AA in the middle.

[0025] Figure 9 This is a flowchart illustrating the etching of a first filler and a silicon substrate to form a first initial blind via according to an embodiment of this disclosure;

[0026] Figure 10 This is a top view illustrating the etching of the first filler and the silicon substrate according to an embodiment of the present disclosure;

[0027] Figure 11 According to Figure 10 A cross-sectional view of the first filler and silicon substrate after etching, as shown by line AA in the middle;

[0028] Figure 12 According to Figure 10 A cross-sectional view of the first filler and silicon substrate after etching, as shown by the BB line in the middle;

[0029] Figure 13 This is a top view illustrating the filling of a first initial blind hole with a second filler, according to an embodiment of this disclosure.

[0030] Figure 14 According to Figure 13 A cross-sectional view of the first initial blind hole after the second filler material has been filled, as shown by line AA in the middle.

[0031] Figure 15 This is a top view of the second structure illustrated according to an embodiment of the present disclosure;

[0032] Figure 16 According to Figure 15 A sectional view of the second structure shown by line AA in the middle;

[0033] Figure 17 This is a flowchart illustrating the formation of a target trench and a first target blind hole by a second structure according to an embodiment of this disclosure;

[0034] Figure 18 This is a top view illustrating the formation of a target trench and a first target blind hole in the second structure according to an embodiment of the present disclosure;

[0035] Figure 19 According to Figure 18 A cross-sectional view showing the formation of the target trench and the first target blind hole in the second structure, drawn with line AA in the middle;

[0036] Figure 20 This is a top view of the third structure illustrated according to an embodiment of the present disclosure;

[0037] Figure 21 According to Figure 20 A sectional view of the third structure shown by line AA in the middle;

[0038] Figure 22 This is a top view of the fourth structure illustrated according to an embodiment of the present disclosure;

[0039] Figure 23 According to Figure 22 A cross-sectional view of the fourth structure, drawn along line AA.

[0040] Figure 24 According to Figure 22 A cross-sectional view of the fourth structure, drawn with the CC line in the center;

[0041] Figure 25 A bottom view of a self-aligned nano-silicon through-hole structure illustrated according to an embodiment of this disclosure;

[0042] Figure 26 According to Figure 25 A cross-sectional view of a self-aligned nano-silicon through-hole structure, drawn with line AA in the middle;

[0043] Figure 27 This is a flowchart illustrating a method for preparing another self-aligned nano-silicon through-hole structure according to embodiments of this disclosure;

[0044] Figure 28 This is a cross-sectional view of another self-aligned nano-silicon through-hole structure drawn according to an embodiment of this disclosure;

[0045] Figure 29 According to Figure 28 The diagram shows the structure of the self-aligned nano-silicon through-hole structure after it forms the back power supply network.

[0046] Figure 30 This is a flowchart illustrating a method for preparing another self-aligned nano-silicon through-hole structure according to embodiments of this disclosure;

[0047] Figure 31 A bottom view of yet another self-aligned nano-silicon through-hole structure drawn according to an embodiment of this disclosure;

[0048] Figure 32 According to Figure 31 Another cross-sectional view of a self-aligned nano-silicon through-hole structure drawn along line AA;

[0049] Figure 33 According to Figure 32 The diagram shows the structure of the self-aligned nano-silicon through-hole structure after it forms the back power supply network.

[0050] [Explanation of Labels in the Attached Image]

[0051] 1-Silicon substrate; 11-Fin; 2-First SiO2 layer; 3-Sacrificial layer; 4-Initial trench; 4′-Target trench; 41-First trench; 42-Second trench; 43-Third trench; 44-First filler; 45-Second filler; 46-Third filler; 47-Fourth filler; 48-Fifth filler; 49-Sixth filler; 40-Seventh filler; 5-First initial blind via; 51-First target blind via; 52-Second target blind via; 53-Third target blind via; 6-Second SiO2 layer. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description, in conjunction with specific embodiments and accompanying drawings, further illustrates the present disclosure. Those skilled in the art should understand that the various embodiments of the present disclosure listed in the following description are merely illustrative examples to make the objectives, technical solutions, and advantages of the present disclosure clearer, and are not intended to limit the content and scope of protection of the present disclosure. In the embodiments listed below, the same or similar reference numerals will be used to represent the same or similar elements or components. Furthermore, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

[0053] It should be noted that in this specification, when a component is described as "comprising", "having", or "containing" an element, it means that the component may include one or more elements, and the component may include other elements at the same time, and does not mean that the component has only one element, unless otherwise stated.

[0054] Furthermore, in this specification, ordinal numbers such as "first" or "second" are used only to distinguish multiple elements with the same name and do not imply an inherent hierarchy, rank, execution order, or manufacturing order between the elements, unless otherwise stated. The element numbers in the specification may differ from those in the claims. For example, an element referred to as "second" in the specification may be an element referred to as "first" in the claims.

[0055] In this specification, unless otherwise stated, "or" for feature A and "and / or" for feature B means the existence of only feature A, the existence of only feature B, or the existence of both feature A and feature B. "and" for feature A means the existence of both feature A and feature B.

[0056] Furthermore, in this specification, terms such as "top," "upper," "bottom," "front," "back," or "middle," as well as terms such as "above," "on top," "on the surface," "below," "below," or "between," are used to describe the relative positions between multiple elements. These directional terms are referenced to the directions shown in the accompanying drawings, and the described relative positions can be interpreted as including their translation, rotation, or reflection.

[0057] Furthermore, terms used in the specification and claims, such as “above,” “over,” “on top,” “below,” or “under,” are intended to allow an element to contact not only directly but also indirectly.

[0058] Furthermore, terms used in the specification and claims, such as "connection," mean that an element can be directly connected to other elements or indirectly connected to other elements. On the other hand, terms such as "electrical connection" and "coupled" used in the specification and claims mean that an element can be directly electrically connected to other elements or indirectly connected to other elements; this disclosure does not limit the connection methods between the various elements.

[0059] Furthermore, the dimensions of the components in the accompanying drawings are only schematic and are not drawn to scale. For clarity, some details have been enlarged, and others may have been omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are exemplary only. In reality, deviations may occur due to manufacturing tolerances or technical limitations. Those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs. The similarity in size between two components in the figures does not imply that their actual dimensions will be similar in the product. Parameters such as assembly clearances and surface quality of the components are not shown in the accompanying drawings.

[0060] In this specification, unless otherwise stated, the terms used herein (including technical and scientific terms) have the meanings commonly known to those skilled in the art. It should be noted that, unless otherwise stated in the embodiments of this disclosure, these terms (e.g., terms as defined in a general dictionary) should have the same meaning as those skilled in the art, the background of this disclosure, or the context of this specification, and should not be read in an idealized or overly formal manner.

[0061] This disclosure may be presented in various forms, some of which are described below. In the following description, the selection of various materials is discussed. The selection of materials takes into account not only their function (e.g., semiconductor materials for forming active regions, dielectric materials for forming electrical isolation) but also etch selectivity. In the following description, the desired etch selectivity may or may not be indicated. Those skilled in the art will understand that when the following references to etching a material layer, unless it is mentioned that other layers are also etched or not shown in the figures, then such etching may be selective, and the material layer may possess etch selectivity relative to other layers exposed to the same etch formulation.

[0062] This disclosure provides a method for preparing a self-aligned nano-silicon through-hole structure. Figure 1 The flowchart illustrates a method for fabricating a self-aligned nano-silicon through-hole structure according to embodiments of this disclosure, as shown below. Figure 1 As shown, the method includes steps S1-S9:

[0063] In step S1, a silicon substrate 1 is provided, the silicon substrate 1 includes a fin 11 structure that is perpendicular to the surface of the silicon substrate 1 and extends upward. A first SiO2 layer 2 is grown on the silicon substrate 1, the first SiO2 layer 2 covers the fin 11 and is at the same height as the fin 11, to obtain a first structure.

[0064] In some embodiments of this disclosure, the first structure described above is fabricated using a standard FinFET process. Specifically, the FinFET process is performed until the "inter-fin isolation oxide filling" step of the FinFET process is completed, at which point the FinFET process is paused to obtain the first structure.

[0065] Figure 2 This is a top view of the first structure illustrated according to an embodiment of the present disclosure. Figure 3 According to Figure 2 A sectional view of the first structure, drawn along line AA. Figure 2 and Figure 3 In the embodiment shown, two sets of fins 11 extend from the upper surface of the silicon substrate 1 of the first structure, each set consisting of 3 fins 11. A first SiO2 layer 2, which covers the fins 11 and is at the same height as the fins 11, is grown around each fin 11.

[0066] In step S2, a sacrificial layer 3 is grown on the top surface of the first structure, and a first preset pattern is formed on the top surface of the sacrificial layer 3. According to the first preset pattern, the sacrificial layer 3, the first SiO2 layer 2 and the silicon substrate 1 at a first preset depth are sequentially etched from the top surface of the sacrificial layer 3 downwards to form an initial trench 4 parallel to the fin 11. The initial trench 4 includes a first trench 41, a second trench 42 and a third trench 43 arranged in sequence.

[0067] Figure 4 This is a flowchart illustrating the formation of an initial trench in a first structure according to an embodiment of the present disclosure. Figure 4 As shown, in some embodiments of this disclosure, step S2 specifically includes:

[0068] Step S21: Coat the upper surface of the sacrificial layer 3 with photoresist;

[0069] Step S22: A first preset pattern is formed by exposure. The first preset pattern is parallel to the direction of the fin 11 and is not above the fin 11.

[0070] Step S23: According to the first preset pattern, the sacrificial layer 3, the first SiO2 layer 2 and the silicon substrate 1 at the first preset depth are etched sequentially from the top surface of the sacrificial layer 3 downwards.

[0071] Step S24: Remove the remaining photoresist on the upper surface of the sacrificial layer 3 to obtain the initial trench 4.

[0072] In some embodiments of this disclosure, step S23 specifically involves using photoresist as a barrier layer and employing anisotropic reactive ion etching (RIE) to complete the etching operation. According to embodiments of this disclosure, the operation of "removing the remaining photoresist" can be performed after the operation of "etching the sacrificial layer 3," or after sequentially etching the sacrificial layer 3, the first SiO2 layer 2, and the silicon substrate 1 from the top surface of the sacrificial layer 3 downwards. In one embodiment of this disclosure, after etching the sacrificial layer 3, step S23 removes the remaining photoresist on the upper surface of the sacrificial layer 3, and then continues etching downwards the first SiO2 layer 2 and the silicon substrate 1 to a first predetermined depth. Based on this, a buried power rail with a better morphology can be obtained. It should be understood that the use of anisotropic reactive ion etching in the above operation is merely an illustrative example; for example, high-density plasma etching or other methods can also be used for etching. This disclosure does not limit the specific etching method.

[0073] like Figure 5 The image shown is a top view of the first structure after the initial trench has been formed, according to an embodiment of this disclosure. Figure 6 The following is based on Figure 5 The figure shows a cross-sectional view of the first structure after the initial trenches are formed, as illustrated by line AA. As shown, the initial trenches 4 formed after etching include a first trench 41, a second trench 42, and a third trench 43 arranged sequentially from left to right. The first trench 41 is located on the far left of the structure, the second trench 42 is located in the middle of the structure, between the two sets of fins 11, and the third trench 43 is located on the far right of the structure. The positions of the formed trenches in the figure correspond to the positions of the first preset pattern before etching. By adjusting the first preset depth, the depth of the initial trenches 4 is changed, thereby adjusting the final depth of the embedded power rail, which allows for precise control of the embedded power rail depth.

[0074] Step S3: Fill the initial trench 4 with a first filler 44 until the first filler 44 is flush with the top surface of the sacrificial layer 3. The first filler 44 includes SiO2.

[0075] like Figure 7 The image shown is a top view illustrating the initial trench after filling with a first filler material, according to an embodiment of this disclosure. Figure 8 The following is based on Figure 7The diagram, drawn along line AA, shows a cross-sectional view after the first filler has been filled into the initial trench. In some embodiments of this disclosure, filling until the first filler 44 is flush with the top surface of the sacrificial layer 3 includes: after filling, planarizing the first filler 44 with the sacrificial layer 3 as a stop layer by chemical mechanical polishing (CMP), so that the first filler 44 is flush with the top surface of the sacrificial layer 3. It should be understood that the planarization by chemical mechanical polishing in the above operation is merely an illustrative example and is not intended to limit this disclosure.

[0076] In step S4, a second preset pattern is formed on the top surface of the first filler 44. The second preset pattern is located at the positions of the first trench 41 and the second trench 42. According to the second preset pattern, the first filler 44 and the silicon substrate 1 at the second preset depth are etched sequentially from the top surface of the first filler 44 downward to form the first initial blind hole 5.

[0077] Figure 9 This is a flowchart illustrating the etching of a first filler and a silicon substrate to form a first initial blind via according to an embodiment of this disclosure. Figure 9 As shown, in some embodiments of this disclosure, step S4 includes:

[0078] Step S41: Photoresist is applied to the top surface of the first filler 44 and the top surface of the sacrificial layer 3.

[0079] Step S42: Expose photoresist within a preset range along a direction perpendicular to the fin 11, and determine the position corresponding to the exposed first filler 44 as the second preset pattern;

[0080] Step S43: According to the second preset pattern, the first filler 44 and the silicon substrate 1 at the second preset depth are etched sequentially from the top surface of the first filler 44 downwards.

[0081] Step S44: Remove the remaining photoresist from the top surface of the first filler 44 and the top surface of the sacrificial layer 3 to form the first initial blind hole 5.

[0082] According to embodiments of this disclosure, the operation of "removing remaining photoresist" is performed after the etching of the first filler 44, or after sequentially etching the first filler 44 and the silicon substrate 1 at a second predetermined depth from the top surface of the first filler 44 downwards. In some embodiments of this disclosure, by removing the remaining photoresist after the operation of "etching the first filler 44" and then continuing to etch the silicon substrate 1 at the second predetermined depth, a first initial blind hole 5 with a better morphology can be obtained.

[0083] Figure 10 This is a top view (photoresist not yet removed) illustrating the etching of the first filler and silicon substrate according to an embodiment of this disclosure. Figure 11 According to Figure 10 The cross-sectional view after etching the first filler and the silicon substrate, shown by line AA in the middle. Figure 12 According to Figure 10 The cross-sectional view after etching the first filler and silicon substrate is shown in the middle BB line. As shown, the preset range is perpendicular to fin 11 (i.e., Figure 10 The solid line elongated area referred to in the "preset range" indicates that after the photoresist within the preset range is exposed and removed, part of the first filler 44 in the first trench 41 and part of the first filler 44 in the second trench 42 will be exposed. The outline of the exposed first filler 44 (i.e., the position where the first initial blind hole 5 will be formed later) is the second preset pattern. According to the second preset pattern, the first filler 44 is selectively etched from the top surface downwards, using the sacrificial layer 3 and photoresist as a barrier layer, to expose the silicon substrate 1. Then, the silicon substrate 1 at a second preset depth is selectively etched using the first filler 44 and the sacrificial layer 3 as a barrier layer (it should be noted that it cannot penetrate the silicon substrate 1). The etched cavity is the first initial blind hole 5.

[0084] In the above method, after coating photoresist on the top surface of the first filler 44 and the top surface of the sacrificial layer 3, the photoresist within a preset range is removed by exposure in a direction perpendicular to the fin 11 (i.e., perpendicular to the first filler 44). The preset range intersects with the first filler 44 to determine the location of the first initial blind hole 5 (i.e., the location of the nano-silicon via). Compared to directly exposing the pattern of the location of the first initial blind hole 5 on the photoresist, this method improves positional accuracy, avoids potential photolithographic misalignment problems between the buried power rail and the nano-silicon via, and facilitates further miniaturization of metal-oxide-semiconductor field-effect transistor devices. By changing the second preset depth, the depth of the first initial blind hole 5 can be adjusted, thereby enabling precise control of the depth of the nano-silicon via.

[0085] Step S5: Fill the first initial blind hole 5 with the second filler 45 until the second filler 45 is flush with the top surface of the sacrificial layer 3. Remove the sacrificial layer 3 and the first filler 44 and the second filler 45 located within the height range of the sacrificial layer 3 to obtain the second structure. The second filler 45 includes SiO2.

[0086] like Figure 13 The image shown is a top view illustrating the filling of a second filler into a first initial blind hole according to an embodiment of this disclosure. Figure 14 The following is based on Figure 13 The cross-sectional view, drawn along line AA, shows the first initial blind hole after the second filler material has been filled. (See figure.) Figure 15 The image shown is a top view of a second structure according to an embodiment of this disclosure, as follows: Figure 16 The following is based on Figure 15The cross-sectional view of the second structure is shown by line AA in the diagram. In some embodiments of this disclosure, filling the second filler 45 to be flush with the top surface of the sacrificial layer 3 includes: planarizing the second filler 45 with the top surface of the sacrificial layer 3 by chemical mechanical polishing after filling is completed. It should be understood that the planarization by chemical mechanical polishing with the sacrificial layer 3 as the stop layer in the above operation is merely an illustrative example and is not intended to limit this disclosure.

[0087] In the embodiments of this disclosure, the material used in the sacrificial layer 3 has an anisotropic etching selectivity ratio of less than or equal to a preset ratio with respect to the silicon substrate 1, the first SiO2 layer 2, the first filler 44, and the second filler (45), and the preset ratio is 1:10; for example, the sacrificial layer 3 is made of silicon nitride or other nitrogen-doped silicon oxide, and the growth method of the sacrificial layer 3 includes, but is not limited to, deposition.

[0088] Step S6: A second SiO2 layer 6 is grown on the top surface of the second structure. The second SiO2 layer 6 at the position corresponding to the remaining first filler 44 and the second SiO2 layer 6 at the position corresponding to the remaining second filler 45 are etched. The remaining first filler 44 is etched to form the target trench 4′. The remaining second filler 45 is etched to form the first target blind hole 51.

[0089] Figure 17 This is a flowchart illustrating the formation of a target trench and a first target blind hole by a second structure according to an embodiment of this disclosure. Figure 17 As shown, in some embodiments of this disclosure, step S6 includes:

[0090] Step S61: A second SiO2 layer 6 is grown on the top surface of the second structure;

[0091] Step S62: Coat the second SiO2 layer 6 with photoresist;

[0092] Step S63: Expose and remove the photoresist at the corresponding positions of the remaining first filler 44 and the remaining second filler 45;

[0093] Step S64: According to the pattern formed by exposure on the photoresist, the second SiO2 layer 6 and the first filler 44 are etched downwards to expose the silicon substrate 1 and form the target trench 4′.

[0094] Step S65: Remove the remaining photoresist and apply photoresist to the second SiO2 layer 6 and the exposed silicon substrate 1, and then expose the photoresist at the position corresponding to the "preset range" in step S42.

[0095] Step S66: According to the pattern formed by exposure on the photoresist, the second filler 45 is etched downward to expose the silicon substrate 1 and form the first target blind hole 51.

[0096] Step S67: Remove the remaining photoresist.

[0097] like Figure 18 The diagram shown is a top view illustrating the formation of a target trench and a first target blind hole in the second structure according to an embodiment of this disclosure. Figure 19 The following is based on Figure 18 The cross-sectional view shown by line AA in the middle shows the formation of the target trench and the first target blind hole in the second structure.

[0098] In some embodiments of this disclosure, the order of the operations of forming the target trench 4' and forming the first target blind hole 51 can be selected arbitrarily. Due to the existence of the etching selectivity, during etching, the etching rate of one object is greater than the etching rate of another object (e.g., when etching the first filler, the etching rate of the second filler is much less than the etching rate of the first filler). That is, the target trench 4' can be etched first, followed by the first target blind hole 51, or the first target blind hole 51 can be etched first, followed by the target trench 4'.

[0099] In some embodiments of this disclosure, the first filler 44 and the second filler 45 are both SiO2, which can be etched in one step to form the target trench 4' and the first target blind hole 51. Then, the above steps S63-S66 can be adjusted to: expose and remove the photoresist at the corresponding positions of the remaining first filler 44 and the second filler 45; according to the pattern formed by exposure on the photoresist, etch the second SiO2 layer 6 downwards; etch and remove the remaining first filler 44 and the remaining second filler 45; expose the silicon substrate 1 at the corresponding position of the remaining second filler 45; and form the target trench 4' and the first target blind hole 51. Based on this, after the silicon substrate 1 at the position corresponding to the "remaining first filler 44" is exposed, the "remaining second filler 45" will still remain. During the subsequent etching process until the silicon substrate 1 at the position corresponding to the "remaining second filler 45" is exposed, the silicon substrate 1 at the position corresponding to the "remaining first filler 44" that has already been exposed will be etched in small amounts and the depth will change. However, due to the existence of the etching selectivity, this depth change can be ignored, and the depth change can be quantitatively calculated based on the etching selectivity.

[0100] In some embodiments of this disclosure, step S6 further includes: after forming the target trench 4′, continuing to etch the silicon substrate 1 to a third preset depth (after etching, it should be higher than the bottom surface of the first target blind hole 51), and / or after forming the first target blind hole 51, continuing to etch the silicon substrate 1 to a fourth preset depth (after etching, it should still not penetrate the silicon substrate 1), thereby adjusting the depth of the target trench 4′ and / or adjusting the depth of the first target blind hole 51, thereby adjusting the depth of the final buried power rail and / or adjusting the depth of the final nano-silicon via.

[0101] In some embodiments of this disclosure, step S61, growing a second SiO2 layer 6 on the top surface of the second structure, is achieved by continuing to use the standard fin field-effect transistor process on the basis of the second structure until the "front-end process" of the fin field-effect transistor process is completed, and then pausing the fin field-effect transistor process to obtain a structure in which a second SiO2 layer 6 is grown on the top surface of the second structure.

[0102] Step S7: Fill the target trench 4′ and the first target blind hole 51 with a third filler 46. The third filler 46 is higher than the root of the fin 11 and lower than the top of the fin 11. Fill the top surface of the third filler 46 with a fourth filler 47 until the fourth filler 47 is flush with the second SiO2 layer 6 to obtain the third structure. The third filler 46 includes tungsten and the fourth filler 47 includes SiO2.

[0103] like Figure 20 The diagram shown is a top view of a third structure according to an embodiment of this disclosure, as follows: Figure 21 The following is based on Figure 20 A cross-sectional view of the third structure, drawn along line AA.

[0104] In embodiments of this disclosure, before filling the target trench 4′ and the first target blind via 51 with the third filler 46, the method further includes: forming an electrical isolation layer on one side of the cavity of the target trench 4′ and the first target blind via 51 by growing a pad oxide layer to achieve electrical isolation between the buried power rail, the nano-silicon via, and the substrate; and sequentially growing a diffusion barrier layer and an adhesion layer on the inner side of the electrical isolation layer (i.e., one side of the cavity of the target trench 4′ and the first target blind via 51) using a standard contact forming process. In some embodiments of this disclosure, the electrical isolation layer is a SiO2 layer. It should be noted that in the accompanying drawings, for ease of drawing, the electrical isolation layer, the diffusion barrier layer, and the adhesion layer are drawn together and labeled as "electrical isolation layer." The reference numeral "electrical isolation layer" in the drawings includes the electrical isolation layer, the diffusion barrier layer, and the adhesion layer.

[0105] In some embodiments of this disclosure, filling the fourth filler 47 to be flush with the second SiO2 layer 6 includes: after filling, planarizing the second SiO2 layer 6 by chemical mechanical polishing, so that the fourth filler 47 is flush with the top surface of the second SiO2 layer 6. It should be understood that the planarization by chemical mechanical polishing described above is merely an illustrative example and not intended to limit this disclosure. In step S7 above, the third filler 46 is higher than the root of the fin 11 and lower than the top of the fin 11 to form an effective mid-segment interconnect.

[0106] Step S8: A third preset pattern is formed on the top surface of the third structure. The second SiO2 layer 6, the fourth filler 47, and the first SiO2 layer 2 are etched downwards from the top surface of the third structure according to the third preset pattern until the third filler 46 is exposed. The trenches created by the etching are filled with a fifth filler 48 until the fifth filler 48 is flush with the second SiO2 layer 6, resulting in the fourth structure. The fifth filler 48 comprises tungsten, and the third preset pattern does not include the position corresponding to the first target blind via 51. In the fourth structure, the fifth filler 48 exists as a metal interconnect layer. In a preferred embodiment of this disclosure, a diffusion barrier layer and an adhesion layer exist between the fifth filler 48 and the SiO2 layer. In some embodiments of this disclosure, this step can be fabricated using a standard fin field-effect transistor mid-segment interconnect process.

[0107] like Figure 22 The diagram shown is a top view of the fourth structure according to an embodiment of this disclosure, as follows: Figure 23 The following is based on Figure 22 The sectional view of the fourth structure, drawn with line AA in the middle, is as follows: Figure 24 The following is based on Figure 22 A sectional view of the fourth structure, drawn with the CC line in the center. It should be noted that... Figure 24 In the process of fin-type field-effect transistor manufacturing, the fin structure at the CC line section has changed during the "front-end process". Figure 24 The illustration is schematic, and this variation falls within the scope of standard fin field-effect transistor (FFET) technology, so it will not be described in detail here. In some embodiments of this disclosure, filling the fifth filler 48 to be flush with the second SiO2 layer 6 includes: after filling, planarizing the second SiO2 layer 6 using chemical mechanical polishing (CMP) as a stop layer, so that the top surface of the fifth filler 48 is flush with the top surface of the second SiO2 layer 6. It should be understood that the planarization using CMP in the above operation is merely an illustrative example and is not intended to limit this disclosure.

[0108] In some embodiments of this disclosure, the second SiO2 layer 6, the fourth filler 47, and the first SiO2 layer 2 are all SiO2. In this case, the etching operation in step S8 is as follows: according to the third preset pattern, etch SiO2 from the top surface of the third structure downwards until the third filler 46 is exposed.

[0109] Step S9: Thin the fourth structure from one side of the silicon substrate 1 until the third filler 46 in the first target blind hole 5′ is exposed, to obtain a self-aligned nano-silicon through-hole structure.

[0110] like Figure 25 The image shown is a bottom view of a self-aligned nano-silicon through-hole structure according to an embodiment of this disclosure, as follows: Figure 26 The following is based on Figure 25A cross-sectional view of a self-aligned nano-silicon through-hole structure, shown by line AA in the middle. The electrical isolation layer is shown in the figure.

[0111] In some embodiments of this disclosure, after thinning to expose the third filler 46 in the first target blind hole 51 in step S9 above, thinning can continue as needed to adjust the depth of the nano-silicon via.

[0112] In some embodiments of this disclosure, the thinning operation can be achieved by chemical mechanical polishing. In order to shorten the preparation cycle, other less precise methods can be used for preliminary thinning first, and when the target thinning amount is about to be reached, chemical mechanical polishing can be used for fine thinning.

[0113] In some embodiments of this disclosure, prior to step S9, the process further includes continuing to use a standard fin field-effect transistor process on the fourth structure until the "back-end process" of the fin field-effect transistor process is completed, pausing the fin field-effect transistor process, and then thinning the fourth structure from the silicon substrate 1 side.

[0114] Figure 27 This is a flowchart illustrating a method for preparing another self-aligned nano-silicon through-hole structure according to embodiments of this disclosure, such as... Figure 27 As shown, in another embodiment of this disclosure, the method is based on the self-aligned nano-silicon through-hole structure obtained in step S9 above, and the method includes steps S10-S11:

[0115] Step S10: Etch the third filler 46 in the first target blind hole 51 exposed in step S9 to form a second target blind hole 52. The second target blind hole 52 does not exceed the plane where the root of the fin 11 is located.

[0116] Step S11: Fill the second target blind hole 52 with a sixth filler 49 to obtain another self-aligned nano-silicon through-hole structure. The conductivity of the sixth filler 49 is better than that of the third filler 46. In some embodiments of this disclosure, the sixth filler 46 is made of copper.

[0117] Another self-aligned nano-silicon via structure prepared according to an embodiment of this disclosure has a bottom view that is roughly the same as the self-aligned nano-silicon via structure obtained in step S9, the only difference being that the third filler 46 at a certain depth is replaced by a sixth filler 49.

[0118] Figure 28 This is a cross-sectional view of another self-aligned nano-silicon through-hole structure drawn according to an embodiment of this disclosure. Figure 29 According to Figure 28 The diagram shows the structure of the self-aligned nano-silicon through-hole structure after it has been used to form the back-side power supply network. Figure 28 , Figure 29In this design, both the backside metal (BSM) and the sixth filler 49 are copper. The contact portion between the backside metal and the silicon substrate 1 also contains an electrical isolation layer, a diffusion barrier layer, and an adhesion layer, with the electrical isolation layer located on the side where the silicon substrate 1 is situated.

[0119] According to embodiments of this disclosure, replacing the etched third filler 46 with copper, which has superior conductivity, can reduce the interfacial contact resistance between the embedded power rail and the nano-silicon via, which is beneficial for the widespread application of back-side power supply network technology.

[0120] Figure 30 This is a flowchart illustrating a method for preparing another self-aligned nano-silicon through-hole structure according to embodiments of this disclosure, such as... Figure 30 As shown, in another embodiment of this disclosure, the method is based on the structure obtained in step S10 above, and the method includes steps S11′-S12′:

[0121] Step S11′: Etch the silicon substrate 1 and the third filler 46 around the second target blind hole 52 to obtain the third target blind hole 53, wherein the size of the third target blind hole 53 gradually increases from one side of the second SiO2 layer 6 to the thinned side.

[0122] Step S12′: Fill the third target blind hole 53 with a seventh filler 40 to obtain another self-aligned nano-silicon through-hole structure. The seventh filler 40 includes copper or tungsten.

[0123] According to embodiments of this disclosure, before etching the silicon substrate 1 and the third filler 46 around the second target blind hole 52 in step S11′, the method further includes: sequentially removing the adhesion layer, diffusion barrier layer, and electrical isolation layer from the sidewalls of the second target blind hole 52. In embodiments of this disclosure, before filling the third target blind hole 53 with the seventh filler 40 in step S12′, the method further includes: sequentially growing an electrical isolation layer, a diffusion barrier layer, and an adhesion layer on the sidewalls of the third target blind hole 53. In some embodiments of this disclosure, the electrical isolation layer is a SiO2 layer. The specific methods for growing the electrical isolation layer, diffusion barrier layer, and adhesion layer have been described in detail above and will not be repeated here.

[0124] According to embodiments of this disclosure, the etching in the above-described method for fabricating self-aligned nano-silicon through-hole structures includes reactive ion etching or high-density plasma etching.

[0125] Figure 31 This is a bottom view of yet another self-aligned nano-silicon through-hole structure drawn according to an embodiment of this disclosure. Figure 32 According to Figure 31 A cross-sectional view of another self-aligned nano-silicon through-hole structure drawn along line AA. Figure 33 According to Figure 32The diagram shows the structure of the self-aligned nano-silicon through-hole structure after it forms the back power supply network.

[0126] In step S11′ above, the third target blind hole 53 is obtained by etching the silicon substrate 1 and the third filler 46 around the second target blind hole 52, wherein the size of the third target blind hole 53 gradually increases from one side of the second SiO2 layer 6 to the thinned side. Figure 32 The location of the seventh filler 40 is the location of the third target blind via 53. (Both the third filler 46 and the seventh filler 40 in the figure are tungsten). This results in a third target blind via 53 with a larger size than the second target blind via 52, thus increasing the final size of the nano-silicon via. Based on this, the interface contact resistance between the embedded power rail and the nano-silicon via in the self-aligned nano-silicon via structure can be reduced, which is beneficial for the widespread application of back-side power supply network technology. Figure 33 The diagram shows the structure after the self-aligned nano-silicon via structure forms the back power supply network. The third filler 46 in the figure is tungsten, and the seventh filler 40 and the back metal are both made of copper, which has better conductivity. This can further reduce the interface contact resistance between the embedded power rail and the nano-silicon via, which is conducive to the widespread application of back power supply network technology.

[0127] By configuring a back metal on the thinned side of the self-aligned nano-silicon through-hole structure formed in step S12 above, a back power supply network can be interconnected to form. The back metal is typically copper, which has excellent conductivity.

[0128] This disclosure also provides a self-aligned through-silicon nanopore structure, which is prepared by the above-described method. The self-aligned through-silicon nanopore structure according to this disclosure can be applied to various electronic devices, such as smartphones, computers, tablets (PCs), wearable smart devices, artificial intelligence devices, and power banks.

[0129] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0130] The specific embodiments described above further illustrate the purpose, technical solutions, and beneficial effects of this disclosure. It should be understood that the above descriptions are merely specific embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A method for preparing a self-aligned nano-silicon through-hole structure, characterized in that, include: Step S1, a silicon substrate (1) is provided, the silicon substrate (1) includes a fin (11) structure that is perpendicular to the surface of the silicon substrate (1) and extends upward, a first SiO2 layer (2) is grown on the silicon substrate (1), the first SiO2 layer (2) covers the fin (11) and is at the same height as the fin (11), to obtain a first structure; Step S2: A sacrificial layer (3) is grown on the top surface of the first structure. A first preset pattern is formed on the top surface of the sacrificial layer (3). The sacrificial layer (3), the first SiO2 layer (2), and the silicon substrate (1) of a first preset depth are etched sequentially from the top surface of the sacrificial layer (3) downward according to the first preset pattern to form an initial trench (4) parallel to the fin (11). The initial trench (4) includes a first trench (41), a second trench (42), and a third trench (43) arranged sequentially. Step S3: Fill the initial trench (4) with a first filler (44) until the first filler (44) is flush with the top surface of the sacrificial layer (3). The first filler (44) includes SiO2. Step S4: A second preset pattern is formed on the top surface of the first filler (44). The second preset pattern is located at the positions of the first trench (41) and the second trench (42). According to the second preset pattern, the first filler (44) and the silicon substrate (1) at a second preset depth are etched sequentially from the top surface of the first filler (44) downward to form a first initial blind hole (5). Step S5: Fill the first initial blind hole (5) with a second filler (45) until the second filler (45) is flush with the top surface of the sacrificial layer (3), remove the sacrificial layer (3) and the first filler (44) and the second filler (45) located within the height range of the sacrificial layer (3) to obtain the second structure, wherein the second filler (45) includes SiO2; Step S6: Grow a second SiO2 layer (6) on the top surface of the second structure; etch the second SiO2 layer (6) at the position corresponding to the remaining first filler (44) and the second SiO2 layer (6) at the position corresponding to the remaining second filler (45); etch the remaining first filler (44) to form a target trench (4′); etch the remaining second filler (45) to form a first target blind hole (51); Step S7: Fill the target trench (4′) and the first target blind hole (51) with a third filler (46). The third filler (46) is higher than the root of the fin (11) and lower than the top of the fin (11). Fill the top surface of the third filler (46) with a fourth filler (47) until the fourth filler (47) is flush with the second SiO2 layer (6) to obtain a third structure. The third filler (46) includes tungsten and the fourth filler (47) includes SiO2. Step S8: A third preset pattern is formed on the top surface of the third structure. The second SiO2 layer (6), the fourth filler (47) and the first SiO2 layer (2) are etched downward from the top surface of the third structure according to the third preset pattern until the third filler (46) is exposed. The fifth filler (48) is filled in the groove generated by the etching until the fifth filler (48) is flush with the second SiO2 layer (6) to obtain the fourth structure. The fifth filler (48) includes tungsten, and the third preset pattern does not include the position corresponding to the first target blind hole (51). Step S9: Thin the fourth structure from one side of the silicon substrate (1) until the third filler (46) in the first target blind hole (51) is exposed, to obtain the self-aligned nano-silicon through-hole structure. The material used in the sacrificial layer (3) has an anisotropic etching selectivity ratio less than or equal to a preset ratio with respect to the silicon substrate (1), the first SiO2 layer (2), the first filler (44), and the second filler (45), wherein the preset ratio is 1:

10. In step S7, before filling the target trench (4′) and the first target blind hole (51) with the third filler (46), the method further includes: An electrical isolation layer, a diffusion barrier layer, and an adhesive layer are sequentially grown on the bottom and sidewalls of the target trench (4′) and the first target blind hole (51).

2. The method according to claim 1, characterized in that, The process after step S9 also includes: Step S10: Etch the third filler (46) in the first target blind hole (51) exposed in step S9 to form a second target blind hole (52), wherein the second target blind hole (52) does not exceed the plane where the root of the fin (11) is located; Step S11: Fill the second target blind hole (52) with a sixth filler (49) to obtain another self-aligned nano-silicon through-hole structure, wherein the sixth filler (49) comprises copper.

3. The method according to claim 2, characterized in that, The process after step S10 also includes: Step S11′, etch the silicon substrate (1) and the third filler (46) around the second target blind hole (52) to obtain the third target blind hole (53), wherein the size of the third target blind hole (53) gradually increases from one side of the second SiO2 layer (6) to the thinned side; Step S12′: Fill the third target blind hole (53) with a seventh filler (40) to obtain another self-aligned nano-silicon through-hole structure, wherein the seventh filler (40) includes copper or tungsten.

4. The method according to claim 1, characterized in that, The first structure is obtained in the following way: Perform the fin field-effect transistor process until the interfin isolation oxide filling step of the fin field-effect transistor process is completed to obtain the first structure.

5. The method according to claim 1, characterized in that, Step S2 includes: Photoresist is coated on the upper surface of the sacrificial layer (3), and the first preset pattern is formed by exposure. The first preset pattern is parallel to the direction of the fin (11) and is not above the fin (11). According to the first preset pattern, the sacrificial layer (3), the first SiO2 layer (2) and the silicon substrate (1) are etched sequentially from the top surface of the sacrificial layer (3) downwards, and the remaining photoresist is removed to obtain the initial trench (4); The removal of the remaining photoresist is performed after the etching of the sacrificial layer (3), or after the sacrificial layer (3), the first SiO2 layer (2) and the silicon substrate (1) are etched sequentially from the top surface of the sacrificial layer (3) downwards.

6. The method according to claim 1, characterized in that, In step S4, forming a second preset pattern on the top surface of the first filler (44), the second preset pattern being located at the positions of the first trench (41) and the second trench (42), and sequentially etching the first filler (44) and the silicon substrate (1) at a second preset depth from the top surface of the first filler (44) downwards according to the second preset pattern to form a first initial blind hole (5) includes: Photoresist is coated on the top surface of the first filler (44) and the top surface of the sacrificial layer (3); Photoresist within a preset range is exposed along a direction perpendicular to the fin (11), and the position corresponding to the exposed first filler (44) is determined as the second preset pattern; According to the second preset pattern, the first filler (44) and the silicon substrate (1) of the second preset depth are etched sequentially from the top surface of the first filler (44) downwards, and the remaining photoresist is removed to form the first initial blind hole (5). The removal of the remaining photoresist is performed after the etching of the first filler (44), or after the first filler (44) and the silicon substrate (1) of the second preset depth are etched sequentially from the top surface of the first filler (44) downwards.

7. The method according to claim 1, characterized in that, Step S6 further includes: After forming the target trench (4′), the silicon substrate (1) is etched downwards to a third predetermined depth and / or After the formation of the first target blind hole (51), the silicon substrate (1) is etched downward to a fourth predetermined depth.

8. The method according to claim 3, characterized in that, Before etching the silicon substrate (1) surrounding the second target blind hole (52) in step S11', the process further includes: The adhesive layer, diffusion barrier layer and electrical isolation layer of the sidewall of the second target blind hole (52) are removed in sequence.

9. The method according to claim 3, characterized in that, In step S12′, before filling the third target blind hole (53) with the seventh filler (40), the method further includes: An electrical isolation layer, a diffusion barrier layer, and an adhesion layer are sequentially grown on the sidewall of the third target blind hole (53).

10. A self-aligned nano-silicon through-hole structure, characterized in that, Prepared by the method described in any one of claims 1-9.

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