Field-effect transistors, their fabrication methods, and peripheral circuit structures

Abstract

This disclosure relates to a field-effect transistor (FET), its fabrication method, and peripheral circuit structure. The FET includes an active region; a gate, comprising a first portion on the active region and a second portion outside the active region; a gate contact plug electrically connected to the second portion; a source region and a drain region, respectively located in the active regions on opposite sides of the first portion; a source contact layer including multiple source contact plugs connected to the source region and spaced apart along the extension direction of the first portion; and a drain contact layer including multiple drain contact plugs connected to the source region and spaced apart along the extension direction of the first portion. By reducing the coupling area between the source contact layer and the gate, and between the drain contact layer and the gate, and thus reducing the coupling capacitance, the delay time of the FET is reduced, while keeping the contact resistance constant.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a field-effect transistor, a method for fabricating the same, and a peripheral circuit structure. Background Technology

[0002] As semiconductor manufacturing technology advances to deep submicron nodes, the requirements for signal delay in semiconductor devices are becoming increasingly stringent. To reduce the contact resistance of the contact plug, the contact plug area needs to be maximized. This leads to a larger coupling area between the contact plug and the gate, resulting in a larger coupling capacitance. This increases the delay of the semiconductor device, and the increased coupling capacitance exacerbates the overshoot of the lateral electric field in field-effect transistors, accelerating semiconductor device degradation. Therefore, reducing the delay of semiconductor devices while simultaneously lowering the contact resistance has become a critical problem to solve. Summary of the Invention

[0003] This disclosure provides a field-effect transistor, a method for fabricating the same, and a peripheral circuit structure, which can optimize signal delay in the field-effect transistor and the peripheral circuit structure.

[0004] This disclosure provides a field-effect transistor, including:

[0005] Active region;

[0006] The gate includes a first portion located on the active region and a second portion located outside the active region;

[0007] The gate contact plug is electrically connected to the second part;

[0008] The source and drain regions are located in the active regions on opposite sides of the first part, respectively;

[0009] The source contact layer includes a plurality of source contact plugs, each source contact plug being connected to a source region and spaced apart along the extension direction of the first portion; and

[0010] The drain contact layer includes a plurality of drain contact plugs, each drain contact plug being connected to the source region and spaced apart along the extension direction of the first portion.

[0011] In one embodiment, the ratio of the extension length of the source contact plug to the extension length of the active region is 0.1 to 0.2; and / or the ratio of the extension length of the drain contact plug to the extension length of the active region is 0.1 to 0.2.

[0012] In one embodiment, the distance between adjacent source contact plugs is a first spacing, the ratio of the first spacing to the extension length of the source contact plug is 0.1 to 0.2; and / or the distance between adjacent drain contact plugs is a second spacing, the ratio of the second spacing to the extension length of the drain contact plug is 0.1 to 0.2.

[0013] In one embodiment, the source contact plug includes:

[0014] The metal silicide layer is in contact with the source region;

[0015] The source conductive layer is located on the metal silicide layer; and

[0016] The source barrier layer is located between the source conductive layer and the metal silicide layer, in contact with the top surface of the metal silicide layer, and extends along the top surface of the metal silicide layer to cover the sidewall of the source conductive layer.

[0017] In one embodiment, the extension direction of the source contact plug is the same as the extension direction of the first portion, and the distance between each source contact plug and the first portion is the same; the extension direction of the drain contact plug is the same as the extension direction of the first portion, and the distance between each drain contact plug and the first portion is the same.

[0018] In one embodiment, the extension direction of the source contact plug intersects the extension direction of the first portion, and the extension directions of each source contact plug are the same; the extension direction of the drain contact plug intersects the extension direction of the first portion, and the extension directions of each drain contact plug are the same.

[0019] In one embodiment, the angle between the extension direction of the source contact plug and the extension direction of the active region is 10° to 30°; the angle between the extension direction of the drain contact plug and the extension direction of the active region is 10° to 30°; wherein the direction of the extension width of the active region intersects with the extension direction of the active region.

[0020] In the aforementioned field-effect transistor, the source contact layer includes a plurality of source contact plugs connected to the source region and spaced apart along the extension direction of the first portion. With the contact resistance of the source contact layer remaining constant, the coupling area between the source contact layer and the gate is reduced by setting the source contact plugs, thereby reducing the coupling capacitance and the delay time of the field-effect transistor. The drain contact layer includes a plurality of drain contact plugs connected to the drain region and spaced apart along the extension direction of the first portion. With the contact resistance of the drain contact layer remaining constant, the coupling area between the drain contact layer and the gate is reduced by setting the drain contact plugs, thereby reducing the coupling capacitance and further shortening the delay time of the field-effect transistor.

[0021] This disclosure also provides a peripheral circuit structure, including:

[0022] Base;

[0023] The first field-effect transistor, as described above, is located on a substrate;

[0024] The second field-effect transistor, as described above, is located on the substrate;

[0025] A first pseudo-gate structure is located on the substrate and is spaced apart from the first source region and / or the first drain region of the first field-effect transistor.

[0026] The second pseudo-gate structure is located on the substrate and is spaced apart from the second source region and / or the second drain region of the second field-effect transistor.

[0027] A first interconnect wire, one end of which is connected to the first gate contact plug of the first field-effect transistor, and the other end of which is connected to the second gate contact plug of the second field-effect transistor;

[0028] The second interconnect wire has one end connected to the first source contact layer of the first field-effect transistor, and the other end connected to the second source contact layer of the second field-effect transistor.

[0029] The third interconnect wire is connected to the first drain contact layer of the first field-effect transistor; and

[0030] The fourth interconnect wire is connected to the second drain contact layer of the second field-effect transistor.

[0031] In one embodiment, the projection of the second portion of the first gate of the first field-effect transistor onto the substrate is T-shaped, and the projection of the second portion of the second gate of the second field-effect transistor onto the substrate is L-shaped.

[0032] In the aforementioned peripheral circuit structure, the first source contact layer includes a plurality of first source contact plugs that are connected to the first source region and spaced apart along the extension direction of the first portion of the first gate. The second source contact layer includes a plurality of second source contact plugs that are connected to the second source region and spaced apart along the extension direction of the first portion of the second gate. With the contact resistance of the first source contact layer and the second source contact layer remaining unchanged, the coupling area between the first source contact layer and the first gate is reduced by setting the first source contact plugs, thereby reducing the coupling capacitance and shortening the delay time of the peripheral circuit structure. The coupling area between the second source contact layer and the second gate is reduced by setting the second source contact plugs, thereby reducing the coupling capacitance and further shortening the delay time of the peripheral circuit structure.

[0033] This disclosure also provides a method for fabricating a field-effect transistor, comprising:

[0034] Active regions are formed in the substrate;

[0035] A gate is formed on an active region, the gate including a first portion located on the active region and a second portion located outside the active region;

[0036] Source and drain regions are formed in the active regions on opposite sides of the first part;

[0037] Multiple source contact plugs are formed on the source region to obtain a source contact layer. Each source contact plug is connected to the source region and is arranged at intervals along the extension direction of the first part.

[0038] Multiple drain contact plugs are formed on the drain region to obtain a drain contact layer. Each drain contact plug is connected to the drain region and is arranged at intervals along the extension direction of the first part.

[0039] The above-described method for fabricating a field-effect transistor involves forming multiple source contact plugs on the source region, which are connected to the source region and spaced apart along the extension direction of the first portion. With the contact resistance of the source contact layer remaining constant, the source contact plugs reduce the coupling area between the source contact layer and the gate, thereby reducing the coupling capacitance and the delay time of the field-effect transistor. Similarly, multiple drain contact plugs are formed on the drain region, which are connected to the drain region and spaced apart along the extension direction of the first portion. With the contact resistance of the drain contact layer remaining constant, the drain contact plugs reduce the coupling area between the drain contact layer and the gate, thereby reducing the coupling capacitance and further shortening the delay time of the field-effect transistor. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a top view schematic diagram of a field-effect transistor in one embodiment;

[0042] Figure 2 This is a top view of a field-effect transistor in another embodiment;

[0043] Figure 3 As one embodiment Figure 2 A cross-sectional view of the corresponding semiconductor structure along the AA direction;

[0044] Figure 4 As one embodiment Figure 2A cross-sectional view of the corresponding semiconductor structure along the BB direction;

[0045] Figure 5 This is a top view of the peripheral circuit structure in one embodiment;

[0046] Figure 6 This is a top view schematic block diagram of a storage device in one embodiment;

[0047] Figure 7 This is a schematic flowchart of a method for fabricating a field-effect transistor in one embodiment.

[0048] Explanation of reference numerals in the attached figures:

[0049] 102. Active region; 104. Gate; 106. Gate contact plug; 108. Source region; 110. Drain region; 112. Source contact layer; 114. Drain contact layer; 116. Interlayer dielectric layer; 118. Dummy gate; 202. Source contact plug; 204. Drain contact plug; 302. Metal silicide layer; 304. Source barrier layer; 306. Source conductive layer; 308. Second metal silicide layer; 310. Drain barrier layer; 312. Drain conductive layer; 402. First field-effect transistor; 404. Second field-effect transistor; 406. First dummy gate structure; 408. Second dummy gate structure; 410. First interconnect wire; 412. Second interconnect wire; 414. Third interconnect wire Line; 416, Fourth interconnect wire; 502, First source region; 504, First drain region; 506, First gate; 508, First gate contact plug; 510, First source contact layer; 512, First source contact plug; 514, First drain contact layer; 516, First drain contact plug; 602, Second source region; 604, Second drain region; 606, Second gate; 608, Second gate contact plug; 610, Second source contact layer; 612, Second source contact plug; 614, Second drain contact layer; 616, Second drain contact plug; 702, Substrate; 704, Device region; 706, Peripheral region; 708, Memory array; 710, Row decoder; 712, Column decoder. Detailed Implementation

[0050] To facilitate understanding of the embodiments of this disclosure, a more complete description of the embodiments of this disclosure will be provided below with reference to the accompanying drawings. Preferred embodiments of the embodiments of this disclosure are shown in the drawings. However, the embodiments of this disclosure can be implemented in many different forms and are not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of this disclosure belong. The terminology used herein in the description of embodiments of this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0052] In the description of the embodiments of this disclosure, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the method or positional relationship shown in the drawings. They are only for the convenience of describing the embodiments of this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this disclosure.

[0053] It is understood that the terms "first," "second," etc., as used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first field-effect transistor may be referred to as a second field-effect transistor, and similarly, a second field-effect transistor may be referred to as a first field-effect transistor. Both the first and second field-effect transistors are field-effect transistors, but they are not the same field-effect transistor.

[0054] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise expressly specified. In the description of this disclosure, "a number" means at least one, such as one, two, etc., unless otherwise expressly specified. It should also be understood that the terms "comprising / including" or "having," etc., specify the presence of the stated features, integrals, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, integrals, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term "and / or" includes any and all combinations of the associated listed items.

[0055] As used herein, the terms “substrate” and “base” refer to and include the base material or structure of the transistor material described in this disclosure. A substrate can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. A substrate can be a conventional silicon substrate or other bulk substrate comprising layers of semiconductor material.

[0056] In this disclosure, the upper surface of the substrate is the surface on which the gate is formed, and the lower surface of the substrate is the surface of the substrate facing away from the gate. The upper and lower surfaces of other structures or layers are relative to the upper surface of the substrate. For structures or layers located within the substrate, in the longitudinal direction, the surface closer to the upper surface of the substrate is called the upper surface / top surface / top / top face, and the surface facing away from the upper surface is called the lower surface / bottom surface / bottom / bottom face. Conversely, for structures or layers located on the substrate, the surface closer to the upper surface of the substrate is called the lower surface / bottom surface / bottom / bottom face, and the surface facing away from the upper surface is called the upper surface / top surface / top / top face. For structures, trenches, holes, or layers in a semiconductor structure, the surface in the horizontal direction is the sidewall of the structure, trench, hole, or layer. The extension direction in this disclosure is the length direction of the long side.

[0057] Figure 1This is a top view schematic diagram of a field-effect transistor (FET) in one embodiment. The present disclosure provides a FET including: an active region 102, a gate 104, a gate contact plug 106, a source region 108, a drain region 110, a source contact layer 112, and a drain contact layer 114. The gate 104 includes a first portion located on the active region 102 and a second portion located outside the active region 102. The active region 102 is located in a substrate. In a first direction, the gate 104 includes the first portion and the second portion, wherein the first direction is the direction in which the gate 104 extends on the gate 104. The orthographic projection of the first portion onto the substrate is located in the active region 102, and the orthographic projection of the second portion onto the substrate is located outside the active region 102 (there is no overlapping area with the active region 102). It is understood that the first portion extends along the first direction. The gate contact plug 106 is electrically connected to the second portion and is located on the gate 104, used to lead the gate 104 to the field-effect transistor. For example, the bottom surface of the gate contact plug 106 on the transistor surface contacts the top surface of the second portion; the source region 108 and the drain region 110 are respectively located in the active regions 102 on opposite sides of the first portion; the source contact layer 112 includes a plurality of source contact plugs 202, each source contact plug 202 is connected to the source region 108 and is spaced apart along the extension direction (first direction) of the first portion, and the bottom surface of each source contact plug 202 is contacted with the same... The top surface of the source region 108 is in contact with the top surface of the source region 110 for leading the source region 108 to the source pad of the field-effect transistor. The drain contact layer 114 includes a plurality of drain contact plugs 204, each drain contact plug 204 connected to the source region 110 and spaced apart along the extension direction (first direction) of the first portion. The bottom surface of each drain contact plug 204 is in contact with the top surface of the same drain region 110 for leading the drain region 110 to the drain pad of the field-effect transistor. Exemplarily, the first direction is the X direction.

[0058] Compared to leading out the source region 108 through the entire source contact layer 112, this disclosure reduces the equivalent contact area between the source contact layer 112 and the source region 108, and reduces the coupling area between the source contact layer 112 and the gate 104, while keeping the total source contact resistance between the source contact layer 112 and the source region 108 constant. The capacitance calculation formula is as follows: Where ε is the dielectric constant, S is the area of ​​one side of the capacitor plate, d is the distance between the capacitor plates, and k is a constant of electrostatic force. The capacitance increases with the increase of the capacitor plate area and decreases with the increase of the distance between the capacitor plates. Therefore, as the coupling area between the source contact layer 112 and the gate 104 decreases, the coupling capacitance decreases, and the delay time of the field-effect transistor decreases. Simultaneously, by setting the source contact layer 112 to include multiple spaced source contact plugs 202 connected to the source region 108, the current density increases, further reducing the resistivity of the source contact plugs 202. With the total source contact resistance remaining constant, the size of the source contact plugs 202 can be further reduced, achieving the goal of further reducing the delay time of the field-effect transistor.

[0059] In the aforementioned field-effect transistor, the source contact layer 112 includes a plurality of source contact plugs 202 connected to the source region 108 and spaced apart along the extension direction of the first portion. With the contact resistance of the source contact layer 112 remaining constant, the coupling area between the source contact layer 112 and the gate 104 is reduced by setting the source contact plugs 202, thereby reducing the coupling capacitance and decreasing the delay time of the field-effect transistor. The drain contact layer 114 includes a plurality of drain contact plugs 204 connected to the drain region 110 and spaced apart along the extension direction of the first portion. With the contact resistance of the drain contact layer 114 remaining constant, the coupling area between the drain contact layer 114 and the gate 104 is reduced by setting the drain contact plugs 204, thereby reducing the coupling capacitance and further shortening the delay time of the field-effect transistor.

[0060] like Figure 1As shown, in one embodiment, the ratio of the extension length L1 of the source contact plug 202 to the extension length L2 of the active region 102 is 0.1 to 0.2. When the ratio is higher than 0.2, the extension length L1 of the source contact plug 202 is too large, which not only increases the coupling area between the source contact layer 112 and the gate 104 and increases the coupling capacitance, but also reduces the uniformity of silicide deposition and increases the series resistance of the source contact layer 112 as the extension length L1 of the source contact plug 202 increases. When the ratio is lower than 0.1, the contact area between a single source contact plug 202 and the source is too small, which also leads to an increase in contact resistance and greater process difficulty. A ratio within this range can achieve a good balance between the two and effectively improve the circuit delay of the device. Specifically, the source contact plug 202 extends along the second direction X1, and the active region 102 extends along the third direction X2. The extension length L1 of the source contact plug 202 is the length of the source contact plug 202 in the second direction X1, and the extension length L2 of the active region 102 is the length of the active region 102 in the third direction X2. The ratio of the extension length L1 to the extension length L2 is 0.1 to 0.2, for example, 0.1, 0.12, 0.14, 0.15, 0.17, 0.19, 0.2, etc.

[0061] In one embodiment, the extension length L1 of each source contact plug 202 is the same, which simplifies the fabrication process of the source contact plug 202.

[0062] In some embodiments, the dimensions of each source contact plug 202 are the same as those of existing contact plugs in the field-effect transistor. This arrangement reduces the size of the contact plugs in the field-effect transistor, simplifying the contact plug fabrication process. For example, the dimensions of the source contact plug 202 are the same as those of the gate contact plug 106.

[0063] like Figure 1 As shown, in one embodiment, the extension direction (second direction X1) of the source contact plug 202 is the same as the extension direction (first direction X) of the first portion, and the distance D1 between each source contact plug 202 and the first portion is the same.

[0064] like Figure 1 As shown, in one embodiment, the extension direction (second direction X1) of the source contact plug 202 is the same as the extension direction (first direction X) of the first part. The distance D1 between the source contact plug 202 and the first part is affected by the operating voltage and the device area. After the first distance D3 in the X direction and the extension length L1 of the source contact plug 202 are determined, the distance D1 in the Y direction is determined according to the operating voltage and the device area, and the circuit delay of the device is further improved.

[0065] Figure 2 This is a top view schematic diagram of a field-effect transistor in another embodiment, as shown below. Figure 2 As shown, in this embodiment, the extension direction (second direction X1) of the source contact plug 202 intersects the extension direction (first direction X) of the first part, and the extension directions of each source contact plug 202 are the same. Since the coupling capacitance decreases as the distance between the capacitor plates increases, compared with the extension direction of the source contact plug 202 being the same as the extension direction of the first part, setting the extension direction of the source contact plug 202 to intersect the extension direction of the first part makes the source contact plug 202 and the gate 104 have an inclined angle, which increases the overall distance between the two plates of the coupling capacitor (source contact plug 202 and gate 104), further reducing the coupling capacitance, and achieving the purpose of further shortening the delay time of the field-effect transistor.

[0066] like Figure 2 As shown, in one embodiment, the angle between the extension direction (second direction X1) of the source contact plug 202 and the extension direction (third direction X2) of the active region 102, i.e., the tilt angle, is 10° to 30°. The minimum distance D11 between the source contact plug 202 and the first portion, and the maximum distance D12 between the source contact plug 202 and the first portion, are also considered. Similarly, the minimum distance D11 in the Y direction is affected by the operating voltage and device area. After the first distance D3 in the X direction, the extension length L1 of the source contact plug 202, and the tilt angle are determined, the minimum distance D11 is determined based on the operating voltage and device area. It can be understood that when the same device is arranged parallel to and spaced apart from the contact plug, the minimum distance D11 when the contact plug is tilted is equal to the distance D1.

[0067] In some embodiments, the second direction X1 and the third direction X2 are both parallel to the first direction X. In other embodiments, at least one of the second direction X1, the third direction X2, and the first direction X intersects with other directions.

[0068] like Figure 1As shown, in one embodiment, the ratio of the extension length L3 of the drain contact plug 204 to the extension length L2 of the active region 102 is 0.1 to 0.2. Specifically, the drain contact plug 204 extends along the fourth direction X3, and the extension length L3 of the drain contact plug 204 is the length of the drain contact plug 204 in the fourth direction X3. The extension length L2 of the active region 102 is the length of the active region 102 in the third direction X2. The ratio of the extension length L3 to the extension length L2 is 0.1 to 0.2, for example, 0.1, 0.12, 0.14, 0.15, 0.17, 0.19, 0.2, etc. It can be understood that the drain contact plug 204 and the source contact plug 202 are the same size and are symmetrically distributed along the first portion of the gate 104.

[0069] In one embodiment, the extension length L3 of each drain contact plug 204 is the same, which simplifies the fabrication process of the drain contact plug 204.

[0070] In some embodiments, the dimensions of each drain contact plug 204 are the same as those of existing contact plugs in the field-effect transistor. This arrangement reduces the size of the contact plugs in the field-effect transistor, simplifying the contact plug fabrication process. For example, the dimensions of the drain contact plug 204 are the same as those of the gate contact plug 106 and / or the source contact plug 202.

[0071] like Figure 1 As shown, in one embodiment, the extension direction (fourth direction X3) of the drain contact plug 204 is the same as the extension direction (first direction X) of the first portion, and the spacing D2 between each drain contact plug 204 and the first portion is the same.

[0072] like Figure 1 As shown, in one embodiment, the extension direction (fourth direction X3) of the drain contact plug 204 is the same as the extension direction (first direction X) of the first portion, and the distance D2 between the drain contact plug 204 and the first portion is the same as the distance D1 between the source contact plug 202 and the first portion.

[0073] like Figure 2As shown, the extension direction (fourth direction X3) of the drain contact plug 204 intersects the extension direction of the first part, and the extension directions of each drain contact plug 204 are the same. Since the coupling capacitance decreases as the distance between the capacitor plates increases, compared with the extension direction of the drain contact plug 204 being the same as the extension direction of the first part, setting the extension direction of the drain contact plug 204 to intersect the extension direction of the first part makes the drain contact plug 204 and the gate 104 have an inclined angle, which increases the overall distance between the two plates of the coupling capacitor (drain contact plug 204 and gate 104), further reducing the coupling capacitance, and achieving the purpose of further shortening the delay time of the field-effect transistor.

[0074] like Figure 2 As shown, the angle between the extending direction (fourth direction X3) of the drain contact plug 204 and the extending direction (third direction X2) of the active region 102, i.e., the tilt angle, is 10° to 30°, specifically, the same as the tilt angle of the source contact plug 202. The minimum distance D21 between the drain contact plug 204 and the first part, and the maximum distance D22 between the drain contact plug 204 and the first part, are the same as the distances D21 and D22 between the active region 202 and the distances D11 and D12 between the source contact plug 202 and the first part.

[0075] In some embodiments, the fourth direction X3 and the third direction X2 are both parallel to the first direction X. In other embodiments, at least one of the fourth direction X3, the third direction X2, and the first direction X intersects with other directions.

[0076] In one embodiment, the fourth direction X3 is parallel to the second direction X1, which facilitates the arrangement of the source contact plug 202 and the drain contact plug 204.

[0077] like Figure 1As shown, in one embodiment, the distance between adjacent source contact plugs 202 is a first spacing D3, that is, the source contact plugs 202 are arranged at equal intervals on the top surface of the source region 108. The first spacing D3 is the distance between adjacent source contact plugs 202 in the extension direction (second direction X1) of the source contact plugs 202. The ratio of the first spacing D3 to the extension length L1 of the source contact plugs 202 is 0.1 to 0.2. When the ratio is greater than 0.2, the spacing between adjacent source contact plugs 202 is too large, which not only reduces the number of source contact plugs 202 in the source contact layer 112, but also reduces the contact area of ​​a single source contact plug 202 in contact with the source region, and increases the contact resistance. When the ratio is less than 0.1, the spacing between adjacent source contact plugs 202 is too small, the coupling area between the source contact plugs 112 and the gate 104 is too large, and the coupling capacitance increases. A ratio within this range can achieve a good balance between the two and effectively improve the circuit delay of the device. This ratio is, for example, 0.1, 0.12, 0.14, 0.15, 0.17, 0.19, 0.2, etc. It is understood that when the source contact plug 202 extends in a direction parallel to the first direction X, the first spacing D3 is the distance between adjacent source contact plugs 202 in the first direction X.

[0078] In some embodiments, the source contact plugs 202 are spaced apart along the extension direction of the source region 108. In another embodiment, the source contact plugs 202 are spaced apart along the extension direction (third direction X2) of the active region 102. It is understood that the orthographic projection of the bottom surface of each source contact plug 202 onto the substrate lies within the active region 102.

[0079] like Figure 1 As shown, in one embodiment, the distance between adjacent drain contact plugs 204 is a second spacing D4. That is, the drain contact plugs 204 are evenly spaced on the top surface of the drain region 110. The second spacing D4 is the distance between adjacent drain contact plugs 204 in the extending direction (fourth direction X3) of the drain contact plugs 204. The ratio between the second spacing D4 and the extending length L3 of the drain contact plugs 204 is 0.1 to 0.2, for example, 0.1, 0.12, 0.14, 0.15, 0.17, 0.19, 0.2, etc. It is understood that when the extending direction of the drain contact plugs 204 is parallel to the first direction X, the second spacing D4 is the distance between adjacent drain contact plugs 204 in the first direction X. It is understood that the second spacing D4 and the first spacing D3 have the same dimensions.

[0080] In some embodiments, the drain contact plugs 204 are spaced apart along the extension direction of the drain region 110. In another embodiment, the drain contact plugs 204 are spaced apart along the extension direction (third direction X2) of the active region 102. It is understood that the orthographic projection of the bottom surface of each drain contact plug 204 onto the substrate lies within the active region 102.

[0081] In some embodiments, the orthographic projections of the source contact plug 202 and the drain contact plug 204 onto the active region 102 may include, but are not limited to, one or more of the following: rectangle (square, elongated rectangle), ellipse, or circle.

[0082] In some embodiments, the shape of the orthographic projection of the source contact plug 202 onto the active region 102 is the same as the shape of the orthographic projection of the drain contact plug 204 onto the active region 102.

[0083] Figure 3 As one embodiment Figure 2 A cross-sectional view of the corresponding semiconductor structure along the AA direction. Figure 4 As one embodiment Figure 2 A cross-sectional view of the corresponding semiconductor structure along the BB direction, as shown below. Figure 3 , Figure 4 As shown, in this embodiment, the source contact plug 202 includes: a metal silicide layer 302, a source barrier layer 304, and a source conductive layer 306. The metal silicide layer 302 is in contact with the source region 108; the source conductive layer 306 is located on the metal silicide layer 302; the source barrier layer 304 is located between the source conductive layer 306 and the metal silicide layer 302, in contact with the top surface of the metal silicide layer 302, and extends along the top surface of the metal silicide layer 302 to cover the sidewall of the source conductive layer 306. Specifically, the metal silicide layer 302 can be located at the position of the source region 108 in the substrate. In this embodiment, multiple metal silicide layers 302 are formed only at the positions where multiple contact plugs contact the source region 108. No metal silicide is formed at the positions where there are no contact plugs. This avoids the continuous formation of large areas of metal silicide, and thus avoids the situation where there are many thermal processes during the metal silicide process, resulting in great non-uniformity of the metal silicide.

[0084] Optionally, the source barrier layer 304 may be composed of materials including, but not limited to, metallic titanium and / or titanium nitride.

[0085] Optionally, the constituent materials of the source conductive layer 306 include, but are not limited to, one or more of conductive polycrystalline silicon, metal, conductive metal nitride, and conductive metal oxide. For example, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), gold (Au), silver (Ag), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); and the conductive metal oxide includes iridium oxide (IrO2).

[0086] like Figure 3 , Figure 4 As shown, in one embodiment, the drain contact plug 204 includes: a second metal silicide layer 308, a drain barrier layer 310, and a drain conductive layer 312. The second metal silicide layer 308 is in contact with the drain region 110; the drain conductive layer 312 is located on the second metal silicide layer 308; the drain barrier layer 310 is located between the drain conductive layer 312 and the second metal silicide layer 308, in contact with the top surface of the second metal silicide layer 308, and extends along the top surface of the second metal silicide layer 308 to cover the sidewall of the drain conductive layer 312. Specifically, similar to the second metal silicide layer 302 of the source region 108, the metal silicide 308 is located at the position of the drain region 110 in the substrate.

[0087] Optionally, the drain barrier layer 310 may be made of materials including but not limited to titanium and / or titanium nitride, and the materials of the drain barrier layer 310 and the source barrier layer 304 may be the same or different.

[0088] Optionally, the drain conductive layer 312 may be composed of one or more of conductive polycrystalline silicon, metal, conductive metal nitride, and conductive metal oxide. For example, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), gold (Au), silver (Ag), or titanium (Ti); the conductive metal nitride may include titanium nitride (TiN); and the conductive metal oxide may include iridium oxide (IrO2). For example, the drain conductive layer 312 may be composed of the same or different materials as the source conductive layer 306.

[0089] like Figure 1 , Figure 3 , Figure 4As shown, in one embodiment, the field-effect transistor further includes: an interlayer dielectric layer 116 located on the active region 102 and extending along the sidewall of the gate 104 to cover the top surface of the gate 104; a gate contact plug 106 penetrating the interlayer dielectric layer 116 and contacting the gate 106; each source contact plug 202 penetrating the interlayer dielectric layer 116 and contacting the source region 108; and each drain contact plug 204 penetrating the interlayer dielectric layer 116 and contacting the drain region 110. Exemplarily, the top surface of the gate contact plug 106 is lower than or flush with the top surface of the interlayer dielectric layer 116, the top surface of the source contact plug 202 is lower than or flush with the top surface of the interlayer dielectric layer 116, and the top surface of the drain contact plug 204 is lower than or flush with the top surface of the interlayer dielectric layer 116.

[0090] For example, the constituent materials of the interlayer dielectric layer 116 include, but are not limited to, one or more of silicon oxide (e.g., silicon dioxide), silicon nitride (silicon oxynitride), and nitride (e.g., silicon nitride).

[0091] In one embodiment, the substrate includes a device region and a peripheral region, the device region being used to form memory cells and the peripheral region being used to form peripheral circuit structures, with field-effect transistors located in the peripheral region.

[0092] For example, a field-effect transistor includes a plurality of gate contact plugs 106. While keeping the overall contact resistance of the gate contact plugs unchanged, the area occupied by the gate contact plugs 106 is reduced, thereby further reducing the size of the field-effect transistor.

[0093] Figure 5 This is a top view of the peripheral circuit structure in one embodiment, such as... Figure 5As shown, in this embodiment, a peripheral circuit structure is provided, such as an input / output circuit. This input / output circuit can amplify current. Specifically, it includes: a substrate, a first field-effect transistor 402, a second field-effect transistor 404, a first dummy gate structure 406, a second dummy gate structure 408, a first interconnect wire 410, a second interconnect wire 412, a third interconnect wire 414, and a fourth interconnect wire 416. The first field-effect transistor 402 is located on the substrate; the second field-effect transistor 404 is also located on the substrate. That is, the structures of the first and second field-effect transistors are the same as those of the aforementioned field-effect transistors, and will not be described in detail here. The first field-effect transistor 402 includes a first source region 502, a first drain region 504, a first gate 506, a first gate contact plug 508, and a first source contact layer 510. The first source contact plug 512, the first drain contact layer 514, and the first drain contact plug 516; the second field-effect transistor 404 includes a second source region 602, a second drain region 604, a second gate 606, a second gate contact plug 608, a second source contact layer 610, a second source contact plug 612, a second drain contact layer 614, and a second drain contact plug 616; a first dummy gate structure 406 is located on the substrate, and the first dummy gate structure 406 is spaced apart from the first source region 502 and / or the first drain region 504; specifically, the first dummy gate structure 406 is located on the side of the first source region 502 away from the first gate 506, and / or the first dummy gate structure 406 is located on the side of the first drain region 504 away from the first gate 506, and the first dummy gate structure 406 can ensure the consistency of the overall pattern density of the area on the substrate where the first field-effect transistor 402 is formed. The second dummy gate structure 408 is located on the substrate and is spaced apart from the second source region 602 and / or the second drain region 604. Specifically, the second dummy gate structure 408 is located on the side of the second source region 602 away from the second gate 606, and / or the second dummy gate structure 408 is located on the side of the second drain region 604 away from the second gate 606. The second dummy gate structure 408 can ensure the consistency of the overall pattern density of the area on the substrate where the second field-effect transistor 404 is formed.One end of the first interconnect wire 410 is connected to the first gate contact plug 508, and the other end of the first interconnect wire 410 is connected to the second gate contact plug 608, for connecting the first gate 506 and the second gate 606 to the surface of the peripheral circuit structure; one end of the second interconnect wire 412 is connected to the first source contact layer 510, and the other end of the second interconnect wire 412 is connected to the second source contact layer 610, for connecting the first source region 502 and the second source region 602 to the surface of the peripheral circuit structure, wherein the first source contact layer 510 includes a plurality of first source contact plugs 512, the second source contact layer 610 includes a plurality of second source contact plugs 612, and the second interconnect wire 412 includes a first segment that is simultaneously connected to a plurality of first source contact plugs 512 and a second segment that is simultaneously connected to a plurality of second source contact plugs 512. The second segment is connected to the plug 612, and the third segment is connected to the first segment and the second segment and extends to the surface of the peripheral circuit structure; the third interconnecting wire 414 is connected to the first drain contact layer 514 to connect the first drain region 504 to the surface of the peripheral circuit structure, wherein the first drain contact layer 514 includes a plurality of first drain contact plugs 516, and the third interconnecting wire 414 contacts the plurality of first drain contact plugs 516 on the first drain region 504; the fourth interconnecting wire 416 is connected to the second drain contact layer 614 to connect the second drain region 604 to the surface of the peripheral circuit structure, wherein the second drain contact layer 614 includes a plurality of second drain contact plugs 616, and the fourth interconnecting wire 416 contacts the plurality of second drain contact plugs 616 on the second drain region 604.

[0094] like Figure 5 As shown, in one embodiment, the projection of the second portion of the first gate 506 of the first field-effect transistor 402 onto the substrate is T-shaped, and the projection of the second portion of the second gate 606 of the second field-effect transistor 404 onto the substrate is L-shaped.

[0095] In the aforementioned peripheral circuit structure, the first source contact layer 510 includes a plurality of first source contact plugs 512 that are connected to the first source region 502 and spaced apart along the extension direction of the first portion of the first gate 506, and the second source contact layer 610 includes a plurality of second source contact plugs 612 that are connected to the second source region 602 and spaced apart along the extension direction of the first portion of the second gate 606. With the contact resistance of the first source contact layer 510 and the second source contact layer 610 remaining constant, the coupling area between the first source contact layer 510 and the first gate 506 is reduced by setting the first source contact plugs 512, thereby reducing the coupling capacitance and shortening the delay time of the peripheral circuit structure. Similarly, the coupling area between the second source contact layer 610 and the second gate 606 is reduced by setting the second source contact plugs 612, thereby reducing the coupling capacitance and further shortening the delay time of the peripheral circuit structure.

[0096] In other embodiments, the peripheral circuit structure includes, but is not limited to, control circuits, antifuse units, and buffer circuits, and other peripheral circuit structures can be formed using the field-effect transistors described above.

[0097] Figure 6 This is a top view schematic block diagram of a storage device in one embodiment, as shown below. Figure 6 As shown, this disclosure also provides a memory device including a substrate 702. The substrate 702 includes a device region 704 and a peripheral region 706. The device region 704 is used to form memory cells in the memory device. The memory cells include a memory array 708, a row decoder 710, and a column decoder 712. The peripheral region 706 is used to form any of the peripheral circuit structures described above.

[0098] Figure 7 This is a schematic flowchart of a method for fabricating a field-effect transistor in one embodiment, as shown below. Figure 1 , Figure 7 As shown, this disclosure also provides a method for fabricating a field-effect transistor, comprising:

[0099] S102 forms an active region in the substrate.

[0100] A substrate is provided, and an active region 102 is formed in the substrate. The substrate is composed of materials including, but not limited to, undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). As an example, in this embodiment, the substrate is composed of single-crystal silicon.

[0101] S104, a gate is formed on the active region, the gate including a first portion located on the active region and a second portion located outside the active region.

[0102] A gate 104 is formed on the active region 102. The gate 104 includes a first portion located on the active region 102 and a second portion located outside the active region 102. In a first direction X, the gate 104 includes the first portion and the second portion. The first direction is the direction in which the gate 104 extends on the gate 104. The orthographic projection of the first portion on the substrate is located in the active region 102, and the orthographic projection of the second portion on the substrate is located outside the active region 102 (there is no overlapping area with the active region 102). It can be understood that the first portion extends along the first direction X.

[0103] S106 forms source and drain regions in the active regions on opposite sides of the first part.

[0104] S108, a plurality of source contact plugs are formed on the source region to obtain a source contact layer, and each source contact plug is connected to the source region and is arranged at intervals along the extension direction of the first part.

[0105] Multiple source contact plugs 202 are formed on the source region 108 to obtain the source contact layer 112. Each source contact plug 202 is connected to the source region 108 and is arranged at intervals along the extension direction of the first part. The bottom surface of each source contact plug 202 is in contact with the top surface of the same source region 108.

[0106] S110, a plurality of drain contact plugs are formed on the drain region to obtain a drain contact layer, and each drain contact plug is connected to the drain region and is arranged at intervals along the extension direction of the first part.

[0107] Multiple drain contact plugs 204 are formed on the drain region 110 to obtain a drain contact layer 114. Each drain contact plug 204 is connected to the drain region 110 and is arranged at intervals along the extension direction of the first portion. The bottom surface of each drain contact plug 204 is in contact with the top surface of the same drain region 110.

[0108] The above-described method for fabricating a field-effect transistor involves forming a plurality of source contact plugs 202 on the source region 108, which are connected to the source region 108 and spaced apart along the extension direction of the first portion of the gate 104. With the contact resistance of the source contact layer 112 remaining constant, the source contact plugs 202 reduce the coupling area between the source contact layer 112 and the gate 104, thereby reducing the coupling capacitance and the delay time of the field-effect transistor. Similarly, a plurality of drain contact plugs 204 are formed on the drain region 110, which are connected to the drain region 110 and spaced apart along the extension direction of the first portion. With the contact resistance of the drain contact layer 114 remaining constant, the drain contact plugs 204 reduce the coupling area between the drain contact layer 114 and the gate 104, thereby reducing the coupling capacitance and further shortening the delay time of the field-effect transistor.

[0109] The limitations of the source contact plug 202, drain contact plug 204, and gate contact plug 106 in the fabrication method of the field-effect transistor in this disclosure are the same as the limitations of the source contact plug 202, drain contact plug 204, and gate contact plug 106 in the field-effect transistor, and will not be repeated here.

[0110] In one embodiment, the method for fabricating a field-effect transistor further includes: forming a gate contact plug 106 electrically connected to the second portion of the gate 104 on the second portion, and leading the gate 104 to the gate pad on the surface of the field-effect transistor through the gate contact plug 106. For example, the bottom surface of the gate contact plug 106 is in contact with the top surface of the second portion.

[0111] like Figure 3 As shown, in one embodiment, a plurality of source contact plugs 202 are formed on the source region 108 and a plurality of drain contact plugs 204 are formed on the drain region 110. This includes: forming an interlayer dielectric layer 116 on a substrate; and simultaneously opening a plurality of first contact holes exposing the source region 108 and a plurality of second contact holes exposing the drain region 110 in the interlayer dielectric layer 116. For example, the bottom of the first contact hole is lower than or flush with the top surface of the source region 108, and the bottom of the second contact hole is lower than or flush with the top surface of the drain region 110; and forming source contact plugs 202 in the first contact holes and forming drain contact plugs 204 in the second contact holes.

[0112] In one embodiment, a plurality of first contact holes exposing the source region 108 and a plurality of second contact holes exposing the drain region 110 are simultaneously formed in the interlayer dielectric layer 116. The embodiment further includes: forming a third contact hole in the interlayer dielectric layer 116 that exposes a second portion of the gate 104. The bottom of the third contact hole is lower than or flush with the top surface of the gate 104, wherein the gate contact plug 106 is filled in the third contact hole.

[0113] like Figure 3 As shown, in one embodiment, forming a source contact plug 202 in a first contact hole includes: forming a metal silicide layer 302 at the bottom of the first contact hole; forming a source barrier layer 304 on the top surface of the metal silicide layer 302, the source barrier layer 304 extending along the top surface of the metal silicide layer 302 to cover the sidewall of the first contact hole; and filling the first contact hole with a source conductive layer 306, the source conductive layer 306 filling the first contact hole, wherein the metal silicide layer 302, the source barrier layer 304 and the source conductive layer 306 together constitute the source contact plug 202.

[0114] like Figure 3 As shown, in one embodiment, forming a drain contact plug 204 in the second contact hole includes: forming a second metal silicide layer 308 at the bottom of the second contact hole; forming a drain barrier layer 310 on the top surface of the second metal silicide layer 308, the drain barrier layer 310 extending along the top surface of the second metal silicide layer 308 to cover the sidewall of the second contact hole; and filling the second contact hole with a drain conductive layer 312, the drain conductive layer 312 filling the second contact hole, wherein the second metal silicide layer 308, the drain barrier layer 310 and the drain conductive layer 312 together constitute the drain contact plug 204.

[0115] It should be understood that, although Figure 7The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 7 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0116] This disclosure also provides an electronic device including any of the aforementioned field-effect transistors. This electronic device may include a smartphone, computer, tablet computer, artificial intelligence, wearable device, or smart mobile terminal. This application does not impose any special limitations on the specific form of the described electronic device.

[0117] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0118] The above-described embodiments are merely illustrative of several implementation methods of the present disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present disclosure embodiments, and these modifications and improvements all fall within the protection scope of the present disclosure embodiments.

Claims

1. A field effect transistor, characterized by include: Active region; The gate includes a first portion located on the active region and a second portion located outside the active region; The gate contact plug is electrically connected to the second part; The source region and the drain region are respectively located in the active regions on opposite sides of the first part; The source contact layer includes a plurality of source contact plugs, each of which is connected to the source region and is spaced apart along the extension direction of the first portion. as well as The drain contact layer includes a plurality of drain contact plugs, each of which is connected to the source region and is spaced apart along the extension direction of the first portion. The angle between the extension direction of the source contact plug and the extension direction of the active region is 10° to 30°; the angle between the extension direction of the drain contact plug and the extension direction of the active region is 10° to 30°; wherein, the direction of the extension width of the active region intersects with the extension direction of the active region.

2. The field effect transistor of claim 1, wherein The ratio of the extension length of the source contact plug to the extension length of the active region is 0.1 to 0.2; and / or the ratio of the extension length of the drain contact plug to the extension length of the active region is 0.1 to 0.

2.

3. The field effect transistor of claim 1, wherein The distance between adjacent source contact plugs is a first spacing, and the ratio of the first spacing to the extension length of the source contact plug is 0.1 to 0.2; and / or the distance between adjacent drain contact plugs is a second spacing, and the ratio of the second spacing to the extension length of the drain contact plug is 0.1 to 0.

2.

4. The field effect transistor of claim 1, wherein The source contact plug includes: A metal silicide layer is in contact with the source region; The source conductive layer is located on the metal silicide layer; and A source barrier layer is located between the source conductive layer and the metal silicide layer, in contact with the top surface of the metal silicide layer, and extends along the top surface of the metal silicide layer to cover the sidewall of the source conductive layer.

5. The field effect transistor of claim 1, wherein The extension direction of the source contact plug is the same as that of the first part, and the distance between each source contact plug and the first part is the same. The extension direction of the drain contact plug is the same as that of the first part, and the distance between each drain contact plug and the first part is the same.

6. The field-effect transistor according to claim 1, characterized in that, The extension direction of the source contact plug intersects the extension direction of the first portion, and the extension directions of each source contact plug are the same; the extension direction of the drain contact plug intersects the extension direction of the first portion, and the extension directions of each drain contact plug are the same.

7. A peripheral circuit structure, characterized in that, include: Base; A first field-effect transistor, wherein the first field-effect transistor is the field-effect transistor according to any one of claims 1-6, is located on the substrate; The second field-effect transistor, which is the field-effect transistor according to any one of claims 1-6, is located on the substrate; A first pseudo-gate structure is located on the substrate and is spaced apart from the first source region and / or the first drain region of the first field-effect transistor. The second pseudo-gate structure is located on the substrate and is spaced apart from the second source region and / or the second drain region of the second field-effect transistor. A first interconnect wire, one end of which is connected to the first gate contact plug of the first field-effect transistor, and the other end of which is connected to the second gate contact plug of the second field-effect transistor; A second interconnect wire, one end of which is connected to the first source contact layer of the first field-effect transistor, and the other end of which is connected to the second source contact layer of the second field-effect transistor. A third interconnect wire is connected to the first drain contact layer of the first field-effect transistor; and The fourth interconnect wire is connected to the second drain contact layer of the second field-effect transistor.

8. The peripheral circuit structure according to claim 7, characterized in that, The projection of the second portion of the first gate of the first field-effect transistor onto the substrate is T-shaped, and the projection of the second portion of the second gate of the second field-effect transistor onto the substrate is L-shaped.

9. A method for fabricating a field-effect transistor, characterized in that, include: Active regions are formed in the substrate; A gate is formed on the active region, the gate including a first portion located on the active region and a second portion located outside the active region; Source and drain regions are formed in the active regions on opposite sides of the first portion; Multiple source contact plugs are formed on the source region to obtain a source contact layer. Each source contact plug is connected to the source region and is arranged at intervals along the extension direction of the first portion. Multiple drain contact plugs are formed on the drain region to obtain a drain contact layer. Each drain contact plug is connected to the drain region and is spaced apart along the extension direction of the first portion. The angle between the extension direction of the source contact plug and the extension direction of the active region is 10° to 30°; the angle between the extension direction of the drain contact plug and the extension direction of the active region is 10° to 30°; wherein, the direction of the extension width of the active region intersects with the extension direction of the active region.

Images