Method for manufacturing a quantum bit and quantum chip

Abstract

The application discloses a manufacturing method of a quantum bit and a quantum chip, and belongs to the technical field of quantum computation. According to the scheme, the electrical parameter measurement of a superconducting quantum interference device is realized by contact connection of a first superconducting film, a second superconducting film and a test circuit, and then a patterning process is implemented on the first superconducting film and the second superconducting film, so that constituent elements of the quantum bit can be formed on the basis of the first superconducting film and the second superconducting film. According to the application, the superconducting film is directly used to construct a region for realizing contact connection during the test of the superconducting quantum interference device, and this is helpful to realize efficient electrical detection of the superconducting quantum interference device squid.

Description

Technical Field

[0001] This application belongs to the field of quantum information, especially the field of quantum computing technology. In particular, this application relates to a method for manufacturing qubits and a quantum chip. Background Technology

[0002] Quantum chips are the core components of quantum computers. The basic structure of a quantum chip in a superconducting physics system is as follows: a superconducting quantum interference device (Squid), formed by parallel Josephson junctions, is connected in parallel with an additional capacitor plate. The superconducting quantum bit circuit formed based on this parallel structure serves as the basic unit for performing quantum computation on the quantum chip—the qubit. A Josephson junction is generally a structure consisting of two superconductors sandwiched by a very thin barrier layer (thickness ≤ the coherence length of the Cooper pair), such as an S (superconducting material layer)—I (semiconductor or insulating material layer)—S (superconducting material layer) structure. The performance quality of the superconducting quantum interference device (Squid) directly determines the performance of the qubits; therefore, testing is necessary to confirm its suitability. Invention Content

[0003] The embodiments of this application provide a method for manufacturing qubits and a quantum chip to achieve efficient electrical detection of the superconducting quantum interference device squid.

[0004] One embodiment of this application provides a method for manufacturing qubits, comprising:

[0005] A superconducting film is formed on the surface of a substrate, and the superconducting film is patterned to form a first superconducting film and a second superconducting film for contact connection with a test circuit, as well as a junction preparation region located between the first superconducting film and the second superconducting film;

[0006] A superconducting quantum interference device is formed in the junction preparation region, with one end connected to the first superconducting film and the other end connected to the second superconducting film;

[0007] The first and second superconducting films are connected in contact with the test circuit, and the electrical parameters of the superconducting quantum interference device are tested.

[0008] When the electrical parameters meet the design requirements, the first superconducting film and the second superconducting film are used to form the constituent elements of the quantum bit, and the constituent elements include at least one capacitor.

[0009] In some embodiments of the manufacturing method described above, the step of forming the constituent elements of a quantum bit using the first superconducting film and the second superconducting film includes: patterning the first superconducting film to form a capacitor and patterning the second superconducting film to form a ground, wherein the capacitor is connected to one end of the superconducting quantum interference device and the ground is connected to the other end of the superconducting quantum interference device.

[0010] In some embodiments of the manufacturing method described above, the step of forming the constituent elements of a quantum bit using the first superconducting film and the second superconducting film includes: patterning the first superconducting film to form a first capacitor, and patterning the second superconducting film to form a second capacitor, wherein the first capacitor is connected to one end of the superconducting quantum interference device, and the second capacitor is connected to the other end of the superconducting quantum interference device.

[0011] In some embodiments of the manufacturing method described above, the superconducting quantum interference device includes at least two Josephson junctions, and the Josephson junctions are connected in parallel.

[0012] In some embodiments of the manufacturing method described above, the number of Josephson knots is odd.

[0013] In some embodiments of the manufacturing method described above, the critical current of the Josephson junction is not the same.

[0014] In some embodiments of the manufacturing method described above, the Josephson junction is a tunnel junction, a point contact, or other structure exhibiting the Josephson effect.

[0015] In some embodiments of the manufacturing method described above, the method further includes: removing the superconducting quantum interference device when the electrical parameters do not meet the design requirements, and returning to the step of forming a superconducting quantum interference device in the junction preparation region, with one end connected to the first superconducting film and the other end connected to the second superconducting film.

[0016] In some embodiments of the manufacturing method described above, the electrical parameters include resistance values.

[0017] Another embodiment of this application provides a quantum chip comprising qubits manufactured according to the manufacturing method described above.

[0018] Compared with existing technologies, the quantum bit manufacturing method provided in this application involves forming a superconducting film on a substrate surface and patterning the superconducting film to form a first superconducting film and a second superconducting film for contact connection with a test circuit, as well as a junction preparation region located between the first and second superconducting films; then forming a superconducting quantum interference device (QFID) in the junction preparation region, with one end connected to the first superconducting film and the other end connected to the second superconducting film; next, contacting the first and second superconducting films with the test circuit and testing the electrical parameters of the superconducting QFID; finally, when the electrical parameters meet the design requirements, forming the constituent elements of the quantum bit using the first and second superconducting films, wherein the constituent elements include at least one capacitor. The proposed solution first uses the first and second superconducting films to contact the test circuit to achieve electrical parameter measurement of the superconducting QFID, and then performs patterning processes on the first and second superconducting films, thereby forming the constituent elements of the quantum bit based on the first and second superconducting films. This application utilizes a superconducting film to directly construct a region that facilitates contact connection during testing of a superconducting quantum interference device (Squid), which helps to achieve efficient electrical detection of the Squid device. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of a quantum bit on a quantum chip in related technologies;

[0020] Figure 2 A flowchart illustrating a method for manufacturing qubits according to an embodiment of this application;

[0021] Figures 3 to 6 This is a schematic diagram of the steps in a method for manufacturing a quantum bit according to an embodiment of this application.

[0022] Figure 7 This is a schematic diagram of the structure of a first superconducting membrane 21 provided in one embodiment of this application.

[0023] Explanation of reference numerals in the attached figures:

[0024] 1-Substrate, 2-Superconducting film, 3-Superconducting quantum interference device

[0025] 21-First superconducting film, 211-First bit component, 212-First contact film,

[0026] 22-Second superconducting film, 221-Second bit component, 222-Second contact film. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the various embodiments of this application to help readers better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments. The division of the various embodiments below is for the convenience of description and should not constitute any limitation on the specific implementation of this application. The various embodiments can be combined with and referenced by each other without contradiction.

[0028] It should be noted that the terms "comprising" and "having" and any variations thereof in the specification, claims and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product or device.

[0029] Additionally, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be located directly on another layer or substrate, and / or intercalation layers may also be present. Furthermore, it should be understood that when a layer is referred to as being "under" another layer, it can be located directly under that layer, and / or one or more intercalation layers may also be present. Additionally, references to "on" and "under" the layers may be made based on the accompanying drawings.

[0030] For example, in a quantum chip within a superconducting physical system, the quantum chip has at least one qubit, and a readout cavity and control signal line coupled to it are formed nearby. The qubit includes a capacitance to ground and a superconducting quantum interference device (Squid) connected in parallel with the capacitance. This Squid is composed of parallel Josephson junctions, for example, two Josephson junctions connected in parallel. A Josephson junction, also known as a superconducting tunnel junction, is generally a structure consisting of two superconductors sandwiching a very thin barrier layer (thickness ≤ the coherence length of the Cooper pair), such as an S (superconducting material layer) – I (semiconductor or insulating material layer) – S (superconducting material layer) structure, abbreviated as SIS. The performance quality of the Josephson junction directly determines the performance of the superconducting qubit. Therefore, the fabrication process of the Squid (i.e., the parallel Josephson junctions) is crucial and directly affects the performance of the qubit, such as its coherence.

[0031] See Figure 1The diagram shows a quantum bit structure with a cross-shaped capacitor plate C. q Surrounded by a ground plane (GND), and with a cross-shaped capacitor plate C q With a gap between it and the ground plane (GND), one end of the superconducting quantum interference device squid is connected to a cross-shaped capacitor plate C. q The other end is connected to the ground plane (GND), due to the cross-shaped capacitor plate C q The first end is typically used to connect to the superconducting quantum interference device (Squid), and the second end is used for coupling with the readout resonant cavity. Sufficient space needs to be reserved near both ends for wiring; for example, space needs to be reserved near the first end for arranging the xy and z signal lines. (C-shaped capacitor plate) q The other two ends are used for coupling with adjacent qubits, combining Figure 1 As shown, it can be understood that qubits with this structure are easy to arrange in a one-dimensional chain.

[0032] Currently, the manufacturing process for qubits generally follows these steps: First, a thin film is deposited on a substrate and patterned to form a readout cavity, control signal lines, and ground and ground capacitances that constitute the qubit, exposing the area for fabricating the Josephson junction (i.e., the junction preparation region). Then, photoresist is coated onto the substrate, exposed, and developed to form a mask pattern with windows. Using this mask pattern, superconducting layers, thin oxide layers, and superconducting layers are fabricated on the junction preparation region of the substrate through evaporation, oxidation, and re-evaporation, respectively, resulting in a parallel Josephson junction (i.e., a superconducting quantum interference device, squid). One superconducting layer of the squid is connected to ground, and the other is connected to the ground capacitance. The capacitor plates are not directly connected to the ground plane (GND), but rather have a suitable gap between them. The physical dimensions of this gap are designed and determined according to the performance parameters required by the quantum chip. It should be noted that a capacitor C is formed between the capacitor plates and the ground plane (GND). q The capacitance C can be calculated and determined based on the performance parameters of the quantum chip. q The values ​​are then used to calculate and determine the physical dimensions of the capacitor plates.

[0033] Typically, to determine whether the performance parameters of a manufactured superconducting quantum interference device (Squid) meet the design requirements, electrical testing is required to confirm electrical parameters such as the resistance value of the Squid. However, direct contact between the electrical components that make up the qubits during electrical contact can easily cause structural damage, leading to irreversible effects on the qubits and consequently affecting the normal use of the superconducting quantum chip.

[0034] Therefore, embodiments of this application provide a method for manufacturing qubits and a quantum chip. During the manufacturing process of qubits, electrical detection is performed on a superconducting quantum interference device (SQID) to improve the electrical detection efficiency of the SQID. Furthermore, the contact connection during this process can avoid damage to the circuit elements constituting the qubits.

[0035] Figure 2 A flowchart illustrating a method for manufacturing qubits according to an embodiment of this application;

[0036] Figures 3 to 6 This is a schematic diagram of the steps in a method for manufacturing a quantum bit according to an embodiment of this application.

[0037] Combination Figure 2 , Figures 3 to 6 As shown, one embodiment of this application provides a method for manufacturing qubits, including the following steps S101 to S104, wherein:

[0038] S101, see also Figure 3 As shown, a superconducting film 2 is formed on the surface of a substrate 1 made of high-resistivity silicon, sapphire, or other materials using a superconducting material. The superconducting film 2 is patterned to form a first superconducting film 21 and a second superconducting film 22 for contact connection with the test circuit, as well as a junction preparation region located between the first superconducting film 21 and the second superconducting film 22. The first superconducting film 21, the second superconducting film 22, and the junction preparation region are surrounded by a superconducting film serving as ground (as shown in the area where GND is located in the figure), and a suitable gap is formed between them. The superconducting material includes one of TiN, Nb, NbTiN, Al, or Ta. In specific implementations, it is not limited to these types. Any material that exhibits superconducting properties at a temperature equal to or below the critical temperature is acceptable.

[0039] S102, see also Figure 4 As shown, a superconducting quantum interference device 3 is formed in the junction preparation region, with one end connected to the first superconducting film 21 and the other end connected to the second superconducting film 22. The Josephson junction included in the superconducting quantum interference device 3 is a structure composed of two superconducting layers sandwiched by a very thin barrier layer (thickness ≤ coherence length of Cooper electron pairs), such as an S (superconducting material layer) — I (semiconductor or insulating material layer) — S (superconducting material layer) structure. The superconducting quantum interference device 3 is connected to the first superconducting film 21 through one superconducting layer and to the second superconducting film 22 through the other superconducting layer.

[0040] S103, see also Figure 5As shown, the first superconducting membrane 21 and the second superconducting membrane 22 are connected in contact with the test circuit, and the electrical parameters of the superconducting quantum interference device 3 are tested. For example, the resistance value can be determined by applying a current signal to the test circuit and testing the voltage signal between the first superconducting membrane 21 and the second superconducting membrane 22.

[0041] S104, see also Figure 6 As shown, when the electrical parameters meet the design requirements, the first superconducting film 21 and the second superconducting film 22 are used to form the constituent elements of the quantum bit. Specifically, patterning processes are performed on the first superconducting film 21 and the second superconducting film 22, and the constituent elements of the quantum bit are formed based on the first superconducting film 21 and the second superconducting film 22. The constituent elements include at least one capacitor.

[0042] In implementing the quantum bit manufacturing method proposed in this application, the electrical parameters of the superconducting quantum interference device 3 are first measured by contacting and connecting the first superconducting film 21 and the second superconducting film 22 with the test circuit. For example, the first superconducting film 21 may include an integrated first bit component 211 and a first contact film 212, and the second superconducting film 22 may include an integrated second bit component 221 and a second contact film 222. Then, patterning processes are applied to the first superconducting film 21 and the second superconducting film 22, thereby forming the components of the quantum bit, such as the first bit component 211 and the second bit component 221, on the basis of the first superconducting film 21 and the second superconducting film 22. This application utilizes the superconducting film 2 to directly construct a region (such as the first contact film 212 and the second contact film 222) that facilitates contact connection during testing of the superconducting quantum interference device 3. Connecting this region with the test circuit helps to achieve efficient electrical detection of the superconducting quantum interference device (Squid).

[0043] Furthermore, based on the solution proposed in this application, when patterning and other processes are performed on the first superconducting film 21 and the second superconducting film 22 to obtain the constituent elements of the qubit, there is sufficient space to avoid the positions that are in contact with the test circuit. That is, when performing patterning and other processes, the parts of the first superconducting film 21 and the second superconducting film 22 that are in contact with the test circuit (such as the first contact film 212 and the second contact film 222 shown in the figure) can be removed, and the uncontacted first bit constituent element 211 and second bit constituent element 221 can be retained, thereby avoiding damage to the circuit elements constituting the qubit.

[0044] For example, when performing a patterning process on the first superconducting film 21 and the second superconducting film 22 made of aluminum to obtain the desired shape structure, a wet etching process can be used, such as using a TMAH solution to remove excess parts, or a gaseous dry etching process can be used to remove them. The etching gas can be chlorine gas or boron trichloride gas.

[0045] Figure 7 This is a schematic diagram of the structure of a first superconducting membrane 21 provided in one embodiment of this application.

[0046] It should be noted that the shape and structure of the first superconducting film 21 and the second superconducting film 22 are not limited to those specified in the original text. Figures 3 to 6 As shown. Taking the first superconducting film 21 as an example, as long as the first superconducting film 21 includes two parts: the first bit constituent element 211 and the first contact film 212, and after the electrical parameter test is performed by contacting and connecting the first contact film 212 with the test circuit, the first contact film 212 can be removed using semiconductor technology, leaving only the first bit constituent element 211 as the constituent element of the quantum bit. For example, combined with... Figure 7 As shown, the first superconducting film 21 includes a first contact film 212 located on the periphery, and a first bit component element 211 that is partially (or entirely) surrounded by and integral with the first contact film 212. The first contact film 212 is used to connect to the test circuit. Specifically, a probe can be inserted into the first contact film 212 to connect it to the test circuit. After performing electrical testing, the first contact film 212 located on the periphery is etched away, thus obtaining the capacitor plate used to form a qubit with the superconducting quantum interference device 3. Since the first contact film 212, which suffers structural damage due to the probe insertion, is independent of the capacitor plate, this structure can achieve electrical detection while ensuring that the component elements of the qubit do not suffer structural damage.

[0047] In some embodiments, the step of forming constituent elements of a quantum bit using the first superconducting film and the second superconducting film includes: patterning the first superconducting film 21 to form a first capacitor (as shown in the figure, the first bit constituent element 211), and patterning the second superconducting film 22 to form a second capacitor (as shown in the figure, the second bit constituent element 221), wherein the first capacitor is connected to one end of the superconducting quantum interference device 3, and the second capacitor is connected to the other end of the superconducting quantum interference device 3.

[0048] In other embodiments, the step of forming constituent elements of a qubit using the first superconducting film 21 and the second superconducting film 222 includes: patterning the first superconducting film 21 to form a capacitor, and patterning the second superconducting film 22 to form a ground, wherein the capacitor is connected to one end of the superconducting quantum interference device 3, and the ground is connected to the other end of the superconducting quantum interference device 3. It should be noted that the formed capacitor can refer to the first qubit constituent element 211 shown in the accompanying drawings, and the formed ground, not shown in the drawings, can be an integral part of or connected to the ground.

[0049] In some embodiments, the superconducting quantum interference device 3 includes at least two Josephson junctions connected in parallel. To ensure that the frequency of the qubits has two or more insensitive points to the flux modulation signal, the number of Josephson junctions is, for example, odd, and the critical currents of the Josephson junctions are not identical. In one embodiment, the Josephson junction is a tunnel junction, a point contact, or other structure exhibiting the Josephson effect.

[0050] In some embodiments, the method for manufacturing qubits provided in this application further includes: when the electrical parameters do not meet the design requirements, removing the superconducting quantum interference device 3 and returning to the step of forming the superconducting quantum interference device 3 in the junction preparation region, with one end connected to the first superconducting film 21 and the other end connected to the second superconducting film 22, thereby re-performing the process of manufacturing the superconducting quantum interference device 3 in the junction preparation region. The removal of the superconducting quantum interference device 3 can be achieved through dry etching or wet etching, etc.

[0051] Fabricating a qubit according to embodiments of this application may require depositing one or more materials, such as superconductors, dielectrics, and / or metals. Depending on the materials chosen, these materials can be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), epitaxial techniques, or other deposition processes. The fabrication process of a qubit described in embodiments of this application may require removing one or more materials from the device during the fabrication process. Depending on the material to be removed, the removal process may include, for example, wet etching, dry etching, or lift-off processes. The materials forming the circuit elements described herein can be patterned using known lithographic techniques (e.g., photolithography or electron beam lithography).

[0052] One embodiment of this application provides a quantum chip comprising qubits manufactured according to the manufacturing method described above.

[0053] It should be noted that the qubits in the above quantum chip are obtained according to the above manufacturing method and have the same beneficial effects as those in the above manufacturing method embodiments, therefore, they will not be described in detail here. For technical details not disclosed in the superconducting quantum chip embodiments of this application, those skilled in the art should refer to the description of the above quantum chip for understanding; for the sake of brevity, they will not be repeated here.

[0054] The embodiments of this application also provide a quantum computer, which is a superconducting system, and the quantum computer is equipped with at least the quantum chip described in the embodiments of this application.

[0055] The above description, based on the embodiments shown in the drawings, details the structure, features, and effects of this application. The above description is only a preferred embodiment of this application, but this application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of this application, or modifications to equivalent embodiments, that do not exceed the spirit covered by the specification and drawings, should be within the protection scope of this application.

Claims

1. A method for manufacturing a quantum bit, characterized in that, include: A superconducting film is formed on the surface of a substrate, and the superconducting film is patterned to form a first superconducting film and a second superconducting film for contact connection with a test circuit, as well as a junction preparation region located between the first superconducting film and the second superconducting film; A superconducting quantum interference device is formed in the junction preparation region, with one end connected to the first superconducting film and the other end connected to the second superconducting film; The first and second superconducting films are connected in contact with the test circuit, and the electrical parameters of the superconducting quantum interference device are tested. When the electrical parameters meet the design requirements, the parts of the first and second superconducting films that are in contact with the test circuit are removed, and the uncontacted parts are retained to form the constituent elements of the quantum bit, the constituent elements including at least one capacitor.

2. The manufacturing method according to claim 1, characterized in that, The step of removing the portions of the first and second superconducting films that are in contact with the test circuit, and retaining the uncontacted portions to form the constituent elements of the quantum bit, includes: The first superconducting film is graphically represented as a capacitor, and the second superconducting film is graphically represented as a ground. The capacitor is connected to one end of the superconducting quantum interference device, and the ground is connected to the other end of the superconducting quantum interference device.

3. The manufacturing method according to claim 1, characterized in that, The step of removing the portions of the first and second superconducting films that are in contact with the test circuit, and retaining the uncontacted portions to form the constituent elements of the quantum bit, includes: The first superconducting film is graphically represented to form a first capacitor, and the second superconducting film is graphically represented to form a second capacitor. The first capacitor is connected to one end of the superconducting quantum interference device, and the second capacitor is connected to the other end of the superconducting quantum interference device.

4. The manufacturing method according to any one of claims 1 to 3, characterized in that, The superconducting quantum interference device includes at least two Josephson junctions, which are connected in parallel.

5. The manufacturing method according to claim 4, characterized in that, The number of Josephson knots is odd.

6. The manufacturing method according to claim 4, characterized in that, The critical currents of the Josephson junctions are different.

7. The manufacturing method according to claim 4, characterized in that, The Josephson junction is a tunnel junction, a point contact, or other structure that exhibits the Josephson effect.

8. The manufacturing method according to any one of claims 1 to 3 or any one of claims 5 to 7, characterized in that, Also includes: If the electrical parameters do not meet the design requirements, the superconducting quantum interference device is removed, and the process returns to the step of forming a superconducting quantum interference device in the junction preparation region, with one end connected to the first superconducting film and the other end connected to the second superconducting film.

9. The manufacturing method according to any one of claims 1 to 3 or any one of claims 5 to 7, characterized in that, The electrical parameters include resistance values.

10. A quantum chip, characterized in that, This includes qubits manufactured by the manufacturing method according to any one of claims 1 to 9.

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