Semiconductor structure

Abstract

A semiconductor structure is provided. The semiconductor structure includes at least a first well region disposed in a semiconductor substrate and having a first conductivity type. At least a gate of a transistor is disposed over the first well region and extends in a first direction. At least a second well region and at least a third well region are disposed on opposite sides of the first well region and extend in the first direction. The second well region and the third well region have a second conductivity type that is complementary to the first conductivity type. A first shield structure is disposed at least one end of the gate and partially overlaps the first well region in a perpendicular projection direction. The first shield structure is separated from the end of the gate. A bulk ring is disposed in the semiconductor substrate and surrounds the gate, the second well region, the third well region, and the first shield structure.

Description

Technical Field

[0001] This invention relates to a semiconductor structure, and more particularly to a semiconductor structure having a shielding structure. Background Technology

[0002] The electronics industry is experiencing an increasing demand for smaller, faster electronic devices that simultaneously support a larger volume of increasingly complex and high-tech functions. Therefore, a continuing trend in the semiconductor industry is the production of low-cost, high-performance, and low-power integrated circuits (ICs).

[0003] Today, integrated circuits comprise millions or billions of semiconductor elements formed on a semiconductor substrate (such as silicon). Depending on the application, many different types of semiconductor structures can be used in integrated circuits. In recent years, the increasing market for cellular devices and radio frequency (RF) components has led to a significant increase in the use of high-voltage semiconductor structures. For example, high-voltage semiconductor structures are commonly used in power amplifiers in RF transmitters / receivers due to their ability to manipulate high breakdown voltages and high frequencies. Furthermore, high-voltage semiconductor structures are also used in electrostatic discharge (ESD) protection circuits. Summary of the Invention

[0004] This invention provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate, at least one first well region, at least one gate of a transistor, at least one second well region and at least one third well region, a first shielding structure, and a bulk ring. The at least one first well region is disposed in the semiconductor substrate and has a first conductivity type. The at least one gate of the transistor is disposed above the at least one first well region and extends along a first direction. The at least one second well region and the at least one third well region are disposed on opposite sides of the at least one first well region and extend along the first direction. The at least one second well region and the at least one third well region have a second conductivity type, which is complementary to the first conductivity type. The first shielding structure is disposed at at least one end of the at least one gate and partially overlaps with the at least one first well region in a vertical projection direction. The first shielding structure is separated from the at least one end of the at least one gate. The bulk ring is disposed in the semiconductor substrate and surrounds the at least one gate, the at least one second well region, the at least one third well region, and the first shielding structure. Attached Figure Description

[0005] Figure 1 This is a top view showing a semiconductor structure according to some embodiments of the present invention.

[0006] Figure 2 This is to illustrate the embodiments described in the present invention. Figure 1 A top view of a semiconductor structure with metal lines and metal plates removed.

[0007] Figure 3 This is to illustrate the embodiments described in the present invention. Figures 1-2 A cross-sectional view of the semiconductor structure along line A-AA.

[0008] Figure 4 This is to illustrate the embodiments described in the present invention. Figures 1-2 A cross-sectional view of the semiconductor structure along the B-BB line.

[0009] Figure 5 This is a top view showing a semiconductor structure according to some embodiments of the present invention.

[0010] Figure 6 This is to illustrate the embodiments described in the present invention. Figure 5 A cross-sectional view of the semiconductor structure along the C-CC line.

[0011] Figure 7 This is to illustrate the embodiments described in the present invention. Figure 5 A cross-sectional view of the semiconductor structure along the D-DD line.

[0012] Figure 8 This is a top view showing a semiconductor structure according to some embodiments of the present invention.

[0013] Figure 9 This is to illustrate the embodiments described in the present invention. Figure 8 A cross-sectional view of the semiconductor structure along the E-EE line.

[0014] Figure 10 This is a top view showing a semiconductor structure according to some embodiments of the present invention.

[0015] Figure 11 This is to illustrate the embodiments described in the present invention. Figure 10 Top view of a semiconductor structure.

[0016] Figure 12 This describes an electrostatic discharge protection circuit implemented using a semiconductor structure according to some embodiments of the present invention.

[0017] Figure 13 This is a top view showing a semiconductor structure according to some embodiments of the present invention.

[0018] Explanation of reference numerals in the attached figures:

[0019] 10A, 10A_1-10A_4: Shielding structure

[0020] 10B, 10B_1-10B_4: Shielding structure

[0021] 10C_1-10C_3: Shielding structure

[0022] 10D_1-10D_2: Shielding structure

[0023] 10E_1-10E_3: Shielding structure

[0024] 10F_1-10F_2: Shielding structure

[0025] 15: Semiconductor substrate

[0026] 30A: Shielding structure

[0027] 30B: Shielding structure

[0028] 50: Electrostatic discharge protection circuit

[0029] 52: Joint pad

[0030] 100: Semiconductor Structure

[0031] 105a-105b: First Well Area

[0032] 110a-110e: Second Well Area

[0033] 120a-120e: Annular well area

[0034] 122: Block Ring

[0035] 125a-125d: First Well Area

[0036] 130: Field Oxide

[0037] 132a-132e: First doped region

[0038] 134: Second doped region

[0039] 205:Contact

[0040] 210a-210e: Metal wire

[0041] 215a, 215b: Electrodes

[0042] 300: Semiconductor Structure

[0043] 400: Semiconductor Structure

[0044] 500: Semiconductor Structure

[0045] 510: Electrode

[0046] 512, 514, 516: Sub-electrodes

[0047] 520, 522: Metal wire

[0048] 600: Semiconductor Structure

[0049] D: Drain region

[0050] G: Gate

[0051] S: Source region

[0052] VSS: Grounding terminal Detailed Implementation

[0053] To make the above and other objects, features, and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings:

[0054] The following disclosure provides numerous embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, the embodiments of the invention may repeat reference values ​​and / or letters in various examples. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0055] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," and "higher," may be used to facilitate the description of the relationship between one or more components or features in the accompanying drawings and another component or feature(s). Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0056] Figure 1This is a top view showing a semiconductor structure 100 according to some embodiments of the present invention. In some embodiments, the semiconductor structure 100 is an N-type symmetric semiconductor structure. In some embodiments, the semiconductor structure 100 is a high-voltage semiconductor structure. In this embodiment, the semiconductor structure 100 includes a transistor, and the bulk region of the transistor forms a ring, hereinafter referred to as bulk ring 122. Bulk ring 122 is an interconnect structure (not shown) electrically coupled to an upper layer via a contact 205 and a metal line 210a. In some embodiments, the gate G of the transistor in the semiconductor structure 100 includes a metal gate structure. Furthermore, the gate G is an interconnect structure (not shown) electrically coupled to an upper layer via a contact 205 and metal lines 210d and 210e. The source region S of the transistor in the semiconductor structure 100 is formed in a second well region 110a and electrically coupled to an upper layer interconnect structure (not shown) via a contact 205 and a metal line 210b. Furthermore, the drain region D of the transistor in semiconductor structure 100 is formed in the second well region 110b and electrically coupled to the upper interconnect structure (not shown) via contact 205 and metal line 210c. In this embodiment, metal line 210a partially overlaps the bulk ring 122. Additionally, metal lines 210b, 210c, 210d, and 210e extend along the Y direction, while metal lines 210d and 210e cross a portion of the bulk ring 122 (i.e., the portion not covered by metal line 210a).

[0057] exist Figure 1 In this embodiment, the semiconductor structure 100 also includes shielding structures 10A and 10B. In this embodiment, the bulk ring 122 is a square ring. Shielding structures 10A and 10B are formed between the gate G and the bulk ring 122. For example, in layout, shielding structure 10A is formed between the gate G and a first side (or first edge) of the bulk ring 122, while shielding structure 10B is formed between the gate G and a second side (or second edge) of the bulk ring 122. For the bulk ring 122, the first side is relative to the second side. Similarly, shielding structure 10A is disposed near one end (e.g., the upper end) of the gate G, while shielding structure 10B is disposed near the other end (e.g., the lower end) of the gate G. For the gate G, shielding structures 10A and 10B are disposed at opposite ends of the gate G. In this embodiment, shielding structure 10A is also disposed between metal lines 210d and 210e. Shielding structure 10A includes an electrode (or metal plate) 215a and a contact 205, while shielding structure 10B includes an electrode (or metal plate) 215b and a contact 205. Figure 1In the top view of the semiconductor structure, the gate G extends along the Y direction. In some embodiments, the gate G is formed of polysilicon. In some embodiments, the gate G is formed of metal. The drain region D and the source region S are disposed on the left and right sides of the gate G, while the shielding structures 10A and 10B are formed on the top and bottom sides of the gate G. In other words, the gate G and the shielding structures 10A and 10B are disposed on the same straight line along the Y direction.

[0058] In the semiconductor structure 100, the metal lines 210a-210e and the metal plates 215a and 215b are formed of the same conductive material. Furthermore, the metal lines 210a-210e and the metal plates 215a and 215b are disposed in the same metal layer (e.g., the lowest metal layer). Additionally, the metal plate 215b is connected to the metal line 210a on the second side of the bulk ring 122.

[0059] Figure 2 This is to illustrate the embodiments described in the present invention. Figure 1 A top view of the semiconductor structure 100 with metal lines 210a-210e and metal plates 215a and 215b removed. Also refer to... Figure 1 and Figure 2 A first doped region 132a is formed in the second well region 110a, and a metal line 210b is electrically coupled to the source region S of the transistor via a contact 205 and the first doped region 132a. Furthermore, an N-type doped region 132b is formed in the second well region 110b, and a metal line 210c is electrically coupled to the drain region D of the transistor via a contact 205 and the first doped region 132b. The first doped regions 132a and 132b extend along the Y direction. In some embodiments, the first doped regions 132a and 132b are N-type doped regions.

[0060] In one embodiment, shielding structure 10A is made of polysilicon and is electrically coupled to metal plate 215a via contact 205. Shielding structure 10A is separate from the gate G and bulk ring 122 and partially overlaps with the second well regions 110a and 110b. Furthermore, shielding structure 10A is electrically connected to bulk ring 122 via metal plate 215a and contact 205. Similarly, in one embodiment, shielding structure 10B is made of polysilicon and is electrically coupled to metal plate 215b via contact 205. Shielding structure 10B is separate from the gate G and bulk ring 122 and partially overlaps with the second well regions 110a and 110b. Furthermore, shielding structure 10B is electrically connected to bulk ring 122 via metal plate 215b and contact 205.

[0061] In some embodiments, the gate G and shielding structures 10A and 10B are disposed on the same layer and formed of the same polysilicon material, but the present invention is not limited thereto. In some embodiments, the gate G and shielding structures 10A and 10B may be formed of different materials. The gate G comprises polysilicon, metal, or other suitable materials. The shielding structures 10A and 10B comprise polysilicon, metal, or other suitable materials. In the X direction, the width of the shielding structures 10A and 10B is smaller than the width (or dimension) of the gate G. In the Y direction, the length of the shielding structures 10A and 10B is also smaller than the length (or dimension) of the gate G. Specifically, the area of ​​the shielding structure 10A or 10B is smaller than the area of ​​the gate G to achieve better area utilization, which is beneficial for the miniaturization of semiconductor devices.

[0062] Figure 3 This is to illustrate the embodiments described in the present invention. Figures 1-2 A cross-sectional view of the semiconductor structure 100 along line A-AA. Second well regions 110a and 110b are formed in the semiconductor substrate 15. In some embodiments, the semiconductor substrate 15 may be a bulk silicon substrate, a silicon-on-insulator substrate, a binary compound semiconductor substrate, a ternary compound semiconductor substrate, or a higher-order compound semiconductor substrate, etc. The second well regions 110a and 110b are formed by implantation of one or more dopants or by ion implantation processes.

[0063] In semiconductor structure 100, the source region S is formed by a second well region 110a, and the second well region 110a is electrically coupled to the metal line 210b sequentially via a first doped region 132a and a contact 205. Furthermore, in semiconductor structure 100, the drain region D is formed by the second well region 110b, and the second well region 110b is electrically coupled to the metal line 210c sequentially via a first doped region 132b and a contact 205.

[0064] A bulk ring 122 and first well regions 105a and 105b are formed in a semiconductor substrate 15. The first well region 105a is formed between second well regions 110a and 110b, while the first well region 105b is formed between the second well regions 110a and 110b and the bulk ring 122. In some embodiments, the first well regions 105a and 105b are P-type well regions, and the second well regions 110a and 110b are N-type well regions. In some embodiments, the first well regions 105a and 105b may be the semiconductor substrate 15. In some embodiments, the first well regions 105a and 105b and the bulk ring 122 are formed of the same material. Furthermore, the transistor channel in the semiconductor structure 100 is formed in the first well region 105a. The bulk ring 122 is formed of a P-type well region. A second doped region 134 is formed in the bulk ring 122, and the metal line 210a is electrically coupled to the bulk ring 122 via the contact 205 and the second doped region 134. In some embodiments, the second doped region 134 is a heavily p-type doped region.

[0065] The second well regions 110a and 110b and the bulk ring 122 are separated by the first well region 105a. Furthermore, the first doped region 132a and the second doped region 134 are separated by field oxide 130, as are the first doped region 132b and the second doped region 134. A gate G is formed above the first well region 105a. For simplicity, other features of the gate G in the semiconductor structure 100 (e.g., the gate dielectric layer) will be omitted. Furthermore, the gate G is electrically coupled to metal lines 210d and 210e via contact 205. Additionally, the gate G and the first doped regions 132a and 132b are separated by field oxide 130.

[0066] Figure 4 This is to illustrate the embodiments described in the present invention. Figures 1-2 A cross-sectional view of the semiconductor structure 100 along line B-BB. Second well regions 110a and 110b, a bulk ring 122, and first well regions 105a and 105b are formed in the semiconductor substrate 15. A shielding structure 10B is formed on the first well region 105a and separated from the first well region 105a and the second well regions 110a and 110b via a field oxide 130. Figure 2 and Figure 4It is understood that shielding structures 10A and 10B partially overlap with the first well region 105a and the second well regions 110a and 110b in the vertical projection direction. As previously described, shielding structure 10B is electrically coupled to bulk ring 122 sequentially via contact 205, metal plate 215b, metal line 210a, contact 205, and second doped region 134. Therefore, when bulk ring 122 is grounded via interconnects in the semiconductor structure, shielding structure 10B is grounded. Thus, when a metal line formed by a higher metal layer is configured (wound) above the first well region 105a and the second well regions 110a and 110b, shielding structure 10B can prevent the voltage of the higher metal layer (e.g., the drain voltage to be supplied to the semiconductor structure 100) from coupling to the first well region 105a. Therefore, the parasitic NPN bipolar transistor (NPN BJT) 113 formed by the second well region 110a, the first well region 105a, and the second well region 110b will not be turned on, so no leakage current will be generated. In addition, leakage current generated by the gate bias voltage of the semiconductor structure 100 at high temperatures can also be suppressed, thus improving the breakdown voltage.

[0067] Figure 5 This is a top view showing a semiconductor structure 300 according to some embodiments of the present invention. In some embodiments, the semiconductor structure 300 is an N-type symmetric semiconductor structure. In some embodiments, the semiconductor structure 300 is a high-voltage semiconductor structure. In this embodiment, the semiconductor structure 300 includes a transistor, and the bulk region of the transistor forms a ring, hereinafter referred to as bulk ring 122. The gate G of the transistor in the semiconductor structure 300 is formed by a plurality of sub-gates 150a-150d. In some embodiments, the sub-gates 150a-150d are electrically coupled to the same finger electrode (not shown) on the upper layer via a contact 205. The source region S of the transistor in the semiconductor structure 300 is formed in second well regions 110a, 110c, and 110e, and electrically coupled to an interconnect structure (not shown) on the upper layer via first doped regions 132a, 132c, and 132e and contact 205. In semiconductor structure 300, the drain region D of the transistor is formed in the second well regions 110b and 110d and electrically coupled to the upper interconnect structure (not shown) via the first doped regions 132b and 132d and the contact 205. In this embodiment, for simplicity, the electrodes and metal lines in the lowest metal layer used to electrically couple the features of semiconductor structure 300 are omitted. Furthermore, the second well regions 110a, 110c, and 110e and the second well regions 110b and 110d are arranged alternately along the X direction, i.e., the drain region D and the source region S are arranged alternately along the X direction.

[0068] In this embodiment, sub-gate 150a is disposed between first doped regions 132a and 132b and above first well region 125a. Sub-gate 150b is disposed between first doped regions 132b and 132c and above first well region 125b. Sub-gate 150c is disposed between first doped regions 132c and 132d and above first well region 125c. Sub-gate 150d is disposed between first doped regions 132d and 132e and above first well region 125d. First well regions 125a-125d can be P-type well regions. Furthermore, second well regions 110a-110e are respectively surrounded by annular well regions 120a-120e. For example, second well region 110a is completely surrounded by annular well region 120a, and second well region 110b is completely surrounded by annular well region 120b. In some embodiments, the annular well regions 120a-120e may be formed by a P-type well region. In some embodiments, the annular well regions 120a-120e may be formed by a P-type substrate.

[0069] exist Figure 5 In this embodiment, the semiconductor structure 300 includes shielding structures 10A_1-10A_4 and 10B_1-10B_4. In this embodiment, the bulk ring 122 is a square ring. Shielding structures 10A_1-10A_4 are formed on a first side near the bulk ring 122, while shielding structures 10B_1-10B_4 are formed on a second side near the bulk ring 122. As previously described, shielding structures 10A_1-10A_4 and 10B_1-10B_4 are formed of polysilicon. Shielding structures 10A_1-10A_4 and 10B_1-10B_4 can be connected via a contact 205 and an upper metal plate (e.g., Figure 1 Electrodes 215a and 215b are electrically coupled to the block ring 122.

[0070] Furthermore, sub-gate 150a and shielding structures 10A_1 and 10B_1 are arranged on the same straight line along the Y direction. Sub-gate 150b and shielding structures 10A_2 and 10B_2 are arranged on the same straight line along the Y direction. Sub-gate 150c and shielding structures 10A_3 and 10B_3 are arranged on the same straight line along the Y direction. Sub-gate 150d and shielding structures 10A_4 and 10B_4 are arranged on the same straight line along the Y direction.

[0071] Figure 6 This is to illustrate the embodiments described in the present invention. Figure 5A cross-sectional view of the semiconductor structure 300 along the C-CC line. Second well regions 110a and 110b are formed in the semiconductor substrate 15. Second well region 110a forms the source region S of the semiconductor structure 300, and is electrically coupled to the metal line above via the first doped region 132a and the junction 205. Furthermore, second well region 110b forms the drain region D of the semiconductor structure 300, and is electrically coupled to the metal line above via the first doped region 132b and the junction 205.

[0072] As previously described, the second well region 110a is surrounded by an annular well region 120a, and the second well region 110b is surrounded by an annular well region 120b. A first well region 125a is formed in the semiconductor substrate 15 and between the annular well regions 120a and 120b. A sub-gate 150a is formed above the second well region 110a, the annular well region 120a, the first well region 125a, the annular well region 120b, and the second well region 110b. Furthermore, the sub-gate 150a is electrically coupled to the above metal line (e.g., a finger electrode) via a contact 205. Notably, the sub-gate 150a completely overlaps the first well region 125a.

[0073] Figure 7 This is to show the embodiments described according to the present invention. Figure 5 A cross-sectional view of the semiconductor structure 300 along the D-DD line. Second well regions 110a and 110b and a bulk ring 122 are formed in the semiconductor substrate 15. A shielding structure 10B_1 is formed on the first well region 125a and separated from the first well region 125a and the annular well regions 120a and 120b via a field oxide 130. A shielding structure 10B_2 is formed on the first well region 125b and separated from the first well region 125b and the annular well regions 120b and 120c via a field oxide 130. As previously described, shielding structures 10B_1 and 10B_2 are electrically coupled to the bulk ring 122 via a contact 205, an upper metal plate and metal lines, a contact 205, and a second doped region 134. Therefore, when the bulk ring 122 is grounded via the interconnect structure in the semiconductor structure, the shielding structures 10A_1-10A_4 and 10B_1-10B_4 are grounded. Therefore, when a metal line formed by a higher metal layer is configured (wound) above the first well regions 125a and 125b, the shielding structures 10B_1 and 10B_2 can prevent voltage on the metal line (e.g., the drain voltage to be supplied to the semiconductor structure 300) from coupling to the first well regions 125a and 125b. Therefore, the parasitic NPN bipolar transistor (e.g., formed by the second well region 110a, the first well region 125a, and the second well region 110b) Figure 4 The bipolar transistor 113 will not be turned on, so there will be no leakage current.

[0074] Figure 8 This is a top view showing a semiconductor structure 400 according to some embodiments of the present invention. In some embodiments, the semiconductor structure 400 is an N-type symmetric semiconductor structure. In some embodiments, the semiconductor structure 400 is a high-voltage semiconductor structure. The structure of the semiconductor structure 400 is similar to... Figure 5 The structure of semiconductor structure 300. (Compared to...) Figure 5 The difference in the semiconductor structure of 300 is that Figure 8 The semiconductor structure 400 includes shielding structures 30A and 30B. Shielding structure 30A is formed on a first side near the bulk ring 122, while shielding structure 30B is formed between a second side near the bulk ring 122. Shielding structures 30A and 30B can be connected via a contact 205 and an upper metal plate (e.g., Figure 1 The electrodes 215a and 215b are electrically coupled to the bulk ring 122. In some embodiments, the contacts 205 above the shielding structures 30A and 30B are located near the source region S, the drain region D, and the gate G. In this embodiment, the shielding structures 30A and 30B extend along the X direction, while the sub-gates 150a-150d extend along the Y direction.

[0075] Sub-gates 150a-150d and shielding structures 30A and 30B are disposed on the same layer and formed of the same polysilicon material. In some embodiments, sub-gates 150a-150d and shielding structures 30A and 30B may be formed of the same conductive material. In the X direction, the width (or dimension) of sub-gates 150a-150d is smaller than the width of shielding structures 30A and 30B. In the Y direction, the length (or dimension) of sub-gates 150a-150d is also greater than the length of shielding structures 30A and 30B. Figure 8 In the middle, the shielding structures 30A and 30B extend from the first doped region 132a to the first doped region 132e in the X direction.

[0076] Figure 9 This is to show the embodiments described according to the present invention. Figure 8A cross-sectional view of the semiconductor structure 400 along line E-EE. Second well regions 110a and 110b and a bulk ring 122 are formed in the semiconductor substrate 15. A shielding structure 30B is formed above the field oxide 130. As previously described, the shielding structure 30B is electrically coupled to the bulk ring 122 via contact 205, an upper metal plate and metal wire, contact 205, and a second doped region 134. Therefore, when the bulk ring 122 is grounded via the interconnect structure in the semiconductor structure, the shielding structures 30A and 30B are grounded. Therefore, when a metal wire formed by a higher metal layer is configured (wound) above the first well regions 125a and 125b, the shielding structure 30B prevents voltage on that metal wire (e.g., the drain voltage to be supplied to the semiconductor structure 400) from coupling to the first well regions 125a and 125b. Therefore, parasitic NPN bipolar transistors are not turned on, thus preventing leakage current.

[0077] Figure 10 This is a top view showing a semiconductor structure 500 according to some embodiments of the present invention. In some embodiments, the semiconductor structure 500 is an N-type semiconductor structure serving as electrostatic discharge (ESD) protection. The structure of the semiconductor structure 500 is similar to... Figure 8 The structure of the semiconductor structure 400. (Compared to...) Figure 8 The difference in the semiconductor structure of 500 is that... Figure 10 The configuration of the contacts 205 of the sub-gates 150a-150d in the semiconductor structure 500 is different. Figure 8 The configuration of contacts 205 of the sub-gates 150a-150d in the semiconductor structure 400. Figure 8 In this structure, each sub-gate 150a-150d is electrically coupled to the upper electrode (or metal line) via contacts 205 arranged in a row along the Y direction, so as to receive the gate voltage applied to the gate G of the semiconductor structure 400. Figure 10 In this process, each subgate 150a-150d is electrically coupled to the upper electrode (or metal line) via contacts 205 arranged in a row along the X direction.

[0078] Figure 11 This is to show the embodiments described according to the present invention. Figure 10The image shows a top view of the semiconductor structure 500 and electrode 510. Electrode 510 is a metal ring formed by metal lines formed on the lowest metal layer. Electrode 510 overlaps the bulk ring 122 and the first doped regions 132a, 132c, and 132e, and is electrically coupled to the bulk ring 122 and the first doped regions 132a, 132c, and 132e via contact 205. Thus, the bulk B of the semiconductor structure 500 and the source region S are electrically coupled together via electrode 510. Furthermore, electrode 510 includes sub-electrodes 512, 514, and 516 for electrical coupling to sub-gates 150a-150d via contact 205. Thus, the bulk B, source region S, and gate G of the semiconductor structure 500 are electrically coupled together via electrode 510.

[0079] Figure 12 This illustrates an electrostatic discharge (ESD) protection circuit 50 implemented by a semiconductor structure 500 according to some embodiments of the present invention. The ESD protection circuit 50 includes the semiconductor structure 500. See also... Figures 10-12 The drain region D of semiconductor structure 500 is electrically coupled to bonding pad 52 via metal lines 520 and 522 and other interconnect structures. The gate G and source region S of the transistor in semiconductor structure 500 are electrically coupled to ground terminal VSS via electrode 510 and other interconnect structures. As previously described, by using shielding structures 30A and 30B, electrostatic discharge energy or higher voltage signals from bonding pad 52 are prevented from coupling to the gate G of semiconductor structure 500, thus avoiding the conduction of parasitic NPN bipolar transistors and preventing leakage current.

[0080] Figure 13 This is a top view showing a semiconductor structure 600 according to some embodiments of the present invention. In some embodiments, the semiconductor structure 600 is an N-type symmetric semiconductor structure. In some embodiments, the semiconductor structure 600 is a high-voltage semiconductor structure. The configuration of the semiconductor structure 600 is similar to... Figure 5 The configuration of the semiconductor structure 300. With Figure 5 The difference in the semiconductor structure of 300 is that Figure 13 The semiconductor structure 600 also includes shielding structures 10C_1-10C_3, shielding structures 10D_1 and 10D_2, shielding structures 10E_1-10E_3, and shielding structures 10F_1 and 10F_2. Shielding structures 10C_1-10C_3 and shielding structures 10D_1 and 10D_2 are formed on a first side close to the bulk ring 122, while shielding structures 10E_1-10E_3 and shielding structures 10F_1 and 10F_2 are formed between a second side close to the bulk ring 122.

[0081] Shielding structures 10C_1-10C_3 and 10D_1-10D_2 can be electrically coupled to the first side of the block ring 122 via contact 205 and the upper metal plate (not shown). Shielding structures 10E_1-10E_3 and 10F_1-10F_2 can be electrically coupled to the second side of the block ring 122 via contact 205 and the upper electrode (not shown).

[0082] exist Figure 13 In this configuration, the first doped region 132a and the shielding structures 10C_1 and 10E_1 are arranged on the same straight line along the Y direction. The first doped region 132b and the shielding structures 10D_1 and 10F_1 are arranged on the same straight line along the Y direction. The first doped region 132c and the shielding structures 10C_2 and 10E_2 are arranged on the same straight line along the Y direction. The first doped region 132d and the shielding structures 10D_2 and 10F_2 are arranged on the same straight line along the Y direction. The first doped region 132e and the shielding structures 10C_3 and 10E_3 are arranged on the same straight line along the Y direction.

[0083] In the X direction, the width (or dimension) of the first doped regions 132a, 132c, and 132e is smaller than the width of shielding structures 10C_1-10C_3 and 10E_1-10E_3. Furthermore, in the X direction, the width (or dimension) of the first doped regions 132b and 132d is smaller than the width of shielding structures 10D_1 and 10D_2 and shielding structures 10F_1 and 10F_2.

[0084] Shielding structures 10C_1-10C_3, 10D_1-10D_2, 10E_1-10E_3, and 10F_1-10F_2 can be electrically coupled to the block ring 122 via contact 205 and the metal plate of the lowest metal layer. Compared to Figure 8 In the semiconductor structure 400, the space above the gaps between the continuous shielding structures 30A and 30B, shielding structures 10C_1-10C_3, shielding structures 10D_1-10D_2, shielding structures 10E_1-10E_3, and shielding structures 10F_1-10F_2 can be reserved for the metal lines of the lowest metal layer to be wound, thus increasing the flexibility of the layout. Furthermore, as previously described, by adjusting the configuration of the contact 205, the semiconductor structure 600 can be configured as an N-type semiconductor structure with electrostatic discharge protection.

[0085] In this embodiment of the invention, by setting a shielding structure formed by shielded polysilicon between the gate and bulk ring of the semiconductor structure, high voltage signals from the upper layer can be prevented from coupling to the P-type well region of the gate, thus avoiding the conduction of parasitic NPN bipolar transistors and preventing leakage current.

[0086] Although the present invention has been described above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A semiconductor substrate; At least one first well region is disposed in the semiconductor substrate and has a first conductivity type; At least one gate of a transistor is disposed above the at least one first well region and extends along a first direction; At least one second well region and at least one third well region are disposed on opposite sides of the at least one first well region and extend along the first direction, wherein the at least one second well region and the at least one third well region have a second conductivity type, and the second conductivity type is complementary to the first conductivity type; An oxide is disposed between the first well region and the second well region, and extends along the first direction and a second direction, wherein the first direction is perpendicular to the second direction; A first shielding structure is disposed at at least one end of the at least one gate in the first direction and does not overlap the at least one gate in a vertical projection direction; A metal wire is disposed above the first shielding structure, wherein the first shielding structure is disposed between the metal wire and the field oxide; as well as A body ring is disposed in the semiconductor substrate and surrounds the at least one gate, the at least one second well region, the at least one third well region and the first shielding structure.

2. The semiconductor structure as described in claim 1, characterized in that, Also includes: A first electrode is formed above the first shielding structure, wherein the first shielding structure is electrically coupled to the block ring and electrically connected to a ground terminal via the first electrode.

3. The semiconductor structure as described in claim 1, characterized in that, Also includes: A second shielding structure is disposed between the other end of the at least one gate and the block ring and partially overlaps with the at least one first well area in the vertical projection direction.

4. The semiconductor structure as described in claim 1, characterized in that, The block ring has the first conductivity type.

5. The semiconductor structure as described in claim 1, characterized in that, The at least one second well region and the at least one third well region are a source region and a drain region of the transistor, and the first shielding structure partially overlaps the at least one second well region and the at least one third well region.

6. The semiconductor structure as described in claim 1, characterized in that, Also includes: A first annular well region is formed in the semiconductor substrate, wherein at least a second well region is surrounded by the first annular well region; and A second annular well region is formed in the semiconductor substrate, wherein the third well region is surrounded by the second annular well region, and wherein the first annular well and the second annular well have the first conductivity type.

7. The semiconductor structure as described in claim 6, characterized in that, The first well zone is formed between the first annular well zone and the second annular well zone.

8. The semiconductor structure as described in claim 1, characterized in that, The at least one gate, the at least one first well region, the at least one second well region, and the at least one third well region are each a plurality and all extend along the first direction, and the gate, the second well region, and the third well region are alternately arranged in a second direction, wherein the first direction is perpendicular to the second direction.

9. The semiconductor structure as described in claim 8, characterized in that, The second well region and the third well region are a source region and a drain region of the transistor.

10. The semiconductor structure as claimed in claim 1, characterized in that, Also includes: A first interconnect structure is formed over the semiconductor substrate; A bonding pad is formed above the semiconductor substrate, wherein the bonding pad is electrically coupled to a drain region of the transistor via the first interconnect structure; as well as A second interconnect structure is formed over the semiconductor substrate; The at least one gate, a source region of the transistor, the bulk ring, and the first shielding structure are electrically connected to a ground terminal via the second interconnect structure.

11. The semiconductor structure as claimed in claim 1, characterized in that, Also includes: A third shielding structure is formed above the semiconductor substrate; The third shielding structure is disposed between the at least one second well region and / or the at least one third well region and the block ring, wherein the first shielding structure and the third shielding structure are disposed on the same side of the at least one gate.

12. The semiconductor structure as claimed in claim 11, characterized in that, The first shielding structure is electrically connected to the third shielding structure.

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