Array substrate and display panel

Abstract

The application discloses an array substrate and a display panel, the array substrate comprises a substrate, a pixel electrode, a planar layer, a passivation layer and a thin film transistor which are sequentially stacked on the substrate from top to bottom; the drain electrode of the thin film transistor is made of a light-reflecting material, and the drain electrode of the thin film transistor is also located in a pixel area of the array substrate and overlaps with the pixel electrode; the pixel electrode is connected with the drain electrode of the thin film transistor through at least two transfer vias, and the at least two transfer vias are respectively located at two opposite corners of the drain electrode. After the above design, when the pixel electrode is accidentally broken in a subsequent process of the array substrate, no matter whether the pixel electrode is broken horizontally or vertically, the broken pixel electrode can still be connected with the drain electrode through the transfer vias, so that the area can normally display by receiving the electric signal transmitted by the drain electrode.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to an array substrate and a display panel. Background Technology

[0002] With the development of digital technology, more and more display devices are entering people's lives, such as electronic paper (EP). Electronic paper displays can maintain their display for a long time even when the power is off, and have advantages such as being lightweight, thin, having low power consumption, and simple manufacturing processes, thus gaining increasing popularity. Electronic paper can be divided into color electronic paper and monochrome electronic paper. Its display principle is to use an electric field to drive color particles in microcapsules, causing the color particles to align in a specific direction to display the desired text and patterns.

[0003] Traditional electronic paper pixel structures consist of a TFT (thin-film transistor) layer, an insulating layer, and pixel electrodes stacked on a substrate. Due to the characteristics of the electronic paper unit structure, the pixel electrodes are easily scratched or broken during processes after the array substrate fabrication (including blue film attachment, cutting, and edge sealing), resulting in poor electronic paper display. If multiple pixel electrodes are scratched or broken, it can even cause visible display defects, thus affecting the product yield of electronic paper. Summary of the Invention

[0004] The purpose of this application is to provide an array substrate and a display panel that can maintain normal display even after the pixel electrodes are scratched or broken.

[0005] This application discloses an array substrate, which includes a substrate and a pixel electrode, a planarization layer, a passivation layer, and a thin-film transistor stacked sequentially on the substrate from top to bottom; the drain of the thin-film transistor is made of a reflective material, and the drain of the thin-film transistor is also located in the pixel region of the array substrate, overlapping with the pixel electrode; the pixel electrode is connected to the drain of the thin-film transistor through at least two vias, and the at least two vias are respectively located at two opposite corners of the drain.

[0006] Optionally, the array substrate is divided into multiple pixel regions and multiple switching regions, with each switching region corresponding to one of the pixel regions. The active layer of the thin-film transistor is disposed in the switching region, and the drain of the thin-film transistor is disposed in both the switching region and the pixel region. The pixel electrode is disposed in both the switching region and the pixel region. The pixel electrode is connected to the drain of the thin-film transistor through two vias, one of which is located in the pixel region and the other is located in the switching region.

[0007] Optionally, the area of ​​the via located in the pixel region is greater than or equal to the area of ​​the drain of the thin-film transistor in the pixel region.

[0008] Optionally, the thickness of the pixel electrode located in the pixel region is greater than the thickness of the pixel electrode located in the switching region.

[0009] Optionally, the array substrate further includes a common electrode located in the pixel region of the array substrate, disposed parallel to the gate of the thin-film transistor on the substrate, and the common electrode is located between the substrate and the drain of the thin-film transistor; wherein the orthogonal projection of the transition via located in the pixel region on the substrate covers the orthogonal projection of the common electrode on the substrate.

[0010] Optionally, the pixel electrode includes a first sub-electrode and a second sub-electrode that are not connected. The first sub-electrode and the second sub-electrode are arranged along the data line direction in the array substrate and are respectively connected to the drain through different adapter vias. The pixel electrode in the array substrate is divided into multiple electrode groups, and each electrode group includes two adjacent pixel electrodes. In the electrode group, the first sub-electrodes of two adjacent pixel electrodes are connected, and the second sub-electrodes of two adjacent pixel electrodes are connected.

[0011] Optionally, the pixel electrode is connected to the drain of the thin-film transistor through four adapter vias, with the four adapter vias located at the four corners of the drain.

[0012] Optionally, the pixel electrode includes four non-connected third sub-electrodes, which are arranged in a 2*2 configuration and connected to the drain electrode through four different adapter vias. The pixel electrodes in the array substrate are divided into multiple electrode groups, each of which includes three adjacent pixel electrodes. In the electrode group, adjacent third sub-electrodes of two adjacent pixel electrodes are connected to each other.

[0013] Optionally, all four vias are located in the pixel area of ​​the array substrate, and the four vias are of equal size and shape.

[0014] Optionally, the array substrate further includes a common electrode located in the pixel region of the array substrate, disposed parallel to the gate of the thin-film transistor on the substrate, and the common electrode is located between the substrate and the drain of the thin-film transistor; the orthographic projection of the common electrode on the substrate and the orthographic projection of the via on the substrate are disposed parallel to each other.

[0015] This application also discloses a display panel, which includes an array substrate as described above, and further includes a counter substrate and a particle layer; the array substrate and the counter substrate are disposed opposite to each other, and the particle layer is located between the array substrate and the counter substrate.

[0016] Compared to the current approach where pixel electrodes are connected to the drain via a single via, this application increases the number of vias at different locations on the pixel electrodes. At least two of these vias are located at opposite corners of the drain. When the array substrate is accidentally scratched or broken during subsequent processing, regardless of whether the scratch is horizontal or vertical, the broken pixel electrode remains connected to the drain via the via. This allows it to still receive electrical signals from the drain, maintaining a potential and enabling the corresponding particles to move normally, thus ensuring proper display in that area and preventing display failures. Even with multiple pixel electrode scratches or breaks, or even irregular scratches, a large area of ​​particles will not become uncontrollable, preventing visible display anomalies. Attached Figure Description

[0017] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings:

[0018] Figure 1 This is a schematic diagram of a display panel provided in this application;

[0019] Figure 2 This is a planar schematic diagram of an array substrate provided in the first embodiment of this application;

[0020] Figure 3 It is a kind of based Figure 2 Schematic diagram of the cross section at MM';

[0021] Figure 4 This is a planar schematic diagram of an array substrate implementation provided in the first embodiment of this application;

[0022] Figure 5 It is a kind of based Figure 4 Schematic diagram of the cross section at MM';

[0023] Figure 6 This is a cross-sectional schematic diagram of another type of array substrate;

[0024] Figure 7 This is a planar schematic diagram of an array substrate provided in one embodiment of the first embodiment of this application;

[0025] Figure 8 This is a planar schematic diagram of an array substrate provided in another embodiment of the first embodiment of this application;

[0026] Figure 9 This is a planar schematic diagram of an array substrate provided in the second embodiment of this application;

[0027] Figure 10 This is a planar schematic diagram of an array substrate provided in one embodiment of the second embodiment of this application.

[0028] 10. Display panel; 100. Opposing substrate; 200. Array substrate; 210. Substrate; 220. Thin film transistor; 221. Gate; 222. Active layer; 223. Source; 224. Drain; 225. Gate insulating layer; 230. Passivation layer; 240. Planarization layer; 250. Pixel electrode; 251. First sub-electrode; 252. Second sub-electrode; 253. Third sub-electrode; 260. Transition via; 270. Common electrode; 280. Electrode group; A. Pixel area; B. Switching area; 290. Transparent insulating layer; 300. Particle layer. Detailed Implementation

[0029] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0030] Furthermore, unless otherwise explicitly specified and limited, "connected" or "linked" should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral connection; it can refer to a mechanical connection or an electrical connection; it can refer to a direct connection or an indirect connection through an intermediate medium, or a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0031] The present application will be further described below with reference to the accompanying drawings and optional embodiments.

[0032] like Figure 1The diagram shows a schematic of a display panel. As the display panel 10 provided in this application, the display panel 10 includes an array substrate 200, a counter substrate 100, and a particle layer 300. The array substrate 200 and the counter substrate 100 are disposed opposite to each other, and the particle layer 300 is located between the array substrate 200 and the counter substrate 100. The display panel 300 can be a general liquid crystal panel, in which case the particle layer 300 is a liquid crystal layer; the display panel 300 can also be electronic paper, in which case the particle layer 300 is a charged particle layer, and the charged particles can be black and white electrophoretic particles or colored charged particles, without limitation.

[0033] For the array substrate 200, this application provides the following specific embodiments.

[0034] Example 1:

[0035] like Figure 2 and Figure 3 As shown, in the first embodiment provided in this application, the array substrate 200 includes a substrate 210 and a plurality of pixel electrodes 250, a passivation layer 230 and a plurality of thin film transistors 220 stacked on the substrate 210 from top to bottom.

[0036] The drain 224 of the thin-film transistor 220 is made of a reflective material to reflect external light; and the drain 224 of the thin-film transistor 220 is also located in the pixel area A of the array substrate 200, forming a planar structure that overlaps with the pixel electrode 250; each pixel electrode 250 is connected to the drain 224 of the corresponding thin-film transistor 220 through two transition vias 260, and the two transition vias 260 are respectively located at two diagonals of the drain 224 or the pixel electrode 250, which can also be understood as the two transition vias 260 being located on the diagonal of the drain 224 or the pixel electrode 250.

[0037] Compared to the current solution where the pixel electrode 250 is only connected to the drain electrode 224 through a single adapter via 260, and when the pixel electrode 250 is scratched or broken, the broken pixel electrode 250 cannot receive the electrical signal from the drain electrode 224 and therefore cannot have a potential, resulting in a failure to display normally.

[0038] This application increases the number of transition vias 260 at different positions on the pixel electrode 250, such that two transition vias 260 are located at two opposite corners of the drain 224. When the array substrate 200 is accidentally scratched or broken during subsequent processes, regardless of whether the pixel electrode 250 is scratched or broken laterally or vertically, the broken pixel electrode 250 can still be connected to the drain 224 through the transition vias 260, thus still receiving the electrical signal transmitted by the drain 224. This ensures that the broken pixel electrode 250 still has a potential, allowing the particles above it to move normally (deflection if they are liquid crystal molecules, and up-and-down movement if they are charged particles), enabling the area to display normally and avoiding display failures. Even if multiple pixel electrodes 250 are scratched or broken, or even if the scratches are irregular, it will not cause a large area of ​​particles to become uncontrollable, resulting in visible display abnormalities.

[0039] Furthermore, when the pixel electrode 250 is not scratched and broken during subsequent processes, the added via 260 can also increase the contact area between the pixel electrode 250 and the drain 224, thereby improving electrical conductivity and stability. In addition, since electrical signals can be transmitted to the pixel electrode 250 from two opposite corners, the signal attenuation problem that occurs when the signal is transmitted from one end of the pixel electrode 250 to the other end can be avoided.

[0040] Furthermore, this embodiment of the application adds a planarization layer 240 between the passivation layer 230 and the pixel electrode 250, and the thickness of the planarization layer 240 is greater than the thickness of the passivation layer 230. Specifically, the planarization layer 240 can be made of soluble polytetrafluoroethylene (PFA) material. The added planarization layer 240 not only improves the flatness of the pixel electrode 250, but also prevents the drain 224 or other traces in the pixel area A from breaking when the array substrate 200 is scratched, thus affecting the display effect.

[0041] Combination Figure 4 and Figure 5 As shown, the array substrate 200 can be divided into multiple pixel regions A and multiple switch regions B. Each switch region B corresponds to one pixel region A. Most of the structure of the thin-film transistor 220 (e.g., gate 221, active layer 222) is located within the switch regions B, with only the drain 224 located in pixel regions A. Simultaneously, the pixel electrode 250 is also disposed in both the switch regions B and pixel regions A. Of the two vias 260 connecting the pixel electrode 250 to the drain 224 of the thin-film transistor 220, one via 260 is located in pixel region A, and the other via 260 is located in switch region B.

[0042] Compared to placing both vias 260 in pixel area A, placing one of the vias 260 in switching area B reduces the dwell time of the electrical signal on the drain 224. When the thin-film transistor 220 is turned on, the electrical signal received by the drain 224 can be transmitted to the pixel electrode 250, thus avoiding display delay. Of course, depending on the actual situation, both vias 260 can also be placed in pixel area A.

[0043] Furthermore, such as Figure 6 As shown, the area of ​​the via 260 located in pixel region A is greater than or equal to the area of ​​the drain 224 of the thin-film transistor 220 in pixel region A. Since the via 260 needs to penetrate the planarization layer 240 and the passivation layer 230, in this embodiment, the planarization layer 240 and the passivation layer 230 in pixel region A are hollowed out, so that the subsequent pixel electrode 250 is directly deposited on the drain 224 in pixel region A, so that the pixel electrode 250 and the drain 224 are in full contact, and the drain 224 of the thin-film transistor 220 is directly connected to the pixel electrode 250. At this time, no matter what angle the pixel electrode 250 is scratched or broken, or even if the pixel electrode 250 is broken into multiple parts, the broken pixel electrode 250 can still contact the drain 224 and receive the electrical signal transmitted by the drain 224, so that the area corresponding to the pixel electrode 250 can be displayed normally. In addition, removing the planarization layer 240 and passivation layer 230 in pixel area A can reduce the loss that occurs when light passes through the planarization layer 240 and passivation layer 230, thereby improving light transmittance.

[0044] Furthermore, in pixel region A, a transparent insulating layer 290 can be added above the pixel electrode 250 to avoid the problem of uneven thickness of the particle layer 300; or, the thickness of the pixel electrode 250 can be adjusted so that the thickness of the pixel electrode 250 in pixel region A is greater than the thickness of the pixel electrode 250 in switching region B. This can also ensure the flatness of the array substrate 200 surface and the uniformity of the particle layer 300. Of course, it is also feasible not to add an insulating layer to the surface of the pixel electrode 250 or adjust the thickness of the pixel electrode 250, but the surface height difference of the array substrate 200 needs to be ≤2mm. This is because even if the surface of the array substrate 200 is uneven, the unevenness of the surface of the array substrate 200 will not necessarily affect the display. Moreover, there are mass production records of the surface height difference of the array substrate 200 being ≤2mm. It is only necessary to ensure that the surface height difference of the array substrate 200 does not exceed 2mm.

[0045] As one embodiment of this application, such as Figure 7As shown, each pixel electrode 250 is composed of a first sub-electrode 251 and a second sub-electrode 252 that are not connected. The first sub-electrode 251 and the second sub-electrode 252 are arranged along the data line direction in the array substrate 200 (vertically arranged), or the first sub-electrode 251 and the second sub-electrode 252 in each pixel electrode 250 are arranged along the scan line direction in the array substrate 200 (left-right arranged).

[0046] The first sub-electrode 251 and the second sub-electrode 252 are respectively connected to the drain 224 through different transition vias 260; wherein, the pixel electrodes 250 in the array substrate 200 are divided into multiple electrode groups 280, and each electrode group 280 consists of two adjacent pixel electrodes 250, which can be adjacent left and right or adjacent top and bottom.

[0047] In the electrode group 280, the first sub-electrodes 251 of two adjacent pixel electrodes 250 are connected, and the second sub-electrodes 252 of two adjacent pixel electrodes 250 are connected; or, the first sub-electrode 251 of the first pixel electrode 250 is connected to the second sub-electrode 252 of the second pixel electrode 250, and the second sub-electrode 252 of the first pixel electrode 250 is connected to the first sub-electrode 251 of the second pixel electrode 250.

[0048] In this embodiment, when a pixel electrode 250 is broken due to multiple scratches or irregular scratches and is not connected to the drain 224 in the pixel, the broken pixel electrode 250 can still be connected to the pixel electrode 250 in the adjacent pixel. During the display of the adjacent pixel, it can be displayed accordingly, avoiding the problem of dark spots.

[0049] As another implementation method in the embodiments of this application, such as Figure 8 As shown, only a portion of the pixel electrodes 250 are composed of unconnected first sub-electrodes 251 and second sub-electrodes 252. Specifically, the pixel electrodes 250 in the array substrate 200 are divided into multiple electrode groups 280. In each electrode group 280, there are three parallel pixel electrodes 250. Only the middle pixel electrode 250 is composed of unconnected first sub-electrodes 251 and second sub-electrodes 252. The pixel electrodes 250 on both sides are integral structures. In this case, the first sub-electrode 251 in the middle pixel electrode 250 is connected to the pixel electrode 250 on one side, and the second sub-electrode 252 in the middle pixel electrode 250 is connected to the pixel electrode 250 on the other side.

[0050] In this embodiment, the array substrate 200 further includes a common electrode 270, which is located in the pixel region A of the array substrate 200, and is disposed parallel to the gate 221 of the thin-film transistor 220 on the substrate 210. The common electrode 270 is located between the substrate 210 and the drain 224 of the thin-film transistor 220, and forms a storage capacitor with the pixel electrode 250. The orthogonal projection of the via 260 located in the pixel region A onto the substrate 210 covers the orthogonal projection of the common electrode 270 onto the substrate 210. When the passivation layer 230 and planarization layer 240 in the pixel region A are hollowed out, the spacing between the pixel electrode 250 and the common electrode 270 is very small, which helps to increase the amount of electricity stored in the capacitor, resulting in better subsequent pixel charging.

[0051] This application also discloses the fabrication process of the array substrate 200. Specifically, firstly, a common electrode 270, a scan line, and the gate 221 of the thin-film transistor 220 are simultaneously formed on the substrate 210. Then, a gate insulating layer 225 composed of silicon nitride compound is formed on the common electrode 270, the scan line, and the gate 221. Next, the active layer 222 and the channel of the thin-film transistor 220 are formed, wherein the active layer 222 can be a single layer structure or a two-layer structure. Next, the source 223 and the drain 224 of the thin-film transistor 220 are formed simultaneously. Then, a passivation layer 230 is formed, and a first layer of openings is made on the passivation layer 230. Subsequently, a planarization layer 240 is formed, and a second layer of openings is formed on the planarization layer 240. The first layer of openings and the second layer of openings are stacked one on the other to form a transition via 260. Finally, a pixel electrode 250 is formed, and the pixel electrode 250 is connected to the drain 224 through the transition via 260.

[0052] Compared to the approach of forming the passivation layer 230 and planarization layer 240 first and then etching the via 260 together, this embodiment forms an opening on the passivation layer 230 before fabricating the planarization layer 240, and etches the vias in the planarization layer 240 and the passivation layer 230 separately. This avoids the problems of uneven etching and incomplete etching that occur when different materials are etched. It also avoids the problem of severe undercutting of the via 260 due to its large depth, which can cause the pixel electrode 250 to break when the via 260 is etched in one step.

[0053] Furthermore, the via area in the planarization layer 240 is larger than the via area in the passivation layer 230. This way, after the pixel electrode 250 is formed, the pixel electrode 250 forms a step shape within the transition via 260, avoiding the risk of the pixel electrode 250 breaking due to the excessive depth of the transition via 260.

[0054] Example 2:

[0055] like Figure 9 As shown, the array substrate provided in the second embodiment of this application differs from that in the first embodiment in that each pixel electrode 250 is connected to the drain 224 of the thin film transistor 220 through four transition vias 260, and the four transition vias 260 are respectively located at the four corners of the drain 224.

[0056] In this embodiment, further increasing the number and location of the adapter vias 260 can further overcome more scratches and breaks, thereby further improving the product yield.

[0057] Furthermore, in this embodiment, all four vias 260 are located in pixel area A of the array substrate 200, so that the depths of the vias 260 are all the same; and the size and shape of the four vias 260 are also equal. This allows for simultaneous fabrication during the fabrication of the vias 260, making the fabrication process more efficient.

[0058] like Figure 10 As shown, in one embodiment of this application, the pixel electrode 250 includes four non-connected third sub-electrodes 253, which are arranged in a 2*2 configuration and connected to the drain 224 through four different transition vias 260. The pixel electrodes 250 in the array substrate 200 are divided into multiple electrode groups 280, each of which includes three adjacent pixel electrodes 250. In each electrode group 280, adjacent third sub-electrodes 253 of two adjacent pixel electrodes 250 are interconnected.

[0059] In this embodiment, when a pixel electrode 250 is broken due to multiple scratches or irregular scratches and is not connected to the drain 224 in the pixel, the broken pixel electrode 250 can still be connected to the pixel electrode 250 in the adjacent pixel. During the display of the adjacent pixel, it can be displayed accordingly, avoiding the problem of dark spots.

[0060] In other embodiments, based on dividing the pixel electrode 250 into at least two unconnected sub-electrodes, the insulating structure under each sub-electrode can be hollowed out so that each sub-electrode is in contact with the drain 224. In this case, it is not necessary to add an additional structure to connect adjacent sub-electrodes.

[0061] Alternatively, the insulating structure under some of the sub-electrodes can be hollowed out, so that these sub-electrodes are directly attached to the drain 224, while the other sub-electrodes are still connected to the drain 224 through the adapter via 260. Furthermore, these two types of sub-electrodes are connected. In this way, while reducing the area of ​​the hole on the surface of the array substrate 200, the situation of no power supply after the sub-electrodes are scratched or broken can be greatly avoided.

[0062] Of course, in other implementations, more adapter vias 260 can be added, and the adapter vias 260 can be placed in the four edges and the center area of ​​the drain 224 to further increase the connection points between the pixel electrode 250 and the drain 224, so as to overcome the situation where the pixel electrode 250 breaks into small pieces or irregular parts under bad conditions. The specific adjustments can be made according to the actual situation.

[0063] Of course, it is also possible to connect some of the pixel electrodes 250 in the array substrate 200 to the drain 224 through at least two transition vias 260. Specifically, only the pixel electrodes 250 that are prone to scratches can adopt the design in the above embodiment, or a portion of the pixel electrodes 250 on the array substrate 200 can adopt the design in the above embodiment, while the other pixel electrodes 250 are still connected to the drain 224 through only one via. The pixel electrodes 250 designed in the above embodiment are distributed at intervals. In this way, even if scratches occur, some individual pixel electrodes 250 that do not adopt the design in the above embodiment will not work properly. However, since these pixel electrodes 250 that do not work properly will be separated by the pixel electrodes 250 that work properly, they cannot form a continuous area, so they will not affect the display to the naked eye.

[0064] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. An array substrate, comprising a substrate and pixel electrodes, a planarization layer, a passivation layer, and thin-film transistors stacked sequentially from top to bottom on the substrate, characterized in that, The drain of the thin-film transistor is made of a reflective material, and the drain of the thin-film transistor is also located in the pixel area of ​​the array substrate, overlapping with the pixel electrode; The pixel electrode is connected to the drain of the thin-film transistor through at least two vias, and the at least two vias are located at two opposite corners of the drain. The array substrate is divided into multiple pixel regions and multiple switch regions. The switch regions are arranged in a one-to-one correspondence with the pixel regions. The active layer of the thin film transistor is disposed in the switch region. The drain of the thin film transistor is disposed in both the switch region and the pixel region. The pixel electrode is disposed in both the switch region and the pixel region. The pixel electrode is connected to the drain of the thin-film transistor through two vias, one of which is located in the pixel region and the other is located in the switching region. The pixel electrode includes a first sub-electrode and a second sub-electrode that are not connected. The first sub-electrode and the second sub-electrode are arranged along the data line direction in the array substrate and are respectively connected to the drain through different transition vias. The pixel electrodes in the array substrate are divided into multiple electrode groups, and each electrode group includes two adjacent pixel electrodes. In the electrode group, the first sub-electrode of two adjacent pixel electrodes is connected, and the second sub-electrode of two adjacent pixel electrodes is connected.

2. The array substrate as described in claim 1, characterized in that, The area of ​​the via located within the pixel region is greater than or equal to the area of ​​the drain of the thin-film transistor within the pixel region.

3. The array substrate as described in claim 2, characterized in that, The thickness of the pixel electrode located within the pixel region is greater than the thickness of the pixel electrode located within the switching region.

4. The array substrate as described in claim 2, characterized in that, The array substrate further includes a common electrode, which is located in the pixel region of the array substrate and is disposed on the substrate in parallel with the gate of the thin film transistor, and the common electrode is located between the substrate and the drain of the thin film transistor. The orthogonal projection of the adapter via located in the pixel area onto the substrate covers the orthogonal projection of the common electrode onto the substrate.

5. An array substrate, comprising a substrate and pixel electrodes, a planarization layer, a passivation layer, and thin-film transistors stacked sequentially from top to bottom on the substrate, characterized in that, The drain of the thin-film transistor is made of a reflective material, and the drain of the thin-film transistor is also located in the pixel area of ​​the array substrate, overlapping with the pixel electrode; The pixel electrode is connected to the drain of the thin-film transistor through at least two vias, and the at least two vias are located at two opposite corners of the drain. The pixel electrode is connected to the drain of the thin-film transistor through four connecting vias, and the four connecting vias are located at the four corners of the drain. The pixel electrode includes four non-connected third sub-electrodes, which are arranged in a 2*2 configuration and connected to the drain electrode through four different adapter vias. The pixel electrodes in the array substrate are divided into multiple electrode groups, and each electrode group includes three adjacent pixel electrodes; in the electrode group, the adjacent third sub-electrodes of two adjacent pixel electrodes are connected to each other.

6. The array substrate as described in claim 5, characterized in that, All four vias are located in the pixel area of ​​the array substrate, and all four vias are the same size and shape.

7. A display panel, characterized in that, The display panel includes an array substrate as described in any one of claims 1-6, and further includes a counter substrate and a particle layer; the array substrate is disposed opposite to the counter substrate, and the particle layer is located between the array substrate and the counter substrate.

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