Field effect transistor device

Abstract

The application discloses a field effect transistor device for solving the short channel effect of the prior art field effect transistor, which comprises an active layer, the active layer comprising a source region, a drain region and a channel region between the source region and the drain region; when the device is turned on, an effective channel is formed in the channel region, and an equivalent source region and an equivalent drain region are formed away from the effective channel in at least the thickness direction of the channel region, the field effect transistor device communicates the source region and the drain region through the effective channel and the equivalent source region and the equivalent drain region to contribute working current, and the length of the equivalent source region is greater than the length of the equivalent drain region.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a field-effect transistor device. Background Technology

[0002] With the development of integrated circuit technology, the gate length (corresponding to the channel length) of field-effect transistors (FETs) is constantly shrinking. Currently, VLSI chips based on submicron or even sub-10 nanometer gate length devices are already in mass production. For these small-sized devices, how to deal with their short-channel effect is a major challenge in device technology. The short-channel effect causes a comprehensive degradation of the threshold voltage and subthreshold characteristics of small-sized devices. Specifically, the device threshold voltage is no longer constant, but decreases with decreasing channel length and decreases with increasing drain voltage; the subthreshold swing of the device transfer characteristics also deteriorates simultaneously.

[0003] Currently, methods to improve the short-channel effect of field-effect transistors mainly include FinFETs, silicon-on-insulator (SOI), lightly doped drain (LDD) structures, and metal-source-drain Schottky barrier transistors (SB MOSFETs). ① FinFETs use a 3D fin-shaped channel region and a three-sided gate-around structure. The two side gates enhance the gate's control over the channel, effectively suppressing the short-channel effect. The fabrication process for this approach is much more complex than for planar devices. Currently, chips using technology nodes below 22nm mostly adopt the FinFET approach. ② SOI technology introduces a buried oxide layer between the silicon channel layer and the back substrate. Under conditions of a very thin and fully depleted channel layer, it can effectively suppress leakage current between the source and drain. The challenge of this approach lies in the very high cost of SOI silicon wafers. Currently, chips based on SOI at the 10nm technology node are already in mass production. ③ A lightly doped drain LDD is placed near the drain channel, while the source and drain regions far from the channel remain heavily doped. The drain PN junction formed by this lightly doped region reduces the impact of the drain voltage on the channel, making it the mainstream technology for submicron-level short-channel devices. In this scheme, both the on-state current and field-effect mobility of the device are reduced to some extent by the LDD. ④ The operating current of a Schottky barrier transistor is the tunneling current of the Schottky barrier between the metal source and the semiconductor channel. It is not sensitive to short-channel effects. This scheme is more difficult to fabricate, has limited choices of barrier materials, and it is difficult to simultaneously suppress the off-state current of the device.

[0004] On the other hand, the kink effect appearing on the output characteristic curve of short-channel devices has also attracted much attention. When the device operates in saturation, the high drain voltage depletes the drain terminal and forms a high electric field region. Carriers are prone to collisional ionization here and are amplified by coupling with the parasitic bipolar transistors of the MOS device. This causes the drain current to increase rapidly with the increase of the drain voltage, forming the so-called kink current. The output characteristic curve of the device is significantly warped, which seriously affects the normal output characteristics.

[0005] Common methods to mitigate the kink effect include increasing the device channel length and using lightly doped drain (LDD) structures. Increasing the channel length reduces the impact of carriers generated by drain collisional ionization on the source, weakening parasitic transistor effects and alleviating the kink effect. However, increasing the channel length will correspondingly reduce the device's output current. LDD structures can reduce the peak electric field intensity in the drain depletion region, weakening the carrier collisional ionization effect and thus suppressing the kink effect. However, LDD structures introduce additional parasitic resistance, reducing the device's field-effect mobility and on-state current.

[0006] The information disclosed in this background section is intended only to enhance the understanding of the overall background of this application and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0007] The purpose of this application is to provide a field-effect transistor device that solves the problem of short-channel effect in existing field-effect transistors.

[0008] To achieve the above objectives, this application provides a field-effect transistor device, including an active layer, wherein the active layer includes a source region, a drain region, and a channel region located between the source region and the drain region;

[0009] When the device is turned on, an effective channel is formed in the channel region, as well as an equivalent source region and an equivalent drain region that are at least away from the effective channel in the thickness direction of the channel region. The field-effect transistor device connects the source region and the drain region through the effective channel, the equivalent source region and the equivalent drain region to contribute the operating current.

[0010] Wherein, the length of the equivalent source region is greater than the length of the equivalent drain region.

[0011] In one embodiment, the equivalent source region includes a first conductive region located in the channel region and connected to the source region, and the equivalent drain region includes a second conductive region located in the channel region and connected to the drain region, with a gap between the first conductive region and the second conductive region.

[0012] In one embodiment, a first gate is disposed on one side surface of the active layer, and the vertical projections of the first gate and the first conductive region and the second conductive region on the channel region overlap; wherein, the first gate can control the channel region and form a channel therein, and the portion of the channel that does not overlap with the vertical projections of the first conductive region and the second conductive region on the channel region constitutes the effective channel.

[0013] In one embodiment, when the device is turned on, the conductivity of the first conductive region and the second conductive region is greater than the conductivity of the remaining portion of the channel excluding the effective channel, so that the first conductive region can inject charge carriers into the effective channel and the effective channel can inject charge carriers into the second conductive region.

[0014] In one embodiment, the conductivity of the first conductive region and the second conductive region is at least three times greater than the conductivity of the remaining portion of the channel excluding the effective channel.

[0015] In one embodiment, when the device is turned on, the conductance per unit length of the effective channel in the channel is less than the conductance per unit length of the remaining portion of the channel excluding the effective channel.

[0016] In one embodiment, when the field-effect transistor device is an N-type device, the work function of the portion of the first gate corresponding to the effective channel is greater than the work function of the remaining portion of the first gate.

[0017] When the field-effect transistor device is a P-type device, the work function of the portion of the first gate corresponding to the effective channel is less than the work function of the remaining portion of the first gate.

[0018] In one embodiment, the field-effect transistor device includes a gate insulating layer disposed between the first gate and the channel region, wherein the thickness of the portion of the gate insulating layer corresponding to the effective channel is greater than the thickness of the remaining portion of the gate insulating layer.

[0019] In one embodiment, the field-effect transistor device includes a gate insulating layer disposed between the first gate and the channel region, wherein the dielectric constant of the portion of the gate insulating layer corresponding to the effective channel is greater than the dielectric constant of the remaining portion of the gate insulating layer.

[0020] In one embodiment, when the field-effect transistor device is an N-type device, the following condition is met:

[0021] Preferably, Preferably,

[0022] When the field-effect transistor device is a P-type device, the following conditions are met:

[0023] Preferably, Preferably,

[0024] in, This is the threshold voltage of the portion of the first gate corresponding to the effective channel. It is the threshold voltage of the portion of the first gate corresponding to the equivalent drain region.

[0025] In one embodiment, a second gate is further provided on the surface of the active layer adjacent to the first conductive region and the second conductive region, the second gate being capable of controlling the formation of the first conductive region and the second conductive region in the channel region.

[0026] In one embodiment, the first conductive region and the second conductive region are formed by carriers introduced by doping on the surface of the channel region on the side away from the effective channel.

[0027] In one embodiment, an insulating layer is further disposed on the surface of the active layer away from the effective channel, wherein the first conductive region and the second conductive region are composed of charge carriers generated by the injected charge in the insulating layer through electrostatic induction in the channel region near the insulating layer.

[0028] In one embodiment, a semiconductor material layer is further disposed on the surface of the active layer away from the effective channel. The active layer and the semiconductor material layer form a heterostructure. The first conductive region and the second conductive region are composed of two-dimensional electron gas channels or two-dimensional hole gas channels distributed in the heterostructure.

[0029] In one embodiment, the first conductive region and the second conductive region are formed by surface treatment of the surface of the channel region away from the effective channel to form a two-dimensional electron gas channel or a two-dimensional hole gas channel.

[0030] In one embodiment, the length ratio of the equivalent source region to the equivalent drain region ranges from 1.1:1 to 2.5:1; preferably 1.2:1 to 2.3:1; preferably 1.1:1 to 2.2:1; preferably 1.4:1 to 2.2:1; preferably 1.8:1 to 2.2:1.

[0031] In one embodiment, the sum of the lengths of the equivalent source region and the equivalent drain region is no greater than three times the effective channel length.

[0032] In one embodiment, the source region and drain region are doped semiconductor or Schottky metal source / drain regions.

[0033] In one embodiment, the gate of the field-effect transistor device is a metal-insulator-semiconductor MOS structure gate or a Schottky junction gate.

[0034] In one embodiment, the active layer comprises at least two semiconductor materials that vary along its thickness direction or planar extension direction.

[0035] In one embodiment, the field-effect transistor device is a planar structure device or a vertical structure device.

[0036] Compared with the prior art, in the embodiments of this application, by configuring the device to form an effective channel in the channel region and an equivalent source region and an equivalent drain region that are far away from the effective channel in the thickness direction of the channel region when it is turned on, the source region and the drain region are connected to contribute the operating current. In this way, the equivalent drain region (source) connected to the drain (source) region is structurally far away from the effective channel, which can reduce the influence of the drain voltage on the effective channel. It also reduces the peak electric field in the drain depletion region when the device is saturated, thereby suppressing the short-channel effect of the device and improving the output characteristics of the device. At the same time, by setting the length of the equivalent source region to be greater than that of the equivalent drain region, the output characteristics of the device can be significantly improved without significant loss in the short-channel effect suppression capability.

[0037] On another front, depending on the device type, the work function of the portion of the first gate corresponding to the equivalent source and equivalent drain regions is set to be different from the work function of the portion corresponding to the effective channel. This ensures good suppression of short-channel effects while also allowing the device to have a smaller saturation voltage V. dsat and a large saturation current I dsat Kink voltage and output impedance R o . Attached Figure Description

[0038] Figure 1 This is a schematic diagram showing the formation of an equivalent source region, an equivalent drain region, and an effective channel in a field-effect transistor device in the on state according to an embodiment of this application.

[0039] Figure 2 This is a schematic diagram of the structure of a field-effect transistor device in the on state according to an embodiment of this application;

[0040] Figure 3 This is a schematic diagram showing the state of a field-effect transistor device forming a conductive region according to an embodiment of this application;

[0041] Figures 4 to 7 This is a schematic diagram of the structure of the field-effect transistor device according to various embodiments of this application.

[0042] Figures 8 to 15 This is a schematic diagram illustrating the principle of fabricating the conductive region in various embodiments of this application;

[0043] Figures 16 to 18 This is a schematic diagram of the structure of an SOI device using the solution of this application;

[0044] Figure 19 It is a schematic diagram of the structure where there is a gap between the effective channel and the conductive region of the field-effect transistor device in an embodiment of the present application in the vertical projection on the channel region;

[0045] Figures 20 to 21 It is a comparison diagram of the transfer characteristics of the SOI device of the present application and the comparative SOI device in Simulation Example 1;

[0046] Figures 22 to 23 It is a comparison diagram of the output characteristics of the SOI device of the present application and the comparative SOI device in Simulation Example 1;

[0047] Figures 24 to 39 It is a comparison diagram of the transfer characteristics and the output characteristics of the SOI device of the present application and the comparative SOI device in Simulation Example 2. Specific Embodiments

[0048] The present application will be described in detail below in conjunction with the various embodiments shown in the drawings. However, these embodiments do not limit the present application, and structural, method, or functional transformations made by those of ordinary skill in the art based on these embodiments are all included within the protection scope of the present application.

[0049] Refer Figure 1 , and introduce a specific embodiment of the field-effect transistor device of the present application. In this embodiment, the field-effect transistor device 100 includes an active layer 10, and the active layer 10 includes a source region 101, a drain region 102, and a channel region 103.

[0050] The source region 101 and the drain region 102 are respectively located on both sides of the active layer 10, and the channel region 103 is located between the source region 101 and the drain region 102. In cooperation with Figure 1 the schematic diagram of the device when it is turned on as shown, an effective channel 1041 is formed in the channel region 103 of the field-effect transistor, and an equivalent source region 1051 and an equivalent drain region 1052 that are far from the effective channel 1041 in the thickness direction of the channel region 103. The field-effect transistor device 100 connects the source region 101 and the drain region 102 through the effective channel 1041, the equivalent source region 1051, and the equivalent drain region 1052 to contribute a working current.

[0051] In some embodiments of the present application, the "far from" between the effective channel 1041 and the equivalent source region 1051 and the equivalent drain region 1052 may include being far from each other in the length direction of the channel region in addition to the thickness direction of the channel region. In these embodiments, regardless of whether it is far from each other in the thickness or length direction of the channel region, it is limited to not affecting the connection of the effective channel 1041, the equivalent source region 1051, and the equivalent drain region 1052 to the source region 101 and the drain region 102 when the device is turned on.

[0052] In a typical field-effect transistor device 100, the source region 101 in the active layer 10 provides charge carriers when the device is turned on, while the drain region 102 collects the charge carriers provided by the source region 101. Correspondingly, in this application, the equivalent source region 1051 refers to a structure in which a portion of the charge carriers provided by the source region 101 are directly injected into the effective channel 1041, while the equivalent drain region 1052 refers to a structure in which a portion of the charge carriers are directly received from the effective channel 1041 and injected into the drain region 102.

[0053] Reference Figure 2 In this application, "effective channel 1041" refers to the portion of the channel through which the charge carriers of the operating current pass when the device is turned on. Taking this embodiment as an example, a first gate 20 can be disposed on one side surface of the active layer 10, and there is no gap between the vertical projection of the first gate 20 on the active layer 10 and the source region 101 and drain region 102. Therefore, when a gate bias voltage is applied to the first gate 20 to turn on the device, a channel 104 can be controlled to form below the first gate 20, and this channel 104 is structurally connected to the source region 101 and drain region 102. However, from a functional perspective, only the portion of this channel that does not overlap with the vertical projections of the equivalent source region 1051 and equivalent drain region 1052 on the channel region 103 is used to carry the entire operating current; therefore, only this portion of the channel is referred to as "effective channel 1041" here.

[0054] In this embodiment, the carrier path when the device is turned on includes two main parts: one part is from the source region 101 sequentially entering the equivalent source region 1051, the effective channel 1041, the equivalent drain region 1052, and the drain region 102; the other part is from the source region 101 directly entering the drain region 102 through the channel 104. From the perspective of the carrier path, the remaining portion of the channel 104, excluding the effective channel 1041, is only used to transmit a portion of the operating current.

[0055] It can be seen that the effective channel 1041 in this application is not limited to having a different device structure or parameter settings than the rest of the channel 104. In fact, in some embodiments, the channel 104 described above can be formed on the entire channel region, and only the setting of the equivalent source region 1051 and the equivalent drain region 1052 is needed to ensure that when the device is turned on, the carriers provided by the source region 101 are not directly injected into the drain region 102 through the channel 104. Furthermore, the channel control shown in some embodiments below, such as changing the work function of the first gate corresponding to the effective channel or the thickness of the gate insulating layer, should not be regarded as a necessary prerequisite for forming an effective channel.

[0056] The arrangement of the equivalent source region 1051 and the equivalent drain region 1052 effectively shortens the length of the portion of the channel 104 that can conduct all the operating current, thus creating a gap between the effective channel 1041 and the source region 101 and the drain region 102. Furthermore, the equivalent drain region 1052, which is connected to the drain region 102, is structurally located away from the effective channel 1041, reducing the influence of the drain potential on the effective channel 1041. Similarly, the equivalent source region 1051, which is connected to the source region 101, is structurally located away from the effective channel 1041, and its potential is consistent with that of the source region (typically zero potential), further reducing the influence of the drain potential on the effective channel 1041, thereby improving the short-channel effect of the device.

[0057] In this embodiment, the length of the equivalent source region 1051 is greater than the length of the equivalent drain region 1052. Furthermore, in one embodiment, the length ratio of the equivalent source region to the equivalent drain region ranges from 1.1:1 to 2.5:1; preferably 1.2:1 to 2.3:1; preferably 1.1:1 to 2.2:1; preferably 1.4:1 to 2.2:1; preferably 1.8:1 to 2.2:1. Additionally, the sum of the lengths of the equivalent source region and the equivalent drain region can be no greater than three times the effective channel length.

[0058] Within the length ratio range of the equivalent source region and equivalent drain region shown above, the kink voltage and output impedance of the device can be improved while controlling the saturation drain voltage and saturation drain current with almost no loss; that is, the output characteristics of the device can be improved without having much impact on the suppression of short-channel effects.

[0059] Reference Figure 3 In the specific preparation of the equivalent source region 1051 and the equivalent drain region 1052, a first conductive region A1 connected to the source region 101 can be formed in the channel region 103, and a second conductive region A2 connected to the drain region 102 can be formed in the channel region 103, with a gap between the first conductive region A1 and the second conductive region A2.

[0060] When the device is turned on, the conductance of the first conductive region A1 and the second conductive region A2 is set to be greater than the conductance of the remaining portion 1042 of the channel 104 excluding the effective channel 1041, so that the first conductive region A1 can inject carriers into the effective channel 1041 and the effective channel 1041 can inject carriers into the second conductive region A2. Specifically, the carriers in the source region 101 are attracted by the equivalent source region 1051 with a larger conductance, and are not directly injected into the remaining portion 1042 of the channel 104 directly connected to the source region 101; similarly, the carriers transported in the effective channel 1041 are also attracted by the equivalent drain region 1052, and are not all transported through the remaining portion 1042 of the channel 104.

[0061] To achieve the carrier injection setting among the equivalent source region 1051, the equivalent drain region 1052, and the effective channel 1041 herein, the conductances of the first conductive region A1 and the second conductive region A2 can be set to be at least three times greater than the conductance of the remaining part 1042 of the channel 104 except for the effective channel 1041. And, since carriers flow in the thickness direction of the channel region 103 during the above-mentioned "injection" process, in this embodiment, the intervals of the first conductive region A1, the second conductive region A2, and the effective channel 1041 in the thickness direction of the channel region 103 can be set to 5 nm to 10 μm, or more preferably 10 nm to 1 μm, or more preferably 10 nm to 100 nm according to the specific design of different devices to ensure the normal injection of carriers and the performance of the device.

[0062] It should be noted that the "carriers" mentioned in this application refer to the charge particles that can move freely in the corresponding polar channel / conductive region. Generally, we call the electrons in the N-type channel or the holes in the P-type channel the "carriers" here. Correspondingly, the holes in the N-type channel or the electrons in the P-type channel are not called the "carriers" here. Therefore, in this application, the polarities of the effective channel 1041, the first conductive region A1, and the second conductive region A2 are set to be the same so that the carrier interaction between the effective channel and the first conductive region A1 and the second conductive region A2 can ultimately substantially contribute to the working current of the device.

[0063] The shapes and positions of the first conductive region A1 and the second conductive region A2 can be set according to the application requirements of the device, and are not limited to Figure 3 the form shown. For example, Figure 4 the first conductive region A1 and the second conductive region A2 in the field effect transistor device 200 shown in Figure 3 can have a larger overall thickness and an irregular region shape relative to Figure 5 . Also, for example,

[0064] In the above embodiment, a structure in which a part of the channel formed by gate control constitutes the effective channel has been shown. In such a structure, to further improve the ability of the device to suppress the short-channel effect, the unit length conductance of the effective channel in the channel can be set to be less than the unit length conductance of the remaining part of the channel except for the effective channel. Some corresponding embodiments are introduced below.

[0065] Refer to Figure 6 to introduce another embodiment of the field effect transistor device 400 of this application.

[0066] The field effect transistor device 400 includes an active layer 10, which includes a source region 101, a drain region 102, and a channel region 103. The source region 101 and the drain region 102 are respectively located on both sides of the active layer 10, and the channel region 103 is located between the source region 101 and the drain region 102.

[0067] An insulating layer 30 and a first gate 20 are sequentially provided above the channel region. Moreover, the thickness of the gate insulating layer 302 corresponding to the effective channel 1041 is greater than the thickness of the gate insulating layer 301 of the remaining part. That is, the gate insulating layer 301 corresponding to the equivalent source region 1051 and the equivalent drain region 1052 is relatively thinned, so that the modulation ability of the gate corresponding to the remaining part of the channel 1042 other than the effective channel 1041 to the corresponding part of the channel 1042 can be enhanced, thereby increasing the conductance of the corresponding part of the channel 1042.

[0068] Correspondingly, in this embodiment, the dielectric constant of the gate insulating layer 302 corresponding to the effective channel 1041 can also be set to be greater than that of the gate insulating layer 301 of the remaining part, so as to further increase the conductance of the remaining part of the channel 1042 other than the effective channel 1041.

[0069] Refer Figure 7 to introduce another embodiment of the field effect transistor device 500 of the present application.

[0070] The field effect transistor device 500 includes an active layer 10, which includes a source region 101, a drain region 102, and a channel region 103. The source region 101 and the drain region 102 are respectively located on both sides of the active layer 10, and the channel region 103 is located between the source region 101 and the drain region 102.

[0071] A first gate 20 is provided above the channel region 103. Moreover, the part 201 corresponding to the effective channel 1041 and the remaining part 202 in the first gate 20 are made of different materials, so that the part 201 corresponding to the effective channel 201 and the remaining part 202 in the first gate 20 have different modulation abilities for the corresponding formed channel, and the conductance of the effective channel 1041 is greater than the conductance of the remaining part 1042 of the channel 104 except the effective channel 1041.

[0072] In this embodiment, if the field effect transistor device 500 is an N-type device, the work function of the part 201 corresponding to the effective channel 1041 in the first gate 20 is set to be greater than the work function of the remaining part 202 of the first gate 20; correspondingly, if the field effect transistor device 500 is a P-type device, the work function of the part 201 corresponding to the effective channel 1041 in the first gate 20 is set to be less than the work function of the remaining part 202 of the first gate 20.

[0073] Specifically, if it is an N-type device, the portion 201 of the first gate 20 corresponding to the effective channel 1041 can be a metal with a large work function, such as gold or platinum, or P-type doped (P+) polysilicon, or ITO, RuO2, WN, MoN, etc. with a large work function obtained by adjusting the compound composition as the gate material; the remaining portion 202 can be a metal with a small work function, such as aluminum, hafnium, titanium, or N-type doped (n+) polysilicon, or Ru-Hf, WN, HfN, TiN, TaN, TaSiN, etc. with a small work function obtained by adjusting the compound composition as the gate material. If it is a P-type device, the portion 201 of the first gate 20 corresponding to the effective channel 1041 can be a metal with a smaller work function, such as aluminum, hafnium, titanium, or N-type doped (n+) polysilicon, or Ru-Hf, WN, HfN, TiN, TaN, TaSiN, etc., with a smaller work function obtained by adjusting the compound composition, as the gate material; the remaining portion 202 can be a metal with a larger work function, such as gold, platinum, or P-type doped (P+) polysilicon, or ITO, RuO2, WN, MoN, etc., with a larger work function obtained by adjusting the compound composition, as the gate material.

[0074] Exemplary, in the above embodiments, by adjusting the work function, thickness, and dielectric constant of the gate insulating layer, the following can be satisfied when the field-effect transistor device is an N-type device:

[0075] Preferably, Preferably,

[0076] Furthermore, when the field-effect transistor device is a P-type device, the following conditions must be met:

[0077] Preferably, Preferably,

[0078] in, This is the threshold voltage of the portion of the first gate corresponding to the effective channel. It is the threshold voltage of the portion of the first gate corresponding to the equivalent drain region.

[0079] The following describes the formation methods of the first conductive region and the second conductive region in this application using some specific embodiments:

[0080] Example 1

[0081] The first conductive region A1 and the second conductive region A2 are formed by carriers introduced by surface doping of the channel region 103A on the side away from the effective channel 1041A.

[0082] Correspondingly, refer to Figure 8, if it is an N-type silicon-based device 100A, the doping concentration of the interface can be changed by doping donor atoms, such as phosphorus, arsenic, etc. on the surface of the channel region 103A far from the effective channel 1041A; refer to Figure 9 , if it is a P-type silicon-based device 100A, the doping concentration of the interface can be changed by doping acceptor atoms, such as boron, on the surface of the channel region 103A far from the effective channel 1041A.

[0083] Example 2

[0084] Cooperate with reference Figure 10 and Figure 11 , the field effect transistor device 100B further includes an insulating layer 40B provided on the surface of the active layer 10B on the side far from the effective channel 1041B, and the first conductive region A1 and the second conductive region A2 are formed on one surface of the channel region by electrostatic induction of the injected charges in the insulating layer 40B.

[0085] Correspondingly, refer to Figure 10 , if it is an N-type device, it can be achieved by locally injecting positive charges, such as H+, holes, into the insulating layer 40B; refer to Figure 11 , if it is a P-type device, it can be achieved by locally injecting negative charges, such as F-, Cl-, electrons, etc. into the insulating layer 40B. In this way, a high density of fixed charges is formed in the insulating layer 40B, and carriers of the first conductive region A1 and the second conductive region A2 are generated in the channel region 103B adjacent to the insulating layer 40B by electrostatic induction. It should be noted that the "local" here refers to the partial region in the insulating layer 40B corresponding to the parts in the channel region where the first conductive region A1 and the second conductive region A2 need to be formed.

[0086] In the specific charge injection process, the charges can be injected into a position in the insulating layer 40B closer to the channel region 103B, so that the first conductive region A1 and the second conductive region A2 formed in the channel region 103B can store more carriers. Of course, in some other alternative embodiments, a "double insulating layer" structure can also be adopted, which specifically includes a charge trapping layer provided on the surface of the channel region 103B and a conventional insulating layer covering the charge trapping layer. The charge trapping layer can be made of a material that is more likely to store charges, or metal or semiconductor nanoparticles are introduced therein to store charges more stably, so as to ensure the stable control of the carriers in the conductive region.

[0087] Example 3

[0088] Refer to Figure 12, the field effect transistor device 100C includes a semiconductor material layer 40C disposed on the active layer 10C. The semiconductor material layer 40C and the active layer 10C form a heterostructure, and the first conductive region A1 and the second conductive region A2 are formed by a two-dimensional electron gas channel or a two-dimensional hole gas channel distributed in the heterostructure.

[0089] Specifically, the semiconductor material layer 40C and the active layer 10C have different bandgap widths. The semiconductor material layer 40C can be divided into two parts respectively connected to the source region 101C and the drain region 102C, so that the formed two-dimensional electron gas channel does not conduct the source and drain regions.

[0090] Of course, in some alternative embodiments, for example, the channel region 103C can be surface-treated to form a two-dimensional electron gas channel or a two-dimensional hole gas channel. These alternative embodiments of forming a two-dimensional electron gas channel or a two-dimensional hole gas channel known to those skilled in the art should all fall within the protection scope of this application. And, the semiconductor material layer 40C mentioned here can be a barrier layer, and the barrier layer can be doped or intrinsic.

[0091] Embodiment 4

[0092] Refer Figure 13 , the field effect transistor device 100D is fabricated as a device including at least two gates. Specifically, the field effect transistor device 100D includes a first gate insulating layer 30D and a first gate 20D sequentially disposed on one surface of the active layer 10D, and a second gate insulating layer 40D and a second gate 50D sequentially disposed on one surface of the active layer 10D adjacent to the first conductive region A1 and the second conductive region A2.

[0093] The second gate 50D is correspondingly divided into two parts. One part of the vertical projection of the second gate 50D on the active layer 10D is connected to the source region 101D, and the other part of the vertical projection of the second gate 50D on the active layer 10D is connected to the drain region 102D. Thus, when appropriate bias voltages are applied to these two parts of the second gate 50D, the first conductive region A1 connecting the source region 101D and the second conductive region A2 connecting the drain region 102D can be respectively formed at corresponding positions in the channel region 103D.

[0094] In this embodiment, the absolute value of the bias voltage applied to the second gate 50D should be greater than the absolute value of the turn-on voltage applied to the device. Correspondingly, if it is an N-type device, a positive bias voltage greater than the first gate 20D is applied to the second gate 50D; if it is a P-type device, a negative bias voltage with an absolute value greater than the first gate 20D is applied to the second gate 50D.

[0095] Embodiment 5

[0096] Refer Figure 14, the field effect transistor device 100E is fabricated to include at least two gates similar to Example 4. However, the difference is that in this embodiment, in order to make the conductance of the first conductive region A1 and the second conductive region A2 greater than that of the portion 1042E of the channel 104E other than the effective channel 1041E, the first gate 20E and the second gate 50E with different work function gate materials can be adopted. That is: the work function difference between the first gate 20E and the active layer 10E, and the work function difference between the second gate 50E and the active layer 10E are not equal to achieve this.

[0097] Correspondingly, if it is an N-type device, the first gate 20E can adopt a metal with a larger work function such as gold, platinum, or P-type doped (P+) polysilicon, or ITO, RuO2, WN, MoN, etc. with a larger work function obtained by adjusting the compound composition as the gate material; the second gate 50E can adopt a metal with a smaller work function such as aluminum, hafnium, titanium, or N-type doped (n+) polysilicon, or Ru-Hf, WN, HfN, TiN, TaN, TaSiN, etc. with a smaller work function obtained by adjusting the compound composition as the gate material. If it is a P-type device, the first gate 20E can adopt a metal with a smaller work function such as aluminum, hafnium, titanium, or N-type doped (n+) polysilicon, or Ru-Hf, WN, HfN, TiN, TaN, TaSiN, etc. with a smaller work function obtained by adjusting the compound composition as the gate material; the second gate 50E can adopt a metal with a larger work function such as gold, platinum, or P-type doped (P+) polysilicon, or ITO, RuO2, WN, MoN, etc. with a larger work function obtained by adjusting the compound composition as the gate material.

[0098] In the N-type device, the work function difference between the first gate 20E and the active layer 10E can also be set to be greater than zero (Φms > 0V), so that the channel 104E is an enhancement-mode channel; at the same time, the work function difference between the second gate 50E and the active layer 10E is set to be less than zero (Φms < 0V), so that a certain number of carriers can be formed under the bias voltage applied to the first conductive region A1 and the second conductive region A2 when the device is in the off state. In the P-type device, the work function difference between the first gate 20E and the active layer can be set to be less than zero (Φms < 0V), so that the channel 104E is an enhancement-mode channel; at the same time, the work function difference between the second gate 50E and the active layer 10E is set to be greater than zero (Φms > 0V), so that a certain number of carriers can be formed under the bias voltage applied to the first conductive region A1 and the second conductive region A2 when the device is in the off state.

[0099] Example 6

[0100] See Figure 15, the field effect transistor device 100F is fabricated to include at least two gates 20F and 50F similar to those in Embodiment 4. However, the difference is that in this embodiment, in order to make the conductance of the first conductive region A1 and the second conductive region A2 greater than the conductance of the part 1042F in the channel 104F other than the effective channel 1041F, the capacitance per unit area of the second gate insulating layer 40F can be set to be greater than the capacitance per unit area of the first gate insulating layer 30F.

[0101] Specifically, this can be achieved by adjusting the dielectric constants of the first gate insulating layer 30F and the second gate insulating layer 40F, or the thicknesses of the first gate insulating layer 30F and the second gate insulating layer 40F.

[0102] For example, when the thicknesses of the first gate insulating layer 30F and the second gate insulating layer 40F are equal, only the dielectric constant factor of the gate insulating layer needs to be considered, and the dielectric constant of the second gate insulating layer 40F can be set to be higher than that of the first gate insulating layer 30F. Demonstratively, the first gate insulating layer 30F can be made of silicon dioxide, and the second gate insulating layer 40F can be made of a high dielectric constant medium such as hafnium dioxide, aluminum oxide, etc.

[0103] For another example, when the materials of the first gate insulating layer 30F and the second gate insulating layer 40F are the same, only the thickness factor of the gate insulating layer needs to be considered, and the thickness of the second gate insulating layer 40F can be set to be less than the thickness of the first gate insulating layer 30F.

[0104] In specific device applications, the second gate in the above Embodiments 4 to 6 can also be directly floating or grounded to avoid excessive device connection terminals increasing the complexity of device applications.

[0105] Moreover, the methods of forming the conductive regions in the above embodiments can also be applied in combination with each other to achieve better implementation effects.

[0106] The field effect transistor devices introduced in the above embodiments / mode of implementation can be planar structure devices or vertical structure devices. Hereinafter, taking a SOI device (TFT device) as an example, the specific settings of the solution of the present application when applied to a SOI device will be demonstratively described.

[0107] Embodiment 7

[0108] Refer Figure 16 , it is a planar top-gate structure TFT device 100G, and includes a light-transmissive insulating substrate 40G, and an active layer 10G, a gate dielectric layer 30G, and a gate 20G sequentially disposed on the substrate 40G. Source regions 101G and drain regions 102G are respectively doped on both sides of the active layer 10G, and source electrodes and drain electrodes are respectively externally connected; a channel region 103G is located between the source region 101G and the drain region 102G.

[0109] On the substrate 40G, positive charge regions 60G are formed on both sides of the source region 101G and the drain region 102G by means of ion implantation or the like. There is an overlapping portion between the vertical projection of the positive charge region 60G and the gate 20G in the channel region 103G. Correspondingly, the positive charge region in this overlapping portion can form a two-dimensional electron gas 70G that is respectively connected to the source region 101G and the drain region 102G in the channel region 103G. Here, the two-dimensional electron gas 70G constitutes the first conductive region and the second conductive region.

[0110] When the device is turned on, a channel is formed under the gate 20G, and the portion of the channel whose vertical projection is between the first conductive region and the second conductive region constitutes the actual effective channel.

[0111] Example 8

[0112] Refer Figure 17 to a planar bottom-gate structure TFT device 100H, which includes a light-transmitting insulating substrate 40H, and a gate 20H, a gate dielectric layer 30H, and an active layer 10H that are sequentially disposed on the substrate 40H. In this embodiment, an upper-layer metal source electrode 501H and a metal drain electrode 502H are respectively disposed on both sides of the active layer 10H. The active layer 10H can adopt an amorphous IGZO metal oxide semiconductor layer, and an ohmic contact is formed between the source electrode 501H and the drain electrode 502H and the active layer 10H. The portions of the active layer below the source electrode 501H and the drain electrode 502H respectively constitute the source region and the drain region, and the channel region is located between the source region and the drain region.

[0113] Positive charge regions 60H that are respectively connected to the source electrode 501H and the drain electrode 502H are formed by ion implantation in the passivation layer covering the upper layer of the device. There is an overlapping portion between the vertical projection of the positive charge region 60H and the gate 20H in the channel region. Correspondingly, the positive charge region in this overlapping portion can form a two-dimensional electron gas 70H that is respectively connected to the source region and the drain region in the channel region. Here, the two-dimensional electron gas 70H constitutes the first conductive region and the second conductive region.

[0114] When the device is turned on, a channel is formed above the gate 20H, and the portion of the channel whose vertical projection is between the first conductive region and the second conductive region constitutes the actual effective channel.

[0115] Example 9

[0116] Refer Figure 18The device is a vertical SOI device 100I, comprising a substrate 60I, a buried insulating layer 50I and an active layer 10I sequentially disposed on the substrate 60I, a gate insulating layer 30I disposed on one side of the active layer 10I, and a gate 20I. In a direction away from the substrate 60I, a source region 101I and a drain region 102I are located below and above the active layer 10I, respectively. An equivalent source region 1051I connected to the active region 101I and an equivalent drain region 1052I connected to the drain region 102I are formed in the channel region 103I.

[0117] When a bias voltage is applied to the gate 20I of the device to turn it on, the gate 20I controls the formation of a channel 104I in the channel region 103I of the device, which connects the source region 101I and the drain region 102I. However, only the portion of the channel 104I that does not overlap with the equivalent source region 1051I and the equivalent drain region 1052I in the vertical projection on the channel region 103I constitutes an effective channel 1041I for transmitting the operating current when the device is turned on. That is, the remaining portion 1042I in the channel 104I is not used to transmit the operating current when the device is turned on.

[0118] In the above embodiments / examples, the source and drain regions in the device can be common heavily doped semiconductor sources and drains, or Schottky metal sources and drains of metal-semiconductor structures; the gate can be a common metal-insulator-semiconductor MOS structure gate, or a Schottky junction gate of a metal-semiconductor structure; the active layer can be composed of a single semiconductor material, or it can include at least two semiconductor materials that vary along its thickness direction or planar extension direction to form a composite channel.

[0119] Furthermore, the equivalent source region and equivalent drain region can be formed spontaneously or controlled by the gate structure of the corresponding structure.

[0120] In general, in the above embodiments, the vertical projection of the effective channel, equivalent source region, and / or equivalent drain region superimposed on the channel region connects the source and drain regions, thereby ensuring that carriers in the effective channel and the equivalent source and / or equivalent drain regions can be injected unidirectionally or bidirectionally at least in the thickness direction, and constructing a carrier path from the source region to the drain region. Of course, referring to... Figure 19, in this application, it does not exclude that in some specific embodiments, if the vertical projections of the effective channel, the equivalent source region, and the equivalent drain region superimposed on the channel region 103J do not connect the source region 101J and the drain region 102J of the device 100J, but have an "appropriate interval", and this interval does not completely cut off the path of carriers flowing from the equivalent source region 1051J to the effective channel 1041J and from the effective channel 1041J to the equivalent drain region 1052J, and the injection direction of carriers among the effective channel 1041J, the equivalent source region 1051J, and the equivalent drain region 1052J forms an angle with the thickness direction of the channel region 103J, such an implementation manner should also fall within the protection scope of this application.

[0121] The following are the results of Silvaco TCAD simulation verification for the SOI device applying the above implementation manners / embodiments of this application.

[0122] Simulation Example 1

[0123] In Simulation Example 1, the SOI device applying the above implementation manners / embodiments of this application is referred to as the "SOI device of this application". For comparison, there is an SOI device with a similar structure to the SOI device of this application, and the difference is only that the lengths of the equivalent source region and the equivalent drain region in the SOI device for comparison (referred to as the comparative SOI device in this simulation example) are equal.

[0124] Simulation parameters: The source-drain doping is N-type, and the doping concentration is 1E21 cm -3 , the channel doping is P-type, and the doping concentration is 1E17 cm -3 , the channel length L g is 130 nm, the effective channel length L eff is 70 nm, the length of the equivalent source region L es and the length of the equivalent drain region L ed sum up to 60 nm (where the length of the equivalent source region takes 10 nm, 30 nm, 35 nm, 50 nm, and when the length of the equivalent source region is 30 nm, it is the SOI device for comparison), the thickness of the active layer is 50 nm, the thickness of the gate insulating layer is 5 nm, the fixed charge surface density at the interface where the equivalent source region and the equivalent drain region are formed is 1E14 cm -2 , the drain terminal voltage V d = 2V or 0.1V.

[0125] Ref. Figure 20 and Figure 21 , are respectively the SOI device of this application and the comparative SOI device at the drain terminal voltage V dComparison graph of transfer characteristics at 2V and 0.1V. It can be seen that the subthreshold swing of the comparison SOI device is the smallest, while in the SOI device of the present application, the closer the equivalent source region length is to 30nm, the smaller the subthreshold swing. Taking the SOI device of the present application with an equivalent source region length = 35nm as an example, its subthreshold swing loss at the drain voltage V d is very small at 2V and 0.1V.

[0126] Refer to Figure 22 and Figure 23 , which are respectively the comparison graphs of the output characteristics of the SOI device of the present application and the comparison SOI device at the gate voltage V g of 1.5V and 0.5V. In the output characteristics, the V d value corresponding to the significant occurrence of the KINK current is V kink , and the larger V kink is, the weaker the carrier collision ionization effect in the drain depletion region of the device, and the more difficult it is for the device to exhibit the kink current effect. It can be seen that the saturation voltage V dsat and saturation current I dsat of the SOI device of the present application have less loss, but the kink voltage and output impedance R o are significantly improved.

[0127] From the Figures 20 to 23 comparison, it can be seen that the SOI device of the present application can significantly improve the output characteristics of the device while not causing obvious loss in the ability to suppress the short-channel effect compared with the comparison SOI device.

[0128] Simulation Example 2

[0129] In Simulation Example 2, it will be verified that in the SOI device applying the above-mentioned embodiment / embodiment of the present application (referred to as the SOI device of the present application in this simulation example): the work function of the part corresponding to the effective channel in the first gate the work function of the part adjacent to the source region in the remaining part of the first gate the work function of the part adjacent to the drain region in the remaining part of the first gate When changed, the influence on the device. As a comparison, there is a SOI device with a similar structure to the SOI device of the present application (referred to as the comparison SOI device in this simulation example), and the difference is only that it does not have the above-mentioned structural changes.

[0130] Simulation parameters: The source and drain doping is N-type, the doping concentration is 1E21cm -3 , the channel doping is P-type, the doping concentration is 1E17cm -3 , the channel length L g is 130nm, the effective channel length L eff is 70nm, the equivalent source region L es and the equivalent drain region Led Both have a length of 30 nm, the active layer has a thickness of 50 nm, the gate insulating layer has a thickness of 5 nm, and the fixed charge surface density at the interface forming the equivalent source region and the equivalent drain region is 1E14 cm -2 , and the drain terminal voltage V d = 2 V or 0.1 V.

[0131] Refer to Figure 24 and Figure 25 , which are the transfer characteristic comparison diagrams of the SOI devices of this application and the comparative SOI devices with two different first gate work functions at drain terminal voltages V d of 2 V and 0.1 V respectively; and Figure 26 and Figure 27 , which are the output characteristic comparison diagrams of the SOI devices of this application and the comparative SOI devices with two different first gate work functions at gate terminal voltages V g of 1.5 V and 0.5 V respectively. Among them, the first gate work function W of the comparative SOI device is 4.17 eV, and the two SOI devices of this application are respectively increased to 4.67 eV, to 4.67 eV.

[0132] From Figure 24 and Figure 25 it can be seen that, compared with the comparative SOI device, when it is increased, the subthreshold swing characteristic of the SOI device of this application becomes worse, that is, the ability to suppress the short-channel effect becomes weaker; when it is increased, the subthreshold swing of the SOI device of this application is hardly affected. At the same time, from Figure 26 and Figure 27 it can be seen that, compared with the comparative SOI device, whether is increased or is increased, the output characteristics of the SOI device of this application deteriorate.

[0133] Refer to Figure 28 and Figure 29 , which are the transfer characteristic comparison diagrams of the SOI devices of this application and the comparative SOI devices with two different first work functions at drain terminal voltages V d of 2 V and 0.1 V respectively; and Figure 30 and Figure 31 , which are the output characteristic comparison diagrams of the SOI devices of this application and the comparative SOI devices with two different first work functions at gate terminal voltages V g of 1.5 V and 0.5 V respectively. Among them, the first gate work function W of the comparative SOI device is 4.17 eV, and the two SOI devices of this application are respectively decreased to 3.67 eV and 3.2 eV.

[0134] From Figure 28 and Figure 29 it can be seen that, compared with the comparative SOI device, when decreases, the subthreshold swing characteristic of the SOI device of the present application deteriorates slightly, that is, the ability to suppress the short-channel effect becomes slightly weaker; but from 30 and Figure 31 it can be seen that when decreases, the saturation voltage V dsat and the saturation current I dsat of the SOI device of the present application are significantly improved. That is, when decreases, the output characteristics of the device can be significantly improved while not causing a significant loss in the ability to suppress the short-channel effect.

[0135] Refer to Figure 32 and Figure 33 , which are the transfer characteristic comparison diagrams of the SOI devices of the present application with two different first work functions and the comparative SOI device at drain terminal voltages V d of 2V and 0.1V; and Figure 34 and Figure 35 , which are the output characteristic comparison diagrams of the SOI devices of the present application with two different first work functions and the comparative SOI device at gate terminal voltages V g of 1.5V and 0.5V. Among them, the first gate work function W of the comparative SOI device is 4.17 eV, and the two SOI devices of the present application are respectively reduced by to 3.92 eV and 3.67 eV on the basis of the comparative SOI device.

[0136] From Figure 32 and Figure 33 it can be seen that, compared with the comparative SOI device, when decreases, the subthreshold swing characteristic of the SOI device of the present application remains basically unchanged, that is, the ability to suppress the short-channel effect remains basically unchanged; but from 34 and Figure 35 it can be seen that when decreases, the kink voltage of the SOI device of the present application increases significantly. That is, when decreases, the output characteristics of the device can be significantly improved while maintaining the ability to suppress the short-channel effect basically unchanged.

[0137] Refer to Figure 36 and Figure 37 , which are the transfer characteristic comparison diagrams of the SOI devices of the present application with three different first work functions and the comparative SOI device at drain terminal voltages V d of 2V and 0.1V; and Figure 38 and Figure 39 , which are the output characteristic comparison diagrams of the SOI devices of the present application with three different first work functions and the comparative SOI device at gate terminal voltages V gThe output characteristics are compared at 1.5V and 0.5V. The first gate work function W of the comparative SOI device is 4.17eV, while the three SOI devices in this application reduce the voltage by [value missing] compared to the comparative SOI device. 3.67 eV, reduced 3.92 eV, while reducing 3.67 eV and It is 3.92 eV.

[0138] from Figures 36 to 39 It can be seen that, compared to SOI devices, it simultaneously reduces and The SOI device of this application can both ensure good suppression of short-channel effects and enable the device to have a small saturation voltage V. dsat and a large saturation current I dsat Kink voltage and output impedance R o .

[0139] It should be understood that although the terms first, second, etc., may be used herein to describe various elements or structures, the objects being described should not be limited by these terms. These terms are only used to distinguish these objects from one another. For example, a first channel may be referred to as a second channel, and similarly, a second channel may be referred to as a first channel, without departing from the scope of protection of this application.

[0140] Furthermore, the same reference numerals or markings may be used in different implementations, but this does not represent a structural or functional connection, but is merely for the convenience of description.

[0141] The terms used in this invention, such as “above,” “over,” “below,” and “under,” indicating spatial relative position, are for illustrative purposes to describe the relationship of one unit or feature relative to another unit or feature as shown in the accompanying drawings. These terms may be intended to include different orientations of the device in use or operation other than those shown in the figures. For example, if the device in the figures is flipped, a unit described as being “below” or “under” other units or features would be located “above” other units or features. Therefore, the exemplary term “under” can encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or otherwise) and the spatially related descriptive terms used in this invention will be interpreted accordingly.

[0142] When a component or layer is referred to as being "on" or "connected" to another component or layer, it can be directly on or connected to that other component or layer, or there can be intermediate components or layers. Conversely, when a component is referred to as being "directly on" or "directly connected to" another component or layer, there cannot be intermediate components or layers.

[0143] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0144] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style of the specification is merely for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A field-effect transistor device, comprising an active layer, characterized in that, The active layer includes a source region, a drain region, and a channel region located between the source region and the drain region. When the device is turned on, an effective channel is formed in the channel region, as well as an equivalent source region and an equivalent drain region that are at least away from the effective channel in the thickness direction of the channel region. The field-effect transistor device connects the source region and the drain region through the effective channel, the equivalent source region and the equivalent drain region to contribute the operating current. Wherein, the length of the equivalent source region is greater than the length of the equivalent drain region.

2. The field-effect transistor device according to claim 1, characterized in that, The equivalent source region includes a first conductive region located in the channel region and connected to the source region, and the equivalent drain region includes a second conductive region located in the channel region and connected to the drain region, with a gap between the first conductive region and the second conductive region.

3. The field-effect transistor device according to claim 2, characterized in that, The active layer includes a first gate disposed on one side surface, wherein the vertical projections of the first gate and the first conductive region and the second conductive region on the channel region overlap; wherein the first gate can control the channel region and form a channel therein, and the portion of the channel that does not overlap with the vertical projections of the first conductive region and the second conductive region on the channel region constitutes the effective channel.

4. The field-effect transistor device according to claim 3, characterized in that, When the device is turned on, the conductivity of the first conductive region and the second conductive region is greater than the conductivity of the remaining portion of the channel excluding the effective channel, so that the first conductive region can inject charge carriers into the effective channel and the effective channel can inject charge carriers into the second conductive region.

5. The field-effect transistor device according to claim 4, characterized in that, The conductivity of the first conductive region and the second conductive region is at least three times greater than the conductivity of the remaining portion of the channel excluding the effective channel.

6. The field-effect transistor device according to claim 3, characterized in that, When the device is turned on, the conductance per unit length of the effective channel in the channel is less than the conductance per unit length of the remaining portion of the channel excluding the effective channel.

7. The field-effect transistor device according to claim 3, characterized in that, When the field-effect transistor device is an N-type device, the work function of the portion of the first gate corresponding to the effective channel is greater than the work function of the remaining portion of the first gate. When the field-effect transistor device is a P-type device, the work function of the portion of the first gate corresponding to the effective channel is less than the work function of the remaining portion of the first gate; and / or, The field-effect transistor device includes a gate insulating layer disposed between the first gate and the channel region, wherein the thickness of the portion of the gate insulating layer corresponding to the effective channel is greater than the thickness of the remaining portion of the gate insulating layer; and / or, The field-effect transistor device includes a gate insulating layer disposed between the first gate and the channel region, wherein the dielectric constant of the portion of the gate insulating layer corresponding to the effective channel is greater than the dielectric constant of the remaining portion of the gate insulating layer.

8. The field-effect transistor device according to claim 7, characterized in that, When the field-effect transistor device is an N-type device, the following conditions are met: 0.2V - 0.7V; When the field-effect transistor device is a P-type device, the following conditions are met: 0.2V - 0.7V; in, This is the threshold voltage of the portion of the first gate corresponding to the effective channel. It is the threshold voltage of the portion of the first gate corresponding to the equivalent drain region.

9. The field-effect transistor device according to claim 8, characterized in that, When the field-effect transistor device is an N-type device, the following conditions are met: 0.3V - 0.6V; When the field-effect transistor device is a P-type device, the following conditions are met: 0.3V - 0.6V。 10. The field-effect transistor device according to claim 9, characterized in that, When the field-effect transistor device is an N-type device, the following conditions are met: 0.4V - 0.5V; When the field-effect transistor device is a P-type device, the following conditions are met: 0.4V - 0.5V。 11. The field-effect transistor device according to any one of claims 2 to 10, characterized in that, It also includes a second gate disposed on the surface of the active layer adjacent to the first conductive region and the second conductive region, the second gate being capable of controlling the formation of the first conductive region and the second conductive region in the channel region; and / or, The first and second conductive regions are formed by carriers introduced by surface doping of the channel region on the side away from the effective channel; and / or, It also includes an insulating layer disposed on the surface of the active layer away from the effective channel, wherein the first conductive region and the second conductive region are constituted by charge carriers generated by electrostatic induction in the channel region near the insulating layer by the injected charge in the insulating layer; and / or, It also includes a semiconductor material layer disposed on the surface of the active layer away from the effective channel, the active layer and the semiconductor material layer forming a heterostructure, the first conductive region and the second conductive region being composed of two-dimensional electron gas channels or two-dimensional hole gas channels distributed in the heterostructure; and / or, The first conductive region and the second conductive region are formed by surface treatment of the side surface of the channel region away from the effective channel, which is a two-dimensional electron gas channel or a two-dimensional hole gas channel.

12. The field-effect transistor device according to any one of claims 1 to 10, characterized in that, The length ratio of the equivalent source region to the equivalent drain region ranges from 1.1:1 to 2.5:1; And / or, the sum of the lengths of the equivalent source region and the equivalent drain region is not greater than three times the effective channel length.

13. The field-effect transistor device according to claim 12, characterized in that, The length ratio of the equivalent source region to the equivalent drain region ranges from 1.2:1 to 2.3:

1.

14. The field-effect transistor device according to claim 13, characterized in that, The length ratio of the equivalent source region to the equivalent drain region ranges from 1.1:1 to 2.2:

1.

15. The field-effect transistor device according to claim 14, characterized in that, The length ratio of the equivalent source region to the equivalent drain region ranges from 1.4:1 to 2.2:

1.

16. The field-effect transistor device according to claim 15, characterized in that, The length ratio of the equivalent source region to the equivalent drain region ranges from 1.8:1 to 2.2:

1.

17. The field-effect transistor device according to any one of claims 1 to 10, characterized in that, The source and drain regions are doped semiconductor or Schottky metal source / drain regions; and / or, The gate of the field-effect transistor device is a metal-insulator-semiconductor MOS structure gate or a Schottky junction gate; And / or, The active layer comprises at least two semiconductor materials that vary along its thickness direction or planar extension direction; and / or, The field-effect transistor device is a planar structure device or a vertical structure device.

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