Non-uniformly doped field effect transistor device

Abstract

This application discloses a non-uniformly doped field-effect transistor (FET) device to solve the short-channel effect problem of existing FETs. The FET device is configured such that, when the device is turned on, an effective channel is formed in the channel region, along with an equivalent source region and / or an equivalent drain region located at least in the thickness direction of the channel region away from the effective channel. The FET device connects the source region and the drain region through the effective channel, the equivalent source region, and the equivalent drain region to contribute operating current. Specifically, in the direction of the channel region near the effective channel: at least a portion of the doping concentration in the first region gradually decreases; and / or, at least a portion of the doping concentration in the second region gradually increases; and / or, at least a portion of the doping concentration in the third region gradually decreases; and / or, in the direction from the source region to the drain region: at least a portion of the doping concentration in the third region gradually decreases.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a non-uniformly doped field-effect transistor device. Background Technology

[0002] With the development of integrated circuit technology, the gate length (corresponding to the channel length) of field-effect transistors (FETs) is constantly shrinking. Currently, VLSI chips based on submicron or even sub-10 nanometer gate length devices are already in mass production. For these small-sized devices, how to deal with their short-channel effect is a major challenge in device technology. The short-channel effect causes a comprehensive degradation of the threshold voltage and subthreshold characteristics of small-sized devices. Specifically, the device threshold voltage is no longer constant, but decreases with decreasing channel length and decreases with increasing drain voltage; the subthreshold swing of the device transfer characteristics also deteriorates simultaneously.

[0003] Currently, methods to improve the short-channel effect of field-effect transistors mainly include FinFETs, silicon-on-insulator (SOI), lightly doped drain (LDD) structures, and metal-source-drain Schottky barrier transistors (SB MOSFETs). ① FinFETs have a 3D fin-shaped channel region and a three-sided gate-around structure. The two side gates enhance the gate's control over the channel, effectively suppressing the short-channel effect. The fabrication process for this approach is much more complex than for planar devices. Currently, chips using technology nodes below 22nm mostly adopt the FinFET approach. ② SOI technology introduces a buried oxide layer between the silicon channel layer and the back substrate. Under conditions of a very thin and fully depleted channel layer, it can effectively suppress leakage current between the source and drain. The challenge of this approach lies in the very high cost of SOI silicon wafers. Currently, chips based on SOI at the 10nm technology node are already in mass production. ③ A lightly doped drain LDD is located near the drain channel, while the source and drain regions far from the channel remain heavily doped. The drain PN junction formed by this lightly doped region reduces the impact of the drain voltage on the channel, making it the mainstream technology for submicron-level short-channel devices. In this scheme, both the on-state current and field-effect mobility of the device are reduced to some extent by the LDD. ④ The operating current of a Schottky barrier transistor is the tunneling current of the Schottky barrier between the metal source and the semiconductor channel. It is not sensitive to short-channel effects. This scheme is relatively difficult to fabricate, has limited choices of barrier materials, and it is difficult to simultaneously suppress the off-state current of the device.

[0004] On the other hand, the kink effect appearing on the output characteristic curve of short-channel devices has also attracted much attention. When the device operates in saturation, the high drain voltage depletes the drain terminal and forms a high electric field region. Carriers are prone to collisional ionization here and are amplified by coupling with the parasitic bipolar transistors of the MOS device. This causes the drain current to increase rapidly with the increase of the drain voltage, forming the so-called kink current. The output characteristic curve of the device is significantly warped, which seriously affects the normal output characteristics.

[0005] Common methods to mitigate the kink effect include increasing the device channel length and using lightly doped drain (LDD) structures. Increasing the channel length reduces the impact of carriers generated by drain collisional ionization on the source, weakening parasitic transistor effects and alleviating the kink effect. However, increasing the channel length will correspondingly reduce the device's output current. LDD structures can reduce the peak electric field intensity in the drain depletion region, weakening the carrier collisional ionization effect and thus suppressing the kink effect. However, LDD structures introduce additional parasitic resistance, reducing the device's field-effect mobility and on-state current.

[0006] The information disclosed in this background section is intended only to enhance the understanding of the overall background of this application and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0007] The purpose of this application is to provide a field-effect transistor device that solves the problem of short-channel effect in existing field-effect transistors.

[0008] To achieve the above objectives, this application provides a non-uniformly doped field-effect transistor device, including an active layer, wherein the active layer includes a source region, a drain region, and a channel region located between the source region and the drain region; When the device is turned on, an effective channel is formed in the channel region, and an equivalent source region and / or equivalent drain region are formed at least in the thickness direction of the channel region away from the effective channel. The field-effect transistor device connects the source region and the drain region through the effective channel, the equivalent source region and the equivalent drain region to contribute the operating current. Specifically, in the direction of the channel region near the effective channel: The doping concentration in at least a portion of the first region gradually decreases; and / or, In the second region, the doping concentration gradually increases in at least a portion; and / or, In the third region, the doping concentration gradually decreases in at least a portion; and / or, In the direction from the source region to the drain region: The doping concentration in at least a portion of the third region gradually decreases; The first region is the region in the channel region corresponding to the equivalent source region, the second region is the region in the channel region corresponding to the equivalent drain region, and the third region is the region in the channel region corresponding to the effective channel.

[0009] In one embodiment, in the direction of the channel region near the effective channel: The doping concentration gradually decreases in the third region and the first region, while the doping concentration gradually increases in the second region; or, The doping concentration gradually decreases in the third region and the first region, while the second region is uniformly doped; or, The doping concentration gradually decreases in the third region, while the first and second regions are uniformly doped; or, The doping concentration gradually decreases in the third region, the first region, and the second region; or, The third region is uniformly doped, the doping concentration in the first region gradually decreases, and the doping concentration in the second region gradually increases; or, The third region and the first region are uniformly doped, and the doping concentration in the second region gradually increases; or, The third region and the second region are uniformly doped, while the doping concentration in the first region gradually decreases.

[0010] In one embodiment, the doping concentration in the first region, the second region, and the third region varies according to one of the following: linear distribution, exponential distribution, Gaussian distribution, and residual error distribution.

[0011] In one embodiment, a conductive region that does not connect the source region and the drain region is formed in the channel region; wherein, When the conductive region is connected to the source region, the conductive region constitutes the equivalent source region; and / or, When the conductive region is connected to the drain region, the conductive region constitutes the equivalent drain region.

[0012] In one embodiment, a first gate is disposed on one side surface of the active layer, and the vertical projection of the first gate and the conductive region on the channel region overlaps; wherein the first gate can control the channel region and form a channel therein, and the portion of the channel that does not overlap with the vertical projection of the conductive region on the channel region constitutes the effective channel.

[0013] In one embodiment, when the device is turned on, the conductivity of the conductive region is greater than the conductivity of the remaining portion of the channel excluding the effective channel, so that at least one of the conductive region and the effective channel can inject carriers into the other.

[0014] In one embodiment, the conductivity of the conductive region is at least three times greater than the conductivity of the remaining portion of the channel excluding the effective channel.

[0015] In one embodiment, the field-effect transistor device is a planar structure device or a vertical structure device.

[0016] In one embodiment, when the device is turned on, the conductance per unit length of the effective channel in the channel is less than the conductance per unit length of the remaining portion of the channel excluding the effective channel.

[0017] In one embodiment, when the field-effect transistor device is an N-type device, the work function of the portion of the first gate corresponding to the effective channel is greater than the work function of the remaining portion of the first gate. When the field-effect transistor device is a P-type device, the work function of the portion of the first gate corresponding to the effective channel is less than the work function of the remaining portion of the first gate.

[0018] In one embodiment, the field-effect transistor device includes a gate insulating layer disposed between the first gate and the channel region, wherein the thickness of the portion of the gate insulating layer corresponding to the effective channel is greater than the thickness of the remaining portion of the gate insulating layer.

[0019] In one embodiment, the field-effect transistor device includes a gate insulating layer disposed between the first gate and the channel region, wherein the dielectric constant of the portion of the gate insulating layer corresponding to the effective channel is greater than the dielectric constant of the remaining portion of the gate insulating layer.

[0020] In one embodiment, a second gate is further provided on the surface of the active layer adjacent to the conductive region, the second gate being capable of controlling the formation of the conductive region in the channel region.

[0021] In one embodiment, the conductive region is formed by carriers introduced by doping on the surface of the channel region on the side away from the effective channel.

[0022] In one embodiment, an insulating layer is further disposed on the surface of the active layer away from the effective channel, and the conductive region is composed of charge carriers generated by injected charges in the insulating layer through electrostatic induction in the channel region near the insulating layer.

[0023] In one embodiment, a semiconductor material layer is further disposed on the surface of the active layer away from the effective channel, the active layer and the semiconductor material layer form a heterostructure, and the conductive region is composed of two-dimensional electron gas channels or two-dimensional hole gas channels distributed in the heterostructure.

[0024] In one embodiment, the conductive region is formed by surface treatment of the surface of the channel region away from the effective channel, creating a two-dimensional electron gas channel or a two-dimensional hole gas channel.

[0025] This application also provides a field-effect transistor device, including an active layer, the active layer including a source region, a drain region, and a channel region located between the source region and the drain region; When the device is turned on, an effective channel is formed in the channel region, and an equivalent source region and / or equivalent drain region are formed at least in the thickness direction of the channel region away from the effective channel. The field-effect transistor device connects the source region and the drain region through the effective channel, the equivalent source region and the equivalent drain region to contribute the operating current. Wherein, at least a portion of the channel region is non-uniformly doped to form a built-in electric field within the channel region that guides the movement of charge carriers from the equivalent source region to the effective channel, and / or a built-in electric field that guides the movement of charge carriers from the effective channel to the equivalent drain region.

[0026] Compared with the prior art, in the embodiments of this application, by configuring the device to form an effective channel in the channel region and an equivalent source region and an equivalent drain region that are far away from the effective channel in the thickness direction of the channel region when it is turned on, the source region and the drain region are connected to contribute the operating current; in this way, the equivalent drain region (source) connected to the drain (source) region is structurally far away from the effective channel, which can reduce the influence of the drain voltage on the effective channel; and reduce the peak built-in electric field in the drain depletion region when the device is saturated, thereby suppressing the short-channel effect of the device and improving the output characteristics of the device.

[0027] On the other hand, by non-uniform doping in the channel region, a built-in electric field is formed in the channel region to guide the movement of charge carriers from the equivalent source region to the effective channel, and / or to guide the movement of charge carriers from the effective channel to the equivalent drain region. This ensures good suppression of short-channel effects and also enables the device to have a small saturation drain voltage V. dsat and a large saturation leakage current I dsat Kink voltage and output impedance R o . Attached Figure Description

[0028] Figure 1 This is a schematic diagram illustrating the formation of an equivalent source region, an equivalent drain region, and an effective channel in a non-uniformly doped field-effect transistor device in the on-state according to an embodiment of this application. Figure 2 This is a schematic diagram of the structure of a non-uniformly doped field-effect transistor device in the on-state according to an embodiment of this application; Figure 3This is a schematic diagram showing the state of the conductive region formed in a non-uniformly doped field-effect transistor device according to an embodiment of this application. Figures 4 to 13 This is a schematic diagram of the structure of the non-uniformly doped field-effect transistor device according to various embodiments of this application; Figures 14 to 21 This is a schematic diagram illustrating the principle of fabricating the conductive region in various embodiments of this application; Figures 22 to 24 This is a schematic diagram of the structure of an SOI device using the solution of this application; Figure 25 This is a schematic diagram of a non-uniformly doped field-effect transistor device according to an embodiment of the present application, showing a gap between the effective channel and the conductive region in the vertical projection of the channel region. Figure 26 This is a comparison chart of the transfer characteristics of each device in simulation example 1; Figure 27 This is a comparison chart of the output characteristics of each device in simulation example 1; Figure 28 This is a comparison chart of the transfer characteristics of each device in simulation example 2; Figure 29 This is a comparison chart of the output characteristics of each device in simulation example 2; Figure 30 This is a comparison chart of the transfer characteristics of each device in simulation example 3; Figure 31 This is a comparison chart of the output characteristics of each device in simulation example 3; Figure 32 This is a comparison chart of the transfer characteristics of each device in simulation example 4; Figure 33 This is a comparison chart of the output characteristics of each device in simulation example 4; Figure 34 This is a comparison chart of the transfer characteristics of each device in simulation example 5; Figure 35 This is a comparison chart of the output characteristics of each device in simulation example 5; Figure 36 This is a comparison chart of the transfer characteristics of each device in simulation example 6; Figure 37 This is a comparison chart of the output characteristics of each device in simulation example 6; Figure 38 This is a comparison chart of the transfer characteristics of each device in simulation example 7; Figure 39 This is a comparison chart of the output characteristics of each device in simulation example 7. Detailed Implementation

[0029] The present application will be described in detail below in conjunction with the various embodiments shown in the accompanying drawings. However, these embodiments do not limit the present application, and any structural, method, or functional transformation made by those of ordinary skill in the art based on these embodiments is included within the protection scope of the present application.

[0030] Refer to Figure 1 , and a specific embodiment of the non-uniformly doped field effect transistor device of the present application will be introduced. In this embodiment, the field effect transistor device 100 includes an active layer 10, and the active layer 10 includes a source region 101, a drain region 102, and a channel region 103.

[0031] The source region 101 and the drain region 102 are respectively located on both sides of the active layer 10, and the channel region 103 is located between the source region 101 and the drain region 102. Referring to Figure 1 the schematic diagram when the device is turned on as shown, an effective channel 1041 is formed in the channel region 103 of the field effect transistor, and an equivalent source region 1051 and an equivalent drain region 1052 that are far from the effective channel 10 as shown in the thickness direction of the channel region 103. The field effect transistor device 100 connects the source region 101 and the drain region 102 through the effective channel 1041, the equivalent source region 1051, and the equivalent drain region 1052 to contribute a working current.

[0032] In some embodiments of the present application, the "far from" between the effective channel 1041 and the equivalent source region 1051 and the equivalent drain region 1052 may include being far from each other not only in the thickness direction of the channel region but also in the length direction of the channel region. In these embodiments, regardless of whether it is in the thickness or length direction of the channel region, it is limited that when the device is turned on, it does not affect the connection between the effective channel 1041, the equivalent source region 1051, and the equivalent drain region 1052 to the source region 101 and the drain region 102. [[ID=!14]]

[0033] In a typical field effect transistor device 100, the source region 101 of the active layer 10 is used to provide carriers when the device is turned on, and the drain region 102 is used to collect the carriers provided by the source region 101. Correspondingly, in the present application, the mentioned equivalent source region 1051 refers to a structure that directly injects some carriers provided by the source region 101 into the effective channel 1041, and the equivalent drain region 1052 refers to a structure that directly receives some carriers from the effective channel 1041 and injects them into the drain region 102.

[0034] Refer to Figure 2In this application, "effective channel 1041" refers to the portion of the channel through which the charge carriers of the operating current pass when the device is turned on. Taking this embodiment as an example, a first gate 20 can be disposed on one side surface of the active layer 10, and there is no gap between the vertical projection of the first gate 20 on the active layer 10 and the source region 101 and drain region 102. Therefore, when a gate bias voltage is applied to the first gate 20 to turn on the device, a channel 104 can be controlled to form below the first gate 20, and this channel 104 is structurally connected to the source region 101 and drain region 102. However, from a functional perspective, only the portion of this channel that does not overlap with the vertical projections of the equivalent source region 1051 and equivalent drain region 1052 on the channel region 103 is used to carry the entire operating current; therefore, only this portion of the channel is referred to as "effective channel 1041" here.

[0035] In this embodiment, the carrier path when the device is turned on includes two main parts: one part is from the source region 101 sequentially entering the equivalent source region 1051, the effective channel 1041, the equivalent drain region 1052, and the drain region 102; the other part is from the source region 101 directly entering the drain region 102 through the channel 104. From the perspective of the carrier path, the remaining portion of the channel 104, excluding the effective channel 1041, is only used to transmit a portion of the operating current.

[0036] It can be seen that the effective channel 1041 in this application is not limited to having a different device structure or parameter settings than the rest of the channel 104. In fact, in some embodiments, the channel 104 described above can be formed on the entire channel region, and only the setting of the equivalent source region 1051 and the equivalent drain region 1052 is needed to ensure that when the device is turned on, the carriers provided by the source region 101 are not directly injected into the drain region 102 through the channel 104. Furthermore, the channel control shown in some embodiments below, such as changing the work function of the first gate corresponding to the effective channel or the thickness of the gate insulating layer, should not be regarded as a necessary prerequisite for forming an effective channel.

[0037] The arrangement of the equivalent source region 1051 and the equivalent drain region 1052 effectively shortens the length of the portion of the channel 104 that can conduct all the operating current, thus creating a gap between the effective channel 1041 and the source region 101 and the drain region 102. Furthermore, the equivalent drain region 1052, which is connected to the drain region 102, is structurally located away from the effective channel 1041, reducing the influence of the drain potential on the effective channel 1041. Similarly, the equivalent source region 1051, which is connected to the source region 101, is structurally located away from the effective channel 1041, and its potential is consistent with that of the source region (typically zero potential), further reducing the influence of the drain potential on the effective channel 1041 and improving the short-channel effect of the device.

[0038] Reference Figure 3 In the specific preparation of the equivalent source region 1051 and the equivalent drain region 1052, conductive regions A1 and A2 that are not connected to the source region 101 and the drain region 102 can be formed in the channel region 103. When the conductive region A1 is connected to the source region 101, this part of the conductive region A1 constitutes the equivalent source region 1051; when the conductive region A2 is connected to the drain region 102, this part of the conductive region A2 constitutes the equivalent drain region 1052.

[0039] When the device is turned on, the conductance of conductive regions A1 and A2 is set to be greater than the conductance of the remaining portion 1042 of channel 104 excluding the effective channel 1041, so that conductive regions A1 and A2 and the effective channel 1041 can inject charge carriers into each other. In this way, the charge carriers in the source region 101 will be attracted by the equivalent source region 1051 with a larger conductance, instead of being directly injected into the remaining portion 1042 of channel 104 that is directly connected to the source region 101; similarly, the charge carriers transported in the effective channel 1041 will also be attracted by the equivalent drain region 1052, instead of being transported entirely through the remaining portion 1042 of channel 104.

[0040] To achieve the carrier injection configuration between the equivalent source region 1051, the equivalent drain region 1052, and the effective channel 1041, the conductance of the conductive regions A1 and A2 can be set to be at least three times greater than the conductance of the remaining portion 1042 of the channel 104 excluding the effective channel 1041. Furthermore, since carriers flow through the thickness direction of the channel region 103 during the aforementioned "injection" process, the spacing between the conductive region A and the effective channel 1041 in the thickness direction of the channel region 103 in this embodiment can be set to 5nm~10μm, or more preferably 10nm~1μm, or even more preferably 10nm~100nm, depending on the specific design of different devices, to ensure normal carrier injection and device performance.

[0041] It should be noted that the "charge carrier" mentioned in this application refers to the charged particles that can move freely in the corresponding polarity channel / conductive region A. Generally, we refer to electrons in the N-type channel or holes in the P-type channel as "charge carriers" here. Correspondingly, holes in the N-type channel or electrons in the P-type channel are not referred to as "charge carriers" here. Therefore, in this application, the polarity of the effective channel 1041 and the conductive regions A1 and A2 are set to be the same so that the carrier interaction between the two channels can ultimately contribute substantially to the operating current of the device.

[0042] The shape and location of the conductive region can be set according to the application requirements of the device, and are not limited to... Figure 3 The form shown. For example, Figure 4The conductive regions A1 and A2 in the field-effect transistor device 200 shown can be relative to Figure 3 It has a greater overall thickness and irregular regional shapes. For example, Figure 5 In the field-effect transistor device 300 shown, the conductive regions A1 and A2 are not located at the same height in the thickness direction of the channel region.

[0043] Coordination Figure 6 In this embodiment, the region in the channel region 103 corresponding to the equivalent source region 1051 is called the first region S1, the region in the channel region 103 corresponding to the equivalent drain region 1052 is called the second region S2, and the region in the channel region 103 corresponding to the effective channel 1041 is called the third region S3. Here, "corresponding" can be understood as follows: in the thickness direction of the channel region 103, the channel region 103 is "divided" into three regions by the vertical projections of the equivalent source region 1051, the equivalent drain region 1052, and the effective channel 1041. Therefore, the region obtained by dividing by the vertical projection of the equivalent source region 1051 is the first region S1, the region obtained by dividing by the vertical projection of the equivalent drain region 1052 is the second region S2, and the region obtained by dividing by the vertical projection of the effective channel 1041 is the third region S3.

[0044] It should be noted that the “first region S1”, “second region S2” and “third region S3” mentioned in the various embodiments of this application do not include the part of the device channel region 103 used to form the above-mentioned channel, equivalent source region 1051 and equivalent drain region 1052.

[0045] Specifically, in this embodiment, in the direction of the channel region 103 near the effective channel 1041, at least a portion of the doping concentration in the first region S1 gradually decreases; and / or, at least a portion of the doping concentration in the second region S2 gradually increases; and / or, at least a portion of the doping concentration in the third region S3 gradually decreases; and / or, in the direction of the source region 101 toward the drain region 102, at least a portion of the doping concentration in the third region S3 gradually decreases.

[0046] It should be noted that, in the doping mentioned in the various embodiments / examples of this application, for N-type devices, the doping of their channel region should be P-type; similarly, for P-type devices, the doping of their channel region should be N-type.

[0047] Continue to cooperate with the participants Figure 6 In various embodiments of this application, the direction of the channel region 103 near the effective channel 1041 is defined as direction D from the bottom of the channel region 1041 along the thickness direction of the channel region 1041 to the effective channel.

[0048] Taking the example of a gradual decrease in doping concentration in at least a portion of the first region S1, the doping in the first region S1 can be a change in "vertical doping depth" in the thickness direction of the channel region 103. For example, the doping in the first region S1 can be doped to one-quarter, one-half, three-quarters, or full depth of the thickness of the channel region 103.

[0049] Reference Figure 7 Taking the example of a gradual decrease in doping concentration in at least part of the first region S1, the doping in the first region S1 can be a change in the "lateral doping width" along the length of the effective channel 1041. For example, the doping in the first region S1 can be doped at one-quarter, one-half, three-quarters of the length of the first region S1 along the effective channel 1041, or at the full width of the first region S1.

[0050] In the various embodiments of this application, the doping of at least a portion of the second region S2 and the third region S3 can be partially or entirely referred to the above description of doping in the first region. Furthermore, it should be noted that the description of non-uniform doping in the first region S1, the second region S2, and the third region S3 in the various embodiments / examples of this application does not constitute a restrictive exclusion of doping in the remaining portions of the channel region 103. For example, specifying only that the first region S1 is non-uniformly doped does not mean that the remaining portions of the channel region 103 are intrinsic.

[0051] Similarly, in conjunction with reference Figure 8 and Figure 9 In the direction from the source region 101 to the drain region 102, at least part of the doping concentration in the third region S3 gradually decreases. This can be due to a change in the "vertical doping depth" in the thickness direction of the channel region 103, or a change in the "lateral doping width" in the length direction of the effective channel 1041, which will not be elaborated here.

[0052] In general, through at least partial non-uniform doping in the channel region 103, a built-in electric field is formed within the channel region 103 to guide the movement of charge carriers from the equivalent source region 1051 to the effective channel 1041, and / or, to guide the movement of charge carriers from the effective channel 1041 to the equivalent drain region 1052. Therefore, the changes in doping concentration in the first region S1, the second region S2, and the third region S3 mentioned in this embodiment can be implemented in a coordinated manner. Some exemplary embodiments are given below: In one embodiment, in the direction of the channel region 103 near the effective channel 1041, the doping concentration in the third region S3 and the first region S1 gradually decreases, while the doping concentration in the second region S2 gradually increases. In this embodiment, the doping of the third region S3 and the first region S1 provides at least a built-in electric field to guide the movement of charge carriers from the equivalent source region 1051 to the effective channel 1041, and the doping of the second region S2 provides a built-in electric field to guide the movement of charge carriers from the effective channel 1041 to the equivalent drain region 1052.

[0053] In one embodiment, in the direction of the channel region 103 near the effective channel 1041, the doping concentration in the third region S3 and the first region S1 gradually decreases, while the second region S2 is uniformly doped. In this embodiment, the doping of the third region S3 and the first region S1 provides at least a built-in electric field to guide the movement of charge carriers from the equivalent source region 1051 to the effective channel 1041.

[0054] In one embodiment, the doping concentration in the third region S3 gradually decreases in the direction of the channel region 103 near the effective channel 1041, while the first region S1 and the second region S2 are uniformly doped. In this embodiment, the doping in the third region S3 provides at least a built-in electric field to guide the movement of charge carriers from the equivalent source region 1051 to the effective channel 1041.

[0055] In one embodiment, the third region S3 is uniformly doped, and in the direction of the channel region 103 near the effective channel 1041, the doping concentration in the first region S1 gradually decreases, while the doping concentration in the second region S2 gradually increases. In this embodiment, the doping in the first region S1 provides at least a built-in electric field to guide the movement of charge carriers from the equivalent source region 1051 to the effective channel 1041, and the doping in the second region S2 provides a built-in electric field to guide the movement of charge carriers from the effective channel 1041 to the equivalent drain region 1052.

[0056] In one embodiment, the third region S3 and the first region S1 are uniformly doped, and the doping concentration in the second region S2 gradually increases in the direction of the channel region 103 near the effective channel 1041. In this embodiment, the doping in the second region S2 provides at least a built-in electric field to guide the movement of charge carriers from the effective channel 1041 to the equivalent drain region 1052.

[0057] In one embodiment, the third region S3 and the second region S2 are uniformly doped, and the doping concentration in the first region S1 gradually decreases in the direction of the channel region 103 near the effective channel 1041. In this embodiment, the doping of the first region S1 provides at least a built-in electric field to guide the movement of charge carriers from the equivalent source region 1051 to the effective channel 1041.

[0058] In one embodiment, the doping concentrations in the third region S3, the second region S2, and the first region S1 gradually decrease in the direction of the channel region 103 near the effective channel 1041. In this embodiment, the doping of the first region S1 and the third region S3 provides at least a built-in electric field to guide the movement of charge carriers from the equivalent source region 1051 to the effective channel 1041.

[0059] In one embodiment, the doping concentration in the third region S3 gradually decreases in the direction of the channel region 103 near the effective channel 1041, and simultaneously, the doping concentration in the third region S3 also gradually decreases in the direction from the source region to the drain region. In this embodiment, the doping concentration in the third region S3 has a gradual changing trend in both directions, and the third region S3 can at least provide a built-in electric field to guide the movement of charge carriers from the equivalent source region 1051 to the effective channel 1041, and from the effective channel 1041 to the equivalent drain region 1052.

[0060] In this embodiment, the doping concentration in the first region S1, the second region S2, and the third region S3 varies according to one of a linear distribution, an exponential distribution, a Gaussian distribution, or a residual error distribution. Furthermore, in some embodiments, the doping concentration in these regions can have a larger rate of change, thereby forming a larger built-in electric field that guides the movement of charge carriers.

[0061] Taking the doping concentrations in the first region S1, the second region S2, and the third region S3 as an example, which follow an exponential distribution, the exponential factor can be set to be larger (i.e., the exponential function y=a). x (where a is larger), thereby improving at least some of the device's performance.

[0062] In this embodiment, the doping concentration in the channel region 103 can be set such that at the interface adjacent to the channel 104, it does not affect the carrier mobility in the corresponding region of the channel 104, thereby affecting the formation of the inversion layer and degrading the turn-on characteristics of the device.

[0063] For example, for silicon devices, if the doping concentration in channel 104 is 3.5E18cm -3 The doping concentration at the interface adjacent to the channel 104 in the channel region 103 can be, for example, 3.5E12cm. -3 3.5E13cm -3 5.5E14cm -3 wait.

[0064] The above embodiments are used to explain the field-effect transistor device of this application as including both an equivalent source region and an equivalent drain region. In some embodiments, the field-effect transistor device may also include only an equivalent source region or an equivalent drain region.

[0065] Reference Figure 10 , another embodiment of the field effect transistor device 200 of the present application is introduced.

[0066] Different from the above embodiment, in this embodiment, when the device is turned on, an equivalent drain region is not formed in the channel region 103 at this time. The field effect transistor device 200 connects the source region 101 and the drain region 102 through the effective channel 1041 and the equivalent source region 1051 to contribute the working current.

[0067] In this embodiment, it is equivalent to only weakening the influence of the drain terminal potential on the potential near the source end of the channel region 103 through the setting of the equivalent source region 1051, thereby improving the short-channel effect of the device. Correspondingly, the effective channel 1041 is directly connected to the drain region 102.

[0068] When the device is turned on, in the carrier transport, part of the carriers provided by the source region 101 enter the equivalent source region 1051, and are injected into the effective channel 1041 from the end of the equivalent source region 1051 far from the source region 101; the carriers flowing through the effective channel 1041 are then injected back into the drain region 102. That is, in this embodiment, only the conductive region injects carriers into the effective channel 1041 unidirectionally.

[0069] Correspondingly, in the channel region of this embodiment, there is only a first region S1 corresponding to the equivalent source region 1051 and a third region S3 corresponding to the effective channel 1041. Similarly, in the direction of the channel region 103 approaching the effective channel 1041, at least part of the doping concentration in the first region S1 gradually decreases; and / or, at least part of the doping concentration in the third region S3 gradually decreases; and / or, in the direction from the source region 101 to the drain region 102, at least part of the doping concentration in the third region S3 gradually decreases.

[0070] Reference Figure 11 , another embodiment of the field effect transistor device 300 of the present application is introduced.

[0071] Different from the above embodiment, in this embodiment, when the device is turned on, an equivalent source region is not formed in the channel region 103 at this time. The field effect transistor device 300 connects the source region 101 and the drain region 102 through the effective channel 1041 and the equivalent drain region 1052 to contribute the working current.

[0072] In this embodiment, it is equivalent to only weakening the influence of the drain terminal potential on the effective channel 1041 through the setting of the equivalent drain region 1052, thereby improving the short-channel effect of the device. Correspondingly, the effective channel 1041 is directly connected to the source region.

[0073] In carrier transport, carriers provided by the source region 101 enter the effective channel 1041. Some of the carriers are injected into the equivalent drain region 1052 from one end of the effective channel 1041 away from the source region 101, and then injected back into the drain region 102. That is, in this embodiment, only the effective channel 1041 injects carriers into the conductive region unidirectionally.

[0074] Correspondingly, in the channel region of this embodiment, there are only the second region S2 corresponding to the equivalent drain region 1052 and the third region S3 corresponding to the effective channel 1041. Similarly, in the direction of the channel region 103 approaching the effective channel 1041, the doping concentration of at least a part of the second region S2 gradually increases; and / or, the doping concentration of at least a part of the third region S3 gradually decreases; and / or, in the direction from the source region 101 to the drain region 102, the doping concentration of at least a part of the third region S3 gradually decreases.

[0075] In the above embodiments of the field effect transistor devices 200 and 300, for the specific definitions and doping methods of the first region S1, the second region S2, and the third region S3, reference can be made to the embodiments of the field effect transistor device 100, which will not be elaborated here.

[0076] In the above embodiments, a structure in which a part of the channel formed by gate control constitutes the effective channel has been shown. In such a structure, in order to further improve the ability of the device to suppress the short-channel effect, the unit length conductance of the effective channel in the channel can be set to be less than the unit length conductance of the remaining part of the channel except the effective channel. The following introduces some corresponding embodiments.

[0077] Refer Figure 12 , and introduce another embodiment of the field effect transistor device 400 of the present application.

[0078] The field effect transistor device 400 includes an active layer 10, which includes a source region 101, a drain region 102, and a channel region 103. The source region 101 and the drain region 102 are respectively located on both sides of the active layer 10, and the channel region 103 is located between the source region 101 and the drain region 102.

[0079] An insulating layer 30 and a first gate 20 are sequentially provided above the channel region. And, the thickness of the gate insulating layer 302 corresponding to the effective channel 1041 is greater than the thickness of the gate insulating layer 301 of the remaining part. That is, the gate insulating layer 301 corresponding to the equivalent source region 1051 and the equivalent drain region 1052 is relatively thinned. In this way, the modulation ability of the gate corresponding to the remaining part of the channel 1042 outside the effective channel 1041 to the corresponding part of the channel 1042 can be enhanced, so that the conductance of the corresponding part of the channel 1042 increases.

[0080] Cooperatively, in this embodiment, the dielectric constant of the gate insulating layer 302 corresponding to the effective channel 1041 can also be set to be greater than that of the remaining part of the gate insulating layer 301 to further increase the conductivity of the channel 1042 other than the effective channel 1041.

[0081] Refer Figure 13 to another embodiment of the field effect transistor device 500 of the present application.

[0082] The field effect transistor device 500 includes an active layer 10, and the active layer 10 includes a source region 101, a drain region 102, and a channel region 103. The source region 101 and the drain region 102 are respectively located on both sides of the active layer 10, and the channel region 103 is located between the source region 101 and the drain region 102.

[0083] A first gate 20 is provided above the channel region 103, and the part 201 corresponding to the effective channel 1041 and the remaining part 202 in the first gate 20 are made of different materials, so that the channels formed by the part 201 corresponding to the effective channel 201 and the remaining part 202 in the first gate 20 have different modulation capabilities, and the conductivity of the effective channel 1041 is greater than that of the part 1042 other than the effective channel 1041 in the channel 104.

[0084] In this embodiment, if the field effect transistor device 500 is an N-type device, the work function of the part 201 corresponding to the effective channel 1041 in the first gate 20 is set to be greater than the work function of the remaining part 202 of the first gate 20; correspondingly, if the field effect transistor device 500 is a P-type device, the work function of the part 201 corresponding to the effective channel 1041 in the first gate 20 is set to be less than the work function of the remaining part 202 of the first gate 20.

[0085] Specifically, if it is an N-type device, the portion 201 of the first gate 20 corresponding to the effective channel 1041 can be a metal with a large work function, such as gold or platinum, or P-type doped (P+) polysilicon, or ITO, RuO2, WN, MoN, etc. with a large work function obtained by adjusting the compound composition as the gate material; the remaining portion 202 can be a metal with a small work function, such as aluminum, hafnium, titanium, or N-type doped (n+) polysilicon, or Ru-Hf, WN, HfN, TiN, TaN, TaSiN, etc. with a small work function obtained by adjusting the compound composition as the gate material. If it is a P-type device, the portion 201 of the first gate 20 corresponding to the effective channel 1041 can be a metal with a smaller work function, such as aluminum, hafnium, titanium, or N-type doped (n+) polysilicon, or Ru-Hf, WN, HfN, TiN, TaN, TaSiN, etc., with a smaller work function obtained by adjusting the compound composition, as the gate material; the remaining portion 202 can be a metal with a larger work function, such as gold, platinum, or P-type doped (P+) polysilicon, or ITO, RuO2, WN, MoN, etc., with a larger work function obtained by adjusting the compound composition, as the gate material.

[0086] The following describes the formation of the first conductive region and the second conductive region in this application using some specific embodiments: Example 1 The first conductive region A1 and the second conductive region A2 are formed by carriers introduced by surface doping of the channel region 103A on the side away from the effective channel 1041A.

[0087] Correspondingly, refer to Figure 14 If it is an N-type silicon-based device 100A, the doping concentration at the interface can be changed by doping donor atoms, such as phosphorus or arsenic, on the surface of the channel region 103A away from the effective channel 1041A; refer to Figure 15 If it is a P-type silicon-based device 100A, the doping concentration at the interface can be changed by doping acceptor atoms, such as boron, on the surface of the channel region 103A away from the effective channel 1041A.

[0088] Example 2 Coordination Figure 16 and Figure 17 The field-effect transistor device 100B also includes an insulating layer 40B disposed on the surface of the active layer 10B away from the effective channel 1041B. The conductive region A is formed on one side surface of the channel region by the injected charge in the insulating layer 40B through electrostatic induction.

[0089] Correspondingly, participants Figure 16 For N-type devices, this can be achieved by locally injecting positive charges, such as H+ or holes, into the insulating layer 40B; see reference. Figure 17, if it is a P-type device, it can be achieved by locally injecting negative charges such as F-, Cl-, electrons, etc. into the insulating layer 40B. By such a method, a high density of fixed charges is formed in the insulating layer 40B, and through electrostatic induction, carriers of the conductive region A are generated in the channel region 103B adjacent to the insulating layer 40B. It should be noted that the "local" here refers to a partial area in the insulating layer 40B corresponding to the part where the conductive region A needs to be formed in the channel region.

[0090] In the specific charge injection process, the charges can be injected into a position in the insulating layer 40B closer to the channel region 103B, so that the conductive region A formed in the channel region 103B can store more carriers. Of course, in some other alternative embodiments, a "double-insulating layer" structure can also be adopted, specifically including a charge trapping layer disposed on the surface of the channel region 103B and a conventional insulating layer covering the charge trapping layer. The charge trapping layer can adopt a material that is more likely to store charges or introduce metal or semiconductor nanoparticles therein to store charges more stably, so as to ensure the stable control of the carriers in the conductive region.

[0091] Embodiment 3 Refer to Figure 18 , the field effect transistor device 100C includes a semiconductor material layer 40C disposed on the active layer 10C. The semiconductor material layer 40C and the active layer 10C form a heterostructure, and the conductive region A is formed by a two-dimensional electron gas channel or a two-dimensional hole gas channel distributed in the heterostructure.

[0092] Specifically, the semiconductor material layer 40C and the active layer 10C have different bandgap widths. The semiconductor material layer 40C can be divided into two parts respectively connected to the source region 101C and the drain region 102C, so that the formed two-dimensional electron gas channel does not conduct the source and drain regions.

[0093] Of course, in some alternative embodiments, for example, the channel region 103C can be surface-treated to form a two-dimensional electron gas channel or a two-dimensional hole gas channel. These alternative embodiments of forming a two-dimensional electron gas channel or a two-dimensional hole gas channel known to those skilled in the art should all fall within the protection scope of this application. And the semiconductor material layer 40C mentioned here can be a barrier layer, and the barrier layer can be doped or intrinsic.

[0094] Embodiment 4 Refer to Figure 19, the field effect transistor device 100D is fabricated as a device having at least two gates. Specifically, the field effect transistor device 100D includes a first gate insulating layer 30D and a first gate 20D sequentially disposed on one surface of the active layer 10D, and a second gate insulating layer 40D and a second gate 50D sequentially disposed on one surface of the active layer 10D adjacent to the conductive region A.

[0095] The second gate 50D is correspondingly divided into two parts. One part has a vertical projection on the active layer 10D that connects to the source region 101D, and the other part has a vertical projection on the active layer 10D that connects to the drain region 102D. Thus, when appropriate bias voltages are applied to these two parts of the second gate 50D, conductive regions A that connect the source region 101D and the drain region 102D can be respectively formed at corresponding positions in the channel region 103D.

[0096] In this embodiment, the absolute value of the bias voltage applied to the second gate 50D should be greater than the absolute value of the turn-on voltage applied to the device. Correspondingly, if it is an N-type device, a positive bias voltage greater than the first gate 20D is applied to the second gate 50D; if it is a P-type device, a negative bias voltage with an absolute value greater than the first gate 20D is applied to the second gate 50D.

[0097] Embodiment 5 Refer Figure 20 , the field effect transistor device 100E is fabricated as a device having at least two gates similar to Embodiment 4. However, the difference is that in this embodiment, in order to make the conductance of the conductive region A greater than the conductance of the part 1042E of the channel 104E other than the effective channel 1041E, the first gate 20E and the second gate 50E made of gate materials with different work functions can be used. That is: it is achieved by making the work function difference between the first gate 20E and the active layer 10E and the work function difference between the second gate 50E and the active layer 10E not equal.

[0098] Correspondingly, for an N-type device, the first gate 20E can use a metal with a larger work function such as gold, platinum, or P-type doped (P+) polysilicon, or ITO, RuO2, WN, MoN, etc. with a larger work function obtained by adjusting the compound composition as the gate material; the second gate 50E can use a metal with a smaller work function such as aluminum, hafnium, titanium, or N-type doped (n+) polysilicon, or Ru-Hf, WN, HfN, TiN, TaN, TaSiN, etc. with a smaller work function obtained by adjusting the compound composition as the gate material. For a P-type device, the first gate 20E can use a metal with a smaller work function such as aluminum, hafnium, titanium, or N-type doped (n+) polysilicon, or Ru-Hf, WN, HfN, TiN, TaN, TaSiN, etc. with a smaller work function obtained by adjusting the compound composition as the gate material; the second gate 50E can use a metal with a larger work function such as gold, platinum, or P-type doped (P+) polysilicon, or ITO, RuO2, WN, MoN, etc. with a larger work function obtained by adjusting the compound composition as the gate material.

[0099] In an N-type device, the work function difference between the first gate 20E and the active layer 10E can also be set to be greater than zero (Φms>0V), so that the channel 104E is an enhancement-mode channel; at the same time, the work function difference between the second gate 50E and the active layer 10E is set to be less than zero (Φms<0V), so that a certain number of carriers can be formed in the conductive region A under the action of the bias voltage applied thereto when the device is in the off state. In a P-type device, the work function difference between the first gate 20E and the active layer can be set to be less than zero (Φms<0V), so that the channel 104E is an enhancement-mode channel; at the same time, the work function difference between the second gate 50E and the active layer 10E is set to be greater than zero (Φms>0V), so that a certain number of carriers can be formed in the conductive region A under the action of the bias voltage applied thereto when the device is in the off state.

[0100] Embodiment 6 Refer to Figure 21 , the field effect transistor device 100F is fabricated to include at least two gates 20F, 50F similar to Embodiment 4. However, the difference is that in this embodiment, in order to make the conductance of the conductive region A greater than the conductance of the part 1042F of the channel 104F except the effective channel 1041F, the capacitance per unit area of the second gate insulating layer 40F can be set to be greater than the capacitance per unit area of the first gate insulating layer 30F.

[0101] Specifically, it can be achieved by regulating the dielectric constants of the first gate insulating layer 30F and the second gate insulating layer 40F, or the thicknesses of the first gate insulating layer 30F and the second gate insulating layer 40F.

[0102] For example, when the thicknesses of the first gate insulating layer 30F and the second gate insulating layer 40F are equal, only the dielectric constant factor of the gate insulating layer needs to be considered, and it is only necessary to set the dielectric constant of the second gate insulating layer 40F to be higher than that of the first gate insulating layer 30F. Demonstratively, the first gate insulating layer 30F can be made of silicon dioxide, and the second gate insulating layer 40F can be made of a high-k dielectric such as hafnium dioxide, aluminum oxide, etc.

[0103] For another example, when the materials of the first gate insulating layer 30F and the second gate insulating layer 40F are the same, only the thickness factor of the gate insulating layer needs to be considered, and the thickness of the second gate insulating layer 40F is set to be less than that of the first gate insulating layer 30F.

[0104] In a specific device application, the second gate in the above Embodiments 4 to ⑥ can also be directly floating or grounded, so as to avoid increasing the complexity of device application due to excessive device connection terminals.

[0105] Moreover, the methods of forming the conductive regions in the above embodiments can also be applied in combination with each other to achieve better implementation effects.

[0106] The field effect transistor devices introduced in the above embodiments / mode of implementation can be planar structure devices or vertical structure devices. Hereinafter, taking a SOI device (TFT device) as an example, the specific settings of the solution of the present application when applied to a SOI device will be demonstrated.

[0107] Embodiment ⑦ Refer Figure 22 , to a planar top-gate structure TFT device 100G, which includes a light-transmissive insulating substrate 40G, and an active layer 10G, a gate dielectric layer 30G, and a gate 20G that are sequentially disposed on the substrate 40G. Source regions 101G and drain regions 102G are respectively doped on both sides of the active layer 10G, and source electrodes and drain electrodes are respectively externally connected; a channel region 103G is located between the source region ⑩1G and the drain region 102G.

[0108] On the substrate 40G, by means of ion implantation or the like, positive charge regions 60G are respectively formed on both sides of the source region 101G and the drain region 102G. There is an overlapping portion between the positive charge region ⑬G and the vertical projection of the gate 20G in the channel region 103G. Correspondingly, the positive charge region of this overlapping portion can form a two-dimensional electron gas 70G that is respectively connected to the source region 101G and the drain region 102G in the channel region 103G. Here, the two-dimensional electron gas 70G constitutes the conductive region.

[0109] When the device is turned on, a channel is formed under the gate 20G, and the portion of the channel whose vertical projection is located between the conductive regions constitutes the actual effective channel.

[0110] Example 8 Refer to Figure 23 , which is a planar bottom-gate structure TFT device 100H, and includes a light-transmitting insulating substrate 40H, and a gate electrode 20H, a gate dielectric layer 30H, and an active layer 10H sequentially disposed on the substrate 40H. In this embodiment, an upper-layer metal source electrode 501H and a metal drain electrode 502H are respectively disposed on both sides of the active layer 10H. The active layer 10H can adopt an amorphous IGZO metal oxide semiconductor layer, and an ohmic contact is formed between the source electrode 501H and the drain electrode 502H and the active layer 10H. The partial active layer below the source electrode 501H and the drain electrode 502H respectively constitutes a source region and a drain region, and the channel region is located between the source region and the drain region.

[0111] By ion implanting a positive charge region 60H that respectively connects the source electrode 501H and the drain electrode 502H in the passivation layer covered on the upper layer of the device. There is an overlapping portion between the positive charge region 60H and the vertical projection of the gate electrode 20H in the channel region. Correspondingly, the positive charge region of this overlapping portion can form a two-dimensional electron gas 70H that is respectively connected to the source region and the drain region in the channel region. Here, the two-dimensional electron gas 70H constitutes the conductive region.

[0112] When the device is turned on, a channel is formed above the gate electrode 20H, and the portion of the vertical projection in the channel between the conductive regions 70H constitutes the actual effective channel.

[0113] Example 9 Refer to Figure 24 , which is a vertical structure SOI device 100I, and includes a substrate 60I, a buried insulating layer 50I and an active layer 10I sequentially disposed on the substrate 60I, a gate insulating layer 30I and a gate electrode 20I disposed on one side of the active layer 10I. In the direction away from the substrate 60I, the source region 101I and the drain region 102I are respectively located below and above the active layer 10I. An equivalent source region 1051I connected to the source region 101I and an equivalent drain region 1052I connected to the drain region 102I are formed in the channel region 103I.

[0114] When a bias voltage is applied to the gate electrode 20I of the device to turn on the device, the gate electrode 20I controls a channel 104I connecting the source region 101I and the drain region 102I to be formed in the channel region 103I of the device. However, only the portion of the channel 104I that does not overlap between the vertical projections of the equivalent source region 1051I and the equivalent drain region 1052I in the channel region 103I constitutes the effective channel 1041I for transmitting the working current when the device is turned on. That is, the remaining portion 1042I in the channel 104I is not used to transmit the working current when the device is turned on.

[0115] In the above embodiments / examples, the source and drain regions in the device can be common heavily doped semiconductor sources and drains, or Schottky metal sources and drains of metal-semiconductor structures; the gate can be a common metal-insulator-semiconductor MOS structure gate, or a Schottky junction gate of a metal-semiconductor structure; the active layer can be composed of a single semiconductor material, or it can include at least two semiconductor materials that vary along its thickness direction or planar extension direction to form a composite channel.

[0116] Furthermore, the equivalent source region and equivalent drain region can be formed spontaneously or controlled by the gate structure of the corresponding structure.

[0117] In general, in the above embodiments, the vertical projection of the effective channel, equivalent source region, and / or equivalent drain region superimposed on the channel region connects the source and drain regions, thereby ensuring that carriers in the effective channel and the equivalent source and / or equivalent drain regions can be injected unidirectionally or bidirectionally at least in the thickness direction, and constructing a carrier path from the source region to the drain region. Of course, referring to... Figure 25 This application does not exclude the possibility that, in some particular embodiments, if the vertical projection of the effective channel, equivalent source region, and equivalent drain region superimposed on the channel region 103J does not connect the source region 101J and drain region 102J of the device 100J, but has an "appropriate gap" that does not completely cut off the flow of carriers from the equivalent source region 1051J to the effective channel 1041J and from the effective channel 1041J to the equivalent drain region 1052J, and the injection direction of carriers between the effective channel 1041J, the equivalent source region 1051J, and the equivalent drain region 1052J forms an angle with the thickness direction of the channel region 103J, such an implementation should also fall within the protection scope of this application.

[0118] The following are the results of Silvaco TCAD simulation verification using the SOI devices described in the above embodiments / exemplaries of this application. The gradual decrease in doping concentration in the channel region towards the effective channel is referred to as "forward doping," while the gradual increase in doping concentration in the channel region towards the effective channel is referred to as "reverse doping."

[0119] Simulation Example 1 In simulation example 1, the SOI device applying the above-described embodiments / exemplifications of this application is referred to as the "SOI device of this application". The SOI device of this application is forward-doped throughout the entire channel region, and the doping concentration follows an exponential distribution (exponential function y=a). xThe exponential factor a is selected as 1.5, 2, 3). As a comparison, there is a SOI device with a similar structure to the SOI device of this application, and the only difference is that the SOI device for comparison (referred to as the comparison SOI device in this simulation example) does not have the above-mentioned change in doping concentration (uniform doping).

[0120] Simulation parameters: The source and drain doping is N-type, and the doping concentration is 1E21 cm -3 , the channel doping is P-type, and the doping concentration is 1E17 cm -3 , the channel length L g is 130 nm, and the effective channel length L eff is 70 nm, and the equivalent source region L es and the equivalent drain region L ed both have a length of 30 nm,, the active layer thickness is 50 nm, the gate insulation layer thickness is 5 nm, and the fixed charge surface density at the interface forming the equivalent source region and the equivalent drain region is 1E14 cm -2 .

[0121] Parameter Figure 26 , is the comparison diagram of the transfer characteristics of the SOI device of this application and the comparison SOI device when the drain terminal voltage V d is 2V. It can be seen that the ability of the SOI device of this application to suppress the short-channel effect is stronger than that of the comparison SOI device, and the larger the exponential factor, the smaller the subthreshold swing, and the stronger the ability to suppress the short-channel effect.

[0122] Parameter Figure 27 , is the comparison diagram of the output characteristics of the SOI device of this application and the comparison SOI device when the gate terminal voltage V g is 2.5V. It can be seen that the larger the exponential factor of the SOI device of this application, the more it can improve the saturation voltage V dsat and the saturation current I dsat , while there will be a loss of the kink voltage and the output impedance R o .

[0123] Simulation example 2 In simulation example 2, the SOI device applying the above-mentioned embodiment / embodiment of this application is referred to as the "SOI device of this application". Among them, the SOI device of this application is doped forward in the entire channel region, and the doping concentration follows an exponential distribution (the exponential function y = a x in which the exponential factor a is selected as 2). The doping depths are 0.25 times, 0.5 times, 0.75 times and full-depth doping in the thickness direction of the channel region.

[0124] Simulation parameters: The source and drain doping is N-type, and the doping concentration is 1E2,1 cm -3 , the channel doping is P-type, and the doping concentration is 1E17 cm -3, channel length L g is 130 nm, effective channel length L eff is 70 nm, equivalent source region L es and equivalent drain region L ed both have a length of 30 nm, the active layer thickness is 50 nm, the gate insulation layer thickness is 5 nm, and the fixed charge surface density at the interface forming the equivalent source region and the equivalent drain region is 1E14 cm -2 .

[0125] Refer Figure 28 , is the transfer characteristic comparison diagram of the SOI device of this application at the drain terminal voltage V d being 2 V. It can be seen that after the doping depth of the SOI device of this application reaches more than 0.5 times the thickness of the channel region, the subthreshold swing is close. That is, when the doping depth is greater than or equal to 0.5 times the thickness of the channel region, the SOI device of this application can have better suppression ability for the short-channel effect.

[0126] Refer Figure 29 , is the output characteristic comparison diagram of the SOI device of this application at the gate terminal voltage V g being 2.5 V. It can be seen that when the doping depth of the SOI device of this application is less than 0.5 times the thickness of the channel region, the saturation voltage V dsat and the saturation current I dsat are almost lossless, but the kink voltage has an obvious loss.

[0127] Simulation Example 3 In Simulation Example 3, the SOI device applying the above-mentioned embodiments of this application is referred to as the "SOI device of this application". Among them, the SOI device of this application performs forward doping (FC.for) in the entire channel region, forward doping (Les.for) in the first region, forward doping (Led.for) in the second region, and forward doping (Leff.for) in the third region. The doping depth is the thickness of the entire channel region, and the doping concentration follows an exponential distribution (the exponential factor a in the exponential function y = a x is selected as 2). The SOI device for comparison is an SOI device with a similar structure to the SOI device of this application, and the difference is only that the SOI device for comparison (referred to as the comparison SOI device in this simulation example) does not have the above-mentioned change in doping concentration (uniform doping uniform).

[0128] Simulation parameters: The source-drain doping is N-type, and the doping concentration is 1E21 cm -3 , the channel doping is P-type, and the doping concentration is 1E17 cm -3 , channel length L g is 130 nm, effective channel length L eff is 70 nm, equivalent source region Les and the equivalent drain region L ed both have a length of 30 nm, the active layer thickness is 50 nm, the gate insulation layer thickness is 5 nm, and the fixed charge surface density at the interface forming the equivalent source region and the equivalent drain region is 1E14 cm -2 .

[0129] Refer Figure 30 , which is the comparison diagram of the transfer characteristics of the SOI device of the present application and the comparative SOI device at the drain terminal voltage V d being 2V. It can be seen that when doping is carried out throughout the channel and forward doping is carried out in the third region in the SOI device of the present application, the ability to suppress the short-channel effect is the strongest.

[0130] Refer Figure 31 , which is the comparison diagram of the output characteristics of the SOI device of the present application and the comparative SOI device at the gate terminal voltage V g being 2.5V. It can be seen that when doping is carried out throughout the channel in the SOI device of the present application, the saturation voltage V dsat and the saturation current I dsat can be improved, and a larger kink voltage and output impedance R o are obtained.

[0131] Simulation Example 4 In Simulation Example 4, the SOI device applying the above-mentioned embodiment / embodiment of the present application is referred to as the "SOI device of the present application". Among them, the SOI device of the present application performs forward doping (for) and reverse doping (rev) in the first region and the third region near one end of the equivalent source region far from the source electrode region respectively (the doping region covers one end of the equivalent source region far from the source electrode region), the doping depth is 0.75 times the thickness of the channel region, and the doping concentration follows an exponential distribution (the exponential factor a in the exponential function y = a x is selected as 2). As a comparison, there is a SOI device with a similar structure to the SOI device of the present application, and the difference is only that the comparative SOI device (referred to as the comparative SOI device in this simulation example) does not have the above-mentioned change in doping concentration (uniform doping uniform).

[0132] Simulation parameters: The source-drain doping is N-type, the doping concentration is 1E21 cm -3 , the channel doping is P-type, the doping concentration is 1E17 cm -3 , the channel length L g is 130 nm, the effective channel length L eff is 70 nm, the equivalent source region L es and the equivalent drain region L ed both have a length of 30 nm, the active layer thickness is 50 nm, the gate insulation layer thickness is 5 nm, and the fixed charge surface density at the interface forming the equivalent source region and the equivalent drain region is 1E14 cm-2 。

[0133] Refer to Figure 32 , which is the comparison chart of the transfer characteristics of the SOI device of this application and the comparative SOI device when the drain terminal voltage V d is 2V. It can be seen that when the first region and the third region near one end of the equivalent source region far from the source electrode region in the SOI device of this application are doped forward, the ability to suppress the short-channel effect is the strongest; while reverse doping in the corresponding region fails to improve the ability to suppress the short-channel effect of the device compared with forward doping and uniform doping.

[0134] Refer to Figure 33 , which are the comparison charts of the output characteristics of the SOI device of this application and the comparative SOI device when the gate terminal voltage V g is 2.5V. It can be seen that when the first region and the third region near one end of the equivalent source region far from the source electrode region in the SOI device of this application are doped forward, a larger kink voltage can be obtained while hardly losing the saturation voltage V d sat, the saturation current Idsat and the output impedance Ro; while reverse doping in the corresponding region will result in a greater loss of the saturation voltage V dsat and the saturation current I dsat .

[0135] Simulation Example 5 In Simulation Example 5, the SOI device applying the above-mentioned embodiment / embodiments of this application is referred to as the "SOI device of this application". Among them, the SOI device of this application respectively: ① Forward doping is carried out at 1 / 2 depth in the direction of the effective channel length in the third region adjacent to the drain region and reverse doping is carried out in the second region (left65.for_right65.rev), ② Reverse doping is carried out in the second region (left100.for_right30.rev), ③ Reverse doping is carried out at 2 / 3 depth in the direction of the effective channel length in the second region adjacent to the drain region (left110.for_right20.rev). The doping depth is 0.75 times the thickness of the channel region, and the doping concentration follows an exponential distribution (the exponential factor a in the exponential function y = a x is selected as 2). The comparative device is an SOI device with a similar structure to the SOI device of this application, and the only difference is that the comparative SOI device (referred to as the comparative SOI device in this simulation example) does not have the above-mentioned change in doping concentration (uniform doping uniform).

[0136] Simulation parameters: The source-drain doping is N-type, and the doping concentration is 1E21 cm -3 , the channel doping is P-type, and the doping concentration is 1E17 cm -3 , the channel length L gis 130nm, and the effective channel length L eff is 70nm, and the equivalent source region length L es and the equivalent drain region length L ed are both 30nm, the thickness of the active layer is 50nm, the thickness of the gate insulating layer is 5nm, and the surface charge density of fixed charges at the interface forming the equivalent source region and the equivalent drain region is 1E14 cm -2 .

[0137] Refer Figure 34 , which is a comparison chart of the transfer characteristics of the SOI device of this application and the comparative SOI device when the drain terminal voltage V d is 2V. It can be seen that when doping ② and ③ in the SOI device of this application, the ability to suppress the short-channel effect is the strongest.

[0138] Refer Figure 35 , which is a comparison chart of the output characteristics of the SOI device of this application and the comparative SOI device when the gate terminal voltage V g is 2.5V. It can be seen that in the SOI device of this application, when doping ② and ③ as above, compared with uniform doping, the saturation voltage V dsat and the saturation current I dsat can be obtained with a larger kink voltage and output impedance R o without almost any loss.

[0139] Simulation Example 6 In Simulation Example 6, the SOI device applying the above-mentioned embodiments of this application is referred to as the "SOI device of this application". Among them, the SOI device of this application is respectively: ① The first region and the third region are doped reversely and the second region is doped forwardly (leftrev_ledfor), ② The first region and the third region are doped forwardly and the second region is doped reversely (leftfor_ledrev), ③ The first region, the second region and the third region are all doped forwardly (FC.for). The doping depths of doping ① and ② are 0.75 times the thickness of the channel region, and the doping depth of doping ③ is the thickness of the entire channel region, and the doping concentration follows an exponential distribution (the exponential factor a in the exponential function y = a x is selected as 2). As a comparison, there is a SOI device with a similar structure to the SOI device of this application, and the only difference is that the comparative SOI device (referred to as the comparative SOI device in this simulation example) does not have the above-mentioned change in doping concentration (uniform doping uniform).

[0140] Simulation parameters: The source-drain doping is N-type, the doping concentration is 1E21 cm -3 , the channel doping is P-type, the doping concentration is 1E17 cm -3 , the channel length L g is 130nm, and the effective channel length L​is 70 nm, the equivalent source region L es and the equivalent drain region L ed both have a length of 30 nm, the active layer thickness is 50 nm, the gate insulation layer thickness is 5 nm, and the fixed charge surface density at the interface forming the equivalent source region and the equivalent drain region is 1E14 cm -2 .

[0141] Refer Figure 36 , which is a comparison graph of the transfer characteristics of the SOI device of this application and the comparative SOI device when the drain terminal voltage V d is 2 V. It can be seen that in the SOI device of this application when doped as above in ② and ③, it has a better subthreshold swing compared to uniform doping, indicating an improved ability to suppress the short-channel effect; while when doped as above in ①, the subthreshold swing is worse than that of uniform doping.

[0142] Refer Figure 37 , which is a comparison graph of the output characteristics of the SOI device of this application and the comparative SOI device when the gate terminal voltage V g is 2.5 V. It can be seen that in the SOI device of this application when doped as above in ② and ③, it can improve the saturation voltage V d sat, saturation current Idsat compared to uniform doping, and obtain a larger kink voltage and output impedance Ro, and the improvement of doping ② is more significant than that of doping ③; while when doped as above in ①, although it can improve the saturation voltage V dsat , saturation current I dsat to a certain extent compared to uniform doping, but it loses a larger kink voltage and output impedance R o .

[0143] Simulation Example 7 In Simulation Example 7, the SOI device applying the above-mentioned embodiments of this application is referred to as the "SOI device of this application". The SOI device of this application is divided into: ① In the direction from the source region to the drain region, the doping concentration in the third region gradually decreases (Hor.linear.dec), ② In the direction from the source region to the drain region, the doping concentration in the third region gradually increases (Hor.linear.inc), and the doping concentration follows an exponential distribution (the exponential factor a in the exponential function y = a x is selected as 2). As a comparison, there is a SOI device with a similar structure to the SOI device of this application, and the only difference is that the comparative SOI device (referred to as the comparative SOI device in this simulation example) does not have the above-mentioned change in doping concentration (uniform doping uniform).

[0144] Simulation parameters: The source-drain doping is N-type, the doping concentration is 1E21 cm -3 , the channel doping is P-type, and the doping concentration is 1E17 cm-3 , the channel length L g is 130 nm, the effective channel length L eff is 70 nm, the equivalent source region length L es and the equivalent drain region length L ed are both 30 nm. The active layer thickness is 50 nm, the gate insulation layer thickness is 5 nm, and the fixed charge surface density at the interface forming the equivalent source region and the equivalent drain region is 1E14 cm -2 .

[0145] Refer Figure 38 , this is the comparison graph of the transfer characteristics of the SOI device of this application and the comparative SOI device at the drain terminal voltage V d being 2 V. It can be seen that when the SOI device of this application is doped with ① and ② above, the ability to suppress the short-channel effect is improved, and the suppression ability is stronger when doped with ①.

[0146] Refer Figure 39 , this is the comparison graph of the output characteristics of the SOI device of this application and the comparative SOI device at the gate terminal voltage V g being 2.5 V. It can be seen that when the SOI device of this application is doped with ① and ② above, it will lose the saturation voltage V dsat , saturation current I dsat compared with uniform doping, but a larger kink voltage can be obtained. At the same time, the kink voltage and output impedance R o of doping ① are higher than those of doping ②.

[0147] It should be understood that although terms such as first and second can be used in this article to describe various elements or structures, the described objects should not be limited by these terms. These terms are only used to distinguish these described objects from each other. For example, the first channel can be called the second channel, and similarly the second channel can also be called the first channel, which does not depart from the protection scope of this application.

[0148] Moreover, the same reference numerals or marks may be used in different embodiments, but this does not represent a structural or functional connection, but is only for the convenience of description.

[0149] The terms used in this invention, such as “above,” “over,” “below,” and “under,” indicating spatial relative position, are for illustrative purposes to describe the relationship of one unit or feature relative to another unit or feature as shown in the accompanying drawings. These terms may be intended to include different orientations of the device in use or operation other than those shown in the figures. For example, if the device in the figures is flipped, a unit described as being “below” or “under” other units or features would be located “above” other units or features. Therefore, the exemplary term “under” can encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or otherwise) and the spatially related descriptive terms used in this invention will be interpreted accordingly.

[0150] When a component or layer is referred to as being "on" or "connected" to another component or layer, it can be directly on or connected to that other component or layer, or there can be intermediate components or layers. Conversely, when a component is referred to as being "directly on" or "directly connected to" another component or layer, there cannot be intermediate components or layers.

[0151] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0152] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style of the specification is merely for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A non-uniformly doped field effect transistor device comprising an active layer, characterized in that, The active layer includes a source region, a drain region, and a channel region located between the source region and the drain region. When the device is turned on, an effective channel is formed in the channel region, and an equivalent source region and / or equivalent drain region are formed at least in the thickness direction of the channel region away from the effective channel. The field-effect transistor device connects the source region and the drain region through the effective channel, the equivalent source region and the equivalent drain region to contribute the operating current. A conductive region that does not connect the source region and the drain region is formed in the channel region. When the conductive region is connected to the source region, the conductive region constitutes the equivalent source region. When the conductive region is connected to the drain region, the conductive region constitutes the equivalent drain region. When the device is turned on, the conductivity of the conductive region is greater than the conductivity of the rest of the channel except for the effective channel, so that at least one of the conductive region and the effective channel can inject carriers into the other. Specifically, in the direction of the channel region near the effective channel: The doping concentration in at least a portion of the first region gradually decreases; and / or, In the second region, the doping concentration gradually increases in at least a portion; and / or, In the third region, the doping concentration gradually decreases in at least a portion; and / or, In the direction from the source region to the drain region: The doping concentration in at least a portion of the third region gradually decreases; The first region is the region in the channel region corresponding to the equivalent source region, the second region is the region in the channel region corresponding to the equivalent drain region, and the third region is the region in the channel region corresponding to the effective channel.

2. The non-uniformly doped field-effect transistor device according to claim 1, characterized in that, In the direction of the effective channel in the channel region: The doping concentration gradually decreases in the third region and the first region, while the doping concentration gradually increases in the second region; or, The doping concentration gradually decreases in the third region and the first region, while the second region is uniformly doped; or, The doping concentration gradually decreases in the third region, while the first and second regions are uniformly doped; or, The doping concentration gradually decreases in the third region, the first region, and the second region; or, The third region is uniformly doped, the doping concentration in the first region gradually decreases, and the doping concentration in the second region gradually increases; or, The third region and the first region are uniformly doped, and the doping concentration in the second region gradually increases; or, The third region and the second region are uniformly doped, while the doping concentration in the first region gradually decreases.

3. The non-uniformly doped field-effect transistor device according to claim 1, characterized in that, The doping concentration in the first, second, and third regions varies according to one of the following distributions: linear, exponential, Gaussian, or residual error.

4. The non-uniformly doped field-effect transistor device according to claim 3, characterized in that, The active layer includes a first gate disposed on one side surface, wherein the first gate and the conductive region overlap in their vertical projections onto the channel region; wherein the first gate controls the channel region and forms the channel therein, and the portion of the channel that does not overlap with the vertical projection of the conductive region onto the channel region constitutes the effective channel.

5. The field-effect transistor device according to claim 4, characterized in that, The conductivity of the conductive region is at least three times greater than the conductivity of the remaining portion of the channel excluding the effective channel; And / or, the field-effect transistor device is a planar structure device or a vertical structure device.

6. The non-uniformly doped field-effect transistor device according to claim 4, characterized in that, When the device is turned on, the conductance per unit length of the effective channel in the channel is less than the conductance per unit length of the remaining portion of the channel excluding the effective channel.

7. The non-uniformly doped field-effect transistor device according to claim 4, characterized in that, When the field-effect transistor device is an N-type device, the work function of the portion of the first gate corresponding to the effective channel is greater than the work function of the remaining portion of the first gate. When the field-effect transistor device is a P-type device, the work function of the portion of the first gate corresponding to the effective channel is less than the work function of the remaining portion of the first gate; and / or, The field-effect transistor device includes a gate insulating layer disposed between the first gate and the channel region, wherein the thickness of the portion of the gate insulating layer corresponding to the effective channel is greater than the thickness of the remaining portion of the gate insulating layer; and / or, The field-effect transistor device includes a gate insulating layer disposed between the first gate and the channel region, wherein the dielectric constant of the portion of the gate insulating layer corresponding to the effective channel is greater than the dielectric constant of the remaining portion of the gate insulating layer.

8. The non-uniformly doped field-effect transistor device according to any one of claims 4 to 7, characterized in that, It also includes a second gate disposed on the surface of the active layer adjacent to the conductive region, the second gate being capable of controlling the formation of the conductive region in the channel region; and / or, The conductive region is formed by carriers introduced by doping on the surface of the channel region on the side away from the effective channel; and / or, It also includes an insulating layer disposed on the surface of the active layer away from the effective channel, wherein the conductive region is composed of charge carriers generated by electrostatic induction in the channel region near the insulating layer by injected charges in the insulating layer; and / or, It also includes a semiconductor material layer disposed on the surface of the active layer away from the effective channel, the active layer and the semiconductor material layer forming a heterostructure, and the conductive region being composed of two-dimensional electron gas channels or two-dimensional hole gas channels distributed in the heterostructure; and / or, The conductive region is formed by surface treatment of the side of the channel region away from the effective channel, creating a two-dimensional electron gas channel or a two-dimensional hole gas channel.

9. A non-uniformly doped field-effect transistor device, comprising an active layer, characterized in that, The active layer includes a source region, a drain region, and a channel region located between the source region and the drain region. When the device is turned on, an effective channel is formed in the channel region, and an equivalent source region and / or equivalent drain region are formed at least in the thickness direction of the channel region away from the effective channel. The field-effect transistor device connects the source region and the drain region through the effective channel, the equivalent source region and the equivalent drain region to contribute the operating current. A conductive region that does not connect the source region and the drain region is formed in the channel region. When the conductive region is connected to the source region, the conductive region constitutes the equivalent source region. When the conductive region is connected to the drain region, the conductive region constitutes the equivalent drain region. When the device is turned on, the conductivity of the conductive region is greater than the conductivity of the rest of the channel except for the effective channel, so that at least one of the conductive region and the effective channel can inject carriers into the other. Wherein, at least a portion of the channel region is non-uniformly doped to form a built-in electric field within the channel region that guides the movement of charge carriers from the equivalent source region to the effective channel, and / or a built-in electric field that guides the movement of charge carriers from the effective channel to the equivalent drain region.

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