An epitaxial wafer for a light-emitting diode and its fabrication method, LED

Abstract

This invention provides a light-emitting diode epitaxial wafer and its fabrication method, as well as an LED. The light-emitting diode epitaxial wafer includes a substrate and a first semiconductor layer, an active layer, and a second semiconductor layer sequentially deposited on the substrate. The active layer includes M periodically alternating potential well layers and a composite barrier layer. The composite barrier layer includes a first polarization control layer, a first barrier sublayer, a second barrier sublayer, and a second polarization control layer sequentially stacked along the epitaxial direction. The first polarization control layer is a Si-doped InGaN layer, the first barrier sublayer is a BinGaN layer, the second barrier sublayer is a BGaN layer, and the second polarization control layer is a Si-doped GaN layer. The light-emitting diode epitaxial wafer of this invention can solve the problem of lattice mismatch between the potential well layer and the composite barrier layer, which leads to a huge piezoelectric field in the InGaN potential well layer. It also enhances the barrier's ability to confine injected carriers, prevents electron overflow, effectively suppresses the LED efficiency droop effect, and improves the luminous efficiency of the light-emitting diode.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a light-emitting diode epitaxial wafer and its preparation method, and LED. Background Technology

[0002] Semiconductor light-emitting diodes can convert electrical energy into light energy. As a solid-state light source, light-emitting diodes have the characteristics of relatively low energy consumption, fast response and small size. They can be used in many scenarios such as general lighting and backlighting. With its high luminous efficiency, light-emitting diodes have gradually replaced traditional lighting sources and become the new generation of light source, triggering a new lighting revolution.

[0003] The recombination efficiency of electrons and holes in the active layer is closely related to the luminous efficiency of a light-emitting diode (LED). The active layer consists of a potential well and a barrier layer. To improve the wave function coupling between electrons and holes, reduce electron overflow into the P-type layer, and improve the uniform distribution of electrons and holes in the active layer, the barrier layer is usually made of AlGaN material.

[0004] In existing technologies, using AlGaN as the barrier layer has the following drawbacks: First, the quality of AlGaN material is poor. Due to the high bond energy of Al atoms, it is very difficult for Al atoms to migrate on the surface of the epitaxial layer during AlGaN growth, resulting in poor film quality. Second, a quantum confinement Stark effect (QCSE) occurs between the potential well layer and the barrier layer. The high In content in the InGaN potential well increases the lattice mismatch between it and the AlGaN barrier layer, leading to a huge piezoelectric field in the InGaN potential well, thus generating the so-called quantum confinement Stark effect (QCSE). The QCSE effect reduces the coupling between the electron and hole wave functions in the quantum well, thereby reducing the quantum efficiency of the LED. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this invention is to provide a light-emitting diode epitaxial wafer, which aims to solve the two technical problems mentioned in the background art above.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solution:

[0007] An epitaxial wafer for a light-emitting diode includes a substrate and a first semiconductor layer, an active layer, and a second semiconductor layer sequentially deposited on the substrate. The active layer includes M periodically alternating potential well layers and a composite barrier layer. The composite barrier layer includes a first polarization control layer, a first barrier sublayer, a second barrier sublayer, and a second polarization control layer sequentially stacked along the epitaxial direction. The first polarization control layer is a Si-doped InGaN layer, the first barrier sublayer is a BinGaN layer, the second barrier sublayer is a BGaN layer, and the second polarization control layer is a Si-doped GaN layer. The Si doping concentration in the first polarization control layer is 1E+17 atoms / cm². 3 ~1E+19atoms / cm 3 The Si doping concentration in the second polarization control layer is 1E+17 atoms / cm². 3 ~1E+19atoms / cm 3 .

[0008] Furthermore, the thickness of the first polarization control layer ranges from 0.5 nm to 5 nm, the thickness of the first barrier sublayer ranges from 1 nm to 10 nm, the thickness of the second barrier sublayer ranges from 1 nm to 10 nm, and the thickness of the second polarization control layer ranges from 0.5 nm to 5 nm.

[0009] Understandably, in the first polarization control layer SiInGaN layer and the second polarization control layer SiGaN layer, an appropriate thickness reduces the polarization effect of the active layer. If the thickness is too thick, it will lead to an increase in the polarization of the active layer. In the first barrier sublayer BInGaN layer and the second barrier sublayer BGaN layer, an appropriate thickness generates a sufficient barrier to allow carriers to recombine in the active layer. If the thickness is too thick, it will cause the spatial function of electrons and holes to separate, and the recombination efficiency will decrease.

[0010] Furthermore, the composition range of In element in the first polarization control layer is 0.01~0.1, the composition range of B element in the first barrier sublayer is 0.05~0.5, the composition range of In element is 0.01~0.1, and the composition range of B element in the second barrier sublayer is 0.05~0.5.

[0011] Understandably, the Si in the first and second polarization control layers SiInGaN can generate an electric field, reducing the polarization effect of the active layer. The In composition of the first polarization control layer reduces the lattice mismatch between the barrier layer and the InGaN well layer, improving crystal quality. In the first and second barrier sub-layers BInGaN, the B composition can increase the barrier height, improve the uniform distribution of electrons and holes in the active layer, and improve recombination efficiency. However, if the B composition is too high, the barrier height will be too high, increasing the operating voltage of the light-emitting diode. The appropriate In composition of the first barrier sub-layer BInGaN is used to modulate the energy band and reduce the polarization effect of the barrier layer.

[0012] Furthermore, the period M of the alternating arrangement of the potential well layer and the composite barrier layer ranges from 1 to M to 20.

[0013] Understandably, the active region is the area where electrons and holes recombine. A reasonable structural design can significantly increase the overlap of electron and hole wave functions, thereby improving the luminous efficiency of LED devices.

[0014] Furthermore, the first semiconductor layer includes a buffer layer, an undoped GaN layer, and an N-type GaN layer sequentially deposited on the substrate, and the second semiconductor layer includes an electron blocking layer and a P-type GaN layer sequentially deposited on the active layer.

[0015] Furthermore, the present invention also provides a method for preparing a light-emitting diode epitaxial wafer, for preparing the light-emitting diode epitaxial wafer as described above, comprising the following steps:

[0016] Provide a substrate;

[0017] A first semiconductor layer is deposited on the substrate;

[0018] M cycles of potential well layers and composite barrier layers are alternately stacked on the first semiconductor layer to form an active layer. The composite barrier layer includes a first polarization control layer, a first barrier sub-layer, a second barrier sub-layer, and a second polarization control layer stacked sequentially along the epitaxial direction. The first polarization control layer is a Si-doped InGaN layer, the first barrier sub-layer is a BInGaN layer, the second barrier sub-layer is a BGaN layer, and the second polarization control layer is a Si-doped GaN layer.

[0019] A second semiconductor layer is deposited on the composite barrier layer in the last cycle.

[0020] Furthermore, the growth temperature range of the composite barrier layer is 800℃~1000℃, the ratio of N2 / H2 / NH3 in the growth atmosphere of the composite barrier layer is 1:1:1~1:10:20, and the growth pressure range of the composite barrier layer is 50 torr~300 torr.

[0021] Furthermore, the potential well layer is an InGaN layer, the growth temperature range of the potential well layer is 700℃~900℃, the thickness range of the potential well layer is 1nm~10nm, the growth pressure range of the potential well layer is 50torr~500torr, and the In element composition range of the potential well layer is 0.01~0.5.

[0022] Furthermore, the specific steps of depositing the first semiconductor layer on the substrate include:

[0023] A buffer layer, an undoped GaN layer, and an N-type GaN layer are sequentially deposited on the substrate to form the first semiconductor layer;

[0024] The specific steps for depositing a second semiconductor layer on the composite barrier layer in the last cycle include:

[0025] An electron blocking layer and a P-type GaN layer are sequentially deposited on the composite barrier layer in the last cycle to form the second semiconductor layer.

[0026] Furthermore, the present invention also provides an LED, including the light-emitting diode epitaxial wafer as described above.

[0027] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0028] First, the significant lattice mismatch between the InGaN potential well layer and the barrier layer leads to a large piezoelectric field in the InGaN potential well layer. The deposition of the first polarization control layer (Si-doped InGaN) and the second polarization control layer (Si-doped GaN) with Si elements generates an electric field that balances the piezoelectric field of the InGaN potential well layer, reducing the quantum confinement Stark effect of the potential well layer, increasing the overlap of the electron and hole space wave functions, and improving the luminous efficiency of the light-emitting diode. Second, AlGaN is generally used as the barrier layer because its large polarization effect and poor crystal quality affect… The luminous efficiency is improved by depositing the first barrier sublayer (BInGaN layer) and the second barrier sublayer (BGaN layer). By reducing the Al-free component, the polarization effect of the barrier layer caused by the barrier material is reduced. By using BInGaN with a reasonable composition ratio as the quantum well barrier material, lattice matching can be achieved and piezoelectric polarization in the quantum well can be eliminated. The band gap width of the BInGaN / BGaN material is increased, thereby enhancing the barrier's ability to confine injected carriers, preventing electron overflow, effectively suppressing the LED efficiency droop effect, and improving the luminous efficiency of the light-emitting diode. Attached Figure Description

[0029] The described and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments in conjunction with the accompanying drawings, wherein:

[0030] Figure 1 This is a schematic diagram of the layered structure of the light-emitting diode epitaxial wafer in Embodiments 1 and 2 of the present invention;

[0031] Figure 2 This is a flowchart of the method for preparing the epitaxial wafer of a light-emitting diode in Embodiment 3 of the present invention;

[0032] Explanation of key component symbols:

[0033] 100, Substrate; 200, Buffer layer; 300, Undoped GaN layer; 400, N-type GaN layer; 500, Active layer; 510, Potential well layer; 520, Composite barrier layer; 521, First polarization control layer; 522, First barrier sublayer; 523, Second barrier sublayer; 524, Second polarization control layer; 600, Electron blocking layer; 700, P-type GaN layer.

[0034] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0035] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the invention will be thorough and complete.

[0036] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0038] Example 1

[0039] Please see Figure 1 The image shows a light-emitting diode epitaxial wafer according to a first embodiment of the present invention, including a substrate 100, and a first semiconductor layer, an active layer 500, and a second semiconductor layer sequentially deposited on the substrate 100. The active layer 500 includes M periodically alternating potential well layers 510 and a composite barrier layer 520. The composite barrier layer 520 includes a first polarization control layer 521, a first barrier sub-layer 522, a second barrier sub-layer 523, and a second polarization control layer 524 sequentially stacked along the epitaxial direction. The first polarization control layer is a Si-doped InGaN layer, the first barrier sub-layer is a BinGaN layer, the second barrier sub-layer is a BGaN layer, and the second polarization control layer is a Si-doped GaN layer.

[0040] Understandably, firstly, the significant lattice mismatch between the InGaN well layer and the barrier layer leads to a large piezoelectric field in the InGaN well layer. The deposition of the first polarization control layer (Si-doped InGaN) and the second polarization control layer (Si-doped GaN) with Si elements generates an electric field that balances the piezoelectric field of the InGaN well layer, reducing the quantum confinement Stark effect of the 510 well layer, increasing the overlap of the electron and hole space wave functions, and improving the luminous efficiency of the LED. Secondly, AlGaN is generally used as the barrier layer because of its larger polarization effect and crystal quality. Poor performance affects luminous efficiency. However, by depositing a first barrier sublayer (BInGaN layer) and a second barrier sublayer (BGaN layer), the polarization effect caused by the barrier material is reduced by decreasing the Al-free component. By using BInGaN with a rationally designed composition ratio as the quantum well barrier material, lattice matching can be achieved and piezoelectric polarization in the quantum well can be eliminated. This increases the band gap width of the BInGaN / BGaN material, thereby enhancing the barrier's ability to confine injected carriers, preventing electron overflow, effectively suppressing the LED efficiency droop effect, and improving the luminous efficiency of the light-emitting diode.

[0041] Preferably, in this embodiment, the thickness of the first polarization control layer 521 is in the range of 0.5nm to 5nm, the thickness of the first barrier sublayer 522 is in the range of 1nm to 10nm, the thickness of the second barrier sublayer 523 is in the range of 1nm to 10nm, and the thickness of the second polarization control layer 524 is in the range of 0.5nm to 5nm.

[0042] The Si doping concentration in the first polarization control layer 521 is 1E+17 atoms / cm 3 ~1E+19atoms / cm 3 The composition of In element ranges from 0.01 to 0.1. In the first barrier sublayer 522, the composition of B element ranges from 0.05 to 0.5, and the composition of In element ranges from 0.01 to 0.1. In the second barrier sublayer 523, the composition of B element ranges from 0.05 to 0.5. In the second polarization control layer 524, the Si doping concentration is 1E+17 atoms / cm². 3 ~1E+19atoms / cm 3 .

[0043] The period M of the alternating arrangement of the potential well layer 510 and the composite barrier layer 520 has a range of values: 1≤M≤20.

[0044] Specifically, in this embodiment, the first semiconductor layer includes a buffer layer 200, an undoped GaN layer 300, and an N-type GaN layer 400 sequentially deposited on the substrate 100, and the second semiconductor layer includes an electron blocking layer 600 and a P-type GaN layer 700 sequentially deposited on the active layer 500.

[0045] This invention also provides several preferred experimental groups:

[0046] In Experiment 1, the thickness of the first polarization control layer was 1.5 nm, the thickness of the first barrier sublayer was 5 nm, the thickness of the second barrier sublayer was 4 nm, the thickness of the second polarization control layer was 1 nm, and the Si doping concentration in the first polarization control layer was 7E+17 atoms / cm². 3 The In element composition is 0.05; the B element composition in the first barrier sublayer is 0.1 and the In element composition is 0.05; the B element composition in the second barrier sublayer is 0.1; and the Si doping concentration in the second polarization control layer is 8E+17 atoms / cm². 3 The number of cycles for the active layer stack is 10.

[0047] In Experiment 2, the thickness of the first polarization control layer was 1 nm, the thickness of the first barrier sublayer was 6 nm, the thickness of the second barrier sublayer was 4 nm, the thickness of the second polarization control layer was 0.5 nm, and the Si doping concentration in the first polarization control layer was 7E+17 atoms / cm². 3 The indium (In) content is 0.05; the boron (B) content in the first barrier sublayer is 0.1 and the indium (In) content is 0.05; the boron (B) content in the second barrier sublayer is 0.1; and the Si doping concentration in the second polarization control layer is 8E+17 atoms / cm². 3 The number of cycles for the active layer stack is 10.

[0048] In Experiment 3, the thickness of the first polarization control layer was 2 nm, the thickness of the first barrier sublayer was 6 nm, the thickness of the second barrier sublayer was 3 nm, and the thickness of the second polarization control layer was 1 nm. The Si doping concentration in the first polarization control layer was 7E+17 atoms / cm². 3 The indium (In) content is 0.05; the boron (B) content in the first barrier sublayer is 0.1 and the indium (In) content is 0.05; the boron (B) content in the second barrier sublayer is 0.1; and the Si doping concentration in the second polarization control layer is 8E+17 atoms / cm². 3 The number of cycles for the active layer stack is 10.

[0049] In Experiment 4, the thickness of the first polarization control layer was 1.5 nm, the thickness of the first barrier sublayer was 5 nm, the thickness of the second barrier sublayer was 4 nm, the thickness of the second polarization control layer was 1 nm, and the Si doping concentration in the first polarization control layer was 3E+17 atoms / cm². 3 The In element composition is 0.03, the B element composition in the first barrier sublayer is 0.2 and the In element composition is 0.07, the B element composition in the second barrier sublayer is 0.1, and the Si doping concentration in the second polarization control layer is 8E+17 atoms / cm². 3 The number of cycles for the active layer stack is 10.

[0050] In experimental group five, the thickness of the first polarization control layer was 1.5 nm, the thickness of the first barrier sublayer was 5 nm, the thickness of the second barrier sublayer was 4 nm, the thickness of the second polarization control layer was 1 nm, and the Si doping concentration in the first polarization control layer was 1E+18 atoms / cm². 3 The in element composition is 0.08; the boron composition in the first barrier sublayer is 0.1 and the in element composition is 0.03; the boron composition in the second barrier sublayer is 0.1; and the Si doping concentration in the second polarization control layer is 5E+17 atoms / cm². 3 The number of cycles for the active layer stack is 10.

[0051] In Experiment 6, the thickness of the first polarization control layer was 1.5 nm, the thickness of the first barrier sublayer was 5 nm, the thickness of the second barrier sublayer was 4 nm, the thickness of the second polarization control layer was 1 nm, and the Si doping concentration in the first polarization control layer was 7E+17 atoms / cm². 3 The indium (In) content is 0.05; the boron (B) content in the first barrier sublayer is 0.1 and the indium (In) content is 0.05; the boron (B) content in the second barrier sublayer is 0.2; and the Si doping concentration in the second polarization control layer is 1E+18 atoms / cm². 3 The number of cycles for the active layer stack is 10.

[0052] In Experiment 7, the thickness of the first polarization control layer was 1.5 nm, the thickness of the first barrier sublayer was 5 nm, the thickness of the second barrier sublayer was 4 nm, the thickness of the second polarization control layer was 1 nm, and the Si doping concentration in the first polarization control layer was 7E+17 atoms / cm². 3 The In element composition is 0.05; the B element composition in the first barrier sublayer is 0.1 and the In element composition is 0.05; the B element composition in the second barrier sublayer is 0.05; and the Si doping concentration in the second polarization control layer is 8E+17 atoms / cm². 3 The number of cycles for the active layer stack is 10.

[0053] In experimental group eight, the thickness of the first polarization control layer was 1.5 nm, the thickness of the first barrier sublayer was 5 nm, the thickness of the second barrier sublayer was 4 nm, the thickness of the second polarization control layer was 1 nm, and the Si doping concentration in the first polarization control layer was 7E+17 atoms / cm². 3 The indium (In) content is 0.05; the boron (B) content in the first barrier sublayer is 0.1 and the indium (In) content is 0.05; the boron (B) content in the second barrier sublayer is 0.1; and the Si doping concentration in the second polarization control layer is 8E+17 atoms / cm². 3 The number of cycles for the active layer stack is 5.

[0054] In experimental group nine, the thickness of the first polarization control layer was 1.5 nm, the thickness of the first barrier sublayer was 5 nm, the thickness of the second barrier sublayer was 4 nm, the thickness of the second polarization control layer was 1 nm, and the Si doping concentration in the first polarization control layer was 7E+17 atoms / cm². 3 The indium (In) content is 0.05; the boron (B) content in the first barrier sublayer is 0.1 and the indium (In) content is 0.05; the boron (B) content in the second barrier sublayer is 0.1; and the Si doping concentration in the second polarization control layer is 8E+17 atoms / cm². 3 The number of cycles for the active layer stack is 15.

[0055] The control group consists of existing LED epitaxial wafers, the difference being that the barrier layer in existing LED epitaxial wafers is an AlGaN layer with a thickness of 12 nm.

[0056] Using the components from Experimental Groups 1 to 9 respectively, and fabricating 10mil*24mil chips under the same chip manufacturing conditions, 300 LED chips were then selected and tested at 120 mA / 60 mA currents. The experimental data are shown in the table below.

[0057] Table 1

[0058]

[0059] As can be seen from the table above, compared with the existing LED epitaxial wafers, the photoelectric efficiency of the LED epitaxial wafers in experimental groups one to nine is improved by 1% to 5%, and other electrical properties are good.

[0060] Among them, the LED epitaxial wafer provided in Experimental Group 1 showed the greatest improvement in luminous efficacy compared to other experimental groups, approximately 5%. Therefore, the optimal values ​​are: first polarization control layer thickness 1.5 nm, first barrier sublayer thickness 5 nm, second barrier sublayer thickness 4 nm, second polarization control layer thickness 1 nm, and Si doping concentration in the first polarization control layer 7E+17 atoms / cm². 3 The In element composition is 0.05, the B element composition is 0.1 and the In element composition is 0.05 in the first barrier sublayer, the B element composition is 0.1 in the second barrier sublayer, and the Si doping concentration in the second polarization control layer is 8E+17 atoms / cm². 3 The number of stacking cycles for the active layer is 10.

[0061] In embodiment two, the present invention also provides an LED, which includes a light-emitting diode epitaxial wafer as described in embodiment one.

[0062] Example 3, please refer to Figure 2 The figure shows a method for fabricating a light-emitting diode epitaxial wafer according to a third embodiment of the present invention, comprising the following steps:

[0063] S01, providing a substrate;

[0064] Preferably, in some embodiments, the substrate may be selected from one of the following: sapphire substrate, SiO2 sapphire composite substrate, silicon substrate, silicon carbide substrate, gallium nitride substrate, and zinc oxide substrate.

[0065] By way of example and not limitation, in this embodiment, a sapphire substrate is selected. Sapphire is currently the most commonly used GaN-based LED substrate material. Sapphire substrates have mature manufacturing processes, low prices, are easy to clean and process, and have good stability at high temperatures.

[0066] S02, depositing a first semiconductor layer on the substrate;

[0067] The first semiconductor layer includes a buffer layer, an undoped GaN layer, and an N-type GaN layer deposited sequentially on the substrate.

[0068] The specific steps for depositing the first semiconductor layer on the substrate include:

[0069] S021, depositing an AlN / GaN buffer layer with a thickness of 10nm~50nm on the substrate;

[0070] Understandably, the AlN buffer layer, with a thickness of 15 nm, is deposited in the PVD process of the applied materials. The AlN buffer layer provides nucleation centers with the same orientation as the substrate, releasing the stress caused by the lattice mismatch between GaN and the substrate, as well as the thermal stress caused by the mismatch in the coefficient of thermal expansion. Further growth provides a flat nucleation surface, reducing the contact angle of its nucleation growth, allowing the island-shaped GaN grains to connect into a surface within a smaller thickness, thus transforming into two-dimensional epitaxial growth.

[0071] S022, Pre-treat the sapphire substrate with the deposited buffer layer;

[0072] Understandably, transferring a sapphire substrate with an AlN buffer layer into an MOCVD process and pretreating it in an H2 atmosphere for 1 to 10 minutes at a temperature of 1000°C to 1200°C, followed by nitriding, can improve the crystal quality of the AlN buffer layer and effectively enhance the crystal quality of the subsequently deposited GaN epitaxial layer.

[0073] S023, deposit an undoped GaN layer on the buffer layer;

[0074] Preferably, the undoped GaN layer is grown at a temperature of 1050℃~1200℃, a pressure of 100 torr~600 torr, and a thickness of 1µm~5µm.

[0075] In this embodiment, the undoped GaN layer is grown at a temperature of 1100°C, a growth pressure of 150 torr, and a thickness of 2µm to 3µm. It can be understood that the undoped GaN layer has a higher growth temperature and lower pressure, resulting in a higher quality GaN crystal. At the same time, as the thickness of GaN increases, the compressive stress is released through stacking faults, reducing line defects, improving crystal quality, and reducing reverse leakage current. However, increasing the thickness of the GaN layer consumes a large amount of Ga source material, which greatly increases the epitaxial cost of LEDs. Therefore, currently, LED epitaxial wafers are usually grown with undoped GaN at 2µm to 3µm, which not only saves production costs but also provides GaN material with high crystal quality.

[0076] S024, depositing an N-type GaN layer on the undoped GaN layer;

[0077] Preferably, the N-type GaN layer is grown at a temperature of 1050℃~1200℃, a pressure of 100 torr~600 torr, a thickness of 2um~3um, and a Si doping concentration of 1E+19atoms / cm3~5E+19atoms / cm3.

[0078] In this embodiment, the N-type GaN layer is grown at a temperature of 1120°C, a growth pressure of 100 torr, a thickness of 2-3 μm, and a Si doping concentration of 2.5E+19 atoms / cm3. It can be understood that, firstly, the n-type GaN layer provides sufficient electrons for LED light emission; secondly, the resistivity of the n-type GaN layer is higher than that of the transparent electrode on p-GaN, so sufficient Si doping can effectively reduce the resistivity of the n-type GaN layer; and finally, sufficient thickness of the n-type GaN can effectively release stress and improve the luminous efficiency of the LED.

[0079] S03, M cycles of potential well layers and composite barrier layers are alternately stacked on the first semiconductor layer to form an active layer.

[0080] The composite barrier layer comprises, along the epitaxial direction, a first polarization control layer, a first barrier sublayer, a second barrier sublayer, and a second polarization control layer stacked sequentially. The first polarization control layer is a Si-doped InGaN layer, the first barrier sublayer is a BInGaN layer, the second barrier sublayer is a BGaN layer, and the second polarization control layer is a Si-doped GaN layer.

[0081] Optionally, the thickness of the first polarization control layer ranges from 0.5 nm to 5 nm, the thickness of the first barrier sublayer ranges from 1 nm to 10 nm, the thickness of the second barrier sublayer ranges from 1 nm to 10 nm, and the thickness of the second polarization control layer ranges from 0.5 nm to 5 nm.

[0082] Optionally, the Si doping concentration in the first polarization control layer is 1E+17 atoms / cm². 3 ~1E+19atoms / cm 3 The composition of In element ranges from 0.01 to 0.1; the composition of B element in the first barrier sublayer ranges from 0.05 to 0.5; the composition of In element ranges from 0.01 to 0.1; the composition of B element in the second barrier sublayer ranges from 0.05 to 0.5; and the Si doping concentration in the second polarization control layer is 1E+17 atoms / cm². 3 ~1E+19atoms / cm 3 .

[0083] Optionally, the growth temperature range of the composite barrier layer is 800℃~1000℃, the ratio of N2 / H2 / NH3 in the growth atmosphere of the composite barrier layer is 1:1:1~1:10:20, and the growth pressure range of the composite barrier layer is 50 torr~300 torr.

[0084] Optionally, the period M of the alternating arrangement of the potential well layer and the composite barrier layer can be in the range of 1≤M≤20.

[0085] Optionally, the potential well layer is an InGaN layer, the growth temperature of the potential well layer is in the range of 700℃ to 900℃, the thickness of the potential well layer is in the range of 1nm to 10nm, the growth pressure of the potential well layer is in the range of 50 torr to 500 torr, and the composition of In element in the potential well layer is in the range of 0.01 to 0.5.

[0086] As shown in Example 1, the optimal composition of the active layer is as follows: the thickness of the first polarization control layer is 1.5 nm, the thickness of the first barrier sublayer is 5 nm, the thickness of the second barrier sublayer is 4 nm, the thickness of the second polarization control layer is 1 nm, and the Si doping concentration in the first polarization control layer is 7E+17 atoms / cm². 3 The In element composition is 0.05, the B element composition is 0.1 and the In element composition is 0.05 in the first barrier sublayer, the B element composition is 0.1 in the second barrier sublayer, and the Si doping concentration in the second polarization control layer is 8E+17 atoms / cm². 3 The number of stacking cycles for the active layer is 10.

[0087] In addition, the optimal preparation environment is as follows: the growth temperature of the composite barrier layer is 870℃, the ratio of N2 / H2 / NH3 in the growth atmosphere of the composite barrier layer is 2:3:5, the growth pressure of the composite barrier layer is 200 torr, the potential well layer is an InGaN layer, the growth temperature is 790℃, the thickness is 3.2 nm, the growth pressure is 200 torr, and the In composition is 0.15.

[0088] S04, deposit a second semiconductor layer on the composite barrier layer in the last cycle;

[0089] Specifically, the second semiconductor layer includes an electron blocking layer and a P-type GaN layer sequentially deposited on the active layer.

[0090] The specific steps for depositing a second semiconductor layer on the composite barrier layer in the last cycle include:

[0091] S041, deposit an electron blocking layer on the active layer;

[0092] Optionally, the electron blocking layer is an AlInGaN layer with a thickness of 10 nm to 40 nm, a growth temperature of 900 °C to 1000 °C, and a pressure of 100 torr to 300 torr, wherein the Al component is 0.005 to 0.1 and the In component concentration is 0.01 to 0.2.

[0093] In this embodiment, the electron blocking layer is an AlInGaN layer with a thickness of 15 nm, wherein the Al component concentration is 0.05 and the In component concentration is 0.01, the growth temperature is 965℃, and the growth pressure is 200 torr. It can be understood that this ratio can effectively limit electron overflow and reduce the blocking of holes, improve the injection efficiency of holes into the electron trap, reduce carrier Auger recombination, and improve the luminous efficiency of the light-emitting diode.

[0094] S042, depositing a P-type GaN layer on the electron blocking layer;

[0095] Optionally, the p-type GaN layer is grown at a temperature of 900℃~1050℃, a thickness of 10nm~50nm, a growth pressure of 100torr~600torr, and a Mg doping concentration of 1E+19 atoms / cm. 3 ~1E+21 atoms / cm 3 .

[0096] In this embodiment, the P-type GaN layer is grown at a temperature of 985°C, with a thickness of 15 nm, a growth pressure of 200 torr, and a Mg doping concentration of 2E+20 atoms / cm³. It is understood that excessively high Mg doping concentration will compromise crystal quality, while low doping concentration will affect hole concentration. Furthermore, for LED structures containing V-shaped pits, the higher growth temperature of the P-type GaN layer is beneficial for merging the V-shaped pits, resulting in a smooth LED epitaxial wafer.

[0097] In summary, in this invention, firstly, the large lattice mismatch between the InGaN potential well layer and the barrier layer leads to a huge piezoelectric field in the InGaN potential well layer. The deposition of the first polarization control layer SiInGaN layer / second polarization control layer SiGaN layer, containing Si elements, generates an electric field to balance the piezoelectric field of the InGaN potential well layer, reducing the quantum confinement Stark effect of the potential well layer, increasing the overlap of the electron and hole space wave functions, and improving the luminous efficiency of the light-emitting diode. Secondly, AlGaN material is generally used as the barrier layer because AlGaN has a large polarization effect and poor crystal quality. The deposition of the first barrier sublayer (BInGaN layer) and the second barrier sublayer (BGaN layer) reduces the polarization effect caused by the barrier material by reducing the Al-free component. By using BInGaN with a rationally designed composition ratio as the quantum well barrier material, lattice matching can be achieved and piezoelectric polarization in the quantum well can be eliminated. This increases the band gap width of the BInGaN / BGaN material, thereby enhancing the barrier's ability to confine injected carriers, preventing electron overflow, effectively suppressing the LED efficiency droop effect, and improving the luminous efficiency of the light-emitting diode.

[0098] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0099] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A light-emitting diode epitaxial wafer, characterized in that, The system includes a substrate and a first semiconductor layer, an active layer, and a second semiconductor layer sequentially deposited on the substrate. The active layer includes M periodically alternating potential well layers and a composite barrier layer. The composite barrier layer includes a first polarization control layer, a first barrier sublayer, a second barrier sublayer, and a second polarization control layer sequentially stacked along the epitaxial direction. The first polarization control layer is a Si-doped InGaN layer, the first barrier sublayer is a BinGaN layer, the second barrier sublayer is a BGaN layer, and the second polarization control layer is a Si-doped GaN layer. The Si doping concentration in the first polarization control layer is 1E+17 atoms / cm². 3 ~1E+19atoms / cm 3 The Si doping concentration in the second polarization control layer is 1E+17 atoms / cm². 3 ~1E+19atoms / cm 3 The potential well layer is an InGaN layer; the thickness of the first polarization control layer ranges from 0.5nm to 5nm, the thickness of the first barrier sublayer ranges from 1nm to 10nm, the thickness of the second barrier sublayer ranges from 1nm to 10nm, and the thickness of the second polarization control layer ranges from 0.5nm to 5nm. The composition range of In element in the first polarization control layer is 0.01~0.1, the composition range of B element in the first barrier sublayer is 0.05~0.5, the composition range of In element is 0.01~0.1, and the composition range of B element in the second barrier sublayer is 0.05~0.

5.

2. The light-emitting diode epitaxial wafer according to claim 1, characterized in that, The period M of the alternating arrangement of the potential well layer and the composite barrier layer ranges from 1 to 20.

3. The light-emitting diode epitaxial wafer according to claim 1, characterized in that, The first semiconductor layer includes a buffer layer, an undoped GaN layer, and an N-type GaN layer sequentially deposited on the substrate, and the second semiconductor layer includes an electron blocking layer and a P-type GaN layer sequentially deposited on the active layer.

4. A method for preparing a light-emitting diode epitaxial wafer, used to prepare a light-emitting diode epitaxial wafer as described in any one of claims 1-3, characterized in that, Includes the following steps: Provide a substrate; A first semiconductor layer is deposited on the substrate; An active layer is formed by alternately stacking M cycles of potential well layers and composite barrier layers on the first semiconductor layer. The composite barrier layer comprises, along the epitaxial direction, a first polarization control layer, a first barrier sublayer, a second barrier sublayer, and a second polarization control layer stacked sequentially. The first polarization control layer is a Si-doped InGaN layer, the first barrier sublayer is a BinGaN layer, the second barrier sublayer is a BGaN layer, and the second polarization control layer is a Si-doped GaN layer. The Si doping concentration in the first polarization control layer is 1E+17 atoms / cm². 3 ~1E+19atoms / cm 3 The Si doping concentration in the second polarization control layer is 1E+17 atoms / cm². 3 ~1E+19atoms / cm 3 The potential well layer is an InGaN layer; the thickness of the first polarization control layer ranges from 0.5 nm to 5 nm, the thickness of the first barrier sublayer ranges from 1 nm to 10 nm, the thickness of the second barrier sublayer ranges from 1 nm to 10 nm, and the thickness of the second polarization control layer ranges from 0.5 nm to 5 nm; the composition of In element in the first polarization control layer ranges from 0.01 to 0.1, the composition of B element in the first barrier sublayer ranges from 0.05 to 0.5, the composition of In element ranges from 0.01 to 0.1, and the composition of B element in the second barrier sublayer ranges from 0.05 to 0.

5. A second semiconductor layer is deposited on the composite barrier layer in the last cycle.

5. The method for fabricating a light-emitting diode epitaxial wafer according to claim 4, characterized in that, The growth temperature range of the composite barrier layer is 800℃~1000℃, the ratio of N2 / H2 / NH3 in the growth atmosphere of the composite barrier layer is 1:1:1~1:10:20, and the growth pressure range of the composite barrier layer is 50 torr~300 torr.

6. The method for preparing a light-emitting diode epitaxial wafer according to claim 4, characterized in that, The growth temperature range of the potential well layer is 700℃~900℃, the thickness range of the potential well layer is 1nm~10nm, the growth pressure range of the potential well layer is 50torr~500torr, and the In element composition range of the potential well layer is 0.01~0.

5.

7. The method for fabricating a light-emitting diode epitaxial wafer according to claim 4, characterized in that, The specific steps of depositing the first semiconductor layer on the substrate include: A buffer layer, an undoped GaN layer, and an N-type GaN layer are sequentially deposited on the substrate to form the first semiconductor layer; The specific steps for depositing a second semiconductor layer on the composite barrier layer in the last cycle include: An electron blocking layer and a P-type GaN layer are sequentially deposited on the composite barrier layer in the last cycle to form the second semiconductor layer.

8. An LED, characterized in that, Includes the light-emitting diode epitaxial wafer as described in any one of claims 1-3.

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