Charge-pump architecture and EEPROM

Abstract

The embodiment of the application provides a charge pump structure and an EEPROM, the structure comprising: a voltage boosting circuit, a voltage input end of the voltage boosting circuit being electrically connected with a first power supply, and the voltage boosting circuit being configured to boost an input voltage to obtain an output voltage according to a clock signal received by a clock input end and then output the output voltage; a conversion circuit, the conversion circuit being configured to output a reference voltage according to a number of target levels in write data, the reference voltage being in linear relationship with the number, and the write data comprising the target levels; a comparison circuit, a first input end of the comparison circuit being electrically connected with an output end of the conversion circuit, a second input end of the comparison circuit being electrically connected with a voltage output end of the voltage boosting circuit, and the comparison circuit being configured to compare the reference voltage and the output voltage and output a comparison result; and a control circuit, an input end of the control circuit being electrically connected with an output end of the comparison circuit, and an output end of the control circuit being electrically connected with the clock input end, and the control circuit being configured to determine whether to output the clock signal according to the comparison result, so as to control a voltage boosting value of the voltage boosting circuit.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and more specifically, to a charge pump structure and an EEPROM (Electrically Erasable Programmable Read Only Memory). Background Technology

[0002] With the booming development of computers and electronic products, the demand for ROM (Read Only Memory) is no longer primarily for program memory. More and more electronic products are using ROM as data memory, and some have even proposed the feasibility of replacing DRAM in computer products with ROM. Indeed, the application of ROM in this area, both in terms of cell area and its nonvolatile memory characteristics, demonstrates the advantages of ROM development. However, many bottlenecks remain to be overcome, such as read / write time and write cycles. Nevertheless, many products with low requirements for speed and write cycles already extensively use ROM as data memory, such as PDAs (personal digital assistants), digital cameras, audio players, and mobile phones.

[0003] With the advancement of semiconductor technology, the application of Flash ROM (Read-Only Programmable ROM) has become widespread, and it is used in almost all kinds of electronic products. Due to the advancement of process technology, small-size, high-capacity Flash ROM products have emerged, which has brought more convenience to applications in Signal Chip Platforms. However, as we move into the 50nm process, the mutual coupling problem of short channels has become increasingly serious. Therefore, floating gates are gradually losing their advantage in smaller processes. Instead, SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) process technology has been adopted. In applications, to accelerate read and write speeds (especially writes), multi-channel design and increasing the width of the data bus are currently the most common and easiest methods.

[0004] However, as the width of the data bus increases, the current required by the Flash ROM during the erasure and burning process also varies due to the different widths of the data bus. The change in current causes the source line voltage of the memory cell to change under different data conditions, which affects the reliability of the Flash ROM. Summary of the Invention

[0005] This application provides a charge pump structure and an EEPROM to at least solve the problem in the related art where different data bus widths cause changes in the source voltage during the Flash ROM erase / write process, affecting the reliability of the Flash ROM.

[0006] According to one embodiment of this application, a charge pump structure is provided, comprising: a boost circuit, including a clock input terminal, a voltage input terminal, and a voltage output terminal, wherein the voltage input terminal of the boost circuit is electrically connected to a first power supply, the boost circuit is used to receive the input voltage of the first power supply, and boosts the input voltage according to the clock signal received at the clock input terminal to obtain an output voltage and then outputs it; a conversion circuit, used to receive written data, and further used to output a reference voltage according to the number of target levels in the written data, wherein the reference voltage is linearly related to the number, and the written data includes multiple logic levels, the multiple logic levels including the target level; A comparator circuit includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the comparator circuit is electrically connected to the output terminal of the conversion circuit, and the second input terminal of the comparator circuit is electrically connected to the voltage output terminal of the boost circuit. The comparator circuit receives the reference voltage and the output voltage, compares the reference voltage and the output voltage, and outputs the comparison result. A control circuit has its input terminal electrically connected to the output terminal of the comparator circuit, and its output terminal electrically connected to the clock input terminal. The control circuit determines whether to output the clock signal based on the comparison result to control the boost value of the boost circuit.

[0007] In one exemplary embodiment, the conversion circuit includes: a first current source; a plurality of first current mirrors, each first current mirror including a first switch and a second switch, the control terminals of the first switches receiving the logic level in a one-to-one correspondence, a first terminal of the first switch being electrically connected to a first terminal of the second switch, a second terminal of the first switch being electrically connected to a second power supply, and a control terminal of the second switch being electrically connected to the output terminal of the first current source; at least one second current mirror, each second current mirror including a third switch and a fourth switch, the control terminal of the third switch being electrically connected to a third power supply, a first terminal of the third switch being electrically connected to a first terminal of the fourth switch, a second terminal of the third switch being electrically connected to the second power supply, and a control terminal of the fourth switch being electrically connected to the output terminal of the first current source; and a first voltage divider module, the first terminal of the first voltage divider module being the output terminal of the conversion circuit, and the first terminal of the first voltage divider module being electrically connected to the second terminals of each of the second switches and each of the fourth switches.

[0008] In an exemplary embodiment, the first current source includes: a fifth switching transistor, the first terminal of which is electrically connected to a third power supply, and the control terminal of which is electrically connected to the second terminal of which is the output terminal of the first current source; and a sixth switching transistor, the doping type of which is different from that of the fifth switching transistor, the first terminal of which is electrically connected to the second terminal of the fifth switching transistor, the second terminal of which is grounded, and the control terminal of which is electrically connected to the first terminal of which is also electrically connected.

[0009] In one exemplary embodiment, the conversion circuit further includes at least one of the following: a second voltage divider module, wherein a first terminal of the first voltage divider module is electrically connected to the second terminal of each of the second switching transistors and the second terminal of each of the fourth switching transistors via the second voltage divider module; a seventh switching transistor, wherein a first terminal of the seventh switching transistor is electrically connected to the second terminal of the first voltage divider module, the second terminal of the seventh switching transistor is grounded, and the control terminal of the seventh switching transistor is used to be electrically connected to a fifth power supply.

[0010] In one exemplary embodiment, the maximum current that the first current mirror can pass through is less than the maximum current that the second current mirror can pass through.

[0011] In one exemplary embodiment, there are multiple clock input terminals, and the control circuit includes: a NAND gate circuit, the first input terminal of which is the input terminal of the control circuit, and the second input terminal of which is used to receive the original clock signal; and multiple inverter circuits, which are connected in series, with the input terminal of the inverter circuit at the beginning of the series connection electrically connected to the output terminal of the NAND gate circuit, and the output terminal of each inverter circuit electrically connected to the clock input terminals one by one.

[0012] In one exemplary embodiment, the comparator circuit includes a differential amplifier configured to output a first voltage when the reference voltage is greater than the output voltage, and to output a second voltage when the reference voltage is less than the output voltage, wherein the first voltage is greater than the second voltage.

[0013] In one exemplary embodiment, the boost circuit includes: an eighth switch transistor, the first terminal of which is the voltage input terminal of the boost circuit, and the second terminal of which is electrically connected to the control terminal of the eighth switch transistor; a plurality of ninth switches transistors and a plurality of tenth switches transistors, the control terminal of which is electrically connected to the second terminal of the ninth switch transistor, and the control terminal of which is electrically connected to the second terminal of the tenth switch transistor, wherein the two ends of the ninth switch transistor and the two ends of the tenth switch transistor are alternately connected in series, wherein the first terminal of the ninth switch transistor located at the beginning of the series connection is electrically connected to the second terminal of the eighth switch transistor, and the second terminal of the tenth switch transistor located at the end of the series connection is the voltage input terminal of the boost circuit; The voltage output terminal of the boost circuit; multiple first energy storage modules, the first terminal of each first energy storage module is electrically connected to the control terminal of the ninth switch in a one-to-one correspondence, and the second terminals of every two adjacent first energy storage modules are electrically connected to form a clock input terminal; multiple second energy storage modules, the first terminal of each second energy storage module is electrically connected to the control terminal of the tenth switch in a one-to-one correspondence, and the second terminals of every two adjacent second energy storage modules are electrically connected to form a clock input terminal; a third energy storage module, the first terminal of which is electrically connected to the second terminal of the tenth switch located at the end of the series connection, and the second terminal of the third energy storage module is grounded.

[0014] In an exemplary embodiment, the voltage output terminal includes a first output terminal and a second output terminal, and the second terminal of the tenth switch located at the end of the series connection is the first output terminal. The boost circuit further includes: a third voltage divider module, the first terminal of which is electrically connected to the first output terminal; and a fourth voltage divider module, the first terminal of which is electrically connected to the second terminal of the third voltage divider module, the second terminal of which is grounded, the first terminal of which is the second output terminal, and the second output terminal is electrically connected to the second input terminal of the comparator circuit.

[0015] According to another embodiment of this application, an EEPROM is also provided, comprising: any of the charge pump structures described above.

[0016] This application utilizes a boost circuit to boost the input voltage based on a clock signal to obtain an output voltage. A conversion circuit outputs a reference voltage linearly related to the number of target levels in the received write data to a comparator circuit. The comparator circuit compares this reference voltage with the output voltage of the boost circuit and outputs the comparison result. A control circuit determines whether to output a clock signal to the boost circuit based on the comparison result, controlling the boost voltage's boost value and thus the output voltage. This allows for timely adjustment of the output voltage based on changes in the write data, ensuring a stable source voltage for the Flash ROM memory cells. It avoids the problem of source voltage fluctuations during the Flash ROM erase / write process due to variations in data bus widths, which could affect Flash ROM reliability and guarantee high Flash ROM reliability. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a charge pump structure according to an embodiment of this application;

[0018] Figure 2 This is a schematic diagram of the conversion circuit according to an embodiment of this application;

[0019] Figure 3 This is a schematic diagram of the control circuit according to an embodiment of this application;

[0020] Figure 4 This is a schematic diagram of the circuit structure of a differential amplifier according to an embodiment of this application;

[0021] Figure 5 This is a schematic diagram of a boost circuit according to an embodiment of this application;

[0022] Figure 6 This is a schematic diagram of another structure of the boost circuit according to an embodiment of this application;

[0023] Figure 7 This is a schematic diagram of the structure of an EEPROM Cell according to an embodiment of this application;

[0024] Figure 8 This is a schematic diagram of the structure of the EEPROM Cell in the HHI process according to an embodiment of this application;

[0025] Figure 9 This is a schematic diagram illustrating the difference in Vth between logic 0 and logic 1 according to an embodiment of this application;

[0026] Figure 10 This is a schematic diagram of the structure of an EEPROM Cell in the CHE process according to an embodiment of this application;

[0027] Figure 11 This is a schematic diagram of the circuit structure of a Flash ROM according to an embodiment of this application;

[0028] Figure 12 This is a schematic diagram illustrating the influence of the number of logic 0s on Vsl according to an embodiment of this application.

[0029] The above figures include the following reference numerals:

[0030] 10. First power supply; 11. Boost circuit; 12. Conversion circuit; 13. Comparator circuit; 14. Control circuit; 110. Eighth switch; 111. Ninth switch; 112. Tenth switch; 113. First energy storage module; 114. Second energy storage module; 115. Third energy storage module; 116. First output terminal; 117. Second output terminal; 118. Third voltage divider module; 119. Fourth voltage divider module; 120. First current source; 121. First switch; 122. Second switch; 123. Second power supply; 124. Third switch; 125. Fourth switch; 126. First voltage divider module; 127. Fifth switch; 128. Third power supply ; 129, Sixth Switch; 1201, Second Voltage Divider Module; 1202, Seventh Switch; 130, Second Current Source; 131, Seventeenth Switch; 132, Eighteenth Switch; 133, Seventh Power Supply; 134, Nineteenth Switch; 135, Twentieth Switch; 136, Twenty-first Switch; 137, Twenty-second Switch; 138, Twenty-third Switch; 139, Twenty-fourth Switch; 1301, Twenty-fifth Switch; 140, Eleventh Switch; 141, Sixth Power Supply; 142, Twelfth Switch; 143, Thirteenth Switch; 144, Fourteenth Switch; 145, Fifteenth Switch; 146, Sixteenth Switch. Detailed Implementation

[0031] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0032] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0033] This embodiment provides a charge pumping structure. Figure 1 This is a schematic diagram of the charge pump structure according to an embodiment of this application, as shown below. Figure 1 As shown, the charge pump structure includes:

[0034] The boost circuit 11 includes a clock input terminal, a voltage input terminal, and a voltage output terminal. The voltage input terminal of the boost circuit 11 is used to connect to the first power supply 10 (e.g., ...). Figure 5 (As shown) Electrical connection, the boost circuit 11 is used to receive the input voltage of the first power supply, and boost the input voltage according to the clock signal received at the clock input terminal to obtain the output voltage and then output it;

[0035] Specifically, the boost circuit is turned on or off according to the clock signal at the clock input terminal. The output voltage is used to supply voltage to the Flash ROM, providing high-voltage energy for the Flash ROM's erase and write operations. The clock signal is the boost signal that controls the specific boost value of the boost circuit.

[0036] The conversion circuit 12 is used to receive the written data and to output a reference voltage according to the number of target levels in the written data. The reference voltage is linearly related to the number of levels. The written data includes multiple logic levels, and the multiple logic levels include the target level.

[0037] Specifically, the above logic levels include a high level (corresponding to logic 1) and / or a low level (corresponding to logic 0). The target level can be a high level or a low level. In this application, a low level is selected as the target level.

[0038] The comparator circuit 13 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the comparator circuit 13 is electrically connected to the output terminal of the conversion circuit 12, and the second input terminal of the comparator circuit 13 is electrically connected to the voltage output terminal of the boost circuit 11. The comparator circuit 13 is used to receive the reference voltage and the output voltage, compare the reference voltage and the output voltage, and output the comparison result.

[0039] The control circuit 14 has its input terminal electrically connected to the output terminal of the comparison circuit 13, and its output terminal electrically connected to the clock input terminal. The control circuit 14 is used to determine whether to output the clock signal based on the comparison result, so as to control the boost value of the boost circuit 11.

[0040] In the above embodiments, the boost circuit boosts the input voltage according to the clock signal to obtain the output voltage. The conversion circuit outputs a reference voltage linearly related to the number of target levels in the received write data to the comparator circuit. The comparator circuit compares the reference voltage with the output voltage of the boost circuit and outputs the corresponding comparison result. The control circuit determines whether to output a clock signal to the boost circuit based on the comparison result, controls the boost voltage value, and thus controls the magnitude of the output voltage. This achieves timely adjustment of the output voltage according to changes in the write data, ensuring that the source voltage of the Flash ROM memory cell remains stable. This avoids the problem of source voltage changes during the Flash ROM erase and write process due to different data bus widths, which affects the reliability of the Flash ROM and ensures high reliability of the Flash ROM.

[0041] According to some exemplary embodiments of this application, such as Figure 2 As shown, the conversion circuit 12 includes:

[0042] First current source 120;

[0043] Multiple first current mirrors are provided, each including a first switch 121 and a second switch 122. The control terminal of the first switch 121 receives the logic level in a corresponding manner. The first terminal of the first switch 121 is electrically connected to the first terminal of the second switch 122. The second terminal of the first switch 121 is used to be electrically connected to the second power supply 123. The control terminal of the second switch 122 is electrically connected to the output terminal of the first current source 120.

[0044] Specifically, the first and second switching transistors can be any suitable switching transistor, such as MOSFETs or transistors. Those skilled in the art can flexibly set them according to actual conditions, as long as the target level ensures that the first switching transistor is turned on. This application does not impose specific limitations in this regard. Optionally, in this application, the first and second switching transistors are MOSFETs. Specifically, when the target level is high (i.e., logic 1), the first and second switching transistors are PMOS transistors; when the target level is low (i.e., logic 0), the first and second switching transistors are NMOS transistors.

[0045] At least one second current mirror, the second current mirror including a third switch 124 and a fourth switch 125, the control terminal of the third switch 124 is used to be electrically connected to a third power supply (not shown in the figure), the first terminal of the third switch 124 is electrically connected to the first terminal of the fourth switch 125, the second terminal of the third switch 124 is used to be electrically connected to the second power supply 123, and the control terminal of the fourth switch 125 is electrically connected to the output terminal of the first current source 120;

[0046] Specifically, the third power supply is used to provide a turn-on voltage to the third switch. The third and fourth switches can be any suitable switch, such as a MOSFET or a transistor, and those skilled in the art can flexibly configure them according to actual circumstances; this application does not impose specific limitations on this. Optionally, in this application, the third and fourth switches are both MOSFETs. More specifically, when the first and second switches are both PMOS transistors, the third and fourth switches are both PMOS transistors; when the first and second switches are both NMOS transistors, the third and fourth switches are both NMOS transistors.

[0047] Furthermore, when there are multiple second current mirrors, these multiple second current mirrors are equivalent to being connected in parallel.

[0048] The first voltage divider module 126 has its first end being the output terminal of the conversion circuit. The first end of the first voltage divider module 126 is electrically connected to the second end of each of the second switching transistors 122 and the second end of each of the fourth switching transistors 125.

[0049] Specifically, the first voltage divider module described above can be any suitable voltage divider component, such as a resistor, capacitor, inductor, or a combination thereof. Optionally, as... Figure 2 As shown, the first voltage divider module 126 includes a first resistor. The second terminal of the first voltage divider module can be grounded.

[0050] In the above embodiment, a stable and reliable current signal source is provided by the first current source. The current flowing through the first current mirror is 1 / n of the first current source, where n is the number of target levels in the written data. The logic level of the written data acts as a switch for the first current mirror. The more target levels there are, the more first switching transistors are turned on, and thus the more current mirrors are turned on. This increases the current flowing through the first voltage divider module, causing the voltage at the first terminal of the first voltage divider module to rise, and vice versa. Furthermore, the second current mirror provides the basic current source for the conversion circuit. The current provided by the second current mirror, after flowing through the first voltage divider module, can maintain a basic voltage at the first terminal of the first voltage divider module. The first current mirror is then used to control the bias of this voltage. This circuit structure enables the output of a linearly related reference voltage based on changes in the written data, facilitating timely adjustment of the output voltage by the control circuit, thereby further ensuring the reliability of the Flash ROM.

[0051] Those skilled in the art can choose any suitable current source structure as the first current source described above in this application during practical applications. One alternative solution is, for example... Figure 2 As shown, the first current source 120 includes: a fifth switch 127, the first end of which is electrically connected to the third power supply 128, the control terminal of which is electrically connected to the second end of which is the output terminal of the first current source 120; and a sixth switch 129, the doping type of which is different from that of which is which is which is which is which is the fifth switch 127, the first end of which is electrically connected to the second end of which is the fifth switch 127, the second end of which is grounded, and the control terminal of which is electrically connected to the first end of which is the sixth switch 129.

[0052] The second power supply and the fourth power supply can be the same power supply or different power supplies. The fifth switch and the sixth switch can be any suitable switch, such as a MOSFET or a transistor. In the embodiments of this application, the fifth switch and the sixth switch are both MOSFETs, with the fifth switch being a PMOS and the sixth switch being an NMOS.

[0053] In addition to the structure described above, in one exemplary embodiment, such as Figure 2As shown, the conversion circuit further includes at least one of the following: a second voltage divider module 1201, wherein the first end of the first voltage divider module 126 is electrically connected to the second end of each of the second switching transistors 122 and the second end of each of the fourth switching transistors 125 through the second voltage divider module 1201. That is, the first end of the second voltage divider module 1201 is electrically connected to the second end of each of the second switching transistors 122 and the second end of each of the fourth switching transistors 125, and the second end of the second voltage divider module 1201 is electrically connected to the first end of the first voltage divider module 126.

[0054] Specifically, the second voltage divider module described above can be any suitable voltage divider component, such as a resistor, capacitor, inductor, or a combination thereof. Optionally, such as Figure 2 As shown, the second voltage divider module 1201 includes a second resistor.

[0055] The seventh switch 1202 has its first end electrically connected to the second end of the first voltage divider module 126, and its second end grounded. The control terminal of the seventh switch 1202 is used to be electrically connected to the fifth power supply (not shown in the figure).

[0056] The fifth power supply is used to provide a turn-on voltage for the seventh switch. Similarly, the seventh switch can be any suitable switching device in the prior art; in this application, an NMOS is selected as the seventh switch.

[0057] In the above embodiments, the voltage value at the output terminal of the conversion circuit is increased by the second voltage divider module, and the first voltage divider module and the first voltage divider module to ground are controlled by the seventh switch to control whether the conversion circuit has an output voltage.

[0058] According to some further exemplary embodiments of this application, the maximum current that the first current mirror can pass through is less than the maximum current that the second current mirror can pass through. In this way, the second current mirror can provide a larger base voltage, and the bias of this voltage provided by the second current mirror is adjusted by the number of times the first current mirror is turned on.

[0059] When the first and second switching transistors included in the first current mirror and the third and fourth switching transistors included in the second current mirror are all MOSFETs, the maximum current that the first current mirror can pass through is less than the maximum current that the second current mirror can pass through by setting the width-to-length ratio of the first and second switching transistors to be smaller than the width-to-length ratio of the third and fourth switching transistors.

[0060] To enable those skilled in the art to better understand the working principle of the above-mentioned conversion circuit, the following explanation will be based on the example that all the switching transistors in the conversion circuit are MOS and the above-mentioned written data includes 8 of the above-mentioned target levels, that is, the above-mentioned written input is "00000000".

[0061] like Figure 2 As shown, in the first current source, the fifth switch is a PMOS with a width-to-length ratio of 0.5 / 0.5, and the sixth switch is an NMOS with a width-to-length ratio of 0.5 / 0.5. The gates of multiple second switches are electrically connected to the drain of the fifth switch, forming a first current mirror design. By controlling the width-to-length ratio of the second switches, the current flowing through the first current mirror is made 1 / 8 of the first current source. The gates of the multiple first switches are respectively electrically connected to the target voltage level, acting as switches for the first current mirror. The more zeros there are, the more first current mirrors are turned on, thus increasing the current flowing through the first and second voltage divider modules, causing the voltage between the first and second voltage divider modules to rise, and vice versa. In addition, there is one second current mirror, in which the fourth switch is a PMOS with a width-to-length ratio of 5 / 0.5 and the fifth switch is a PMOS with a width-to-length ratio of 5 / 0.5. The second current mirror provides the basic current source requirement of the circuit. After the current provided by the second current mirror flows through the first voltage divider module and the second voltage divider module, it can maintain a basic voltage at the output of the conversion circuit. The remaining first current mirror is used to control the bias of this voltage.

[0062] The formula for the current of the first current source is as follows:

[0063]

[0064] In this circuit, the formula for the current value of the first current mirror corresponding to the first current source is as follows:

[0065]

[0066] In addition, the formula for the basic current value provided by the second current mirror is as follows:

[0067]

[0068] The basic voltage value provided by the second current mirror is as follows:

[0069] V BIAS =I BIAS ×R2

[0070] For each additional logic 0, i.e., Bit = 0, the voltage output offset is as follows:

[0071] V OFFSET =IMIRROR ×R2

[0072] The formula for the reference voltage output by the conversion circuit corresponding to the voltage of n bits = 0 is as follows:

[0073] V REFOUT =(I BIAS +nI MIRROR )×R2=V BIAS +nV OFFSET

[0074] As can be seen from the above formula, the change in the reference voltage output by the conversion circuit only depends on nV. OFFSET The voltage is related and changes linearly. The second power supply 123 provides a low level to the third switch 124, and the reference voltage is an analog voltage.

[0075] In one exemplary embodiment, there are multiple clock input terminals, and the control circuit includes: a NAND gate circuit, the first input terminal of which is the input terminal of the control circuit, and the second input terminal of which is used to receive the original clock signal; and multiple inverter circuits, which are connected in series, with the input terminal of the inverter circuit at the beginning of the series connection electrically connected to the output terminal of the NAND gate circuit, and the output terminal of each inverter circuit electrically connected to the clock input terminals one by one.

[0076] In the above embodiment, the NAND gate circuit determines whether to transmit the original clock signal to the inverter based on the comparison result output by the comparator. The inverter, upon receiving the original clock signal, inverts it to convert it into the clock signal and sends it to the clock input terminal of the boost circuit.

[0077] Specifically, such as Figure 3 As shown, the circuit structure of the above NAND gate circuit can specifically include:

[0078] The eleventh switch 140, the control terminal of the eleventh switch 140 is the first input terminal of the NAND gate circuit, and the first terminal of the eleventh switch 140 is used to be electrically connected to the sixth power supply 141.

[0079] The twelfth switch 142, the control terminal of the twelfth switch 142 is the second input terminal of the NAND gate circuit, and the first terminal of the twelfth switch 142 is used to be electrically connected to the sixth power supply 141.

[0080] The thirteenth switch 143, the control terminal of the thirteenth switch 143 is the first input terminal of the NAND gate circuit, and the first terminal of the thirteenth switch 143 is electrically connected to the second terminal of the eleventh switch 140 and the second terminal of the twelfth switch 142 respectively.

[0081] The fourteenth switch 144, the control terminal of the fourteenth switch 144 is the second input terminal of the NAND gate circuit, the first terminal of the fourteenth switch 144 is electrically connected to the second terminal of the thirteenth switch 143, and the second terminal of the fourteenth switch 144 is grounded.

[0082] like Figure 3 As shown, the inverter circuit described above includes:

[0083] The fifteenth switch transistor 145 and the sixteenth switch transistor 146 have different doping types than the fifteenth switch transistor 145. The control terminals of the fifteenth switch transistor 145 and the sixteenth switch transistor 146 are electrically connected and electrically connected to the second terminal of the eleventh switch transistor 140. The first terminal of the fifteenth switch transistor 145 is used to be electrically connected to the sixth power supply 141. The second terminal of the fifteenth switch transistor 145 is electrically connected to the first terminal of the sixteenth switch transistor 146. The second terminal of the sixteenth switch transistor 146 is grounded. The second terminal of each of the fifteenth switch transistors 145 is the output terminal of the control circuit, that is, the second terminal of the fifteenth switch transistor 145 is electrically connected to the clock input terminal in a one-to-one correspondence.

[0084] Optionally, the eleventh, twelfth, and fifteenth switches are PMOS transistors, the thirteenth switch is a PMOS transistor, and the fourteenth and sixteenth switches are NMOS transistors. Of course, besides MOS transistors, the eleventh, twelfth, thirteenth, fourteenth, fifteenth, and sixteenth switches can also be other types of transistors.

[0085] Since the aforementioned clock signal needs to charge the energy storage module in the boost circuit, a large fan-out current is required. Therefore, the channel width of the switching transistor in the inverter circuit is relatively wide, and the overall area is relatively large.

[0086] To further ensure that the comparison circuit can output a more accurate comparison result, and thus further ensure that the control circuit can accurately adjust the boost value of the boost circuit based on the comparison result, in another optional embodiment, the comparison circuit includes a differential amplifier. The differential amplifier outputs a first voltage when the reference voltage is greater than the output voltage, and outputs a second voltage when the reference voltage is less than the output voltage, wherein the first voltage is greater than the second voltage. By comparing the reference voltage and the output voltage using a differential amplifier, the influence of voltage fluctuations or external interference on the comparison result can be avoided.

[0087] Furthermore, such as Figure 4 As shown, the differential amplifier described above includes:

[0088] The second current source 130 specifically includes a seventeenth switch 131 and an eighteenth switch 132. The control terminal and the first terminal of the seventeenth switch 131 are electrically connected. The first terminal of the seventeenth switch 131 is also used to be electrically connected to the seventh power supply 133. The second terminal of the seventeenth switch 131 is electrically connected to the first terminal of the eighteenth switch 132. The first terminal of the eighteenth switch 132 is also electrically connected to its control terminal. The second terminal of the eighteenth switch 132 is grounded.

[0089] The nineteenth switch 134, the first end of the nineteenth switch 134 is used to be electrically connected to the seventh power supply 133, and the control end of the nineteenth switch 134 is electrically connected to its second end.

[0090] The twentieth switch 135, the first end of which is used to be electrically connected to the seventh power supply 133, and the control end of the twentieth switch 135 is electrically connected to the control end of the nineteenth switch 134.

[0091] The 21st switch 136, the first terminal of the 21st switch 136 is electrically connected to the second terminal of the 19th switch 134, and the control terminal of the 21st switch 136 is the first input terminal of the comparator circuit.

[0092] The 22nd switch 137, the first terminal of the 22nd switch 137 is electrically connected to the second terminal of the 20th switch 135, and the control terminal of the 22nd switch 137 is the second input terminal of the comparator circuit.

[0093] The 23rd switch 138 has its first terminal electrically connected to the second terminal of the 21st switch 136 and the second terminal of the 22nd switch 137, respectively. The second terminal of the 23rd switch 138 is grounded. The control terminal of the 23rd switch 138 is electrically connected to the control terminal of the 18th switch 132.

[0094] The 24th switch 139 has its first terminal electrically connected to the 7th power supply 133, its control terminal electrically connected to the second terminal of the 20th switch 135, and its second terminal is the output terminal of the comparator circuit.

[0095] The 25th switch 1301 has its first terminal electrically connected to the second terminal of the 24th switch 139, its second terminal grounded, and its control terminal electrically connected to the control terminal of the 25th switch 1301.

[0096] Specifically, the switching transistors of the differential amplifier can be any suitable switching device in the prior art. In one option, the nineteenth and twentieth switching transistors in the differential amplifier are PMOS transistors, and the other switching transistors are NMOS transistors.

[0097] In the differential amplifier described above in this application, the second current source is used to provide a current signal, and its output terminal is connected to the control terminal of the twenty-third switch. The twenty-third switch acts as a current mirror to replicate the current of the second current source. The current flowing through the twenty-third switch is adjusted by different channel width-to-length ratios to provide the current required by the differential amplifier. Since the current at the second terminal of the twenty-first switch is fixed, when the reference voltage is greater than the output voltage, the impedance of the twenty-first switch will be lower than that of the twenty-second switch. This will cause the twenty-first switch to receive a larger current, which will also cause the voltage at the control terminal of the nineteenth switch to decrease, the impedance of the twenty-first switch to decrease, and thus the voltage at the control terminal of the twenty-fourth switch to increase, the impedance of the twenty-fourth switch to decrease, and the output comparison result to increase, resulting in a larger first voltage. Conversely, when the reference voltage is less than the output voltage, the impedance of the twenty-second switch will be lower than that of the twenty-first switch, causing a decrease in the current diverted to the twenty-first switch. This, in turn, causes the voltage at the control terminal of the nineteenth switch to rise, increasing the impedance of the twentyth switch. Finally, the voltage at the control terminal of the twenty-fourth switch decreases, increasing its impedance, resulting in a lower output voltage and a smaller second voltage. The control terminal of the twenty-fifth switch is electrically connected to the control terminal of the eighteenth switch, effectively acting as a current mirror. The twenty-fourth and twenty-fifth switches function like two voltage-dividing resistors, and the voltage level of the output comparison result depends on the conduction state of the twenty-fourth switch.

[0098] In practical applications, if the above comparator circuit cannot operate with a single low voltage, the problem can be solved by changing or adjusting the process parameters. If the output frequency response is poor, causing the output level to have an adverse effect on the input of the subsequent stage, the problem can be solved by adjusting the width-to-length ratio of the MOS transistor at the output of the differential amplifier.

[0099] In other embodiments of this application, such as Figure 5 As shown, the boost circuit 11 includes:

[0100] The eighth switch 110 has its first terminal as the voltage input terminal of the boost circuit 11, and its second terminal as electrically connected to the control terminal of the eighth switch 110.

[0101] Multiple ninth switches 111 and multiple tenth switches 112 are provided. The control terminal of the ninth switch 111 is electrically connected to its second terminal, and the control terminal of the tenth switch 112 is electrically connected to its second terminal. The two ends of the ninth switch 111 and the two ends of the tenth switch 112 are alternately connected in series. The first terminal of the ninth switch 111 located at the beginning of the series connection is electrically connected to the second terminal of the eighth switch 110, and the second terminal of the tenth switch 112 located at the end of the series connection is the voltage output terminal of the boost circuit 11.

[0102] Specifically, the eighth, ninth, and tenth switching transistors can be any feasible switching device in the prior art, such as a MOSFET or a transistor. In a more specific embodiment, the eighth, ninth, and tenth switching transistors can each be a PMOS transistor. Of course, these switching transistors can also all be NMOS transistors, and this application does not impose any specific restrictions on this.

[0103] Multiple first energy storage modules 113, the first end of each first energy storage module 113 is electrically connected to the control end of the ninth switch 111, and the second ends of each two adjacent first energy storage modules 113 are electrically connected to form a clock input terminal.

[0104] Multiple second energy storage modules 114, the first end of each second energy storage module 114 is electrically connected to the control end of the tenth switch tube 112, and each pair of adjacent second energy storage modules 114 are electrically connected to form a clock input terminal.

[0105] The third energy storage module 115 has its first end electrically connected to the second end of the tenth switch tube 112 located at the end of the series connection, and the second end of the third energy storage module 115 is grounded.

[0106] Specifically, the first energy storage module, the second energy storage module, and the third energy storage module can be any suitable energy storage device in the prior art, such as a capacitor or an inductor. In this embodiment, each of the first, second, and third energy storage modules includes a capacitor.

[0107] It should be noted that the B-stage of the aforementioned eighth, ninth, and tenth switching transistors is also electrically connected to its own gate.

[0108] In the above embodiment, the eighth, ninth, and tenth switching transistors are equivalent to diodes connected in series. The input current flows through the eighth switching transistor to charge the first energy storage module. When the clock signal connected to the first energy storage module changes, the voltage across the first energy storage module rises and charges the first second energy storage module through the first ninth switching transistor. When the clock signal connected to the first second energy storage module changes, the voltage across the first second energy storage module rises and charges the second first energy storage module through the first tenth switching transistor. At this time, the second first energy storage module can be charged to a higher potential voltage, and so on, until the last second energy storage module can obtain a high voltage and output it. The third energy storage module is used for voltage regulation. The first and / or second energy storage modules are charged and stored according to the received clock signal, and then discharged through the first and / or second energy storage modules. The input voltage is superimposed to achieve voltage boost, further ensuring that the output voltage is higher than the input voltage, to provide the Vpp voltage required for FlashROM programming.

[0109] In addition, such as Figure 6 As shown, the voltage output terminal includes a first output terminal 116 and a second output terminal 117. The second terminal of the tenth switch 112 located at the end of the series connection is the first output terminal 116. The boost circuit 11 further includes: a third voltage divider module 118, the first terminal of which is electrically connected to the first output terminal 116; and a fourth voltage divider module 119, the first terminal of which is electrically connected to the second terminal of the third voltage divider module 118, the second terminal of which is grounded, and the first terminal of which is the second output terminal 117. The second output terminal 117 is electrically connected to the second input terminal of the comparator circuit. In this embodiment, the voltage level after being divided by the third and fourth voltage divider modules is fed back to the comparator circuit, so that the comparator circuit compares the voltage level with the reference voltage, further ensuring accurate control of the output voltage of the entire charge pump structure.

[0110] Those skilled in the art can flexibly configure the specific components of the third voltage divider module and the fourth voltage divider module according to the actual situation. In one embodiment, the third voltage divider module and the fourth voltage divider module are resistors.

[0111] This application Figure 5 and Figure 6An exemplary block diagram of a 2-phase boost circuit is shown, which includes two clock inputs and is divided into 5 stages, capable of boosting the voltage from 1.5V to 4.5V (when all logic voltages for writing data are equal to 1).

[0112] Of course, in actual applications, the boost circuit is not limited to the two-phase design. Different phase boost circuits can be achieved by adjusting the number of the ninth switch, the tenth switch, the first energy storage module, and the second energy storage module, thereby achieving different boost values.

[0113] Since the required Vpp voltage (the peak value of the above output voltage) will change depending on the Flash ROM, to increase or decrease the output Vpp voltage, it is only necessary to adjust the voltage dividing resistors of the third and fourth voltage dividing modules or adjust the reference voltage output by the conversion circuit.

[0114] In another alternative embodiment, the capacitance of the capacitors used in the above boost circuit can all be 100pF, and the width-to-length ratio of each PMOS used is W / L = 3 / 0.35, and it is fabricated using a 0.18um process.

[0115] The charge pump structure of this application is designed using 0.18um CMOS process technology, with an input voltage of only 1.5V and an output that can be adjusted as needed. Currently, it is set to 4.5V. The low input voltage makes it easy to cooperate with the design of low-voltage power supplies for SOC (System on Chip), so that multiple power supply designs are not required.

[0116] Among them, the first power supply, second power supply, third power supply, fourth power supply, fifth power supply, sixth power supply and seventh power supply mentioned above can be the same power supply or different power supplies.

[0117] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0118] According to another aspect of this application, a memory is also provided, including any of the above-described charge pumping structures.

[0119] In the aforementioned memory, the charge pump structure boosts the input voltage using a boost circuit based on a clock signal to obtain an output voltage. A conversion circuit then outputs a reference voltage linearly related to the target level in the received write data to a comparator circuit. The comparator circuit compares this reference voltage with the output voltage of the boost circuit and outputs the comparison result. A control circuit determines whether to output a clock signal to the boost circuit based on the comparison result, controlling the boost voltage's boost value and thus the magnitude of the output voltage. This allows for timely adjustment of the output voltage based on changes in the write data, ensuring a stable source voltage for the Flash ROM memory cells. This avoids changes in the source voltage during the Flash ROM erase / write process due to variations in data bus widths, which could affect the Flash ROM's reliability and guarantee high Flash ROM reliability.

[0120] In one specific embodiment, the memory is an EEPROM, that is, the EEPROM includes the charge pump structure described above.

[0121] To facilitate understanding of this scheme, some relevant principles of EEPROM are explained below. The purpose of the charge pump structure design is mainly to provide the Vpp voltage required during EEPROM programming.

[0122] First, let's discuss the operation of the EEPROM. Whether it's a SONOS architecture or a Floating Gate architecture EEPROM, the principle is similar: it achieves operation by storing charge within the cell, thereby changing the MOSFET's on-state voltage Vth. This application will use a Floating Gate architecture EEPROM for explanation. For example... Figure 7 As shown, this is a typical EEPROM cell (Floating Gate) structure. Unlike a typical MOSFET, it has two poly layers (Poly1 and Poly2) at the gate. The second layer, Poly2, is not connected to the outside and is called the Floating Gate. However, there is an extremely thin oxide layer (tunnel region) between this Floating Gate and the channel. When data needs to be erased (hole injection), a negative high voltage (Vpp) is applied at the gate. This generates HHI (Hot Hole Injection) electron flow, which travels from the Floating Gate through the oxide layer to the N+ region below the tunnel region. Figure 8As shown, this means that a current will flow through the tunnel region to the Floating Gate. When the erasure is complete and the applied bias is removed, the holes in the Floating Gate cannot combine with enough electrons, and the Floating Gate will maintain a positive voltage. This will result in a decrease in the MOSFET turn-on voltage Vth of the cell, as shown. Figure 9 As shown.

[0123] Conversely, when data needs to be written (hot electron injection), a positive high voltage is applied to Vgs, which generates a CHE (Channel Hot Electron) electron flow that travels from the N+ region below the tunneling region through the oxide layer to the Floating Gate, as shown below. Figure 10 As shown, this means that a current will flow through the tunnel region to the N+ region below the tunnel region. When the write operation is complete, the external bias voltage is removed. Similarly, since there is no external bias voltage inside the Floating Gate, a large number of electrons inside the Floating Gate do not have enough energy to pass through the tunnel region, so they will be "trapped" inside the Floating Gate. This result will cause the MOSFET turn-on voltage (Vth) of the cell to increase, as shown. Figure 9 As shown.

[0124] Currently, NAND Flash is widely used in various electronic products as program or data memory. The non-volatile and small cell area characteristics of Flash fully demonstrate its development potential. However, the issues of write cycles and speed are the most criticized. In fact, with the development of SONOS technology, the write cycles can exceed one million times, and the write speed can reach 20 MByte / sec. To effectively improve the speed, a wider data bus can increase the speed several times. The multi-channel design effectively improves the bus bandwidth. However, with a wider bus width, the stability of Vpp write voltage also arises.

[0125] Figure 11This is a schematic diagram of a NAND Flash Cell section. Assuming data is written to Cell 1, the control signal S / L_EN = 0. At this time, there will be a voltage Vsl on the source line. This voltage is slightly lower than Vpp due to the linear impedance of the PMOS. When Data is 1, PROG_EN = 1, Yb = 1, and Q1, Q3, Q4, and QA are turned on. The potential difference between the drain and source terminals of the cell is small, so not much current flows through Q5. Conversely, when Data = 0, Q2, Q3, Q4, and QA are turned on. A current will flow from Vpp through Q5 to the source line, increasing the voltage drop across Q5. This may cause the voltage Vsl to become even lower. When Data... This problem becomes more severe as the number of lines, or logic levels, increases. Furthermore, as the data value changes, the voltage drop varies with the current, causing Vsl to fluctuate as well, which is undesirable. In fact, when Data = 0, the current flowing into each cell is 4uA / cell. If all 32 bits are simultaneously "0", the current will reach 128uA. While this current may seem small, during the programming process, it is sufficient to cause a voltage drop of 0.8 to 1V in Vsl (e.g., ...). Figure 12 (As shown), therefore, it is absolutely necessary to apply the charge pump structure of this application to the EEPROM for voltage pre-adjustment.

[0126] Embodiments of this application also provide an electronic device, including the memory and processor described above.

[0127] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0128] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0129] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0130] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A charge pumping structure, characterized in that, include: A boost circuit includes a clock input terminal, a voltage input terminal, and a voltage output terminal. The voltage input terminal of the boost circuit is used to be electrically connected to a first power supply. The boost circuit is used to receive the input voltage of the first power supply and boost the input voltage according to the clock signal received at the clock input terminal to obtain an output voltage before outputting it. A conversion circuit is used to receive written data and to output a reference voltage based on the number of target levels in the written data, wherein the reference voltage is linearly related to the number of levels, and the written data includes multiple logic levels, wherein the multiple logic levels include the target level. The comparator circuit includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the comparator circuit is electrically connected to the output terminal of the conversion circuit, and the second input terminal of the comparator circuit is electrically connected to the voltage output terminal of the boost circuit. The comparator circuit is used to receive the reference voltage and the output voltage, compare the reference voltage and the output voltage, and output the comparison result. A control circuit is provided, wherein the input terminal of the control circuit is electrically connected to the output terminal of the comparator circuit, and the output terminal of the control circuit is electrically connected to the clock input terminal. The control circuit is used to determine whether to output the clock signal based on the comparison result, so as to control the boost value of the boost circuit.

2. The charge pumping structure according to claim 1, characterized in that, The conversion circuit includes: First current source; Multiple first current mirrors, each first current mirror including a first switch and a second switch, the control terminal of the first switch receives the logic level in a one-to-one correspondence, the first terminal of the first switch is electrically connected to the first terminal of the second switch, the second terminal of the first switch is used to be electrically connected to a second power supply, and the control terminal of the second switch is electrically connected to the output terminal of the first current source. At least one second current mirror, the second current mirror including a third switch and a fourth switch, the control terminal of the third switch is used to be electrically connected to a third power supply, the first terminal of the third switch is electrically connected to the first terminal of the fourth switch, the second terminal of the third switch is used to be electrically connected to the second power supply, and the control terminal of the fourth switch is electrically connected to the output terminal of the first current source; The first voltage divider module has its first terminal being the output terminal of the conversion circuit, and its first terminal is electrically connected to the second terminal of each of the second switching transistors and the second terminal of each of the fourth switching transistors.

3. The charge pumping structure according to claim 2, characterized in that, The first current source includes: The fifth switching transistor has a first terminal for electrical connection to the third power supply, and a control terminal for electrical connection to the second terminal of the fifth switching transistor. The control terminal of the fifth switching transistor is the output terminal of the first current source. The sixth switch has a different doping type than the fifth switch. The first terminal of the sixth switch is electrically connected to the second terminal of the fifth switch. The second terminal of the sixth switch is grounded. The control terminal of the sixth switch is electrically connected to the first terminal of the sixth switch.

4. The charge pumping structure according to claim 2, characterized in that, The conversion circuit further includes at least one of the following: The second voltage divider module is used to electrically connect the first end of the first voltage divider module to the second end of each of the second switching transistors and the second end of each of the fourth switching transistors. The seventh switch has its first terminal electrically connected to the second terminal of the first voltage divider module, and its second terminal grounded. The control terminal of the seventh switch is used to be electrically connected to the fifth power supply.

5. The charge pumping structure according to claim 2, characterized in that, The maximum current that the first current mirror can pass through is less than the maximum current that the second current mirror can pass through.

6. The charge pumping structure according to any one of claims 1 to 5, characterized in that, The clock input terminal has multiple terminals, and the control circuit includes: The NAND gate circuit has its first input terminal as the input terminal of the control circuit, and its second input terminal as the input terminal of the NAND gate circuit for receiving the original clock signal. Multiple inverter circuits are connected in series. The input terminal of the inverter circuit at the beginning of the series connection is electrically connected to the output terminal of the NAND gate circuit. The output terminal of each inverter circuit is electrically connected to the clock input terminal in a corresponding manner.

7. The charge pumping structure according to any one of claims 1 to 5, characterized in that, The comparator circuit includes a differential amplifier, which outputs a first voltage when the reference voltage is greater than the output voltage, and outputs a second voltage when the reference voltage is less than the output voltage, wherein the first voltage is greater than the second voltage.

8. The charge pumping structure according to any one of claims 1 to 5, characterized in that, The boost circuit includes: The eighth switch transistor has its first terminal as the voltage input terminal of the boost circuit and its second terminal as electrically connected to the control terminal of the eighth switch transistor. Multiple ninth switches and multiple tenth switches are provided. The control terminal of the ninth switch is electrically connected to the second terminal, and the control terminal of the tenth switch is electrically connected to the second terminal. The two ends of the ninth switch and the two ends of the tenth switch are alternately connected in series. The first terminal of the ninth switch located at the beginning of the series connection is electrically connected to the second terminal of the eighth switch, and the second terminal of the tenth switch located at the end of the series connection is the voltage output terminal of the boost circuit. Multiple first energy storage modules, the first end of the first energy storage module is electrically connected to the control end of the ninth switch in a one-to-one correspondence, and the second ends of every two adjacent first energy storage modules are electrically connected to form a clock input terminal; Multiple second energy storage modules are provided, with the first end of each second energy storage module electrically connected to the control end of the tenth switching transistor in a one-to-one correspondence. Each pair of adjacent second energy storage modules electrically connected to their second ends serve as a clock input terminal. The third energy storage module has its first terminal electrically connected to the second terminal of the tenth switch located at the end of the series connection, and the second terminal of the third energy storage module is grounded.

9. The charge pumping structure according to claim 8, characterized in that, The voltage output terminal includes a first output terminal and a second output terminal, with the second terminal of the tenth switch located at the end of the series connection serving as the first output terminal. The boost circuit further includes: The third voltage divider module, wherein the first terminal of the third voltage divider module is electrically connected to the first output terminal; The fourth voltage divider module has its first terminal electrically connected to the second terminal of the third voltage divider module, and its second terminal grounded. The first terminal of the fourth voltage divider module is the second output terminal, and the second output terminal is electrically connected to the second input terminal of the comparator circuit.

10. An EEPROM, characterized in that, include: The charge pump structure according to any one of claims 1 to 9.

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