Active current-sharing drive circuit and current slope control method thereof

Abstract

The application belongs to the field of parallel application of silicon carbide MOSFET devices, and discloses an active current sharing driving circuit and a current slope control method thereof, comprising: a silicon carbide MOSFET, comprising a first silicon carbide MOSFET and a second silicon carbide MOSFET connected in parallel, and the gates of the first silicon carbide MOSFET and the second silicon carbide MOSFET are connected with an active gate driver; the active gate driver comprises a master driver and a slave driver with the same structure; the master driver and the slave driver are communicatively connected, and both comprise a logic chip control circuit, a current sampling circuit and a gate resistance switching circuit; the current sampling circuit and the gate resistance switching circuit are connected with the logic chip control circuit. The technical scheme can establish a complete digital closed-loop feedback channel and effectively compensate for dynamic current deviation.

Description

Technical Field

[0001] This invention belongs to the field of parallel silicon carbide MOSFET devices, and in particular relates to an active current sharing drive circuit and its current slope control method. Background Technology

[0002] Limited by the current-carrying capacity of current silicon carbide MOSFET devices, multiple silicon carbide MOSFETs are often connected in parallel in practical high-power applications to improve the overall output capacity of the system. However, due to differences in device parameters, parasitic parameters in parallel branches, and parasitic parameters in the drive circuit, parallel silicon carbide MOSFET devices often exhibit dynamic current imbalance during switching and steady-state current imbalance during conduction, causing individual devices to withstand currents far exceeding their rated values. Furthermore, the unbalanced current also results in significant differences in losses and switching stress between parallel devices, leading to different device aging rates and reducing system stability and reliability.

[0003] To address the uneven current issue in parallel devices, related technologies add coupling devices to the power circuit to force synchronous current of the parallel devices. However, this hardware addition introduces additional losses and complicates system design. Furthermore, some research attempts to actively compensate for dynamic current deviations by focusing on the drive structure. Existing technologies include using analog components to form a closed-loop feedback loop to control the drive current and providing a dynamic deviation compensation scheme with variable drive voltage in conjunction with an MCU digital chip. However, under the high-speed switching conditions of silicon carbide MOSFET devices, the propagation delay of analog devices significantly affects the compensation effect, and potential factors such as crosstalk during closed-loop operation can also affect closed-loop stability. In digital closed-loop systems, simply using a variable drive parameter scheme is insufficient to fully compensate for dynamic current deviations, and the minimum pulse that the push-pull device can generate during high-speed switching also limits the compensation effect. Summary of the Invention

[0004] The purpose of this invention is to provide an active current sharing drive circuit and its current slope control method to solve the problems existing in the prior art.

[0005] To achieve the above objectives, the present invention provides an active current sharing drive circuit, comprising:

[0006] The silicon carbide MOSFET includes a first silicon carbide MOSFET and a second silicon carbide MOSFET connected in parallel, wherein the gates of both the first silicon carbide MOSFET and the second silicon carbide MOSFET are connected to an active gate driver.

[0007] The active gate driver includes a master driver and a slave driver with identical structures;

[0008] The master driver and the slave driver are communicatively connected, and each includes a logic chip control circuit, a current sampling circuit, and a gate resistor switching circuit.

[0009] Both the current sampling circuit and the gate resistor switching circuit are connected to the logic chip control circuit.

[0010] Optionally, the current sampling circuit includes: a first voltage limiter K1, a second voltage limiter K2, a third voltage limiter K3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first operational amplifier OP1, a second operational amplifier OP2, a first comparator CP1, a second comparator CP2, a third comparator CP3, a fourth comparator CP4, and a capacitor C1;

[0011] Wherein, one end of the first voltage limiter K1 is connected to the output terminal of the first resistor R1 and the input terminal of the capacitor C1, and the other end is connected to the input terminal of the second resistor R2 and the positive input terminal of the second operational amplifier OP2. The output terminal of the capacitor C1 is grounded, and the input terminal of the first resistor R1 is used to input the induced voltage.

[0012] The output terminal of the second resistor R2 is connected to the input terminal of the third resistor R3 and the negative input terminal of the first operational amplifier OP1, respectively. The positive input terminal of the first operational amplifier OP1 is grounded. The output terminals of the first operational amplifier OP1 and the third resistor R3 are both connected to one end of the second voltage limiter K2. The other end of the second voltage limiter K2 is connected to the negative input terminal of the first operational amplifier OP1 and the negative input terminal of the second operational amplifier OP2, respectively.

[0013] The negative input terminal of the second operational amplifier OP2 is connected to one end of the fourth resistor R4 and the fifth resistor R5 respectively. The other end of the fourth resistor R4 is grounded. The other end of the fifth resistor R5 and the output terminal of the second operational amplifier OP2 are both connected to one end of the third voltage limiter K3. The other end of the third voltage limiter K3 is connected to the negative input terminals of the third comparator CP3 and the fourth comparator CP4.

[0014] The positive input terminals of the first comparator CP1, the second comparator CP2, the third comparator CP3, and the fourth comparator CP4 are used to input the comparison voltage, and the output terminals are used to output the comparison voltage.

[0015] Optionally, the gate resistor switching circuit includes two parallel-connected push-pull channels for turning on and push-pull channels for turning off.

[0016] The push-pull channel is configured to include: a first N-channel MOSFET Q1, a second N-channel MOSFET Q2, and a first drive resistor R. g1 Second driving resistor R g2 The drain pins of both the first N-channel MOSFET Q1 and the second N-channel MOSFET Q2 are connected to the drive turn-on voltage V. DD The source pins of the first N-channel MOSFET Q1 and the second N-channel MOSFET Q2 are respectively connected to the first drive resistor R. g1 and the second driving resistor R g2 One end is connected in series, and the first driving resistor R g1 and the second driving resistor R g2 The other end of each is connected to the gate pin of the silicon carbide MOSFET device;

[0017] The turn-off push-pull channel includes a first P-channel MOSFET Q3, a second P-channel MOSFET Q4, and a third drive resistor R. g3 and the fourth driving resistor R g4 The drain pins of both the first P-channel MOSFET Q3 and the second P-channel MOSFET Q4 are connected to the drive turn-off voltage V. SS The source pins of the first P-channel MOSFET Q3 and the second P-channel MOSFET Q4 are respectively connected to the third drive resistor R. g3 and the fourth driving resistor R g4 One end is connected in series, the third driving resistor R g3 and the fourth driving resistor R g4 The other end of each is connected to the gate pin of the silicon carbide MOSFET device.

[0018] Optionally, the logic chip control circuit includes: an isolation pulse transformer, a first programmable logic chip LC1, and a second programmable logic chip LC2;

[0019] The first programmable logic chip LC1 and the second programmable logic chip LC2 are communicatively connected through the isolation pulse transformer, which includes a first isolation pulse transformer T1 and a second isolation pulse transformer T2 connected in parallel.

[0020] The first programmable logic chip LC1 is provided with a master / slave communication interface and a PWM receiving interface. The input terminal of the second programmable logic chip LC2 is used to receive the comparison voltage, and the output terminal of the second programmable logic chip LC2 is used to output dynamic current information.

[0021] On the other hand, to achieve the above objectives, the present invention provides a current slope control method for an active current sharing drive circuit, comprising:

[0022] Step 1: Apply a pulse PWM to the active gate driver, acquire the pulse change signal through the first programmable logic chip LC1, and send the pulse change signal to the second programmable logic chip LC2;

[0023] Step 2: Obtain the pulse signals of the first silicon carbide MOSFET and the second silicon carbide MOSFET through the second programmable logic chip LC2, and start counting. While waiting to obtain the current information counting data, load the compensation value of the previous current deviation.

[0024] Step 3: Based on the previous current deviation compensation value, adjust the device turn-on time and current slope through the gate resistor switching circuit to achieve dynamic current deviation compensation; and obtain the dynamic current information of the first silicon carbide MOSFET and the second silicon carbide MOSFET at the current pulse moment through the current sampling circuit.

[0025] Step 4: Send the dynamic current information to the second programmable logic chip LC2; and send the pulse signal and the dynamic current information to the first programmable logic chip LC1 through the second programmable logic chip LC2;

[0026] Step 5: Analyze the pulse signal and the dynamic current information using the first programmable logic chip LC1 to obtain the dynamic current deviation value of the first silicon carbide MOSFET and the second silicon carbide MOSFET;

[0027] Step Six: Analyze the dynamic current deviation value, obtain the compensation amount for the next pulse time based on the analysis results, wait for the next pulse to arrive and load, and realize dynamic current deviation compensation.

[0028] Optionally, the dynamic current information includes: switching delay time t on / off-delay and current slope di ds / dt.

[0029] Optionally, the process of acquiring the dynamic current information includes:

[0030] The common-source inductance L inside the silicon carbide MOSFET device is obtained through a current sampling circuit. SS The induced voltage V during the switching transient process sense The integral voltage Vin is obtained through a passive integrator composed of the first resistor R1 and the capacitor C1:

[0031]

[0032]

[0033] The voltage value V is obtained through a current sampling circuit.in_n With V in_p :

[0034]

[0035]

[0036] Obtain reference voltage data V ref1 V ref2 V ref3 V ref4 The reference voltage data is compared using the first comparator CP1, the second comparator CP2, the third comparator CP3, and the fourth comparator CP4 to obtain the comparison pulse voltage data V. cp1 V cp2 V cp3 V cp4 ;

[0037] di ds (t) / dt is the dynamic (on / off) slope of the drain-source current of the parallel device, V in_n V is the output voltage of the first operational amplifier OP1. in_p This is the output voltage of the second operational amplifier OP2.

[0038] By analyzing the pulse voltage data and current information count data, dynamic current information is obtained;

[0039] Among them, the rising edge of the pulse PWM and V CP1 The count value t between rising edges on-delay The device turn-on delay time is compared with the voltage V. CP1 Rising edge and V CP2 The count value t between rising edges on-slope This represents the slope of the device's turn-on current, the falling edge of the pulse PWM, and V. CP3 The count value t between rising edges off-delay The device turn-off delay time is compared with the voltage V. cp3 With V cp4 The count value t between rising edges off-slope This represents the slope of the device's turn-off current.

[0040] Optionally, the process of obtaining the dynamic current deviation value includes:

[0041] Device turn-on delay time deviation Δt on-delay =t on-delay-M1 -t on-delay-M2 Dynamic current slope deviation Δt during device turn-on on-slope =t on-slope-M1 -t on-slope-M2 ; Turn-off delay time deviation Δt during device turn-off processoff-delay =t off-delay-M1 -t off-delay-M2 Dynamic current slope deviation Δt during device turn-off off-slope =t off-slope-M1 -t off-slope-M2 .

[0042] Optionally, when acquiring current information counting data, there is a switching delay in the parallel devices. The process of compensating for the switching delay of the parallel devices includes: the parallel devices include a first silicon carbide MOSFET and a second silicon carbide MOSFET. A device turn-on delay compensation time Ton-dc is set between the rising edge of the PWM pulse received by the main driver and the rising edge of the actual output pulses PWM1 and PWM2, and a device turn-off delay compensation time Toff-dc is set between the falling edge of the PWM pulse and the rising edge of the actual output pulses PWM3 and PWM4. When there is a turn-on delay deviation Δton-delay between the parallel devices M1 and M2, the turn-on delay compensation is completed by making the current Ton-dc equal to the previous Ton-dc-Δton-delay. When there is a turn-off delay deviation Δtoff-delay, the turn-off delay compensation is completed by making the current Toff-dc equal to the previous Toff-dc-Δtoff-delay.

[0043] Perform dynamic current slope deviation compensation:

[0044] The turn-on process of the first silicon carbide MOSFET and the second silicon carbide MOSFET is divided into turn-on delay T. on-delay With current controlled T on-control In the two time periods, during the turn-on delay phase, both PWM1 and PWM2 are at a high level; the current-controlled phase is divided into two time periods, T... Q1+Q2 Stages and T Q1 Phase, in which T Q1+Q2 During the phase, both PWM1 and PWM2 are at a high level, T Q1 During the phase where PWM1 is high and PWM2 is low, the Δt between parallel devices... on-slope When >0, T Q1+Q2 Decrease by one clock cycle T working T Q1 Add a T working If when Δt on-slope When <0, T Q1+Q2 Add one clock cycle T working T Q1 Decrease by one T working ;

[0045] The device's turn-off process is divided into turn-off delay T. off-delay With current controlled Toff-control During the two time periods, in the turn-off delay phase, both PWM3 and PWM4 are at a high level; in the current-controlled phase T... off-control Divided into two time periods, T Q3+Q4 Stages and T Q3 Phase, in which T Q3+Q4 During the phase, PWM3 and PWM4 are both high, T Q3 During the phase where PWM3 is high and PWM4 is low, the Δt between parallel devices... off-slope When >0, T Q3+Q4 Decrease by one clock cycle T working T Q3 Add a T working If when Δt off-slope When <0, T Q3+Q4 Add one clock cycle T working T Q3 Decrease by one T working .

[0046] The technical effects of this invention are as follows:

[0047] This invention provides an active current sharing drive circuit, comprising: a silicon carbide MOSFET, including a first silicon carbide MOSFET and a second silicon carbide MOSFET connected in parallel, both the first silicon carbide MOSFET and the second silicon carbide MOSFET being connected to an active gate driver; the active gate driver includes a master driver and a slave driver with identical structures; both the master driver and the slave driver include a logic chip control circuit, a current sampling circuit, and a gate resistor switching circuit; the logic chip control circuit of the master driver is communicatively connected to the logic chip control circuit of the slave driver; the above circuit provides a current slope control method for the active current sharing drive circuit;

[0048] This invention addresses the dynamic current deviation problem caused by inconsistencies in device parameters and circuit parasitic parameters in parallel silicon carbide MOSFET devices. By establishing a complete digital closed-loop feedback channel, this invention can effectively compensate for dynamic current deviations.

[0049] This invention achieves lossless transmission of dynamic current information of parallel silicon carbide MOSFET devices through the proposed dynamic current sampling circuit, analog-to-digital sampling method, and serial transmission architecture, and has strong versatility.

[0050] This invention reduces the coupling effect between switch delay deviation compensation and dynamic current slope deviation compensation through a multi-variable segmented compensation scheme, resulting in faster response speed, better compensation effect, and the compensation effect is not limited by the minimum pulse of the push-pull chip. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0053] Figure 1 This is a schematic diagram of the overall structure in an embodiment of the present invention;

[0054] Figure 2 This is a schematic diagram of the dynamic current sampling circuit in an embodiment of the present invention;

[0055] Figure 3 This is a schematic diagram of the logic chip control circuit in an embodiment of the present invention;

[0056] Figure 4 This is a schematic diagram of the gate resistor switching channel circuit in an embodiment of the present invention;

[0057] Figure 5 This is a flowchart of the active flow sharing control method in an embodiment of the present invention;

[0058] Figure 6 This is a schematic diagram and effect of the gate resistor switching scheme during the turn-on process in an embodiment of the present invention;

[0059] Figure 7 The figures shown are comparison diagrams of the effects in the embodiments of the present invention, wherein (a) is the effect diagram without closed-loop compensation and (b) is the effect diagram with closed-loop compensation. Detailed Implementation

[0060] Various exemplary embodiments of the present invention will now be described in detail. This detailed description should not be considered as a limitation of the present invention, but rather as a more detailed description of certain aspects, features, and embodiments of the present invention.

[0061] It should be understood that the terminology used in this invention is merely for describing particular embodiments and is not intended to limit the invention. Furthermore, with respect to numerical ranges in this invention, it should be understood that each intermediate value between the upper and lower limits of the range is also specifically disclosed. Every smaller range between any stated value or intermediate value within a stated range, and any other stated value or intermediate value within said range, is also included in this invention. The upper and lower limits of these smaller ranges may be independently included or excluded from the range.

[0062] Unless otherwise stated, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. While only preferred methods have been described herein, any methods similar or equivalent to those described herein may be used in the implementation or testing of this invention. All references to this specification are incorporated by way of citation to disclose and describe the methods associated with those references. In the event of any conflict with any incorporated reference, the content of this specification shall prevail.

[0063] Various modifications and variations can be made to the specific embodiments described in this specification without departing from the scope or spirit of the invention, as will be apparent to those skilled in the art. Other embodiments derived from this specification will also be obvious to those skilled in the art. This application specification and embodiments are merely exemplary.

[0064] The terms “include,” “including,” “have,” “contain,” etc., used in this article are all open-ended terms, meaning that they include but are not limited to.

[0065] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0066] Example 1

[0067] like Figures 1-7 As shown, this embodiment provides an active current sharing drive circuit and its current slope control method, including:

[0068] The silicon carbide MOSFET includes a first silicon carbide MOSFET and a second silicon carbide MOSFET connected in parallel, wherein the gates of both the first silicon carbide MOSFET and the second silicon carbide MOSFET are connected to an active gate driver.

[0069] The active gate driver includes a master driver and a slave driver with identical structures;

[0070] The master driver and the slave driver are communicatively connected, and each includes a logic chip control circuit, a current sampling circuit, and a gate resistor switching circuit.

[0071] Both the current sampling circuit and the gate resistor switching circuit are connected to the logic chip control circuit.

[0072] A pulsed PWM signal is applied to the active gate driver. The pulse change signal is acquired by the first programmable logic chip LC1 and sent to the second programmable logic chip LC2. The second programmable logic chip LC2 acquires the pulse signals of the first silicon carbide MOSFET and the second silicon carbide MOSFET, and starts counting. While waiting to acquire the current information count data, it loads the compensation value of the previous current deviation. Based on the previous current deviation compensation value, the device turn-on time and current slope are adjusted by the gate resistor switching circuit to achieve dynamic current deviation compensation. The dynamic current information of the first silicon carbide MOSFET and the second silicon carbide MOSFET at the current pulse moment is acquired by the current sampling circuit and sent to the second programmable logic chip LC2. The second programmable logic chip LC2 sends the pulse signal and the dynamic current information to the first programmable logic chip LC1. The first programmable logic chip LC1 analyzes the pulse signal and the dynamic current information to obtain the dynamic current deviation value of the first silicon carbide MOSFET and the second silicon carbide MOSFET. The dynamic current deviation value is analyzed, and the compensation amount for the next pulse moment is obtained based on the analysis result. The compensation is loaded when the next pulse arrives, thus achieving dynamic current deviation compensation.

[0073] In this embodiment, each parallel device is equipped with an independent gate driver. Each gate driver includes three hardware circuits: a current information acquisition circuit, a gate push-pull channel switching circuit, and a logic chip control circuit. The current information acquisition circuit is responsible for acquiring the drain-source current i of the silicon carbide MOSFET device. ds Dynamic information, including switching delay time t on / off-delay and the current slope di ds / dt; The gate push-pull channel switching circuit is responsible for adjusting the turn-on time and current slope of individual devices; the logic chip control circuit is responsible for outputting the PWM signal of the gate push-pull channel switching current and the information transmission between the gate drivers. Using two push-pull channels achieves multi-level adjustment of the dynamic current slope. The combination of the drive circuit and control method realizes dynamic current deviation compensation in the parallel silicon carbide MOSFET structure.

[0074] Each silicon carbide MOSFET device (M1, M2) is equipped with an active gate driver. The active gate driver is connected to the gate (G), drive source (S), and main circuit source (S) interfaces of the silicon carbide MOSFET. Specifically, the active gate driver connected to silicon carbide MOSFET device M1 is the master driver, and the active gate driver connected to M2 is the slave driver. The hardware structure between the master and slave drivers is identical, differing only in the control method. Each active gate driver contains three hardware circuits: a current information acquisition circuit, a logic chip control circuit, and a gate resistor channel switching circuit.

[0075] Using the common-source parasitic inductor L inside the silicon carbide MOSFET SS The obtained induced voltage V sense The system acquires dynamic current information from the device; resistor R1 and capacitor C1 act as filters and integrators; K1, K2, and K3 are voltage limiters; operational amplifier OP1, resistors R2 and R3 together form an inverting voltage follower, outputting an inverting voltage V. s_n Operational amplifier OP2, resistors R4 and R5 together form a positive voltage follower, outputting a positive following voltage V. s_p CP1, CP2, CP3, and CP4 are comparators; the output voltage V of the inverting voltage follower is... s_n The reference voltage V is compared with the comparators CP1 and CP2. ref1 V ref2 The comparison is performed, and the output comparison pulse voltage V is... cp1 V cp2 Includes dynamic current information during the turn-on process; output voltage V of the positive voltage follower. s_p The reference voltage V is compared with the comparators CP3 and CP4. ref3 V ref4 The comparison is performed, and the output comparison pulse voltage V is... cp3 V cp4 Includes current dynamics information during the turn-off process. Furthermore, when setting the comparison reference voltage, V should be followed. ref1 <V ref2 V ref3 <V ref4 .

[0076] It includes two programmable logic chips, LC1 and LC2, and two isolation pulse transformers, T1 and T2, for communication between LC1 and LC2; there are four connection lines between logic chip LC2 and the current dynamic information acquisition circuit, used to transmit the comparison voltage V of the acquisition circuit. cp1 V cp2 V cp3 V cp4The current information is converted into dynamic current information through counting. There are four connection lines between the current information and the gate push-pull channel switching circuit, which are used to output pulse signals (PWM1, PWM2, PWM3, PWM4). The logic chip LC1 has a master-slave communication interface, which is used to transmit PWM pulse signals and dynamic current information of parallel devices to other active gate drivers. When the driver is used as the master driver, the logic chip LC1 also has a PWM receiving interface. The input of the isolation pulse transformer T2 is connected to the logic chip LC2, and the output is connected to the logic chip LC1, providing four unidirectional signal isolation transmission channels. The input of the isolation pulse transformer T1 is connected to the logic chip LC1, and the output is connected to the logic chip LC2, providing four unidirectional signal isolation transmission channels.

[0077] It contains four push-pull channels, where N-MOSFETs Q1 and Q2 are connected to the drive resistor R. g1 R g2 Together, they form the turn-on push-pull channel, while P-MOSFETs Q3 and Q4, along with the drive resistor, form the turn-off push-pull channel. Pulse signals PWM1 and PWM2 from logic chip LC2 control the turn-on and turn-off of Q1 and Q2, while PWM3 and PWM4 control the turn-on and turn-off of Q3 and Q4.

[0078] Step 1: The logic chip LC1 of the master driver receives the rising / falling edge PWM signal and sends it to the logic chip LC1 of the slave driver;

[0079] Step 2: The logic chip LC1 of the master-slave driver sends the rising / falling edge of the pulse PWM to the logic chip LC2 and starts waiting for the logic chip LC2 to return dynamic current information;

[0080] Step 3: After receiving the rising / falling edge of the PWM pulse, the logic chip LC2 of the main driver calculates the pulse signal of M1 (PWM1, PWM2, PWM3, PWM4) based on the current deviation value of the previous moment and sends it. At the same time, it starts counting and waits for the comparison voltage V. cp1 V cp2 V cp3 V cp4 When the rising edge arrives, the count value is saved. After obtaining the dynamic current information of the parallel device M1, it is uploaded to the logic chip LC1.

[0081] After receiving the rising / falling edge of the PWM pulse, the logic chip LC2 of the driver directly sends the pulse signal of M2 (PWM1, PWM2, PWM3, PWM4) and simultaneously starts counting, waiting to compare the voltage V. cp1 V cp2 V cp3 Vcp4 The count value is saved on the rising edge. After obtaining the dynamic current information of the parallel device M2, it is uploaded to the logic chip LC1 of the slave driver.

[0082] Step 4: After receiving the dynamic current information of device M1 sent by logic chip LC2, the logic chip LC1 of the main driver waits for the dynamic current information of parallel device M2 to be uploaded from the logic chip LC1 of the driver.

[0083] After receiving the dynamic current information of the parallel device M2 from the logic chip LC2, the logic chip LC1 of the slave driver sends it to the logic chip LC1 of the master driver, and then waits for the next rising / falling edge of the PWM.

[0084] Step 5: After receiving the dynamic current information of the parallel device M2 sent from the driver, the logic chip LC1 of the main driver calculates the dynamic current deviation value of the parallel device and sends it to the logic chip LC2 of the main driver. This waits for the next PWM pulse.

[0085] Step 3: Dynamic current information counting acquisition method: rising edge of pulse PWM and V cp1 The count value between rising edges is the device turn-on delay time t. on-delay V cp1 Rising edge and V cp2 The count value between rising edges is the dynamic current slope value t of the device turn-on. on-slope ; The falling edge of the pulse PWM and V cp3 The count value between rising edges is the device turn-off delay time t. off-delay V cp3 Rising edge and V cp4 The count value between rising edges is the dynamic current slope value t of the device turn-off. off-slope .

[0086] Step 5 calculates the dynamic current deviation of the parallel devices by calculating the turn-on delay time deviation Δt during device turn-on. on-delay =t on-delay-M1 -t on-delay-M2 Dynamic current slope deviation Δt during device turn-on on-sl ope =t on-slope-M1 -t on-slope-M2 ; Turn-off delay time deviation Δt during device turn-off process off-delay =t off-delay-M1 -t off-delay-M2 Dynamic current slope deviation Δt during device turn-off off-slope =t off-slope-M1 -t off-slope-M2 ;

[0087] The dynamic current information transmission method between logic chips: The dynamic current information exchange method between logic chips LC1 with different drivers, and between logic chips LC1 and LC2 with the same driver, adopts serial communication and each has an independent communication clock.

[0088] Step 3 is responsible for the calculation method of the main driver pulses PWM1, PWM2, PWM3, and PWM4 of device M1. Pulses PWM1 and PWM2 are complementary to pulses PWM3 and PWM4.

[0089] Obtain the main driver pulses PWM1, PWM2, PWM3, and PWM4.

[0090] Parallel device switching delay compensation: The parallel devices include a first silicon carbide MOSFET and a second silicon carbide MOSFET. A device turn-on delay compensation time T is set between the rising edge of the PWM pulse received by the main driver and the rising edge of the actual output pulses PWM1 and PWM2. on-d-c A device turn-off delay compensation time T is set between the falling edge of the PWM pulse and the rising edge of the actual output pulses PWM3 and PWM4. off-d-c When there is a turn-on delay deviation Δt between parallel devices M1 and M2 on-delay When, make the current time T on-d-c Equal to the previous time T on-d-c -Δt on-delay This will complete the activation delay compensation; when there is a shutdown delay deviation Δt off-delay When, make the current time T off-d-c Equal to the previous time T off-d-c -Δt off-delay This will allow for shutdown delay compensation;

[0091] Perform dynamic current slope deviation compensation for parallel devices:

[0092] The turn-on process of the first silicon carbide MOSFET and the second silicon carbide MOSFET is divided into turn-on delay T. on-delay With current controlled T on-control In the two time periods, during the turn-on delay phase, both PWM1 and PWM2 are at a high level; the current-controlled phase is divided into two time periods, T... Q1+Q2 Stages and T Q1 Phase, in which T Q1+Q2 During the phase, both PWM1 and PWM2 are at a high level, T Q1 During the phase where PWM1 is high and PWM2 is low, the Δt between parallel devices... on-slope When >0, T Q1+Q2 Decrease by one clock cycle T working T Q1 Add a Tworking If when Δt on-slope When <0, T Q1+Q2 Add one clock cycle T working T Q1 Decrease by one T working ;

[0093] The device's turn-off process is divided into turn-off delay T. off-delay With current controlled T off-control During the two time periods, in the turn-off delay phase, both PWM3 and PWM4 are at a high level; in the current-controlled phase T... off-control Divided into two time periods, T Q3+Q4 Stages and T Q3 Phase, in which T Q3+Q4 During the phase, PWM3 and PWM4 are both high, T Q3 During the phase where PWM3 is high and PWM4 is low, the Δt between parallel devices... off-slope When >0, T Q3+Q4 Decrease by one clock cycle T working T Q3 Add a T working If when Δt off-slope When <0, T Q3+Q4 Add one clock cycle T working T Q3 Decrease by one T working .

[0094] The purpose of this embodiment is to compensate for the dynamic current deviation between parallel silicon carbide MOSFET devices. For example... Figure 1 The diagram shows an active current-sharing drive circuit for parallel silicon carbide MOSFET devices. Each silicon carbide MOSFET device (M1, M2) is equipped with an active gate driver. The active gate driver is connected to the gate (G), drive source (S), and main circuit source (S) interfaces of the silicon carbide MOSFETs. The active gate driver connected to silicon carbide MOSFET device M1 is the master driver, and the active gate driver connected to M2 is the slave driver. The hardware structure between the master and slave drivers is identical, differing only in the control method. Each active gate driver contains three hardware circuits: a current information acquisition circuit, a logic chip control circuit, and a gate resistor channel switching circuit.

[0095] Among them, the current dynamic information acquisition circuit is as follows Figure 2 As shown, it is mainly responsible for collecting the dynamic current information of parallel devices: turn-on / turn-off delay time t on / off-delay The switching current slope di / dt is used. The common-source inductance L within the silicon carbide MOSFET device is employed. SS The induced voltage V during the switching transient processsense The device dynamic current information is collected. The induced voltage Vsense is shown in equation (1), and after passing through the passive integrator composed of R1 and C1, the integrated voltage Vin is obtained, as shown in equation (2).

[0096]

[0097]

[0098] K1, K2, and K3 are voltage limiters. In this specific embodiment, the limiting value of K1 is ±5V, and the limiting values ​​of K2 and K3 are 0 to 5V. Operational amplifier OP1, resistors R2 and R3 together form an inverting voltage follower, outputting an inverting following voltage V. s_n Operational amplifier OP2, resistors R4 and R5 together form a positive voltage follower, outputting a positive following voltage V. s_p Furthermore, when inconsistencies occur in the parameters of the front-end sampling circuit of parallel devices, the resulting induced voltage V sense The deviation can be compensated by adjusting the ratio between R2, R3, R4, and R5. The adjusted voltage value V in_n With V in_p As shown in equations (3) and (4).

[0099]

[0100]

[0101] CP1, CP2, CP3, and CP4 are comparators; the output voltage V of the inverting voltage follower is... s_n The reference voltage V is compared with the comparators CP1 and CP2. ref1 V ref2 The comparison is performed, and the output comparison pulse voltage V is... cp1 V cp2 Includes dynamic current information during the turn-on process; output voltage V of the positive voltage follower. s_p The reference voltage V is compared with the comparators CP3 and CP4. ref3 V ref4 The comparison is performed, and the output comparison pulse voltage V is... cp3 V cp4 It includes dynamic current information during the shutdown process.

[0102] Ultimately, the dynamic current information is obtained by comparing the pulse voltage (V) using the logic chip LC2. cp1 V cp2 V cp3 V cp4 The result is obtained after counting. The rising edge of the PWM pulse is related to V. CP1The count value t between rising edges on-delay The device turn-on delay time; the comparison voltage V CP1 Rising edge and V CP2 The count value t between rising edges on-slope Represents the slope of the device's turn-on current; the falling edge of the pulse PWM and V CP3 The count value t between rising edges off-delay The device turn-off delay time; the comparison voltage V cp3 With V cp4 The count value t between rising edges off-slope This represents the slope of the device's turn-off current.

[0103] The logic chip control circuit of the active gate driver, such as Figure 3 As shown, the system includes two programmable logic chips, LC1 and LC2. In this embodiment, the logic chips used are ZYNQ-7010 chips. Two isolation pulse transformers, T1 and T2, are connected between the two logic chips LC1 and LC2 for communication. Four connection lines exist between logic chip LC2 and the current dynamic information acquisition circuit, used to transmit the comparison voltage V of the acquisition circuit. cp1 V cp2 V cp3 V cp4 The current information is converted into dynamic current information through counting. There are four connection lines between the current information and the gate push-pull channel switching circuit, which are used to output pulse signals (PWM1, PWM2, PWM3, PWM4). The logic chip LC1 has a master-slave communication interface, which is used to transmit PWM pulse signals and dynamic current information of parallel devices to other active gate drivers. When the driver is used as the master driver, the logic chip LC1 also has a PWM receiving interface. The input of the isolation pulse transformer T2 is connected to the logic chip LC2, and the output is connected to the logic chip LC1, providing four unidirectional signal isolation transmission channels. The input of the isolation pulse transformer T1 is connected to the logic chip LC1, and the output is connected to the logic chip LC2, providing four unidirectional signal isolation transmission channels.

[0104] The gate resistor switching circuit of the active gate driver is as follows: Figure 4 As shown, it contains four push-pull channels, where N-MOSFETs Q1 and Q2 are connected to the drive resistor R. g1 R g2 Together, they form the turn-on push-pull channel, while P-MOSFETs Q3 and Q4, along with the drive resistor, form the turn-off push-pull channel. Pulse signals PWM1 and PWM2 from logic chip LC2 control the turn-on and turn-off of Q1 and Q2, while PWM3 and PWM4 control the turn-on and turn-off of Q3 and Q4.

[0105] The active flow sharing control method used in the embodiment is as follows: Figure 5 As shown, the process can be roughly summarized into the following steps:

[0106] Step 1: The logic chip LC1 of the master driver receives the rising / falling edge PWM signal and sends it to the logic chip LC1 of the slave driver;

[0107] Step 2: The logic chip LC1 of the master-slave driver sends the rising / falling edge of the pulse PWM to the logic chip LC2 and starts waiting for the logic chip LC2 to return dynamic current information;

[0108] Step 3: After receiving the rising / falling edge of the PWM pulse, the logic chip LC2 of the main driver calculates the pulse signal of M1 (PWM1, PWM2, PWM3, PWM4) based on the current deviation value of the previous moment and sends it. At the same time, it starts counting and waits for the comparison voltage V. cp1 V cp2 V cp3 V cp4 When the rising edge arrives, the count value is saved. After obtaining the dynamic current information of the parallel device M1, it is uploaded to the logic chip LC1.

[0109] After receiving the rising / falling edge of the PWM pulse, the logic chip LC2 of the driver directly sends the pulse signal of M2 (PWM1, PWM2, PWM3, PWM4) and simultaneously starts counting, waiting to compare the voltage V. cp1 V cp2 V cp3 V cp4 The count value is saved on the rising edge. After obtaining the dynamic current information of the parallel device M2, it is uploaded to the logic chip LC1 of the slave driver.

[0110] Step 4: After receiving the dynamic current information of device M1 sent by logic chip LC2, the logic chip LC1 of the main driver waits for the dynamic current information of parallel device M2 to be uploaded from the logic chip LC1 of the main driver; after receiving the dynamic current information of parallel device M2 sent by logic chip LC2, the logic chip LC1 of the slave driver sends it to the logic chip LC1 of the main driver, and then waits for the next rising / falling edge of the PWM.

[0111] Step 5: After receiving the dynamic current information of the parallel device M2 sent from the driver, the logic chip LC1 of the main driver calculates the dynamic current deviation value of the parallel device and sends it to the logic chip LC2 of the main driver. This waits for the next PWM pulse.

[0112] In step 3, the current information counting method is as follows: the rising edge of the pulse PWM and Vcp1 The count value between rising edges is the device turn-on delay time t. on-delay V cp1 Rising edge and V cp2 The count value between rising edges is the dynamic current slope value t of the device turn-on. on-slope ; The falling edge of the pulse PWM and V cp3 The count value between rising edges is the device turn-off delay time t. off-delay V cp3 Rising edge and V cp4 The count value between rising edges is the dynamic current slope value t of the device turn-off. off-slope .

[0113] Step 5 calculates the dynamic current deviation of the parallel devices by calculating the turn-on delay time deviation Δt during device turn-on. on-delay =t on-delay-M1 -t on-delay-M2 Dynamic current slope deviation Δt during device turn-on on-slope =t on-slope-M1 -t on-slope-M2 ; Turn-off delay time deviation Δt during device turn-off process off-delay =t off-delay-M1 -t off-delay-M2 Dynamic current slope deviation Δt during device turn-off off-slope =t off-slope-M1 -t off-slope-M2 .

[0114] In the above control methods, the dynamic current information exchange between logic chips LC1 of different drivers and between logic chips LC1 and LC2 of the same driver adopts a serial communication method, and each has an independent communication clock.

[0115] In step 3, the PWM waveform for compensating the dynamic current deviation of the parallel device M1 is as follows: Figure 6 As shown (taking activation as an example). Pulses PWM1 and PWM2 are complementary to pulses PWM3 and PWM4; a device activation delay compensation time T is set between the rising edge of the PWM pulse received by the main driver and the rising edge of the actual output pulses PWM1 and PWM2. on-d-c When there is a turn-on delay deviation Δt between parallel devices M1 and M2 on-delay When, make the current time T on-d-c Equal to the previous time T on-d-c -Δt on-delay The activation delay compensation can then be completed.

[0116] The turn-on process of the device is divided into turn-on delay T. on-delay With current controlled T on-controlIn the two time periods, during the turn-on delay phase, both PWM1 and PWM2 are at a high level; the current-controlled phase is divided into two time periods, T... Q1+Q2 Stages and T Q1 Phase, in which T Q1+Q2 During the phase, both PWM1 and PWM2 are at a high level, T Q1 During the phase where PWM1 is high and PWM2 is low, the Δt between parallel devices... on-slope When >0, T Q1+Q2 Decrease by one clock cycle T working T Q1 Add a T working If when Δt on-slope When <0, T Q1+Q2 Add one clock cycle T working T Q1 Decrease by one T working .

[0117] exist Figure 6 Below are several different T values ​​in this embodiment. Q1+Q2 The measured waveform of the activation time. It can be seen that as T... Q1+Q2 As the duration of action gradually increases, the dynamic current of the device exhibits different slopes.

[0118] Figure 7 The figures show the actual closed-loop effect in this embodiment. Figure (a) shows the dynamic current deviation without compensation, indicating a significant dynamic current deviation. Figure (b) shows the current waveform with dynamic current deviation compensation enabled. It detects the deviation during the second pulse and compensates for it during the third pulse, demonstrating the actual effect of this embodiment.

[0119] The above description is merely a preferred embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An active current sharing drive circuit, characterized in that, include: The silicon carbide MOSFET includes a first silicon carbide MOSFET and a second silicon carbide MOSFET connected in parallel, and both the first silicon carbide MOSFET and the second silicon carbide MOSFET are connected to an active gate driver; The active gate driver includes a master driver and a slave driver with identical structures; Both the master driver and the slave driver include a logic chip control circuit, a current sampling circuit, and a gate resistor switching circuit; the logic chip control circuit of the master driver is communicatively connected to the logic chip control circuit of the slave driver. Both the current sampling circuit and the gate resistor switching circuit are connected to the logic chip control circuit. The current sampling circuit includes: a first voltage limiter K1, a second voltage limiter K2, a third voltage limiter K3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a first operational amplifier. OP 1. Second operational amplifier OP 2. First comparator CP 1. Second comparator CP 2. Third comparator CP 3. Fourth comparator CP 4 and capacitor C1; In this configuration, one end of the first voltage limiter K1 is connected to the output terminal of the first resistor R1 and the input terminal of the capacitor C1, and the other end is connected to the input terminal of the second resistor R2 and the second operational amplifier. OP The positive input terminal of 2 is connected to the output terminal of capacitor C1, and the input terminal of the first resistor R1 is used to input the induced voltage. The output terminal of the second resistor R2 is connected to the input terminal of the third resistor R3 and the negative input terminal of the first operational amplifier OP1, respectively. The positive input terminal of the first operational amplifier OP1 is grounded. The output terminals of the first operational amplifier OP1 and the third resistor R3 are both connected to one end of the second voltage limiter K2. The other end of the second voltage limiter K2 is connected to the first operational amplifier. OP The negative input terminal of 1 and the second operational amplifier OP 2 is the negative input terminal; Second operational amplifier OP The negative input terminal of resistor 2 is connected to one end of the fourth resistor R4 and one end of the fifth resistor R5, respectively. The other end of the fourth resistor R4 is grounded, and the other end of the fifth resistor R5 is connected to the second operational amplifier. OP The output terminals of 2 are all connected to one end of the third voltage limiter K3, and the other end of the third voltage limiter K3 is connected to the third comparator. CP 3 and the fourth comparator CP 4's negative input terminal; The first comparator CP 1. Second comparator CP 2. Third comparator CP 3 and the fourth comparator CP The positive input terminal of 4 is used to input the reference voltage, and the output terminal is used to output the comparison pulse voltage. The gate resistor switching circuit includes two parallel-connected push-pull channels for turning on and push-pull channels for turning off. The push-pull channel opening includes: a first N-channel MOSFET. Q 1. Second N-channel MOSFET Q 2. First driving resistor R g1 Second driving resistor R g2 The first N-channel MOS transistor Q 1 and the second N-channel MOSFET Q The drain pins of 2 are all connected to the drive turn-on voltage. V DD The first N-channel MOS transistor Q 1 and the second N-channel MOSFET Q The source pins of 2 are respectively connected to the first drive resistor. R g1 and the second driving resistor R g2 One end is connected in series, the first driving resistor R g1 and the second driving resistor R g2 The other end of each is connected to the gate pin of the silicon carbide MOSFET device; The turn-off push-pull channel includes a first P-channel MOSFET. Q 3. Second P-channel MOSFET Q 4. Third driving resistor R g3 and the fourth driving resistor R g4 The first P-channel MOS transistor Q 3 and the second P-channel MOSFET Q The drain pins of 4 are all connected to the drive turn-off voltage. V SS The first P-channel MOS transistor Q 3 and the second P-channel MOSFET Q The source pin of 4 is respectively connected to the third driving resistor. R g3 and the fourth driving resistor R g4 One end is connected in series, the third driving resistor R g3 and the fourth driving resistor R g4 The other end of each is connected to the gate pin of the silicon carbide MOSFET device; The logic chip control circuit includes: an isolation pulse transformer and a first programmable logic chip. LC 1 and 2 programmable logic chips LC 2; The first programmable logic chip LC 1 and the second programmable logic chip LC 2. Communication connection via the isolation pulse transformer, the isolation pulse transformer including a first isolation pulse transformer connected in parallel. T 1 and second isolation pulse transformers T 2; The first programmable logic chip LC The first chip is equipped with a master / slave communication interface and a PWM receiving interface. The second programmable logic chip... LC The input terminal of 2 is used to receive the comparison voltage, and the second programmable logic chip LC The output terminal of 2 is used to output dynamic current information.

2. The current slope control method for an active current sharing drive circuit according to claim 1, characterized in that, include: Step 1: Apply pulsed PWM to the active gate driver, via the first programmable logic chip. LC 1. Acquire the pulse change signal and send the pulse change signal to the second programmable logic chip. LC 2 in; Step 2: Through the second programmable logic chip LC 2. Obtain the pulse signals from the first silicon carbide MOSFET and the second silicon carbide MOSFET, start counting, acquire current information counting data, and load the compensation value of the previous current deviation. Step 3: Based on the previous current deviation compensation value, adjust the device turn-on time and current slope through the gate resistor switching circuit to achieve dynamic current deviation compensation; The dynamic current information of the first silicon carbide MOSFET and the second silicon carbide MOSFET at the current pulse moment is obtained through the current sampling circuit. Step 4: Send the dynamic current information to the second programmable logic chip. LC 2; and through the second programmable logic chip LC 2. Send the pulse signal and the dynamic current information to the first programmable logic chip. LC 1 in; Step 5: Through the first programmable logic chip LC 1. Analyze the pulse signal and the dynamic current information to obtain the dynamic current deviation value of the first silicon carbide MOSFET and the second silicon carbide MOSFET; Step Six: Analyze the dynamic current deviation value, obtain the compensation amount for the next pulse time based on the analysis results, wait for the next pulse to arrive and load, and realize dynamic current deviation compensation.

3. The current slope control method according to claim 2, characterized in that, The dynamic current information includes: switching delay time. t on / off-delay The dynamic slope d of the drain-source current of parallel devices i ds / d t .

4. The current slope control method according to claim 3, characterized in that, The process of acquiring the dynamic current information includes: The common-source inductance inside the silicon carbide MOSFET device is obtained through a current sampling circuit. L SS Induced voltage during switching transients V sense The integral voltage V is obtained through a passive integrator composed of the first resistor R1 and the capacitor C1. in : ； ； Obtained through current sampling circuit V in_n and V in_p : ； In the formula, di ds (t) / dt is the dynamic slope of the drain-source current of the parallel device, V in_n V is the output voltage of the first operational amplifier OP1. in_p This is the output voltage of the second operational amplifier OP2; Obtain reference voltage data V ref1 , V ref2 , V ref3 , V ref4 Through the first comparator CP 1. Second comparator CP 2. Third comparator CP 3. Fourth comparator CP 4. Compare the reference voltage data to obtain the comparison pulse voltage data. V cp1 , V cp2 , V cp3 , V cp4 ; By analyzing the pulse voltage data and current information count data, dynamic current information is obtained; Among them, the rising edge of the pulse PWM and V CP1 Count value between rising edges t on-delay The device turn-on delay time is used to compare pulse voltage data. V CP1 rising edge and V CP2 Count value between rising edges t on-slope The slope of the device's turn-on current, the falling edge of the pulse PWM and V CP3 Count value between rising edges t off-delay For the device turn-off delay time, compare the pulse voltage data. V cp3 and V cp4 Count value between rising edges t off-slope This represents the slope of the device's turn-off current.

5. The current slope control method according to claim 4, characterized in that, The process of obtaining dynamic current deviation values ​​includes: Device turn-on delay time deviation Δ t on-delay = t on-delay-M1 - t on-delay-M2 Dynamic current slope deviation Δ during device turn-on t on-slope = t on-slope-M1 - t on-slope-M2 ; Turn-off delay time deviation Δ during device turn-off process t off-delay = t off-delay-M1 - t off-delay-M2 Dynamic current slope deviation Δ during device turn-off t off-slope = t off-slope-M1 - t off-slope-M2 .

6. The current slope control method according to claim 2, characterized in that, There is a switching delay in the parallel devices when acquiring current information counting data. The process of compensating for the switching delay of the parallel devices includes: the parallel devices include a first silicon carbide MOSFET and a second silicon carbide MOSFET, and a device turn-on delay compensation time T is set between the rising edge of the PWM pulse received by the main driver and the rising edge of the actual output pulses PWM1 and PWM2. on-d-c A device turn-off delay compensation time T is set between the falling edge of the PWM pulse and the rising edge of the actual output pulses PWM3 and PWM4. off-d-c When there is a turn-on delay deviation Δt between parallel devices M1 and M2 on-delay When, make the current time T on-d-c Equal to the previous time T on-d-c -Δt on-delay This will complete the activation delay compensation; when there is a shutdown delay deviation Δt off-delay When, make the current time T off-d-c Equal to the previous time T off-d-c -Δt off-delay This will allow for shutdown delay compensation.

7. The current slope control method according to claim 2, characterized in that, The process of dynamic current slope deviation compensation includes: The turn-on process of the first silicon carbide MOSFET and the second silicon carbide MOSFET is divided into turn-on delay T. on-delay With current controlled T on-control During the two time periods, PWM1 and PWM2 are both high during the turn-on delay phase; the current-controlled phase is divided into two time periods, T... Q1+Q2 Stages and T Q1 Phase, in which T Q1+Q2 During the phase, both PWM1 and PWM2 are at a high level, T Q1 During the phase where PWM1 is high and PWM2 is low, when the Δt between the parallel devices... on-slope When >0, T Q1+Q2 Decrease by one clock cycle T working T Q1 Add a T working If when Δt on-slope When <0, T Q1+Q2 Add one clock cycle T working T Q1 Decrease by one T working ; The device's turn-off process is divided into turn-off delay T. off-delay With current controlled T off-control During the two time periods, in the turn-off delay phase, both PWM3 and PWM4 are at a high level; in the current-controlled phase T... off-control Divided into two time periods, T Q3+Q4 Stages and T Q3 Phase, in which T Q3+Q4 During the phase, PWM3 and PWM4 are both high, T Q3 During the phase where PWM3 is high and PWM4 is low, the Δt between parallel devices... off-slope When >0, T Q3+Q4 Decrease by one clock cycle T working T Q3 Add a T working If when Δt off-slope When <0, T Q3+Q4 Add one clock cycle T working T Q3 Decrease by one T working .

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